Since it's not obvious, add comments to acpigen_resource_word,
acpigen_resource_dword and acpigen_resource_qword to clarify out what
the magic number in byte 0 means. The most significant bit of byte 0
indicates if it is a small or large resource data type. In the case of
the MSB being 0, it's a small resource data type (aka type 0), and the
other bits encode bit the type and size of the item; if the MSB is 1,
it's a large resource data type (aka type 1), and the other bits just
encode the type and there are two separate bytes to encode the size.
Beware that the large resource's data type values in the ACPI
specification don't include the MSB that's set, but only the 7 lower
bits.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6a6c9fb1bcde232122bb5899b9a0983ef48e12b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The detachable Starmie will use MIPI panels, which require reading
serializable data from the CBFS. So we add MIPI panel support to the
display configuration and align the configuration sequence with the
panels that use MIPI bridges.
The PMIC Datasheet:
TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf
BUG=b:275470328
BRANCH=corsola
TEST=emerge-corsola coreboot chromeos-bootimage and display normally
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I6f079e54f0317ff2f685f0e3834ebd1ceb8e9fcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Error message ´Cannot map compressed file config without cbfs_cache' is reported.
Compressed parts of CBFS can not be used during bootblock stage.
Remove config from mb_log_list.
Will be added to verified items by CB:74752.
BUG=NA
TEST=booting and verify log on facebook FBG1701
Change-Id: Iacf023bc8b9c2ebc66137c4ea683589751a30d2f
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add _STA field entry for r8168 ACPI device and set to
ACPI_STATUS_DEVICE_HIDDEN_ON in order to hide device from
OS (Windows) as there is no driver needed (or available).
Windows correctly attaches drivers to the PCIe device, the
separate ACPI device is unused and unneeded.
Linux is unaffected as it does not use the ACPI device status.
Change-Id: Ib7ae99fffcb00e71421b93c2794119841aa239d3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75177
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad
Windows drivers to properly attach. Change the interrupt type
from EDGE to LEVEL.
TEST=build/boot samsung/lumpy, verify touchpad functional under
both Windows 10/11 and Linux, verify Windows overlay driver
correctly remaps top row keys.
Change-Id: Ie4268b4de5779ee148699c7bef8c700a99816f1e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad
Windows drivers to properly attach.
TEST=build/boot google/parrot, verify touchpad functional under
both Windows 10/11 and Linux, verify Windows overlay driver
correctly remaps top row keys.
Change-Id: Ic164244eceb52221653bd60f7217f9a09e38c1b6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75180
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad
Windows drivers to properly attach. Change the interrupt type
from EDGE to LEVEL.
TEST=build/boot google/butterfly, verify touchpad functional under
both Windows 10/11 and Linux, verify Windows overlay driver
correctly remaps top row keys.
Change-Id: I971795becfb05fb42921ff6f40a20892f4f5654a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use board-specific ASL for PS2-attached trackpad rather than the EC/SIO
default, so that Windows installs a multitouch-capable driver rather
than the standard PS2 mouse driver.
TEST=build/boot Win11 on google/stout, verify trackpad is multitouch
capable.
Change-Id: Id93bbe53f35b1e2c35e36d8175889786b9f5de8b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75176
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In ACPI 1.0 the processor objects were inside the \_PR scope, but since
ACPI 2.0 the \_SB scope can be used for that. Outside of coreboot some
firmwares still used the \_PR scope for a while for legacy ACPI 1.0 OS
compatibility, but apart from that the \_PR scope is deprecated.
coreboot already uses the \_SB scope for the processor devices
everywhere, so move the \_SB scope out of the ACPI_CPU_STRING to the
format string inside the 3 snprintf statements that use the
ACPI_CPU_STRING.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I76f18594a3a623b437a163c270547d3e9618c31a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Don't set bit 2 of the return value of the _STA method in order for
Windows not to show a warning about an unknown device in the device
manager for this device.
TEST=The unknown device with device instance path ACPI\AMD0040\3
disappeared from the device manager in Windows 10 build 19045 on a
Mandolin board with a Picasso APU.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If005f06843956004c281fd70cf364171148cb9ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68962
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
VMX is enabled through a bit in the IA32_FEATURE_CONTROL MSR, which can
be locked. The MSR remains locked after a non-power cycle reset, though.
If the MSR is locked, coreboot bails out and leaves VMX in the state it
was found. Because of this, changes to the VMX enable option in the BMC
only take effect after the system is power cycled.
This behaviour is highly undesirable because users are likely not aware
that a power cycle is required for changes to VMX state to take effect.
So, if VMX is supported, the IA32_FEATURE_CONTROL MSR is locked and the
current VMX state does not match the requested state, then issue a full
reset. This will power cycle the system and unlock the MSR, so that the
desired VMX state can be programmed into the MSR. This is checked early
to avoid needlessly doing time-consuming operations (running FSP) twice
if we know we will need to power cycle the system anyway.
Note that a user may change the VMX setting after the newly-added check
but before the setting is read in ramstage to program the MSR, but this
is a non-issue as firmware settings need a reset to take effect anyway.
TEST: Toggle VMX setting in BMC and reboot without power cycle, observe
coreboot automatically issues a power cycle reset because the MSR
is locked and the VMX state differs. Verify that the system boots
properly with VMX in the correct state after having power cycled.
Change-Id: Id9061ba896a7062da45a86fb26eeb58927184dcb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Instead of having the maximum number of possible CPU objects defined in
the DSDT, dynamically generate the number of needed CPU devices in the
SSDT like it's done on all other x86 platforms in coreboot.
TEST=APU2 still boots and Linux doesn't show any ACPI errors with this
patch applied and it prints "ACPI: \_SB_.P000: Found 2 idle states".
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id6f057ad130a27b371722fa66ce0a982afc43c6c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73073
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Instead of having binaryPI generate a PSTATE SSDT that uses \_PR_ as the
scope for the CPU objects and patching this SSDT in coreboot to use the
\_SB_ scope in patch_ssdt_processor_scope, request binaryPI to use the
\_SB_ scope instead by setting the late platform configuration option
ProcessorScopeInSb to true.
TEST=APU2 still boots and Linux doesn't show any ACPI errors with this
patch applied and it prints "ACPI: \_SB_.P000: Found 2 idle states".
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I411201b55cfee30ae41da4e6814679bdb49e9bf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73386
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
