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16463 Commits

Author SHA1 Message Date
David Wu
5f9849ebd5 mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for kuldax 
Enable DRIVERS_GENESYSLOGIC_GL9755 support for kuldax.

BUG=b:232858957
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I1b2c0bff8497d727c697ea6287078055a39bd1f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
 2022-08-03 12:46:15 +00:00
Tony Huang
f3e5f9966f mb/google/brya/variants/agah: set tcc_offset to 3 
Set tcc_offset value to 3 in devicetree for Thermal Control Circuit
(TCC) activation feature. This value is suggested by Thermal team.

BUG=b:240600260
TEST=emerge-draco coreboot
     verified by thermal team

Change-Id: I3044643d52f1d6e883beb3ec87a77f32d086f46c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
 2022-08-03 12:45:52 +00:00
Vinod Polimera
4ce67c02b2 mb/google/herobrine: Add support to enable display 
This change adds support to enable edp gpios, display init for
herobrine.

BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.
Monitor name: LQ140M1JW49

Change-Id: I01dbe23afbb3d41d87f24cb7dcfa456cb7f133fb
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64885
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-08-03 03:26:13 +00:00
FrankChu
b85997df25 mb/google/dedede/var/pirika: Add Elan touchscreen support 
Enable I2C2 and register touchscreen ACPI device for pirika.

BUG=b:236564261
TEST=touch screen is functional.

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Id2fd5606b7126eabc1c88bf516198ff00b5d75dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2022-08-02 17:14:28 +00:00
Eric Lai
71a488d428 mb/google/brya/var/ghost: Enable AMP power 
Follow latest schematic, GPP_A17 is used to enable AMP power.

BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=Check I2C scan can see the AMP return ACK.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ia6c52302a12ddec68303714ac07e96a65a8f8fb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
 2022-08-02 17:14:12 +00:00
Tim Crawford
57fecef66f mb/system76: Change touchpad detection method 
Use the new "detect" method instead of "probed". Fixes an uncommon issue
where i2c-hid fails to initialize the device on Linux.

Tested on: gaze15, gaze16-3060, lemp10, oryp8

Tested:
- Linux: Touchpad works across 50 reboots
- Windows: Touchpad is still detected as an I2C HID device
- Windows: Extra I2C HID devices are not shown in Device Manager

Change-Id: I6a899c64a6d77b65a2ae57ab8df81cd84b568184
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
 2022-08-02 15:51:16 +00:00
Rex-BC Chen
1250820916 mb/google/geralt: Enable Chrome EC 
Initialize SPI bus 0 for Chrome EC control.

TEST=build pass
BUG=b:236331724

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6de5ea8a0273a3b0c725e4cdbcf69f4db74c5db7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2022-08-02 12:20:52 +00:00
Simon Yang
60ac26521e mb/google/nissa/craask: Add eMMC DLL tuning value 
Configure eMMC DLL tuning values for Craask board.

BUG=b:238985924
TEST="Use the value to boot on Nivviks and Craask successfully."

Change-Id: I14f3e2329404cca94e14034d1fb52fcb99a2ddc9
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66218
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-08-02 08:12:00 +00:00
Subrata Banik
1bc4bb75fb mb/google/rex: Enable CSE Lite SKU 
The first CSE Lite SKU is available, therefore enable the Kconfig
option to have the CSE reboot the system into its RW FW during a cold
boot.

BUG=b:240228892
TEST=TBD

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I00ef4176cf08cbeed06e446cfe68f06cb1ea27b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66287
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-08-02 07:10:30 +00:00
Veerabhadrarao Badiganti
16611f31eb mb/google/herobrine: Add PCIe domain support 
Add PCIe domain support for herobrine by enabling it in the devicetree.

BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe card
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.

Output logs:
  ->dpch: storage init
    Initializing NVMe controller 1e0f:0001
    Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
    Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
    *  0: NVMe Namespace 1
     1 devices total

Also verified NVMe boot path, that is depthcharge is able to load the
kernel image from NVMe storage.

Change-Id: Ied8fbbc8d20698ee081d93ba184b7d0291bb6a76
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65137
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-08-01 18:04:54 +00:00
Zhixing Ma
a47a490635 mb/google/brya: Disable the Package C-state demotion 
Disabling the Package C-state demotion feature for brya baseboard
as a work around to the S0ix issue and also this doesn't have any
impact on the power and performance measured and verified by the
PNP team.

This feature will be enabled after its functionality is verified with no
issues and also based on its impact on PNP.

BUG=none
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that S0ix issue is resolved.

Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: Id3941c8870d41b25488c8ac5d38534fa94664d4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2022-08-01 18:03:58 +00:00
Bill XIE
4e43abf9c1 mb/hp/z220_series: Improve the port for z220_sff_workstation 
- Move configs for PCIe ports not present on z220_sff_workstation
  from the devicetree.cb of base board to the overridetree.cb of
  z220_cmt_workstation.

- Add a note for ME/AMT Flash Override jumper, for it is hard to
  flash from OEM firmware either internally or externally without
  closing this jumper.

- Add a side note for similar HP Compaq Elite 8300 SFF.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I35d8b97f52a83910a61c12b1f7367ee7a19a9ad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-07-30 18:39:31 +00:00
Raihow Shi
a955efc190 mb/google/brask/variants/moli: Add DPTF setting in Moli 
DPTF Policy and temperature sensor values from thermal team.

BUG=b:236294162
TEST=emerge-brask coreboot

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Iebcfb74c4bc719e6d8d8d9317435becd912eaf85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
 2022-07-30 18:30:06 +00:00
Subrata Banik
8072b420a6 mb/google/rex: Perform display configuration override 
This patch enables display port configuration as per the Rex
schematics.

TEST=Able to dump FSP UPD to ensure the override is successful.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9e81d037416e46e52cb72344425d6d8725dae192
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
 2022-07-29 19:58:01 +00:00
Stanley Wu
828243ebca mb/google/nissa/var/pujjo: Enable OZ711LV2LN SD card controller 
Pujjoflex support OZ711LV2LN SD card controller,
Select the Bayhub LV2 driver for OZ711LV2LN SD card.

BUG=b:215487382
TEST=Build FW and checking SD card work as expected in OS.

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I6759fde1eaf24599a1fdb364d6e78f4e4e12f311
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
 2022-07-29 15:06:46 +00:00
Tarun Tuli
5c83d5efb7 mb/google/rex: Add LP5 RAM IDs 
Create RAM IDs for:
DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B       0 (0000)
MT62F1G32D2DS-026 WT:B         1 (0001)
MT62F2G32D4DS-026 WT:B         2 (0010)

BUG=b:240289148
TEST=emerge-rex coreboot

Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ib24e07bca363984db3484aa500f7d6ea4817e517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-07-29 15:06:17 +00:00
Rex-BC Chen
d699de071f mb/google/geralt: Initialize RTC and clk_buf in romstage 
TEST=build pass.
BUG=b:233720142

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I869c0879d09e00cf66882adb728c9ccb6ac57e03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66183
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-07-29 15:05:14 +00:00
Subrata Banik
8a039031dd mb/google/rex: Enable CNVi BT Core 
This patch override `CnviBtCore` FSP UPD.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I90c9b360969aada0b0e031d62b48476fac5cee0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-29 15:03:01 +00:00
Eric Lai
ff424fbe6b mb/google/brya/var/ghost: Enable CS42L42 codec 
Add CS42L42 support in device tree.

BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=Check cs42l42 driver can probe successfully in kernel.
cs42l42 i2c-10134242:00: Cirrus Logic CS42L42, Revision: B1

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I861f47c12f4cebb016a4cfbe225f97d34d55e233
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
 2022-07-29 15:02:35 +00:00
Eric Lai
e5a9cdc615 mb/google/brya/var/ghost: Update all I2C buses speed to fast 
Remove the parameter and set I2C bus speed to fast. Will fill the
tuning value after real tuning.

BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=build passed.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Iba7fe4551959617ecfa49719c1124bf85d624c31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
 2022-07-29 15:02:24 +00:00
Raymond Chung
e59c5f8f06 mb/google/brya: Create gaelin variant 
Create the gaelin variant of the brask reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:239514438
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_GAELIN

Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Change-Id: I7f1ff8690c7c57f8960e004d0490d5cede8667f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
 2022-07-29 15:02:05 +00:00
Shon Wang
38777e5cc2 mb/google/dedede/var/drawcia: Enable weida touchscreen 
Add weida touchscreen support for drawcia.

BRANCH=dedede
TEST=Build and verify that touchscreen works on drawcia.

Change-Id: Ic76f3529771c6eeeafef7ca50fc400065aac2211
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65471
Reviewed-by: Ivan Chen <yulunchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2022-07-29 15:00:26 +00:00
Mark Hsieh
f84f3e7451 mb/google/nissa/var/joxer: Correct i2c address for touchscreen 
set i2c address to 0x14 for Goodix touchscreen

BUG=b:239180430
TEST=USE="project_joxer emerge-nissa coreboot"

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I11a2d9c684bc511b3942f88f74a2495e796bc3c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
 2022-07-28 23:25:17 +00:00
Tim Wawrzynczak
5625dace84 mb/google/brya/acpi: Add L23 entry/exit sequences during dGPU GCOFF 
When the dGPU is entering GCOFF, the link should first be placed into
L2/L3 as appropriate for the design, then when exiting, the link should
be placed back into L0. This patch fixes that oversight.

BUG=b:239719056
TEST=build

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia3bdfe5641216675e06ebe82ffe58bf8c049b26b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-07-28 20:02:56 +00:00
Tim Wawrzynczak
460fea6523 mb/google/brya/var/agah: Modify GPP_A8 programming 
The EEs noticed this pin was misbehaving; it was accidentally set to a
low output, but should be open-drain (NC). This patch fixes that.

BUG=b:237837108
TEST=verified by EEs

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie76a951320c49b9fbc1f23b96f04c9f86ad44d42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-07-28 20:02:53 +00:00
Tim Wawrzynczak
86b517f88e mb/google/brya/var/agah: Modify GPP_F14 programming 
For some yet unknown reason, when this GPIO is locked, there is an
interrupt storm for IRQ #9 apparently caused by GPE 0x66. GPP_F14 is set
to GPE 0x64 on the ADL platform, so this doesn't quite make sense. This
patch removes the lock and fixes this IRQ storm, but the root cause is
not identified yet.

BUG=b:236997604
TEST=`grep ' 9:' /proc/interrupts` shows a reasonable value now

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I3d1c66fac80a173798ae33e48b1776d9f4fb5eaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-07-28 20:02:45 +00:00
Tim Wawrzynczak
17d71937a1 mb/google/brya/var/agah: Optimize dGPU GCOFF entry 
After staring at lots of scope shots, the EE has determined that a few
modifications to the GCOFF sequence can be made:

 - Remove delay between PERST# assertion and GPU_ALLRAILS_PG deassertion
 - Remove delay after ramping down FBVDD

This patch implements these minor changes.

BUG=b:240199017
TEST=verified by EE

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7d492b3e65a231bc5f64fe9c3add60b5e72eb072
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-07-28 20:02:42 +00:00
Tim Wawrzynczak
1523742d4c mb/google/brya/var/agah: Update ASPM settings for dGPU 
After some debugging, it has been determined that the ASPM L0s substate
is functional, but there is still some problem with ASPM L1 substates,
so this patch updates ASPM status for the dGPU from disabled to L0s
only.

BUG=b:240390998
TEST=tested with nvidia tools

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I584bdbf26eda20246034263446492bf4daf5f3b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-07-28 20:02:24 +00:00
Wisley Chen
05f0e3fe86 mb/google/brya/var/anahera{4es}: Add H54G68CYRBX248 support 
Generate SPD id for hynix H54G68CYRBX248

BUG=b:239899929
BRANCH=firmware-brya-14505.B
TEST=run part_id_gen to generate SPD id

Change-Id: I96babe340678ca9b82b06d3193b93a7676f23fef
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-07-28 20:00:25 +00:00
Wisley Chen
ec61d7a776 mb/google/brya/var/redrix{4es}: Add H54G68CYRBX248 support 
Generate SPD id for Hynix H54G68CYRBX248

BUG=b:239888704
BRANCH=firmware-brya-14505.B
TEST=run part_id_gen to generate SPD id

Change-Id: I9412b988bcdb0c744e016f3add6dacda8185d6db
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-07-28 20:00:14 +00:00
Eric Lai
9473154497 mb/google/brya/var/ghost: Correct CNVi pins 
GPP_F0 to GPP_F4 is for CNVi and should be NF1.
GPP_F5 is for CNVi CLK_REQ, and should be NF3 CRF_XTAL_CLKREQ.

BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=CNVi wifi can get probed in kernel.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ice3fde3a457f6f5c058c0a7d3ca2e63775bda96c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
 2022-07-28 19:59:54 +00:00
Yunlong Jia
ccbf27cbe7 google/trogdor: Add new variant Pazquel360 
This patch adds a new variant called Pazquel360 \
that is identical to Pazquel for now.

BUG=b:239987191
TEST=make

Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I0a9ca4a59fb44256d0d8fcdbdf2a7db533c84412
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Bob Moragues <moragues@google.com>
 2022-07-28 14:53:29 +00:00
Tarun Tuli
646802c598 mb/google/rex: Initial setup for ramstage/early gpio config 
This adds the initial gpio configuration for the rex initial variant.

BUG=b:238165977
TEST=Boots and no errors on simics

Change-Id: I55ab31c7943e22df9cec8db4a9f0c3ab6f065ae1
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65952
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-28 11:14:01 +00:00
Franklin Lin
573fa36c3a mb/google/brya/crota: Remove MAC address passthru support 
ChromeOS connection manager (shill) already
has support for dock MAC address passthrough, therefore remove the
code to pass a dock's MAC address in ACPI.

BUG=b:235045188
TEST=build coreboot

Signed-off-by: Franklin Lin <franklin_lin@wistron.corp-partner.google.com>
Change-Id: I78320a7c6b0fd5392e24b63bff234229a3f4b9bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66040
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-07-27 13:41:06 +00:00
Eric Lai
c1b01ea9f5 mb/google/brya/var/ghost: Update memory DQ map 
Follow latest schematic 6/27 to update the DQ map.

BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=build passed.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I8d0de04a001cab53a245185707ebc9da7a501ec4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66122
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
 2022-07-27 13:40:50 +00:00
Tyler Wang
238c199c79 mb/google/nissa/var/craask: Add DPTF passive and critical policies 
Add critical, passive policy, and pl values from thermal team.

BUG=b:239495499
TEST=Build and test on MB, system can boot to OS.

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I8beb3b57ff56c6fe413bb0e3dd43d693aee08e36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66125
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
 2022-07-27 13:39:43 +00:00
Leo Chou
f92ea61e84 mb/google/nissa/var/pujjo: Enable PCIe port 4 for WLAN 
Pujjo support WLAN device, enable PCIe port 4 for WLAN device

BUG=b:239899932
TEST=Build and boot on pujjo

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ic8b7240941cf87a4f27963d50fffe28875114a81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66073
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-07-27 13:37:23 +00:00
Yu-Ping Wu
7b7250dfae mb/google/cherry: Introduce mainboard_needs_pcie_init 
Implement mainboard_needs_pcie_init() for cherry as a callback for
mt8195 SoC to determine whether to initialize PCIe. When the SKU id is
unknown or unprovisioned (for example at the beginning of the factory
flow), we should still initialize PCIe. Otherwise the devices with NVMe
will fail to boot.

BUG=b:238850212
TEST=emerge-cherry coreboot
BRANCH=cherry

Change-Id: I2ed0ceeb37d2924ca16485fb2d130959a7eff102
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
 2022-07-27 12:59:59 +00:00
David Wu
df721bd0c3 mb/google/brask/var/kuldax: correct Type-A USB3 port0/1 tx_de_emp 
1. Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2 RX
   signal integrity issue.
2. Disable unused USB port.

BUG=b:238230292
TEST=build FW and check Type-A USB3 port0/port1 RX pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I8356ca30a965e5774a1556c5cb81e1586c55496c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-07-26 20:36:31 +00:00
Reka Norman
1411ecf6f0 mb/google/nissa/var/joxer: Configure descriptor for eMMC or UFS 
Joxer will have both eMMC and UFS SKUs, which require different
settings in the descriptor. So update the descriptor at run-time based
on fw_config.

By default, the descriptor is configured for UFS. This configuration
still boots fine on eMMC SKUs, it just might cause problems with S0ix.

This is a temporary workaround. It will be removed once we've
implemented a proper solution for configuring the descriptor differently
for different SKUs.

BUG=b:238234376
TEST=Make an identical change for nivviks. On both nivviks (eMMC) and
nirwen (UFS), check that it boots and that the logs show the descriptor
being configured as expected.

Change-Id: I14232eb773936f2ecd183687208d332136935601
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
 2022-07-26 12:42:24 +00:00
Kapil Porwal
b1c9f7fd12 mb/google/rex: Set GPIO Tier-1 GPEs in devicetree 
Set GPE route as
GPE0_DW0 -> GPP_A
GPE0_DW1 -> GPP_E
GPE0_DW2 -> GPP_F

BUG=b:224325352
TEST=Verified in emulator that there is no regression

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I5e3e09cfc06d2556ea32cca23b3dae114a510498
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-25 21:15:32 +00:00
Subrata Banik
8795c42d29 mb/google/rex: Override LP5 CCC config 
This patch overrides `Lp5CccConfig` UPD as per the CCC mapping data
captured from the Rex schematics dated 07/16.

BUG=b:224325352
TEST=Able to build Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia1d9e3665cff74a803e730c76f62773996efb3dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66049
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-07-25 15:30:22 +00:00
Sean Rhodes
5f40fc61c6 mb/starlabs/lite: Add support for VBOOT 
Add the required files to support VBOOT for when it is enabled.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I083107b21c23f42193fc88aa174ec22850f45bc8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65705
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
 2022-07-25 10:07:03 +00:00
Leo Chou
4b31af493d mb/google/nissa/var/pujjo: Add new supported memory part 
Add pujjo new supported memory parts in mem_parts_used.txt.
Generate SPD id for this part.

Micron MT62F1G32D4DR-031 WT:B

BUG=b:239776504
TEST=Use part_id_gen to generate related settings

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I95eb194ecbd5d39f66eb566132e75af056899325
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66039
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
 2022-07-25 01:03:52 +00:00
Subrata Banik
471e24e987 mb/google/rex: Add memory configuration board straps 
This patch reads various memory configuration GPIOs to fill in below
details:
1. variant_memory_sku()
2. variant_is_half_populated()

BUG=b:224325352
TEST=Able to build Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I23bad8c78523cb56008e6d67e7776e57e42fbeb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
 2022-07-25 01:01:19 +00:00
Felix Singer
c5f7055746 mb/lenovo: Integrate W541 into haswell mainboard 
Lots of code from lenovo/haswell can be reused for lenovo/w541. Thus,
integrate it into lenovo/haswell and make it a variant.

Change-Id: If99d842cff777fe27ff63baabc447e69b9d0333c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2022-07-24 22:24:49 +00:00
Felix Singer
b5bdd70758 mb/lenovo/haswell: Make INT15 support T440p specific 
In preparation to CB:63514, make the INT15 support specific for the
T440p variant since the W541 doesn't support it currently.

Change-Id: I8dfcc061e1b8a831f75bf9a8035770cb678a85d4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66106
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-07-24 22:24:24 +00:00
Felix Singer
104b7db894 mb/lenovo/haswell: Hook up variants Makefile 
Change-Id: I36091118d98f71dc4141aca4e45858a22d519a9b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-07-24 22:24:13 +00:00
Subrata Banik
684d00db4b mb/google/rex: Add GBB related configs 
This patch adds more GBB related configs. Select
`HAS_RECOVERY_MRC_CACHE` config.

Additionally, move VBOOT_LID_SWITCH config under VBOOT config.

TEST=Able to build the Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I28976200cbd70dc23f58868ee89c0ac700793be9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66007
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
 2022-07-23 20:25:04 +00:00
Nick Vaccaro
f0198b65dc mb/google/brya/var/skolas4es: Correct _PLD values 
This patch is to denote the correct value of ACPI _PLD for USB ports.

       +----------------+
       |                |
       |     Screen     |
       |                |
       +----------------+
    C2 |                | A0
    C0 | MLB         DB | C1
       |                |
       +----------------+

BUG=b:216490477
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot

Change-Id: I96202b9ac9586975e960d6577d279c995c67f34e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66031
Reviewed-by: Won Chung <wonchung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-07-23 20:23:43 +00:00