sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
31,192 Commits 47 Branches 30 Tags
c8600c36d7cbda8a8bbfeee63a7fa7e10779cd98
Commit Graph

31192 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Jeremy Soller
c8600c36d7 Merge remote-tracking branch 'upstream/master' into system75 2019-11-04 09:01:17 -07:00
Elyes HAOUAS
1644e48985 sb/intel: Use defined CONFIG_HPET_ADDRESS 
Change-Id: I15ae5e70ba351e89d5ea9d04dbb1efdfbb372bba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-11-04 13:19:42 +00:00
Elyes HAOUAS
4ec67fc82c nb/intel: Use defined DEFAULT_RCBA 
Change-Id: I166dd3edb50699dfca7b60b83cfcae996ced90dc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-11-04 13:13:13 +00:00
Patrick Rudolph
728a06032d soc/intel: Remove unused code 
Delete acpi_create_intel_hpet() which has been replaced
by acpi_write_hpet() in the corresponding soc folders
some time ago.

Change-Id: I788c9ef27cdc575eb8467cbef64ee52f4053e197
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Guckian
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-11-04 12:00:11 +00:00
Patrick Rudolph
b1ef725f39 cpu/qemu-x86: Add x86_64 bootblock support 
Add support for x86_64 bootblock on qemu.

Introduce a new approach to long mode support. The previous patch set
generated page tables at runtime and placed them in heap. The new
approach places the page tables in memory mapped ROM.

Introduce a new tool called pgtblgen that creates x86 long mode compatible
page tables and writes those to a file. The file is included into the CBFS
and placed at a predefined offset.

Add assembly code to load the page tables, based on a Kconfig symbol and
enter long in bootblock.

The code can be easily ported to real hardware bootblock.

Tested on qemu q35.

Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2019-11-04 11:58:58 +00:00
Elyes HAOUAS
6f7c955464 nb/intel/nehalem: Fix 'dead assignment' 
Dead increment spotted out using clang-tools.
Value stored to 'some_delay_3_halfcycles' is never read.

Change-Id: I8133f9e8786006bd278d281a132b6a2bd863a967
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-11-04 11:57:06 +00:00
Marty E. Plummer
20994a763b cbfs: read header offset as explicitly LE 
le32_to_cpu spits out uint32_t on BE targets, cast it.

Change-Id: Idc99b0c133faa2aa15d06f998e7371d332ffa490
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2019-11-04 11:56:04 +00:00
Jamie Chen
ce6f1a53e9 mb/google/hatch: update DLL values for Kindred 
Update emmc DLL values for Kindred

BUG=b:131401116
BRANCH=none
TEST=Boot to OS 100 times on Kindred EVT

Change-Id: Ibd840b31bb0e5a742495758de55b532e6c3946aa
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
 2019-11-04 11:55:24 +00:00
Arthur Heymans
9c0afe6e6b soc/intel/broadwell: Use sb/intel/common/acpi/platform.asl 
Change-Id: I6d8d04289254317af8d7cc55c89431d408414384
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-11-04 11:48:34 +00:00
Arthur Heymans
b9b79d2589 mb/*/*/others: Use sb/intel/common/acpi/platform.asl 
Change-Id: Iabfd680fdb50534e6b9f6cfdecda9f8de0f8a610
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-11-04 11:48:19 +00:00
Arthur Heymans
cf819ea654 soc/intel/{braswell,baytrail}: Use sb/common/intel/platform.asl 
Change-Id: I64a27cb080838c986a12a40c80d0c91824b9d04c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-11-04 11:47:13 +00:00
Arthur Heymans
72c483a95a sb/intel/lynxpoint: Use sb/intel/common/platform.asl 
Change-Id: I86260a374a3f60f16dc73573e7989f0a4ffec818
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-11-04 11:46:42 +00:00
Arthur Heymans
2f9a0cdfa6 mb/*/*{i82801gx}: Use sb/intel/common/acpi/platform.asl 
Change-Id: Ifc0799d26394a525d764fb4ffc096b48060ee22f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2019-11-04 11:45:58 +00:00
Yu-Ping Wu
816326576a include: Remove EC_EVENT_* from elog.h 
All of the EC_EVENT_* macros can be replaced with the EC_HOST_EVENT_*
macros defined in ec_commands.h, which is synchronized from Chromium OS
ec repository.

BRANCH=none
BUG=none
TEST=emerge-kukui coreboot

Change-Id: I12c7101866d8365b87a6483a160187cc9526010a
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2019-11-04 11:43:49 +00:00
Michael Niewöhner
ab0d687fc5 mb/supermicro/x11-lga1151-series: drop console guard in bootblock 
To make debugging possible in a fallback setup, the serial console must
be set up in bootblock, thus drop the guard.

Change-Id: If0dd3c03ba52b4936eb234e6b2b61bb5ce044fcd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36602
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-04 11:43:10 +00:00
Michael Niewöhner
403b70adb9 mb/supermicro/x11-lga1151-series: use new console delay Kconfig option 
This replaces the hardcoded delay by the new Kconfig option.

Change-Id: I8bf4ef7ad9beea7b3dc22e1567623a423597eff9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2019-11-04 11:42:42 +00:00
Michael Niewöhner
4d877c8c7f superio/aspeed/common: add workaround for serial routing delay quirk 
Some mainboards with an ASPEED BMC do the serial routing setup in the
BMC boot phase on cold boot. This results in scrambled console output
when this is not finished fast enough.

This adds a delay of 500ms as workaround in the BMCs uart setup that
can be selected at mainboard level.

A user may disable the workaround when using another BMC firmware like
OpenBMC, u-bmc or some custom BMC bootloader with fast serial setup.

Change-Id: I7d6599b76384fc94a00a9cfc1794ebfe34863ff9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36591
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-04 11:42:29 +00:00
Arthur Heymans
a1b700ff74 arch/mips: Pass cbmem_top to ramstage via calling argument 
This allows to use a common cbmem_top implementation.

Change-Id: I85efe3899607854c36d0ec594868f690eb724a7f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-11-04 11:40:25 +00:00
Arthur Heymans
879c9fc421 soc/nvidia/tegra210: Populate _cbmem_top_ptr 
On this platform the ramstage is run on a different core so passing
cbmem_top via calling arguments is not an option. To work around this
populate _cbmem_top_ptr with cbmem_top_chipset which is also used in
romstage.

Change-Id: I8799c12705e944162c05fb7225ae21d32a2a882b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36557
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-04 11:40:12 +00:00
Arthur Heymans
a09d33ec88 arch/ppc64: Pass cbmem_top to ramstage via calling argument 
This avoids the need for a platform specific implementation of
cbmem_top.

HOW TO TEST? There is no serial console for the qemu target...

Change-Id: I68aa09a46786eba37c009c5f08642445805b08eb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-11-04 11:39:25 +00:00
Kyösti Mälkki
bc78e014c5 cpu/intel/car/p4-netburst: Remove delay loops 
While commented as 10 ms + 250 us, those delay loops actually
accounted for a total of 840 ms. And they seem unnecessary
as followup code has potentially infinite retries when
polling for status changes.

Tested on aopen/dxplplusu, dual-socket P4 Xeon HT model_f2x.

Change-Id: Ib7d1d66ed29c62d97073872f0b7809d719ac2324
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2019-11-04 11:38:38 +00:00
Arthur Heymans
a751eec799 cpu/intel/em64t101: Add Nehalem to compatibility list 
Change-Id: I15a1c824b92e18f9963c60659ead92c988d1239b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-11-04 11:37:54 +00:00
Arthur Heymans
f6a8c5a493 cpu/intel/smm/gen1: Deal with SMM save state compatibility 
Change-Id: I92326e3e0481d750cb9c90f717ed748000e33ad3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-11-04 11:37:42 +00:00
Arthur Heymans
228f004f76 mb/*/*{i82801ix}: Use sb/intel/common/acpi/platform.asl 
Change-Id: I9150db163131d4c3f99a4e0b6922a61c96a6d6e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-11-04 11:36:50 +00:00
Arthur Heymans
6c13b0427a mb/*/*{bd82x6x/ibexpreak}: Use sb/intel/common/acpi/platform.asl 
Change-Id: I36095422559e6c160aa57f8907944faa4c192dee
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-11-04 11:36:39 +00:00
Arthur Heymans
8195aa02f9 sb/intel/common/platform.asl: Remove setting unused GNVS 
Change-Id: I842af0a0e6435d33759649065b2b5a6f6d35071d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-11-04 11:36:25 +00:00
Arthur Heymans
a0365c5809 sb/intel/i82801jx/nvs.h: include required header 
u8, u16, ... are defined in stdint.h.

Change-Id: I045438a7e754d4da936cf2ded411d055f2f69b45
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36556
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-04 11:35:35 +00:00
Arthur Heymans
6190d0bfe6 nb/intel/x4x/x4x.h: Include iomap.h 
This is needed for the definition of the MCHBARx() macros.

Change-Id: I654344451c0568f306f39365fd07371b2d6cff04
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36555
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-04 11:35:25 +00:00
Elyes HAOUAS
085ab5a347 sb/intel: Move 'smbus.asl' to common place 
Change-Id: Ia5b148c54224269bda98afe7c8a2c22c10a3bf56
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Guckian
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2019-11-04 11:35:16 +00:00
Arthur Heymans
ca64305152 nb/intel/gm45: Build test with VBOOT 
Change-Id: I21d20d7c575833ace02b4b8ed9d5c82750b331c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-11-04 11:34:59 +00:00
Arthur Heymans
41f826a498 mb/lenovo/{x200,t400}: Add VBOOT support 
Tested on thinkpad X200 with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW
selected, the RW_A slot is properly selected unless the FN button is
pressed. 600+ms are spend waiting for the EC to be ready.

Change-Id: I689fe310e5b828f2e68fcbe9afd582f35738ed1d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35998
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-04 11:34:53 +00:00
Kyösti Mälkki
334211e4a6 Documentation: Add some significant 4.11 release notes 
Change-Id: I44369bc7dee77beab480d9a16cd7268be6686eb9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
 2019-11-04 11:34:29 +00:00
Eric Lai
5407571168 mb/google/drallion: Update GPIO table 
Follow latest GPIO table to change gpio.

BUG=b:143728355
BRANCH=N/A
TEST=build pass

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iee61c74a5cab5a62a90c0543f212650c4f2420de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
 2019-11-04 11:33:44 +00:00
Eric Lai
3d4f51ef69 mb/google/drallion: Correct GPP_E7 as stop pin 
Current design reset pin is connected to PLTRST.
GPP_E7 is stop pin for touch. Reserve reset pin for
next stage implement.

BUG=b:143733039
BRANCH=N/A
TEST=check touch screen can work properly

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3ebd56ab49b87da425583da04f082e69293a023e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
 2019-11-04 11:33:32 +00:00
Eric Lai
1845fc8947 mb/google/drallion: fix GPP_E16 glitch when enter S5 
Set GPP_E16 reset to DEEP.

BUG=b:143057255
BRANCH=N/A
TEST=Measure GPP_E16 from S0 to S5 has no glitch

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I63932c6f5c8b7e6e9ab8aa55e69c629d29e7d1fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36511
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-04 11:33:23 +00:00
Michael Niewöhner
e979442cd6 payloads/external/GRUB2: fix constantly rebuilding due to git checkout 
Multiple git checkouts cause GRUB2 to constantly rebuild even if there
were no changes to code or config. This is due to changing timestamps.

Fix this by not creating or switching branches but instead rely on
`git checkout -f` which does not touch existing unchanged files.

To be sure to not break anyones workflow checkout is skipped and a
warning gets printed if the tree/index is unclean.

Change-Id: I7cf66f63268de973a654146a0a47c3d5ca516d4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36343
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-04 11:33:17 +00:00
Wim Vervoorn
653a66fa81 vendorcode/eltan/security: Correct debug output 
Correct debug ouput in tpm2_get_capability_pcrs.

BUG=N/A
TEST=build

Change-Id: Ibd12c9dc22980f21ecba204729c5da0d11618e12
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36484
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-04 11:32:46 +00:00
Wim Vervoorn
d1fb78dbfc vendorcode/eltan/security: Address layout issues 
Corrected several layout issues in the mboot.c file.

BUG=N/A
TEST=build

Change-Id: I1599c7be075130345f018a08bede3eb849129a1c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
 2019-11-04 11:32:16 +00:00
Mathew King
be820b3911 smbios: Create a type for smbios_enclosure_type 
Add a name to the SMBIOS enclosure type enum and use it as the return
type for smbios_mainboard_enclosure_type.

BUG=b:143701965
TEST=compiles

Change-Id: I816e17f0de2b0c119ddab638e57b0652f53f5b61
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36516
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-04 11:31:12 +00:00
Elyes HAOUAS
f91c0f9935 arch/x86/Kconfig: drop unused BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP 
Change-Id: I199a4b7771192abf7e7489e84db43b04776dd7b2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36509
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-04 11:31:04 +00:00
Wim Vervoorn
944fdc4771 vendorcode/eltan/security: Use custom hash for little endian only 
Only use the custom hash routine when we need little endian.

Rename the function as well as it is little endian only now.

BUG=N/A
TEST=tested on fbg1701 board.

Change-Id: I037fa38c5961dab7a81e752c1685da2dc6b33d12
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
 2019-11-04 11:30:17 +00:00
Wim Vervoorn
adf344013d mb/facebook/fbg1701: Add logo to the menu 
Allow the user to enable and disable the logo from
make menuconfig. The file can be selected as well.

BUG=N/A
TEST=build

Change-Id: I630a9d14308131c180adaaa9e1fa5e6e11c3c61c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
 2019-11-04 11:30:06 +00:00
Wim Vervoorn
3cf40b68c0 vendorcode/eltan: Cleanup Kconfig files 
The vendorcode/eltan and vendorcode/eltan/security directories
were both adding the mboot and verified_boot Kconfigs.

BUG=N/A
TEST=build

Change-Id: I6b5f19b4660d60345391b7320ce42466fd2cc769
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36479
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-04 11:29:32 +00:00
Subrata Banik
55a2149903 soc/intel/icelake: Make use of "all-y" 
This patch makes use of "all-y" in order to replace all common stage (bootblock, verstage,
romstage, postcar, ramstage) files inclusion in Makefile.inc

Change-Id: I11001d0d381ec9c1df41bc331da845f51e666a44
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36546
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-04 08:20:39 +00:00
Subrata Banik
14d59912f8 soc/intel/icelake: Add alignment check for TSEG base and size 
This patch ensures to not set SMRR if TSEG base is not align with TSEG size

Change-Id: I77d1cb2fd287f45859cde37a564ea7c147d5633f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36542
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-04 08:20:28 +00:00
Subrata Banik
645f244fd0 soc/intel/icelake: Set DCACHE_BSP_STACK_SIZE default ~129KiB unconditionally 
Icelake default selects PLATFORM_USES_FSP2_1 which means stack will be shared
between FSP and coreboot (CONFIG_FSP_USES_CB_STACK) hence no need to have any
other default value than 129KiB (128KiB for FSP and 1KiB for coreboot)

Change-Id: I856f7e48a4a1e86eb082b9e772e0776664edca51
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36538
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-04 08:20:20 +00:00
Subrata Banik
319b096869 soc/intel/icelake: Remove unused headers 
This patch removes inclusion of unused headers from soc/intel/icelake

Change-Id: Icb653dee7992538aadf98d84adadd081f816fd01
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36536
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-04 08:20:11 +00:00
Subrata Banik
6c1b18090d soc/intel/icelake: Skip BIOS OpRom execution based on CONFIG_RUN_FSP_GOP 
This patch replaces BIOS OpRpm execution checks from CONFIG_INTEL_GMA_ADD_VBT
to CONFIG_RUN_FSP_GOP as adding VBT files doesn't mean GFX PEIM is going
to execute to initialize IGD.

Change-Id: Ic76529ba11f621f644d4472be6cbbc34682f00bf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2019-11-04 08:20:03 +00:00
Subrata Banik
522b7c0324 soc/intel/icelake: Clean up report_cpu_info() function 
This patch makes below clean up for report_cpu_info() function
1. Replace cpu_string with cpu_not_found
2. Assign default string "Platform info not available" to cpu_not_found string
3. Add array out of bound check while skiping leading white space in cpu brand
string name

Change-Id: I41c76eb93f0c5229c4a49aa041339b8ad51ad34a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36531
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-04 08:19:50 +00:00
Angel Pons
bda870242e cpu/x86/mtrr/xip_cache.c: Fix inconsistent message 
Change-Id: Ic99e61632664f86cc12507f2ddffa364fdd79202
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36585
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-03 20:48:18 +00:00