T Michael Turney
ff423f749a
sdm845: Add AOP firmware support
...
TEST=build & run
Change-Id: I9845c8638e4b905de5d6985dc9f1fddd8b1a8942
Signed-off-by: T Michael Turney <mturney@codeaurora.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25210
Reviewed-by: Julius Werner <jwerner@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-07-11 15:08:38 +00:00
Frank_Chu
125b48d1d5
mb/google/hatch/variants: Fix nonworking touch pad
...
Correct ELAN Touch pad IRQ GPIO to GPP_A21
BUG=b:135507215
BRANCH=none
TEST=emerge-hatch coreboot chromeos-ec chromeos-bootimage
Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com >
Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33954
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-07-11 15:05:47 +00:00
Tim Wawrzynczak
c5651568ea
mb/google/hatch: Enable/disable GPIO clock gating
...
Before the system enters S0ix or S3, each GPIO community
will have its dynamic clock gating turned on. Upon return
to S0, the dynamic clock gating will be turned back off.
BUG=b:130764684
BRANCH=none
TEST=Used dut-power to verify that the clock gating is enabled
in S0ix and S3. Also used Store(..., Debug) statements in the
ASL code to verify it was getting called.
Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2019-07-11 15:03:09 +00:00
Tim Wawrzynczak
a17242577a
soc/intel/cannonlake: Add GPID and CGPM methods to GPIO ASL
...
The GPID method returns the PCR Port ID of the given GPIO community.
The CGPM method alters the given GPIO community's PM bits, given in
Arg1.
Change-Id: I098ee08573eb4f8a45d9b5ae84f2d85ce525c9b8
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2019-07-11 15:02:43 +00:00
Tim Wawrzynczak
69d73e4d75
soc/intel/intelblocks/gpio: Always expose GPIO PM constants
...
These constants are needed in some ASL files, even when
__ACPI__ is defined.
Change-Id: I0f4f00b93d5d45794b7c9e0f72b51f3191eb3902
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34177
Reviewed-by: Lance Zhao <lance.zhao@gmail.com >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-07-11 15:02:18 +00:00
Tim Wawrzynczak
489c722dcc
mb/google/hatch: Enable LPIT inclusion in DSDT
...
Include the lpit.asl file in Hatch's DSDT definition.
BUG=b:130764684
BRANCH=none
TEST=S3 suspend/resume and S0ix entry/exit work correctly.
Ran > 200 iterations of suspend_stress_test and no issues found.
Change-Id: If8ebff3db091257e8452869636c0e024f3123e8b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
2019-07-11 15:01:59 +00:00
Tim Wawrzynczak
145748bf25
mb/google/hatch: Disable GPIO community dynamic clock gating
...
The dynamic clock gating is causing boards to miss interrupts
whose pulses are shorter than 4us. Disable it using FSP UPDs.
BUG=b:130764684
BRANCH=none
TEST=Compiles
Change-Id: I8f1ec8f7c31192bce2a761ec99b86638435dc27c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Evan Green <evgreen@chromium.org >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
2019-07-11 15:01:41 +00:00
Tim Wawrzynczak
20cfc87ca0
soc/intel/cannonlake: Make EC S0ix notification optional in LPIT
...
Only call the \_SB.PCI0.LPCB.EC0.S0IX method if it exists.
Change-Id: Idf465f8ad7cb016f3ad3d9710b46e35f66f8939b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com >
Reviewed-by: Duncan Laurie <dlaurie@chromium.org >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
2019-07-11 15:01:24 +00:00
Lean Sheng Tan
565b0aada9
mb/intel/coffeelake_rvp: Add cpu count for CFL S62
...
Increases CPU max core count to 16 for coffeelake Refresh-S Platform.
TEST: boot to linux OS on CFL-S refresh Intel RVP and verified the output
of cat /proc/cpuinfo shows no of processor=16.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com >
Change-Id: I579ff6ae8227844741406c503d3994408ec2b617
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34156
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-07-11 15:00:49 +00:00
John Zhao
1ceac4efcf
soc/intel/common: Check bios_size and window_size after MIN operation
...
Clang Static Analyzer version 8.0.0 detects that the result of
log2_ceil(bios_size) and log2_ceil(window_size) is undefined if the
value of bios_size and window_size are negative. Add negative value
Check for bios_size and window_size after MIN operation.
Change-Id: I28577b6e0ba0ab45bb7804c17ba1f26c4b078b15
Signed-off-by: John Zhao <john.zhao@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martinroth@google.com >
2019-07-11 15:00:13 +00:00
Furquan Shaikh
b8501c7c5f
mb/google/hatch: Fix interrupt trigger type for GPP_H0(HP_INT_L)
...
HP_INT_L(GPP_H0) is configured for GPIO IRQ instead of APIC IRQ since
it needs to trigger on both edges. With GPIO IRQ, it is necessary to
configure the trigger type in coreboot to match the ACPI
configuration. This is because:
1. ACPI configuration is used by intel-pinctrl driver in Linux kernel
to re-configure the trigger type for the pad in GPIO DW0 config
register. This is done when kernel driver probes and requests irq for
its device.
2. On resume from S3, the pad configuration gets reset and coreboot
sets the trigger type to LEVEL. However, kernel driver does not probe
again. This results in the trigger type being configured incorrectly.
This change updates the GPIO configuration for GPP_H0 to set the same
trigger type as advertised in ACPI for the kernel.
BUG=b:132672011
TEST=Verified that S3 works fine. Verified that interrupt on GPP_H0
works fine on boot as well as after suspend/resume.
Change-Id: Ieb44c7403a2f4911b4a8f422053dee8bcfb91d85
Signed-off-by: Furquan Shaikh <furquan@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34181
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-07-11 06:01:15 +00:00
Subrata Banik
10a9432cc2
soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timer
...
This patch moves USE_LEGACY_8254_TIMER Kconfig into common/block/timer
for better code sharing. Also ported CB:33512 for SPT and ICP PCH.
Change-Id: Ic767ff97aaa3eb7fa35ffa38fa416d006eaa6e78
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2019-07-11 05:57:41 +00:00
Jacob Garber
5b9948140f
console: Correct printing of hexadecimal integers
...
Commit b19946cc62jgarber1@ualberta.ca >
Found-by: Coverity CID 1402999
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Julius Werner <jwerner@chromium.org >
2019-07-10 20:22:40 +00:00
Jacob Garber
15947182fd
sb/nvidia/ck804: Remove old debugging code
...
These printk() statements were added in commit cdc526e582jgarber1@ualberta.ca >
Found-by: Coverity CID 137058{1,3}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33459
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-07-10 18:23:11 +00:00
Frans Hendriks
509f46953e
drivers/intel/fsp1_1/raminit.c: Always check FSP HOBs
...
Check for FSP HOBs is depending on CONFIG_DISPLAY_HOBS.
Use the CONFIG_DISPLAY_HOBS for display HOB info only and always check HOBs.
Use BIOS_ERR of printk() for FSP errors.
BUG=N/A
TEST=Check console output on Facebook FBG1701.
Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2019-07-10 10:24:12 +00:00
Marshall Dawson
71c6c1725e
arch/cpu/x86: Update AMD detection
...
AMD Picasso, and later, will not use CPU_AMD_AGESA or CPU_AMD_PI.
Those two symbols indicate an Arch2008 system. Add SOC_AMD_COMMON
to cause cpu_is_amd() to return TRUE on Picasso.
This removes an error message of "Unknown CPU".
The patch also assumes AMD Family 10h and non-AGESA Family 15h
devices were seeing the "Unknown CPU" message. No functionality
has been verified on these devices.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Change-Id: I3357606c37082f3587ff91924bf7a0e0f8af9625
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34146
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-07-10 10:20:30 +00:00
Kevin Chiu
808440e6b2
mb/google/octopus: Remove LPDDR4 RAMID index 5,6 CH[1] only SKU
...
From Intel EDS: Table 3-5. LPDDR4 Configurations
CH00 CH01 CH10 CH11
"x32 BGA" "x32 BGA" "x32 BGA" "x32 BGA"
"x32 BGA" "x32 BGA" "Unpopulated" "Unpopulated"
CH[1](CH10/CH11) can't use alone without CH[0]
BUG=b:135498646,b:136694293
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Change-Id: I03af74301aad3e688c97992b37c59b20a4fff58a
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34069
Reviewed-by: Justin TerAvest <teravest@chromium.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-07-10 10:20:00 +00:00
Elyes HAOUAS
ad1456f0d7
vendorcode/amd: Move 'static' to the beginning of declaration
...
Change-Id: Ib9934f103262c57af076bd27d97c3166d8f2318b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martinroth@google.com >
2019-07-10 10:18:37 +00:00
Jacob Garber
975a7e3ba3
nb/intel/nehalem: Tidy quickpath_reserved calculation
...
- Remove unnecessary braces
- Move variable assignment out of function call
- Do not find lowest bit set of 0, which is undefined
- Use unsigned integer when bit shifting
Change-Id: I8651f8cd04165d8d31c44f7919ad5e43499d3d4c
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca >
Found-by: Coverity CID 1229562
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2019-07-10 10:15:51 +00:00
Jacob Garber
64fb4a32e0
nb/intel/nehalem: Die if no memory ranks found
...
Die if there are no memory ranks found to prevent a division by zero.
Change-Id: I6146dd8420f3734d1a672a9f29a098f47fcb739c
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca >
Found-by: Coverity CID 1229628
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2019-07-10 10:15:26 +00:00
Arthur Heymans
b3af349284
soc/intel/block/cpu: remove unused USE_COREBOOT_NATIVE_MP_INIT
...
Only CONFIG_USE_INTEL_FSP_MP_INIT makes a difference whether native MP
init is used or not.
Also make USE_INTEL_FSP_MP_INIT mutually exclusive with
USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI as this option requires
coreboot to set up AP and publish PPI based on it.
Change-Id: I65b80805d3cd7b66f8c9f878d3c741b98f24288d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33357
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-07-10 10:14:39 +00:00
Frans Hendriks
bd4ad6e630
vendorcode/eltan/security/lib: Implement SHA endian function
...
digest from vb2_digest_bufer() does not contains the correct endian.
Create cb_sha_endian() which can convert the calculated digest into big endian
or little endian when required.
BUG=N/A
TEST=Created binary and verify logging on Facebok FBG-1701
Change-Id: If828bde54c79e836a5b05ff0447645d7e06e819a
Signed-off-by: Frans Hendriks <fhendriks@eltan.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com >
2019-07-10 10:13:42 +00:00
Frans Hendriks
6665da81ef
soc/intel/braswell/acpi/lpc.asl: Allocate used ROM size only
...
Fixed ROM area is allocated.
Reduce the ROM size using CONFIG_COREBOOT_ROMSIZE.
BUG=N/A
TEST=Facebook FBG-1701 booting Embedded Linux
Change-Id: I7a47bf2600f546271c5a65641d29f868ff2748bf
Signed-off-by: Frans Hendriks <fhendriks@eltan.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2019-07-10 10:13:03 +00:00
Kyösti Mälkki
0d9f4e9277
soc/intel: Drop some HAVE_SMI_HANDLER guards
...
The necessary conditionals are evaluated within
cpu/x86/Makefile.inc and there are no default
targets added unconditionally to build.
Change-Id: I694cccf6779551445b83659838749dff02aedece
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2019-07-10 09:24:15 +00:00
Kyösti Mälkki
fd10f773db
cpu/x86: Remove obsolete smm_init_completion()
...
This is not used together with PARALLEL_MP and SMM_TSEG.
Platforms with SMM_ASEG continue to have their local
implementation doing the same thing.
Change-Id: I13a2f164804330c93240bff7f048e0a162b3ae25
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34154
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-07-10 09:23:16 +00:00
Kyösti Mälkki
571b7b2118
intel/i82801ix: Rename smm_lock() prototype
...
This southbridge code may be built with either ASEG or TSEG.
Fix minor collision in namespaces.
Change-Id: I04f90fb308c280621a3037fee4bece1e5655480e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2019-07-10 09:21:32 +00:00
Kyösti Mälkki
eac7023f84
soc/intel: Remove invalid smm_relocate stubs
...
Remove the per-platform empty stubs, builds would
just fail as there is no equivalent conditional for
the smmrelocate.c file.
Change-Id: Ie11f307b7bc5415bfdba6a2c66aed01b70d9f0e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
2019-07-10 09:19:25 +00:00
Kyösti Mälkki
f08f266aa2
cpu/amd: Remove empty smm_lock()
...
Change-Id: I599d1d7e28f3a6439b04ef9bd38f671e1a876e92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2019-07-10 09:18:09 +00:00
Kyösti Mälkki
f94aed8773
device/oprom: Replace CONFIG() preprocessor statements
...
Change-Id: I7737b5f2a5c2598af68f2bca769232413f343a39
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Mike Banon <mikebdp2@gmail.com >
2019-07-10 08:24:13 +00:00
Kyösti Mälkki
8261d67ae7
device/oprom: Reduce indentation
...
Change-Id: Iadae9221f7ea549e91cdc501155de058c51a982c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Mike Banon <mikebdp2@gmail.com >
2019-07-10 08:23:38 +00:00
Kyösti Mälkki
b28b6b53cc
arch/x86: Flip HAVE_MONOTONIC_TIMER default
...
Change-Id: Id56139a3d0840684b13179821a77bc8ae28e05ae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2019-07-09 13:36:18 +00:00
Kyösti Mälkki
76c4386699
arch/non-x86: Flip HAVE_MONOTONIC_TIMER default
...
Also remove allwinner/a10 dummy monotonic_timer
implementation.
Change-Id: I9dfa9b92dc63375465e3bb87b73eeefad601c810
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2019-07-09 13:07:38 +00:00
Kyösti Mälkki
517546aaab
emulation/qemu-power8: Select CPU_QEMU_POWER8
...
Change-Id: I5fa6486e96cd81767225a3e1015341c0c89053d1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2019-07-09 13:03:52 +00:00
Kyösti Mälkki
8abf66e4e0
cpu/x86: Flip SMM_TSEG default
...
This is only a qualifier between TSEG and ASEG.
Change-Id: I8051df92d9014e3574f6e7d5b6f1d6677fe77c82
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2019-07-09 12:48:46 +00:00
Kyösti Mälkki
4d372c7353
cpu/x86: Declare SMM_ASEG
...
This is really an inverse of SMM_TSEG to flag
platforms that should potentially move away
from ASEG implementation.
Change-Id: I3b9007c55c75a59a9e6acc0a0e701300f7d21f87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2019-07-09 12:48:01 +00:00
Kyösti Mälkki
328d42f2d8
cpu/intel: Drop SMM_TSEG conditional
...
SMM_TSEG is a qualifier between TSEG and ASEG memory
region. ASEG is deprecated and not supported for
these CPUs in coreboot codebase.
Change-Id: I0602e04957a390473a2449e1c5ff951f9fdff73b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2019-07-09 12:45:48 +00:00
Kyösti Mälkki
8f076f2be8
soc/amd/stoneyridge,picasso: Switch SMM lock condition
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SMM_TSEG is a qualifier between TSEG and ASEG memory
region. ASEG is deprecated and not supported for
this platform in coreboot codebase.
The SMM lock should be set based on whether SMM is
installed or not, HAVE_SMI_HANDLER currently tells
that.
Change-Id: I9756f8a59ccfedd59d5b997b35313452dd0c4f46
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34127
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-07-09 12:44:39 +00:00
Kyösti Mälkki
60012ac64e
arch/x86: Replace some uses of SMM_TSEG
...
No reason why the files could not be used with ASEG.
Attempts to use malloc() from ASEG would still fail,
though, due the lack of heap.
Change-Id: Idf470ae84eb34c442e833925510b08d5314e7638
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34126
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-07-09 12:44:10 +00:00
Kyösti Mälkki
9265f89f4e
arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-class
...
Build of the entire smm-class is skipped if we have
HAVE_SMI_HANDLER=n.
Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Lance Zhao <lance.zhao@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-07-09 12:43:35 +00:00
Subrata Banik
cb587a2522
drivers/intel: Move FSP stage_cache implementation into common block
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Change-Id: Iebb6d698c236a95162b3c7eb07987483a293b50a
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2019-07-09 10:52:33 +00:00
Subrata Banik
df29d23ee3
soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.h
...
Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34085
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com >
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-07-09 10:52:19 +00:00
Arthur Heymans
a3121b0b2f
sb/intel/lynxpoint: Use common final SPI OPs setup
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Change-Id: I12e238b3a33c909103986822bd7398e1c3bac676
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2019-07-08 14:54:54 +00:00
Arthur Heymans
aadd1d0eaf
sb/intel/ibexpeak: Use common final SPI OPs setup
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This also removes the relevant RCBA replays the mainboard dir.
Change-Id: I75dd9d1bcd09d835f205a51c087d52ebb4e166f6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Thomas Heijligen <src@posteo.de >
2019-07-08 14:54:13 +00:00
Arthur Heymans
b429c5be15
sb/intel/i82801gx: Use common final SPI OPs setup
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Change-Id: I30f80c237bccf8dc350249fd12ca6c4559d23d4f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2019-07-08 14:53:32 +00:00
Arthur Heymans
92185e373e
sb/intel/common: Add a common interface to set final OPs settings
...
This adds a common place to set the final opprefix, optype and opmenu,
with a hook to override the opmenu.
Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2019-07-08 14:52:54 +00:00
Elyes HAOUAS
3fcea0dfad
cpu/x86/smm/smm_module_loader: Compare num_concurrent_stacks to size_t
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Spotted out using -Wconversion gcc warning option.
Change-Id: I11e4792804f0f7b5a7ce504c46654c1bff775c32
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
2019-07-08 14:51:49 +00:00
Elyes HAOUAS
cca6e00868
src/arch/x86/acpigen: Compare dev_states_count to size_t
...
Spotted out using -Wconversion gcc warning option.
Change-Id: Ib882cfa6d429fbfcab2b8132280182b427d510aa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33803
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-07-08 14:51:08 +00:00
Patrick Rudolph
fbdeb4af75
qemu-q35: die if started on wrong machine
...
The QEMU machine "PC" doesn't support MCFG.
Die after console init if the user selected the wrong qemu machine
and print a message to use the correct machine type.
Without this patch ramstage dies with non-helpful message:
"get_pbus: dev is NULL!"
Change-Id: I9d1b24176de971c5f827091bc5bc1bac8426f3f6
Signed-off-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
2019-07-08 14:50:12 +00:00
Kyösti Mälkki
26210fa040
intel/socket_mPGA604: Enable TSC_MONOTONIC_TIMER
...
Change-Id: I3ca2b7752905209e8db6b1dc74b930445676792e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2019-07-08 09:47:15 +00:00
Kyösti Mälkki
b14aedc3ad
intel/nehalem: Move TSC_MONOTONIC_TIMER
...
Change-Id: Ib7f2f7773d0eef5ac4e277b44ee9114aa6729527
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2019-07-08 09:46:57 +00:00
