This reverts commit 9f0e21a4da.
It should be allowed for i82801gx/early_init.c to have
#include <southbridge/intel/common/pmutil.h>
But there is a conflict:
src/southbridge/intel/common/pmutil.h:
#define TCO1_CNT 0x68
src/southbridge/intel/common/tco.h:
#define TCO1_CNT 0x08
Followup works resolve the difficulties around the offset
0x60 used for TCO register bank, tree-wide.
Change-Id: I827558a0e0ef1c4d1f866756df51cd1b2abfc7a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fix compilation issue due to enum macro redefinition by safeguarding
definitions with DISPLAY_FSP_VERSION_INFO_2 in SoC Kconfig.
Back-ported from commit f7e8adac7b ("edk2-stable202005: Update
MdePkg/Include/IndustryStandard/SmBios.h") to fix compilation issue due
to enum macro redefinition.
BUG=b:260183604
TEST=Verify MTL Rex0 build with the patch
and verify the version output prints no junk data.
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com>
Change-Id: Ibc65d05a8b4bd232b91184ff8cd52a20cd3538ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Enable NVMe GPIOs based on fw_config and add NVMe to devicetree.
Note, eMMC and NVMe are not probed in devicetree. On first boot in
factory, the device needs to boot with unprovisioned fw_config, so all
storage devices should be enabled when unprovisioned. Currently,
devicetree disables all probed devices when unprovisioned. If we want
eMMC and NVMe to be probed, support needs to be added for enabling
probed devices when unprovisioned.
BUG=b:259211172
TEST=Verified by ODM. On craask, LTE and WCAM still work. On craaskneto,
eMMC and NVMe SKUs can both boot.
Change-Id: I76a056cddff2246cfb5bb26ddbdfc333b49d9aaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69958
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch creates an API for CSE-Lite specific SKU to retrieve the
Write Protect (WP) information (`cse_log_ro_write_protection_info`)
like WP range and limit, if the region is write-protected or not etc.
BUG=none
TEST=Able to compile the cse_lite.c file for google/kano without
any error.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8f4b7880534ded5401b6f8d601ded88019c636c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69968
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
As for mainboard mc_ehl1, a hard real-time dependency is also required
for this mainboard. The L1 prefetcher on Elkhart Lake is too aggressive
which in the end leads to an increased number of cache misses. Disabling
the L1 prefetcher boosts up the performance (in some cases by more than
10 %) in this specific use case.
Change-Id: I07b27dd672533e693a6c2987d16f54333850760e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
`is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers, hence it
makes sense to have a unified name across different device drivers.
BUG=b:259716145
TEST=Verified that the _DSD object is still present in the SSDT.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I4e0829a76a193b0a1e1e0f2b7ce2119bb00dd696
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69937
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A previous CL ("Add missing ACPI device path names",
commit d22500f0c61f8c8e10d8f4a24e3e2bf031163c07) caused some errors
from the Kernel on Brya devices (see Tim's comment on patchset 8):
> ACPI Error: AE_NOT_FOUND, While resolving a named reference
> package element - \_SB_.PCI0.FSPI
FSPI is defined in src/soc/intel/alderlake/chipset.cb:
device pci 1f.5 alias fast_spi on end
This CL adds the corresponding FSPI device to the DSDT to prevent
the error mentioned above.
TEST=Built and tested on brya by verifying the error is gone.
BUG=b:231582182
Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69920
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On a 32-bit host, uintptr_t is defined as 'unsigned int' instead of
'unsigend long int' like on a 64-bit host. When cbfstool is built on a
32-bit host, the printk format specifier '%lx' expects a 'long int'
while new_addr is of type 'uintptr_t', aka 'unsigned int'.
This in the end leads to a build error.
To fix this and make it build on both, 32- and 64-bit hosts, use PRIxPTR
as the format specifier. This macro will be resolved at compile time in
the right way on both, 32- and 64-bit hosts.
Test=Build cbfstool on 32- and 64-bit hosts.
Change-Id: Ia917d2ed31778f3a29c0a6c7368f74c15319b099
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69682
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The current IPU ES entry value is always set to true for RPL and
kernel picks the ES version of the main IPU FW even for the production
bootloader but loading is not successful due to the authentication
failure.
On Raptor Lake silicon, the production binaries are backward
compatible with ES parts.
This change removes the IPU ES support ACPI entry since the
kernel needs to load the production IPU main firmware on both the
ES/QS parts.
BUG=b:258125833
TEST=Verify the Camera functionality by enabling the IPU secure mode
on RPL variants with both ES/QS silicon.
Signed-off-by: Jim Lai <jim.lai@intel.com>
Change-Id: I9fd8ea0dd6ffdb16961bb017ba4388bf99e4d5bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Perform a codec reset before configuring to avoid potential issues like
oryp5 had before 86f410479c ("mb/system76/oryp5: Reset HDA before
configuring").
Inspecting proprietary firmware for multiple boards shows that this is
always done as well.
Change-Id: I64c1fd23f708f77a81fad0bc889f42d4df3f6e61
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66918
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
For the most part, this doesn't change any post codes, simply making the
existing post-codes into macros.
picasso/romstage.c did get a couple of post codes removed to match the
other files.
The POST_ROMSTAGE and POST_BOOTBLOCK codes are intended to become global
at some point, while the POST_AGESA and POST_PSP codes would stay AMD
specific.
Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Taken from Linux which also updated these files.
Clang only works with this syntax, so this fixes builds for arm.
TESTED on qemu vexpress-a9 and verstage on google/vilboz with
BUILD_TIMELESS=1, binaries remain the same.
Change-Id: Ia320dc2c460c99d934b8f17dee7748a9def4e750
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63058
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides the functionality to enable downshift on Marvell
PHY. By setting a downshift counter, the PHY is correspondingly often
attempted to establish Gigabit link before the PHY downshifts to the
next highest speed. The range is limited to 8 trials. To activate
downshift, a software reset must follow to take effect.
Change-Id: I4224eab6c1fc13824d53556c80435bc130a13bdb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69853
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard has three Marvel PHYs connected to the internal SOC GbE
controllers. The default LED status after HW reset of this PHYs shows a
different mode than what is needed. LED[2] is not connected on this
mainboard.
This patch sets the following LED status:
LED[0] - 7 = On - 1000 Mbps Link, Off - Else
LED[1] - 1 = On - Link, Blink - Activity, Off - No Link
LED[2] - not connected
TEST=Try different register values to verify LED feature.
Change-Id: I51d817bc720bf787279777f503efdc17dbb1274d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69387
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This driver enables the usage of an external Marvell PHY 88E1512 which
should be connected to a SOC internal MAC controller. In a first step it
is only the framework of the driver. Functionality will follow with a
second patch.
Change-Id: I24011860caa7bb206770f9779eb34b689293db10
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69384
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
