d08a76e3ea
mb/lenovo/g505s/acpi/ec.asl: Correct the path to "mainboard.h"
...
Change-Id: I273e29a26cf1c1ba34b95eb11bcb59a1360371e1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-02-22 21:25:25 +00:00
6d508dfc2d
mb/lenovo/g505s: Format code
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Change-Id: I9cce00e1634d62a63b3563d54a7a0c56058d0e39
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-02-22 21:23:24 +00:00
8f38e5f5dc
sb/amd/cimx/sb800/amd_pci_int_defs.h: Fix serial IRQ INT name in comment
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Change-Id: If351d93c47de2ef76fb24525ff6d134b35c5f3fe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-02-22 21:18:24 +00:00
4450bee6b3
sb/amd/pi/hudson/early_setup.c: Fix typo in comment
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Change-Id: Ib631cdc0794dc91df27cb984d5c585e0eee4a2ad
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-02-22 21:17:15 +00:00
090fcec945
southbridge/amd/*/*/reset.c: Reduce stylistic differences
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Change-Id: I2f58098e786e9b61b0d059723c375a90559e95a6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-02-22 21:15:39 +00:00
2a6cc959ee
southbridge/amd/*/*/smbus.c: Reformat code and reduce difference
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Change-Id: I43644b757a5a85864162da6a35f7f2a5335f8007
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-02-22 21:13:43 +00:00
f0d4f930a0
mb/gizmosphere/gizmo/acpi/gpe.asl: Remove extra blank line
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Change-Id: I0d9b07183b06915799f221390406e930ca253a0d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-02-22 21:11:46 +00:00
a789643ac9
mb/gizmosphere/gizmo/devicetree.cb: Fix typo on 'pci'
...
While on it, use tab for indent.
Change-Id: I6cb0b4183db819d721f4882ab2168d22bcd664e3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-02-22 21:11:27 +00:00
5996eea5af
sb/intel/i82371eb: Constify pci_devfn_t devices
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Change-Id: I9056464b36cde89d2fe88ff27531e467297bed0b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-02-22 20:58:14 +00:00
d3687cd994
sb/intel/ibexpeak: Constify struct southbridge_intel_ibexpeak_config
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Change-Id: I096ccd0ec224b98038d290422f568666bbede43a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-02-22 20:57:20 +00:00
95231b264d
src/Kconfig: Update the path to 'c_start.S' for GDB_STUB config
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Change-Id: Ib31defde0d4983a9418f05e0b812a7bbbe4fe2b7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-02-22 20:49:10 +00:00
16a55f7a56
mb/starlabs/labtop: Reconfigure GPIOs
...
Reconfigure the GPIO's so that they are configured correctly.
The original configuration was based on the AMI firmware, and
whilst it worked, it wasn't optimal.
Signed-off-by: Sean Rhodes <sean@starlabs.systems >
Change-Id: I27ecf066685f2a81ac884a9f276c518544449443
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
2022-02-22 19:21:36 +00:00
70a1ef0716
mb/starlabs/labtop: Reconfigure CNVi GPIOs
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Reconfigure the CNVi GPIO's so that they are configured correctly.
The original configuration was based on the AMI firmware, and
whilst it worked, it wasn't optimal.
Signed-off-by: Sean Rhodes <sean@starlabs.systems >
Change-Id: I9fc9963e91da0267c8740fee20a3ec41895b4953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
2022-02-22 19:21:22 +00:00
ad58a188e8
mb/starlabs/labtop: Update trackpad GPIO configuration
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Update trackpad GPIO to avoid IRQ Storm, that causes high power
consumption when idling or in S3.
Signed-off-by: Sean Rhodes <sean@starlabs.systems >
Change-Id: Ieee27bd9079617ab95f4f1e27ef98b49e89e5b41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
2022-02-22 19:21:07 +00:00
6306fc2127
mb/starlabs/labtop: Configure TPM_IRQ GPIO for TGL
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Configure the TPM IRQ GPIO for TGL (StarBook Mk V) so that the
hardware TPM can be used.
Signed-off-by: Sean Rhodes <sean@starlabs.systems >
Change-Id: Ife88075e70184b46e69f2e24c70b85ec254edd64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60756
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-02-22 19:20:49 +00:00
3830d7a7f5
mb/starlabs/labtop: Don't configure ESPI GPIOs
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Don't configure ESPI GPIOs as the default values are correct.
Signed-off-by: Sean Rhodes <sean@starlabs.systems >
Change-Id: I052fbfccd075d19340d3e27ad0c62965c80badaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth - Personal <martinroth@google.com >
2022-02-22 19:20:30 +00:00
36bf0947b9
soc/intel/common/block/acpi: Drop duplicated 'fadt->header.revision'
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The 'fadt->header.revision' is already done at src/acpi/acpi.c acpi_create_fadt().
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Change-Id: Ib9b6dc7e86ca17e0b2d374ee2c3bdf06f8b82dfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62222
Reviewed-by: Subrata Banik <subratabanik@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-02-22 19:03:38 +00:00
0884f21042
payloads/tianocore: Rework Makefile
...
Rework edkii makefile so that the various build options are
unified between CorebootPayloadPkg, uefipayload_202107 and
upstream.
This sets the project directory based on the git repository name
i.e. https://github.com/mrchromebox/edk2 becomes mrchomebox
Also builds to $(obj)/UEFIPAYLOAD.fd and allows using a commit
ID without a branch.
Signed-off-by: Sean Rhodes <sean@starlabs.systems >
Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
Reviewed-by: Martin Roth - Personal <martinroth@google.com >
2022-02-22 18:53:17 +00:00
e0e6f07220
vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v3054.02
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The headers added are generated as per FSP v3054.02.
Previous FSP version was v2503_00.
Changes Include:
- UPD Offset Update in FspmUpd.h
BUG=b:220076892
BRANCH=None
TEST=Build and boot adlnrvp
Change-Id: I7b921e2aa467597a1c764fc554e2e83e5bb522e8
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com >
Reviewed-by: Kangheui Won <khwon@chromium.org >
2022-02-22 18:27:06 +00:00
9478527966
soc/amd/sabrina/i2c: remove TODO
...
The SoC-specific I2C code and header file have been verified some time
ago, but it seems that I forgot to remove the corresponding TODOs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Ifd162bda10e5993bc32db3a77588491397e3c19e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
2022-02-22 18:20:18 +00:00
fd93cff329
treewide: Get rid of CONFIG_AZALIA_MAX_CODECS
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Get rid of Kconfig symbol introduced at commit 5d31dfa8ehaouas@noos.fr >
Change-Id: Ib8b656daca52e21cb0c7120b208a2acdd88625e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62202
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-02-22 17:40:30 +00:00
7f7ac206f8
src/driver/intel/mipi_camera: Update ACPI entry to provide silicon info
...
CPUID_ALDERLAKE_N_A0 is ES. Add it to generate is_es = 1 in ACPI
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com >
Change-Id: Icc65c52a9dadebe4ebab3d0c30599eb0db38bc3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Reka Norman <rekanorman@chromium.org >
Reviewed-by: Kangheui Won <khwon@chromium.org >
2022-02-22 15:58:37 +00:00
cbaf753012
soc/amd/common/block/lpc/espi_util: use __fallthrough
...
Using __fallthrough instead of a comment about the fall-through being
intentional should make clang stop complaining about intended fall-
through statements.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I940529be02e20c72f6e97b2cfa10f0dd8f7020b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com >
2022-02-22 15:56:55 +00:00
6f4a5454ac
vc/eltan/security/verified_boot/Makefile: add fmap_config.h dependency
...
Compiling vboot_check.c depends on fmap_config.h already being generated
so add this dependency.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I1fe2b738d76ae16dee3e1ebdca512264303a481c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
2022-02-22 15:56:03 +00:00
6f74d38dc8
mb/siemens/mc_apl2: Enable PCI device for I2C bus 0
...
On mc_apl2 the external RTC is connected to I2C bus 3. All other I2C bus
devices (16.0, 16.1 and 16.2) have been disabled as they are not used.
While coreboot can handle the case where a PCI device does not have
function 0 enabled but a later one (here function 3), Linux seems to
check for function 0 first and ignores the rest if function 0
is missing. So enable PCI device 16.0 in order to let Linux use 16.3
again.
Test=Boot into Linux and make sure that PCI device 16.0 and 16.3 are
visible and I2C attached RTC works properly.
Change-Id: I55a748b6de8128f4b26b908118feff9f06d3fb7c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-02-22 15:25:00 +00:00
88ccd4863c
util/nixshell: Add a Nix shell for building documentation
...
Add a Nix shell config allowing to build the coreboot documentation.
Change-Id: I1c9715c677342241b78fbdef0afeb4536f48d50f
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2022-02-22 10:31:41 +00:00
4045935eb8
include/acpi/acpi.h: Drop non-existing acpi_create_madt_lapic_nmis()
...
Change-Id: Ide854e5c8e2ed507548047cb6e1fad49efaffbb8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
2022-02-22 00:02:27 +00:00
53d13cbb21
mb/google/volteer/var/drobit: update default codec HID to 10EC5682
...
Modify function to set default audio codec HID
to be original setting 10EC5682.
BUG=b:204517112
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com >
Change-Id: Ic37e7e6757476f1d30bea31fcde4deebebd488a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
2022-02-21 23:59:41 +00:00
e46e9b04ae
mb/google/volteer/var/delbin: update default codec HID to 10EC5682
...
Modify function to set default audio codec HID
to be original setting 10EC5682.
BUG=b:204523176
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com >
Change-Id: I36e35522aba2463124b7e6e7046b1a56758b534d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
2022-02-21 23:59:21 +00:00
994c1910e8
mb/google/volteer/var/copano: update default codec HID to 10EC5682
...
Modify function to set default audio codec HID
to be original setting 10EC5682.
BUG=b:218245715
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com >
Change-Id: I30a1fe2ef8d750616f6907f86a5329f035920504
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
2022-02-21 23:58:58 +00:00
f08705db4e
soc/amd/sabrina/fw.cfg: Change the instance of PMUI/D to 2
...
Change-Id: Ie9dbed7d6dd1e5f0c97d4a6cedea3d6bd7b000a2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com >
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com >
2022-02-21 23:49:35 +00:00
e220faa18a
amdfwtool: Add entries for PMUI & PMUD with instance 2
...
Change-Id: I69c4b3cdd2473655064d1329d5319cffdba2425a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com >
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com >
2022-02-21 23:48:57 +00:00
990d154898
amdfwtool: Add support for AMD's BIOS A/B recovery feature
...
The rom layout for A/B recovery:
EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A
0x4A -> PSP L2 B -> BIOS L2 B
The coreboot doesn't implement the AMD's A/B recovery. This is only
for the ROM layout. To save some flash space, the entire B section can
be eliminated.
To enable A/B recovery in PSP layout, add "--recovery-ab" to
amdfwtool.
TEST=Majolica(Cezanne)
Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-02-21 23:47:20 +00:00
1a9e54302b
soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUD
...
Add the information of substance and instance in the string for PMUI
and PMUD. It is amdfwtool's job to extract the number from the string.
Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-02-21 21:29:50 +00:00
5bba93e08a
mb/google/brya: Enable eMMC HS400 mode for nissa
...
Based on the nivviks and nereid schematics, nissa is using eMMC HS400
mode, so enable this in devicetree.
BUG=b:197479026
TEST=Build test nivviks and nereid
Signed-off-by: Reka Norman <rekanorman@google.com >
Change-Id: Ie9772385276d3629079b95024d3ffa04438f22c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kangheui Won <khwon@chromium.org >
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com >
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com >
2022-02-21 17:05:45 +00:00
aade40c3f6
mb/amd/chausie/chromeos.fmd: resize EC size in FMAP to 4kByte
...
Only the info about the location of the EC firmware will be stored right
at the beginning of the flash, so the size can be reduced to 4kByte
which is the erase block size of the flash. The CHAUSIE_MCHP_SIG_FILE
file itself is smaller than this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Icde5f7071183cd8423fc022caf49e2c9ee288527
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62189
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-02-21 16:02:41 +00:00
b4389598cf
soc/intel/alderlake: Make clang static assert happy
...
Change-Id: Ia3cd66f6b735f7430abcdba8a9323d5ee1320fd4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-02-21 15:30:13 +00:00
141163d5ea
drivers/intel/pmc_mux: Fix printing type
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Change-Id: I1cb517323e7d609ae6624363e116e9814fc631cb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-02-21 15:29:55 +00:00
02967e6113
soc/intel/alderlake: Fix function pointer type
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const void is not a proper return type for a function. It's the
function pointer themselves that need to be const.
This fixes building with clang.
Change-Id: I99888ab9d9d80f1d6edb33b9f4a3f556f211a6e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-02-21 15:28:46 +00:00
b53a55930e
drivers/intel/fsp2_0/hob: Remove unused variable
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Change-Id: Ie9f4562be9b019d8dd65d4e9040fefbb6834fa03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
2022-02-21 15:28:06 +00:00
138db0601d
soc/intel/adl/bootblock/report_platform.c: Use the correct format
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Change-Id: I54c40434f44621c4ea6564ac9c87c5b2fa083b5d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-02-21 15:27:35 +00:00
4998aaee23
ec/google/chromeec/ec_acpi.c: Cast compatible enum types
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Clang complains about this.
Change-Id: If7af9d5a81c1c381490c9634e3da68ff7f5edda8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-02-21 15:27:15 +00:00
b55ac09ce3
[acpi]{include,soc/amd,southbridge/amd}: Clarify ARM_boot_arch in comments
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Change-Id: I8b209da90b5a591f62e760961c64c4c63e6ef65b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-02-21 15:26:30 +00:00
3a5e6f529c
util/liveiso: Use programs.flashrom.enable
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NixOS 21.11 introduced the option `programs.flashrom.enable`. The option
allows installing flashrom and hooking up its udev rules. Thus, set it
to `true` and add the user `user` to the `flashrom` group allowing it to
use the programmers.
Change-Id: I017ddb4314702a5252dfc0d05cd1e4961043d23b
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2022-02-21 15:25:18 +00:00
2164c308b4
include/device/dram/ddr3.h: Don't redefine 'printram(x, ...)'
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'printram(x, ...)' is already defined in 'include/device/dram/common.h' file
Change-Id: I75e19065b9e713df3190202b7ca9e9cd8f3f44a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-02-21 15:23:12 +00:00
e0ddea49d1
soc/intel/denverton_ns: Add pmc_mmio_regs as public function
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This patch adds `pmc_mmio_regs` a public function for other IA common
code may need to get access to this function.
BUG=none
TEST=none
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: I67a0f7fdcd0827172426bc938569a5022eff16f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2022-02-21 15:22:35 +00:00
fac11d000a
soc/intel/denverton_ns: Select PMC PCI discoverable config
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This patch selects SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE config to
reflect the SoC actual behaviour where PMC PCI device is still
visible over bus even after FSP-S exit.
Additionally, add DNV PMC PCI ID into PMC IA-common code.
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: Iaaea20e54c909800e4d75b58c29507fc1944cfba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com >
2022-02-21 15:22:01 +00:00
bf81c24e07
mb/google/brya/variants/felwinter: Adjust I2Cs CLK to be around 400 kHz
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Need to tune I2C bus 0/1/3/5 clock frequency under the 400kHz for
audio, TPM, touchscreen, and touchpad.
Audio CLK: 385 kHz
TPM CLK: 380.5 kHz
Touch Screen CLK: 373.3 kHz
Touch Pad CLK: 372.7 kHz
BUG=b:218577918
BRANCH=master
TEST=emerge-brya coreboot chromeos-bootimage
measure by scope with felwinter.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com >
Change-Id: I3e5cc10d6605f9cc41fa6b31da07a81364b72fe0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
2022-02-21 15:21:28 +00:00
aa41f77397
mb/amd/chausie/Kconfig: Move EC firmware image in CBFS
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Move the EC to a location that does not conflict with where the main
CBFS is in the chromeos FMAP
Change-Id: I28c84cbe2ff10d45383d896ae4f942ee49eb15c0
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62190
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-02-21 15:20:47 +00:00
1f5e1b4f3c
src/acpi/acpigen.c: Reformat code
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Change-Id: I58851c8a26cad61975f8ba2910eedef3029aab6f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Lance Zhao
2022-02-21 15:19:24 +00:00
