The headers added are generated as per FSP v2385_02.
Previous FSP version was 2376.
Changes Include:
- add VtdIopEnable, VtdIgdEnable, and VtdIpuEnable UPDs in Fspm.h
TEST=Build and boot JSLRVP
Change-Id: I268eca1bcbbf26d4dc4ecf54d432cdb6ad49b4eb
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47500
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current HID "RX6110SA" does not comply with the ACPI spec in terms
of the naming convention where the first three caracters should be a
vendor ID and the last 4 characters should be a device ID. For now
there is a vendor ID for Epson (SEC) but there is none for this
particular RTC. In order to avoid the reporting of a non ACPI-compliant
HID it will be dropped completely for now.
Once Epson has assigned a valid HID for this RTC, this valid HID will be
used here instead.
Change-Id: Ib77ffad084c25f60f79ec7d503f14731b1ebe9e2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47706
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
By renaming the AMD SOC common Kconfig file the wildcard to source all
AMD SoC-specific Kconfig files won't match to it and it can be sourced
after all SoC-specific Kconfig files in the sub-directories are sourced.
This change allows adding new SoCs without having to edit the soc/amd
Kconfig file.
Change-Id: Iaaa5aad23eb6364d46b279101f3969db9f182607
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The code that uses the GPU device ID uses the correct ATI vendor ID, but
the description wrongly used AMD as vendor. In the AMD APUs the GPU PCI
device and the corresponding audio controller use the ATI PCI vendor ID
while all other PCI devices in the SoC use the AMD PCI vendor ID.
Also move the two entries in a separate section right below the one they
were in.
Change-Id: Ia0b5bd4638f5b07c487f223321872563b36337e9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
SD Card driver needs to access two regulators - MT6360_LDO5 and
MT6360_LDO3. These two regulators are disabled by default.
Two APIs are implemented:
- mainboard_enable_regulator: Configure the regulator as enabled/disabled.
- mainboard_regulator_is_enabled: Query if the regulator is enabled.
BUG=b:168863056,b:147789962
BRANCH=none
TEST=emerge-asurada coreboot
Change-Id: I391f908fcb33ffdcccc53063644482eabc863ac4
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46687
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
google_chromeec_regulator_enable is for enabling/disabling
the regulator. google_chromeec_regulator_is_enabled is for
querying if the regulator is enabled.
BUG=b:168863056,b:147789962
BRANCH=none
TEST=emerge-asurada coreboot
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ia804242042b0026af19025a0c4a74b3ab8475dab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Currently, five regulator controls are implemented for DRAM
calibration and DVFS feature.
The regulators for VCORE and VM18 are controlled by MT6359.
The reguatlors for VDD1, VDD2 and VMDDR are controlled by MT6360
via EC.
BUG=b:147789962
BRANCH=none
TEST=verified with DRAM driver
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Id06a8196ca4badc51b06759afb07b5664278d13b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This function is no longer required to be implemented since
EC/AUXFW sync was decoupled from vboot UI. (See CL:2087016.)
BUG=b:172343019
TEST=Compile locally
BRANCH=none
Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I43e8160a4766a38c4fa14bcf4495fc719fbcd6c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Expose a config option that allows disabling the FSP UPD which controls
Precision Time Measurement for a particular PCIe root port. Since this
is enabled by default the option is inverted to allow disabling for
a particular port while not affecting others.
BUG=b:160996445
TEST=boot on volteer with PTM disabled for the NVMe root port
Change-Id: Icb51b256eb581d942b2d30fcabfae52fa90e48d4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
The device acceptable latency field is only valid for 'endpoints',
but not for bridge devices. Set the maximum acceptable latency on
such devices to allow ASPM being enabled if supported on both sides.
Allows the PCIe link on bridge devices to go into L0s/L1.
This allows the package to enter a deeper sleep state when all links
are idle.
WARNING: This might cause issues on PCIe bridge devices that doesn't
properly support ASPM. In addition it might decrease performance.
Change-Id: I277efe0bd1448ee8bff633428aa729aeedf04e28
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
The virtual/generic device under TBT PCIe root ports has path type as
DEVICE_PATH_GENERIC. While scanning the pcie bus, the generic device
blocks its root ports configuration. This change adds device path type
check and enables ASPM for TBT root ports.
BUG=b:173207454
TEST=Built image and booted to kernel on Voxel board. Verified both of
the TBT Root ports 00:07.0 and 00:07.1 ASPM are enabled.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I82ffaeb5a8821d9034d8dae9d98d3b5953a9608b
