26d1be15ca
src/device: Update pci_class to PCI-SIG Specification
...
Update based on PCI-SIG's specification:
"PCI code and ID assignment specification, Rev 1.11 (24 Jan 2019)"
Change-Id: If51605719fd96e399aec2ae86caedda44f2648d4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-01-10 10:55:49 +00:00
cd57d576eb
mb/msi/ms7707/devicetree.cb: Align contents
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Change-Id: I2e8100d01d1feb29df83c400f712e58ae9a5e402
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-01-10 10:20:24 +00:00
026fd87f39
mb/intel/wtm2/devicetree.cb: Align comments
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Change-Id: I701aea4656e59a369c2e663438a4b2f9644f0ed6
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-01-10 10:20:06 +00:00
8b45399adc
mb/intel/emeraldlake2/devicetree.cb: Align contents
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Change-Id: I4ad24a011bd0711dc9a1133dc6188a213cc3926b
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-01-10 10:19:53 +00:00
45b5e03641
mb/intel/dg43gt: Make devicetree prettier
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Use lowercase for hex constants and align comments and register values.
Change-Id: Ib14906113e366a2a6f268fe8b8be32b1794fb344
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38077
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-01-10 10:19:37 +00:00
221b894e7d
mb/intel/dcp847ske: Make devicetree prettier
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Align contents and fix some redundant comments.
Change-Id: I45fb02ac90fe3d280379b08c9931f1064c71633f
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
2020-01-10 10:19:25 +00:00
8aced763b3
mb/foxconn/d41s/devicetree.cb: Indent with tabs
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As on most other boards, use tabs to indent the devicetree.
Change-Id: I1d2fd6e758a3b2dccb8fc43d425f4520fd2e544f
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38075
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-01-10 10:18:57 +00:00
0d4c593c4f
mb/compulab/intense_pc: Reformat devicetree
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Use subsystemid inheritance, which results in a much more compact
devicetree. In addition, align and correct various comments.
Change-Id: Iafce736691b62ae8f359c2d74f8bd3549493029a
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-01-10 10:18:37 +00:00
60efd6fa53
mb/compulab/intense_pc: Drop zero values
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They default to zero already.
Change-Id: Iaa557b18c34584dccb5c889ab8bd2173ed4ea04b
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-01-10 10:18:28 +00:00
f1f0a0f98b
mb/roda/rk886ex/devicetree.cb: Align comments
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Change-Id: I67e3149657c04f72aac0b20bc31af338129a13b2
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-01-10 10:18:21 +00:00
2d69d594de
mb/asus/p5ql-em/devicetree.cb: Do minor fixes
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Use lowercase for hex constants, remove registers that default to zero
already and drop outdated comment about AHCI mode.
Change-Id: I6833462ea11e988eaab7913cf98853cebe4c7a9f
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-01-10 10:17:57 +00:00
92e000cfff
mb/asus/p8z77-m_pro: Make devicetree prettier
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Align comments, and make PCIe port comments consistent.
Change-Id: Id39337236deff7721183e749a6b63aadaa036b2f
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-01-10 10:17:47 +00:00
5c74911f71
mb/asus/p5qc/devicetree.cb: Drop zero values
...
They default to zero already. Moreover, the comment about AHCI mode no
longer applies, as it was made the default mode.
Change-Id: Ife99a79df0289c6db87510ed917438bf47b7f6ca
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-01-10 10:17:37 +00:00
d2f3afcc17
mb/asus/p5qc/devicetree.cb: Do minor cosmetic fixes
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Use lowercase for hex constants and align some comments.
Change-Id: I418ed29dfbc90feb591a2b30e994d9b3e6176f86
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-01-10 10:17:28 +00:00
7a61c6c398
mb/asus/p5qpl-am/devicetree.cb: Do minor cosmetic fixes
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Use lowercase for hex constants, inline a lone `end` and align a
comment.
Change-Id: Ibf3882dd134d33611138c2a9f89a3b2b37c136b4
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-01-10 10:17:11 +00:00
23d5c4c532
mb/asus/p8h61-m_pro: Make devicetree prettier
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Replace a bunch of spaces with tabs, put host bridge and friends above
southbridge, fix "TPM Module" (Trusted Platform Module Module) and add
some empty lines to help the reader.
Change-Id: I3a89893f943057ef7a4f973eaa65dba259e8a49d
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-01-10 10:16:57 +00:00
dad7f37f72
mb/asus/p8h61-m_pro/devicetree.cb: Drop zero fields
...
They default to zero already.
Change-Id: I5c99043f16bc65de952afa0ce8d40bf947bfee15
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-01-10 10:16:41 +00:00
e1484e4b3e
mb/google/veyron/devicetree.cb: Drop illogical comment
...
This comment seems to have been copied off some QEMU board. As it would
not apply to any veyron variant, drop it.
Change-Id: I70a2923520f5c59ae31d149920cf4b096e5a11d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-01-10 10:16:29 +00:00
c045a02174
mb/google/nyan/devicetree.cb: Correct some comments
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Use a consistent spelling for SoC (System-on-a-Chip), and fix a few
minor typos.
Change-Id: I29eacc9e93b2eb686ce945de0173844ef5eae1b9
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-01-10 10:16:02 +00:00
b6df6b065c
soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper
...
This patch ensures coreboot is not publishing above 4GB mmio resource
if soc common config "enable_above_4GB_mmio" not enable.
Publishing unnecessary 4GB above MMIO resource with wrong base and size
is causing problem while working with discrete GPU.
Unable to boot with dGPU on IA platform with below error:
[ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05]
[ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff]
[ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff]
[ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref]
[ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05]
[ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff]
[ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff]
[ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref]
[ 2.352541] [drm] Not enough PCI address space for a large BAR.
Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com >
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com >
2020-01-10 08:40:57 +00:00
1c3086a603
drivers/spi/spi_flash: explicitly handle STMicro deep power state
...
In order to provide more consistent probing in future refactorings, pull out
the release from deep sleep path in STMicro's SPI flash probing function.
Call that function explicitly when RDID doesn't return anything at all.
The old STMicro parts, even if supporting RDID, won't decode that
instruction while in a deep power down state. Instead of re-issuing RDID after
the successful wake assume the id fixup is valid.
Change-Id: I46c47abcfb1376c1c3ce772f6f232857b8c54202
Signed-off-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-01-10 04:55:09 +00:00
73451fdea2
sb/intel/common: Add smbus_set_slave_addr()
...
Change-Id: I7dddb61fab00e0f4f67d4eebee0cfe8dcd99f4ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38230
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-01-09 21:31:31 +00:00
7cdcc38f29
sb/intel/common: Add smbus_host_reset()
...
Change-Id: I3f6000df391295e2c0ce910a2a919a1dd3333519
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-01-09 21:29:53 +00:00
c528426b26
sb/intel/common: Rename smbus_base to base
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Change-Id: I163c82270d2360fea6c11d9270aad6dddc02e68c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-01-09 21:29:43 +00:00
1cae45432e
device,sb/intel: Move SMBus host controller prototypes
...
Also change some of the types to match the register widths
of the controller. It is expected that these prototypes
will be used with SMBus host controllers inside AMD chipsets
as well, thus the change of location.
Change-Id: I88fe834f3eee7b7bfeff02f91a1c25bb5aee9b65
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38226
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-01-09 21:25:41 +00:00
5e9ae0c2bc
sb/intel/common: Change some local SMBus function signatures
...
Change-Id: I82be883e08ca58fa454b4ad73d20dde2d40a8e3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-01-09 18:48:14 +00:00
bd65985a63
nb/intel/{i945,x4x,pineview}: Remove wrapper spd_read_byte()
...
Change-Id: Ic9554ad2813ee70d0da16857d534aab5e17d808f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-01-09 18:47:28 +00:00
65f5de2bc4
sb/intel/common: Add SMBUS register read-modify-write
...
Change-Id: Ibe967d02fd05f4a8f643a5c5b17885701946d1c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-01-09 18:47:06 +00:00
b49638dbe4
sb/intel/common: Wrap inb/outb()
...
On Intel, accessing the SMBus register banks can be done via
IO and, since at least ICH10, via MMIO. We may want to use the
latter in the future.
Change-Id: I67fcbc7b6f6be61c93bc608e556a577ef9e52325
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-01-09 18:46:30 +00:00
bbcf1a0878
soc/intel/common: Drop old forked version of SMBUS support
...
Switch to use the more recent version in sb/intel/common.
Change-Id: Idbff410991db9592a58b9cc0ae7ee8c45d750b13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-01-09 18:46:05 +00:00
d1c69c65ce
soc/intel/broadwell: Drop old forked version of SMBUS support
...
Switch to use the more recent version in sb/intel/common.
Change-Id: Icbd54b5671ea2a94aea5db4642698ef679540625
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-01-09 18:45:23 +00:00
7ca19b289e
sb/intel/common: Add smbus_{read/write}_word() variants
...
Change-Id: I1a9432c901e7baa545d34c1d0f82212bf59f8e23
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38141
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-01-09 18:44:40 +00:00
265cd9a2ee
soc/intel/common: Remove extra call layer
...
Change-Id: I6987eb58b593e1f2bc6adf91be61bf7b5382440d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38122
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-01-09 18:44:14 +00:00
756646757e
lib/spd_bin,soc/intel/common: Move get_spd_smbus()
...
Only smbuslib.c and spd_bin.c share the same prototypes for SMBUS
functions. Therefore, get_spd_smbus() currently only works with
soc/intel/.../smbuslib.c and can be implemented there locally.
This allows removal of <device/early_smbus.h>.
Change-Id: Ic2d9d83ede6388a01d40c6e4768f6bb6bf899c00
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-01-09 18:43:59 +00:00
4ae9f1e5d8
soc/intel/common: Sync early SMBUS prototypes
...
Change-Id: I6b4b5ffd552b9eb4467689c8df85905a1c199bb0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38120
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-01-09 18:43:35 +00:00
c2ce370f30
src/mainboard: remove MMIO macros
...
This touches several mainboards. Replace the macro with C functions.
The presence of bootblock.c is assumed.
Change-Id: I583034ef0b0ed3e5a5e3dd680c57728ec5efbc8f
Signed-off-by: Idwer Vollering <vidwer@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2020-01-09 16:03:07 +00:00
7c07110923
nb/amd/pi/00730F01/state_machine: Add lost options
...
Add back options that were lost on postcar migration. Some of them
seem to be required for IOMMU initialization.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com >
Change-Id: Ie9cc772d7fcbefded8bab88f9960fef663dc7217
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37999
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-01-09 15:42:08 +00:00
506b9c102c
amd/agesa/state_machine: Add BeforeInitLate hooks
...
Add missing BeforeInitLate hooks in order to bring back certain options
that were lost on postcar migration. This will also allow to disable
CDIT again that caused AmdInitLate error on 00730F01.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com >
Change-Id: I1226e9c0c8a92920f2569ec0f85d0be0adcc9e30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2020-01-09 15:40:15 +00:00
e1e3289052
AGESA,binaryPI boards: Declare some IRQ tables static
...
Change-Id: Ib45c6372df6068ab041a055dad8bacf597717ba2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com >
2020-01-09 15:35:54 +00:00
034cf6390f
drivers/pc80/rtc: Separate {get|set}_option() support
...
Move things depending on option_table.h to a separate file.
Change-Id: Ib23fcd89bf4efef9072fcaea1d8699145c1f2983
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38193
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-01-09 14:38:47 +00:00
cbf9571588
drivers/pc80/rtc: Separate {get|set}_option() prototypes
...
Long-term plan is to support loading runtime configuration
from SPI flash as an alternative, so move these prototypes
outside pc80/.
Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-01-09 14:37:33 +00:00
2a0e3b25ea
drivers/pc80/rtc: Remove duplicate cmos_chksum_valid()
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Change-Id: I5a4b86921876c24cd1d310b674119b960c3d2fd6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38194
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-01-09 14:37:06 +00:00
3838701c84
soc/intel/tigerlake: Update Kconfig
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Update Kconfig:
- use CAR NEM mode for tigerlake only as NEM Enhanced is under debug
- update GSPI, RP max device #s according to
PCH EDS#576591 vol1 rev1.2
- update UART M/N setting according to new PCH baseclock
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com >
Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
2020-01-09 14:35:56 +00:00
c83bab62b3
acpi: Be more ACPI compliant when generating _UID
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* Add function to generate unique _UID using CRC32
* Add function to write the _UID based on a device's ACPI path
ACPI devices that have the same _HID must use different _UID.
Linux doesn't care about _UID if it's not used.
Windows 10 verifies the ACPI code on boot and BSODs if two devices
with the same _HID share the same _UID.
Fixes BSOD seen on Windows 10.
Change-Id: I47cd5396060d325f9ce338afced6af021e7ff2b4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com >
2020-01-09 14:22:51 +00:00
5c8ff794a8
superio/common/ssdt: Make disabled PNP devices ACPI compliant
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Always write a _HID, even for disabled PNP devices.
Fixes a BSOD on Windows 10.
Change-Id: I419a08bd6a3570fb4e1ae31bef4f9ccd6836fe1b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com >
2020-01-09 14:22:29 +00:00
1aba2a32e8
nb/intel/sandybridge: Make MCHBAR arithmetics consistent
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Ensure that the operation order is always the same. This results in
changes to the binary, but the effective result is the same.
Change-Id: I9772832c60089b35889df7298e20a2bd02b35b00
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2020-01-09 14:17:50 +00:00
d5be4e4046
soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi
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This patch creates a common instance of northbridge.asl inside intel common
code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to
refer northbridge.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
Device(MCHC) presence after booting to OS.
Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com >
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com >
Reviewed-by: Lance Zhao <lance.zhao@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-01-09 08:25:12 +00:00
a8280e4cc0
drivers/spi: remove SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B option
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The SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B option is no longer
being used in the code. There's a runtime check for supporting
fast read dual output mode of the spi flash. Remove the references
to SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B.
Change-Id: Ie7d9d3f91f29a700f07ab33feaf427a872bbf7df
Signed-off-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38166
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-01-08 17:18:20 +00:00
a48e8f52d8
Make: Add supermicro/smcbiosinfo to tools
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Build the smcbiosinfo tool with other tools.
Fixes possible race condition on jenkins.
Change-Id: I38f7ee2fdef2818ad685b3de53ad74f7da50600f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Christian Walter <christian.walter@9elements.com >
Reviewed-by: ron minnich <rminnich@gmail.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-01-08 16:24:04 +00:00
6779d2352c
util/autoport: correct build errors of produced files
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Change-Id: I8d1a6af6f1d70268f17692bee130c08502082c97
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2020-01-08 14:25:23 +00:00
