Add definitions for more DMIBAR/EPBAR registers, and specify their sizes
as well. Also, expand a comment as the registers' purpose is now known.
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: I9687d34e0663e70bdd2a1aa682246c2448690e18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45448
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The host bridge PCI device ID can be changed by the firmware. There
is no documentation about it, though. There's 'official' IDs, which
appear in spec updates and Windows drivers, and 'mysterious' IDs,
which Intel doesn't want OSes to know about and thus are not listed.
The current coreboot code seems to be able to change the device ID
of the host bridge, but it seems to be missing a warm reset so that
the device ID changes. Account for the 'mysterious' device IDs in
the northbridge driver, so that booting an OS has a chance to work.
For the sake of completeness, add the PCI device IDs for Clarkdale.
Although only Arrandale is known to work, both of them are Ironlake.
It is possible that the Management Engine handles changing the PCI
device ID, which would not happen when using a broken ME firmware.
Change-Id: I93c9c47e2b0bf13d80c986c7d66b6cdf0e192b22
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45562
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
System BIOS must program some of the Root Complex Topology Capability
Structure registers located in configuration space, specs say. So do it.
Tested on Asrock B85M Pro4, still boots.
Change-Id: Ia2a61706a127bf2b817004a8ec6a723da9826aad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43744
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enhance USB 2.0 C0/C1 A0/A1 SI by increasing the level of
"HS DC Voltage Level" and " Disconnect Threshold Adjustment" registers.
COMPDISTUNE0: 0x3->0x7
TXVREFTUNE0: 0x6->0xf
BUG=b:166398726
BRANCH=zork
TEST=1. emerge-zork coreboot
2. check U2 register is set correctly.
3. U2 SI all pass
Change-Id: I69d942605c6d43ece0d71f67df3a5e00b998219b
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46545
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rework the code moved to common code in CB:46274. This involves
simplification by using appropriate helpers for MSR and CPUID, using
macros instead of plain values for MSRs and cpu features and adding
documentation to the header.
Change-Id: I7615fc26625c44931577216ea42f0a733b99e131
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl,
tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common.
This change just moves the code. Rework is done in CB:46588.
Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46274
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code with this error was copy-pasted from Haswell. It was fixed with
commit dab81a4 (northbridge/intel/haswell: Fix copy paste error) for
Haswell. Do the same for Broadwell. Given that LP SKUs only support one
DIMM per channel, this change makes no difference in practice.
Change-Id: I2a7bee617354870aa4334b6c0e6b49d831e64c23
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Expose the following FSP UPD interface into coreboot:
- AcousticNoiseMitigation
- FastPkgCRampDisable
- SlowSlewRateFor
BUG=b:153015585
BRANCH=none
TEST= Measure the change in noise level by changing the UPD values.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I1924a3bac8beb16a9d841891696f9a3dea0d425f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
There's no need to use reg-script to do this. Since Haswell does not use
reg-script, drop it here to ease comparisons between both platforms.
Change-Id: I28323e891661758c23542c23ad9409d7fafbadf6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46525
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MC_LOCK register was written twice and SA PM no longer has a lock
bit. Update the sequence as per the Broadwell BIOS Specification, but
keep the registers sorted by type.
Change-Id: I91cd0aa61ba6bc578c892c1a5bc973bf4c28d019
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46324
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do not use `System Agent version` to refer to the MRC version, which is
what the register being printed contains under normal circumstances. Use
the code from Broadwell, which also happens to be indented with tabs.
Change-Id: I03b24a8e0e8676af7c5297dc3fc7bf60b9bbb088
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Commit c2ee680 (sandybridge: Use calls rather than asm to call to MRC.)
did it for Sandy Bridge, and this commit does it for Haswell.
Tested on Asrock B85M Pro4, still boots with MRC.
Change-Id: Ic915ae2a30f99805b2c87df8f9a9586a74a40c29
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Update the two load line slope settings for the SVID3 telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current. Proper calibration is determined by the AMD SDLE tool
and the Stardust test.
VDD Slope: 62852 -> 62641
SOC Slope: 28022 -> 28333
BUG=b:170531252
BRANCH=zork
TEST=1. emerge-zork coreboot
2. pass AMD SDLE/Stardust test
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Id831907aa47be27fef2e33bb884a1118ffec14a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
RW_LEGACY region needs to be 1 MiB to accommodate any alternate
firmware. Hence update the flash ROM layout as below:
* Grab ~512 KiB from each FW_MAIN_A/B regions and allocate them to
RW_LEGACY region so that it grows to 1 MiB.
* Remove VBLOCK_DEV region which is not used.
* Re-size the ELOG region to 4 KiB since that is the maximum size of the
ELOG mirror buffer.
* Resize RW_NVRAM, VBLOCK_A/B regions to 8 KiB since no more than that
size is used in those regions.
* Resize SHARED_DATA region to 4 KiB since no more than that size is
used in that region.
* Based on the resizing, allocate each FW_MAIN_A/B regions with 72 KiB.
BUG=b:167943992, b:167498108
TEST=Build and boot to OS in Drawlat. Ensure that the firmware test
setup and flash map test are successful. Ensure that the event logs are
synced properly between reboots. Ensure that the suspend/resume sequence
is working fine. Ensure that the ChromeOS firmware update completes
successfully for the boot image with updated flash map and the system
boots fine after the update.
Change-Id: I53ada5ac3bd73bea50f4dd4dd352556f1eda7838
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46569
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable caching of memory training data for recovery as well as normal
mode because memory training is taking too long in recovery as well.
This required creating a space in the fmap for RECOVERY_MRC_CACHE.
BUG=b:150502246
BRANCH=None
TEST=Run power_state:rec twice on lazor. Ensure that on first boot,
memory training occurs and on second boot, memory training is
skipped.
Change-Id: Id9059a8edd7527b0fe6cdc0447920d5ecbdf296e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46651
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Icaf80bd9da3e082405ba66ef05dd5ea9185784a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46387
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
