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Arthur Heymans
2ea4efeefa nb/intel/nehalem: Start VBOOT in bootblock with a separate verstage 
Tested on Lenovo Thinkpad X201, selects slot or recovery just fine.

Change-Id: Ia2b2f2b95510388599266264eaed0d64ce9b6ec5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-10-13 12:46:32 +00:00
Arthur Heymans
2882253237 nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCK 
A few notable changes:
- Microcode init is done in assembly during the CAR init.
- The DCACHE_BSP_STACK_SIZE is set to 0x2000, which is the same size
  against which the romstage stack guards protected.
- The romstage mainboard_lpc_init() hook is removed in favor of the
  existing bootblock_mainboard_early_init().

Change-Id: Iccd7ceaa35db49e170bfb901bbff1c1a11223c63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-10-13 12:46:18 +00:00
Arthur Heymans
b9c9cd75e7 sb/intel/ibexpeak: Move some early PCH init after console init 
Some of the initialization isn't necessary before console INIT is
done.

EHCI debug still works fine on the Lenovo Thinkpad X201.

Change-Id: I0c33efd98844f7188e0258cf9f90049d45145e7c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35949
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-13 11:07:00 +00:00
Arthur Heymans
b33d8ce5c7 ec/acpi/ec.c Link EC code in bootblock & verstage 
This allows to read and set bits in the EC ram in the bootblock or
verstage. This can be useful if one needs to read a keyboard key as an
input for get_recovery_mode_switch in vboot.

Change-Id: I20b2264012b2a364a4157d85bfe5a2303cc5e677
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2019-10-12 12:57:04 +00:00
Maxim Polyakov
4fb80753f5 util/inteltool: remove unsupported MSRs for 06_9EH 
Change-Id: I5c1e4d20efa7630bf4e6210591790055ead0161c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2019-10-12 11:56:23 +00:00
Maxim Polyakov
9ebf5317bc util/inteltool: fix 6d0H-6dfH MSR names for 06_9EH 
Change-Id: I92e8f5194114f7756e3858ff13c207daebe8167c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2019-10-12 11:53:35 +00:00
Maxim Polyakov
3e7ff29995 util/inteltool/cpu: fix IA32_PLATFORM_ID MSR addr 
According to the documentation [1], IA32_PLATFORM_ID MSR register
address should be 17H.

[1] Table 2-2. Intel (R) 64 and IA-32 Architectures Software Developer’s
    Manual. Volume 4: Model-Specific Registers. May 2019.
    Order Number: 335592-070US

Change-Id: I9a16b162db51d21c7849b3c08c987ab341845b1e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2019-10-12 11:42:47 +00:00
Maxim Polyakov
43a98b9589 util/inteltool: remove duplicate MSR for 06_9EH 
Change-Id: I34981a69ad027444bc757449db2366f51c13f0e3
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2019-10-12 11:40:58 +00:00
Elyes HAOUAS
3c8f9b8291 mb/biostar/am1ml: Use ite's common functions 
Change-Id: I0b1356420c9ae419b2a0a247b9dc6c8e92b7689a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2019-10-12 11:40:31 +00:00
Elyes HAOUAS
cd7adbf9c4 mb/roda/rk886ex: Use pnp_write_config function 
Change-Id: Ic56367d64b9304b36f5ba5a4b7d5237574eb73ae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2019-10-12 11:39:54 +00:00
Elyes HAOUAS
d6c8bdc664 mb/getac/p470: Use pnp_write_config function 
Change-Id: Iaf9a4608f1b7d25cf5d8dbe2c1489b3d2d00f25a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2019-10-12 11:39:25 +00:00
Jeremy Soller
46cc5d6b53 Set prefetch and non-prefetch hotplug memory separately 2019-10-11 10:15:34 -06:00
Nico Huber
484ad0f1f7 mb/{razer,purism}: Don't select NO_POST 
The NO_POST option covers more than classical port 80 output, hence
selecting it seems wrong in any case. The default is still rather
user patronizing, but let's keep it.

As a side effect, this fixes the ability to override the default
for NO_POST which Kconfig rejected while these boards selected it.
(Seems like a bug in Kconfig, though.)

Change-Id: I896b08812b1aa6ce249d7acc8073ebcc0f72eace
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
 2019-10-11 15:28:20 +00:00
Arthur Heymans
2437fe9dfa sb/intel/i82801gx: Move CIR init to a common place 
Some boards with the G41 chipset lacked programming CIR, so this
change add that to those boards too.

Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2019-10-11 12:21:25 +00:00
Arthur Heymans
cbe5357de0 vendorcode/eltan/Kconfig: Hide the Kconfig options when lacking support 
The vendorcode/eltan mboot and verified boot options only build if a
few other Kconfig options are defined.

Change-Id: Ie333d2fbf294e23ec01df06ee551e2d09541c744
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35954
Reviewed-by: Wim Vervoorn
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-11 07:08:27 +00:00
Arthur Heymans
894240d362 vendorcode/siemens: Remove sourcing non existing Kconfig files 
There is only one subdir in vendorcode/siemens and it does not feature
a Kconfig file.

Change-Id: I136743344465cea9c769234aa84d9ebe874ef0d2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2019-10-11 07:08:18 +00:00
Tim Wawrzynczak
bac8e8d8ac mb/google/hatch: Add new touchscreen option for Kohaku 
The next board rev will have a new option for an Elan touchscreen.  Add
support for this in the devicetree, as well as use the 'probed' property
on both touchscreen options.

BUG=b:141957731
BRANCH=none
TEST=compiles (next board rev not available yet)

Change-Id: I135e693304cbb8dffc0caf4c07846033d6802208
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
 2019-10-11 05:05:03 +00:00
Jeremy Soller
0a0b9c599d Add PCIe hotplug bridge support 
Change-Id: I7b7ed634685d85a6ca30130c16b39007bd327167
 2019-10-10 15:36:40 -06:00
Jeremy Soller
610b680154 Remove thunderbolt driver 
Change-Id: I2cfda79ab838e76170219e9081daf8218b4c09fc
 2019-10-10 15:36:15 -06:00
John Su
d4697a0de7 mb/google/octopus/variants/fleex: Update GPIOs to fix EMR 
Update GPIO_138 and GPIO_139 setting to fix EMR function.

BUG=b:141729962,b:141281846
BRANCH=octopus
TEST=verify EMR function in Grob360S.

Change-Id: I28cef592374fb4aeee2f3d3010cc0e237d62a2fd
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2019-10-10 19:00:03 +00:00
Arthur Heymans
246334390b nb/intel/pineview/Kconfig: Remove romcc leftover 
This is unused since C_ENVIRONMENT_BOOTBLOCK is used.

Change-Id: Id5af41e455d211eba89cfeb625f4c728b4145da7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-10-10 15:38:45 +00:00
Michael Niewöhner
6e66d7b8eb soc/intel: sgx: get rid of UEFI-style usage of global variable 
Rework SGX enable status in a clean way without using a global variable.

Change-Id: Ida6458eb46708df8fd238122aed41b57ca48c15b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-10-10 14:06:09 +00:00
Elyes HAOUAS
edfe125bf9 mb/{ibase/mb899,kontron/986lcd-m}: Use pnp_write_hwm5_index function 
Change-Id: If30a17d053da8f0758085fc36469b564d46049cd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2019-10-10 13:52:45 +00:00
Jeremy Soller
486c132f1e Add comments 2019-10-09 21:36:31 -06:00
Jeremy Soller
9ca336f837 Remove debugging 2019-10-09 21:33:58 -06:00
Jeremy Soller
e2e360e3f8 Add hotplug_buses to device struct to allow removal of hack 2019-10-09 21:28:04 -06:00
Jeremy Soller
9f16fa4e74 Hack to add 32 to subordinate 2019-10-09 16:44:38 -06:00
Jeremy Soller
f0e552d664 Enable allocation of resources to device 1 on thunderbolt bus 2019-10-09 16:28:18 -06:00
Arthur Heymans
7f9b90f0a6 soc/qualcomm: Remove default ops to generate bootblock.bin 
This is done by default in the main Makefile.inc.

TEST: With BUILD_TIMELESS=1 the resulting binary is identical before
and after the change.

Change-Id: Ie85e023df1f1c2b0f115e4f92719a511f60019c3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2019-10-09 22:24:56 +00:00
Yu-Ping Wu
0e5b196cb6 soc/mediatek/mt8183: Change argument type of mt_set_emi 
Since struct dramc_param has been defined, we can pass the struct
directly from mt_mem_init().

BUG=b:139099592
BRANCH=none
TEST=emerge-kukui coreboot

Change-Id: If7333fb579eff76dd9d1c2bf6fdfe7eccb22050f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35846
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-09 22:24:00 +00:00
Huayang Duan
078332e4d8 soc/mediatek/mt8183: Run DRAM full calibration 
Load the calibration params from flash first and check the correctness
of the params. If the params have correct format, perform DRAM fast
calibration with these params to reduce bootup time. Otherwise, load the
DRAM blob and perform DRAM full calibration.

Bootup time of DRAM partial calibration:
 - 1,349,385 usecs with low frequency
 -   924,698 usecs with middle frequency
 - 1,270,089 usecs with high frequency
3,544,172 usecs in total.

Bootup time of DRAM fast calibration:
 - 216,663 usecs with low frequency
 - 328,220 usecs with middle frequency
 - 322,612 usecs with high frequency
867,495 usecs in total.

BUG=b:139099592
BRANCH=none
TEST=emerge-kukui coreboot

Change-Id: I8de29b14b1fb24b3b4f351c855c5c4d8f350cc34
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
 2019-10-09 22:22:41 +00:00
Huayang Duan
846be446d3 soc/mediatek/mt8183: Use cached calibration result for faster bootup 
Load calibration params from flash. If the format of the params is
correct, use these calibration params for fast calibration to reduce the
bootup time.

Bootup time of DRAM partial calibration:
 - 1,349,385 usecs with low frequency
 -   924,698 usecs with middle frequency
 - 1,270,089 usecs with high frequency
3,544,172 usecs in total.

Bootup time of DRAM fast calibration:
 - 216,663 usecs with low frequency
 - 328,220 usecs with middle frequency
 - 322,612 usecs with high frequency
867,495 usecs in total.

BUG=b:139099592
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: I9ef4265dd369a1c276bb02294696556df927e7bc
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35164
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-09 22:22:14 +00:00
Yu-Ping Wu
732e215dd8 soc/mediatek/mt8183: Add the shared 'dramc_param' module 
The dramc_param module simplifies the communication between coreboot and
MTK DRAM full calibration blob, and is shared by both implementations to
ensure the same format of parameters.

BUG=b:139099592
BRANCH=none
TEST=emerge-kukui coreboot

Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
 2019-10-09 22:21:10 +00:00
Yu-Ping Wu
093d8ea323 soc/mediatek/mt8183: Simplify usage of dramc_engine2_end 
Since we always write to &ch[chn].ao.dummy_rd after calling
dramc_engine2_end(), this write could be merged into dramc_engine2_end()
to simplify code.

BUG=none
BRANCH=none
TEST=emerge-kukui coreboot

Change-Id: Ibb4bd5ed016118811ad2097098417c19f00f4263
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35749
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-09 22:20:05 +00:00
Jeremy Soller
a22c00bc39 Fix cml-u board info 2019-10-09 16:19:57 -06:00
Arthur Heymans
3cde494000 sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage 
This is now done during the romstage.

Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2019-10-09 22:18:57 +00:00
Bernardo Perez Priego
a31e6e8497 mb/google/drallion: Enable UART console for arcada_cml and sarien_cml 
Drallion uses UART 0 for console, other two variants remain as UART 2.

BUG=b:139095062
TEST=emerge-drallion coreboot chromeos-bootimage.
     Console should be visible.

Change-Id: I520a07ad6f755bc2e6481329fc69bef9a36e31e2
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35785
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-09 22:17:36 +00:00
Wisley Chen
2ef5d1af86 mb/google/hatch: Remove pen device for dratini/dragonair 
Dratini/Dragonair doesn't support pen insertion/ejection feature,
so remove it.

BUG=b:142159117
TEST=emerge-hatch coreboot

Change-Id: I64859a162d8dc75ffe55d98b72a056dd72e8de75
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
 2019-10-09 22:16:51 +00:00
Greg V
84c491a8c8 mb/[google/intel/lenovo]/*: fix posix shell bug with SPD files 
FreeBSD's sh (basic posix shell) did not interpret the '\%o' escape
in the same way bash/zsh do. As a result, the decoded files ended up
with ASCII numbers instead of the decoded binary data.

Change-Id: I95b414d959e5cd4479fcf100adcf390562032c68
Signed-off-by: Greg V <greg@unrelenting.technology>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2019-10-09 22:16:40 +00:00
Greg V
ae47a6f4fa ec/google/chromeec: fix format security warning 
Change-Id: I7a7bcb56523d595e8d4f32849aac53d66d416a12
Signed-off-by: Greg V <greg@unrelenting.technology>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35866
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-09 22:15:38 +00:00
Greg V
1c3dbdbbf6 drivers/spi: ignore -Wvla on clang too 
Change-Id: I99bc6877680b32f2bae78437ab0482baa65496d8
Signed-off-by: Greg V <greg@unrelenting.technology>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2019-10-09 22:15:18 +00:00
Himanshu Sahdev
fa6024e15e acpi_table_header: Replace hard-coded length via sizeof(acpi_fadt_t) 
Minimize use of hard-coded value for acpi_table_header->length to soft
code. Replace length of acpi_header_t with sizeof(acpi_fadt_t).

Change-Id: Ibcae72e8f02497719fcd3f180838557e8e9abd38
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
 2019-10-09 22:14:54 +00:00
Shelley Chen
9b93383f5b mb/google/hatch: Set FPS as wake source 
BUG=b:142131099
BRANCH=None
TEST=powerd_dbus_suspend, ensure DUT in S0ix
     touch fp sensor and ensure DUT wakes up in S0

Change-Id: If57094aa1076d79ac0886b71fa5532411bfeb45f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
 2019-10-09 22:01:23 +00:00
Jeremy Soller
14fa57aa54 Enable PCIE debug info and disable fake devices under thunderbolt controller 2019-10-09 15:11:14 -06:00
Jeremy Soller
57d53e9635 WIP Thunderbolt support 2019-10-09 14:24:00 -06:00
Elyes HAOUAS
86b683a888 SMBIOS (Type 17): Add HBM device type and DIE form factor value 
Add High Bandwidth Memory, High Bandwidth Memory Generation 2 and new
form factor value (Die).

Change-Id: Ia174e09bffdadeed4a18d443f75e2386d756e9bf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35893
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-09 10:40:56 +00:00
Elyes HAOUAS
5d0942baa2 SMBIOS: (Type 9) Add PCI Express Gen 4 values 
Change-Id: I616a435d80715bee6f7530d7318319556a7580e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-10-09 10:39:26 +00:00
Felix Held
6c244bd4dd superio/it8772f: use pnp_ops.h for pnp register access 
Change-Id: I983249fb54b6fbccc4339c955cb5041848b21cf8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2019-10-08 18:09:39 +00:00
Felix Held
08abfa3814 superio/winbond/w83627*: use hwm5_conf.h for HWM setup 
Change-Id: Id78042606f02e02035dc917d162d0c98c9de38a4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2019-10-08 18:08:52 +00:00
Felix Held
4a0899fe52 intel/dcp847ske: use functions from hwm5_conf.h for HWM setup 
Change-Id: I67de5260a756fc7b1cf0ec1903bee0058a2dcb06
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2019-10-08 18:08:19 +00:00