sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
41,382 Commits 47 Branches 30 Tags
dea722b36c00f907f3e080f19a3afa2576ac11a1
Commit Graph

53 Commits

Author SHA1 Message Date
Angel Pons
dea722b36c nb/intel/ironlake: Use new fixed BAR accessors 
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: Ia0a086bd28b796d2cbe1c7a056922721c95612b8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51868
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-04-10 15:54:39 +00:00
Angel Pons
b324df6a54 arch/x86: Provide readXp/writeXp helpers in arch/mmio.h 
These p-suffixed helpers allow dropping pointer casts in call-sites,
which is particularly useful when accessing registers at an offset from
a base address. Move existing helpers in chipset code to arch/mmio.h and
create the rest accordingly.

Change-Id: I36a015456f7b0af1f1bf2fdff9e1ccd1e3b11747
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51862
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-04-06 07:10:40 +00:00
Angel Pons
e24f97c081 nb/intel/ironlake: Drop pci_mmio_size 
There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.

Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52070
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-04-05 13:16:22 +00:00
Angel Pons
b182189326 nb/intel/ironlake: Avoid casting pointers to structs 
Instead, convert the struct to a union and pass in a pointer to it.

Tested on out-of-tree HP ProBook 6550b, still boots.

Change-Id: I60e3dca7ad101d840759bdc0c88c50d9f07d65e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45367
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-27 09:39:28 +00:00
Angel Pons
4447996cc5 nb/intel/ironlake: Handle broken ME firmware 
This allows booting without ME firmware, even though the 30-minute
auto-shutdown still happens. Without this patch, an HP ProBook 6550b
cannot get past the `setup_heci_uma` function call.

Change-Id: I446c02ac6034ede75cb873a2e676c40e4ef84b7c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2021-02-27 09:39:13 +00:00
Angel Pons
56823f53dc nb/intel/ironlake: Rewrite early QPI init 
Rewrite early QPI initialisation to account for variables in the
register values. Trace replays did not capture these relationships.

Tested on out-of-tree HP 630, still boots.

Change-Id: I5d393e8222be286ab4d4dc074d85f721b07bbca4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49586
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-24 22:35:38 +00:00
Angel Pons
3d35756d5a nb/intel/ironlake: Correct even more replay issues 
The per-lane registers need to be modified in some cases. Also, MRC
does not have any delay after the loop, so remove it.

Tested on out-of-tree HP 630, still boots.

Change-Id: If02e171d2e999f4a5be5b43ecc5aafe8ca092951
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49585
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-24 11:42:29 +00:00
Angel Pons
a8b82717ee nb/intel/ironlake: Relocate early QuickPath init 
Given that the PCI devices/registers being accessed are about QuickPath,
this code must be part of QuickPath init. Move it with the other code.

Tested on out-of-tree HP 630, still boots.

Change-Id: I0854e7f0ce3070eed1adc0603f68a9d1552204d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49584
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-24 11:42:24 +00:00
Angel Pons
7a87c9203e nb/intel/ironlake: Split out some QuickPath init code 
The platform performs a CPU-only reset after initializing QPI (QuickPath
Interconnect) and before actually performing raminit. The state is saved
in the sticky scratchpad register at MCHBAR + 0x2ca8.

Relocate some QuickPath init to a separate file. All moved functions are
only used within QPI init code, and had to be relocated in one commit.

Tested on out-of-tree HP 630, still boots.

Change-Id: I48e3517285d8fd4b448add131cd8bfb80641e7ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49582
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-24 11:42:02 +00:00
Angel Pons
a65ff854cd nb/intel/ironlake: Remove unnecessary declaration 
Change-Id: I14c5671dfc611209e28f25f38b4e82d11aef88ab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49580
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-24 11:41:56 +00:00
Angel Pons
266819104f nb/intel/ironlake: Fix more replay issues 
Introduce the `get_bits_420` helper to avoid doing the same thing in
three different ways, and also correct a related register write.

Tested on out-of-tree HP 630, still boots.

Change-Id: Iec87f080714f0f07f5d43200ec01d6d3f31e8120
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49579
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-24 11:41:48 +00:00
Angel Pons
c627dc9f8c nb/intel/ironlake: Fix some replay issues 
Dummy reads followed by writes are actually read-modify-write operations
in disassembled binaries. Handling of the scratchpad register 0x2ca8 is
still nonsense, but that should be taken care of in a separate commit.

Tested on out-of-tree HP 630, still boots.

Change-Id: Ie33f42ecdb25febf3c82febeca13662232dea9ec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45606
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-24 11:41:42 +00:00
Angel Pons
c10f8b219e nb/intel/ironlake: Correct set_4cf 
We only need to toggle one bit at a time. Introduce `rmw_500` to
simplify the code. The rank population doesn't seem to matter.

Tested on out-of-tree HP 630, still boots.

Change-Id: Ic1a680dae90889c84c9b2c536745e254475ff878
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49577
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-24 11:41:36 +00:00
Kyösti Mälkki
c92c5e5450 nb/intel/ironlake: Drop redundant clear of SLP_TYP 
Bits are already cleared in southbridge_detect_s3_resume().

Change-Id: If8bb85abacd59c7968876906e126300c9e4314e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-23 02:37:09 +00:00
Angel Pons
a3868296ce nb/intel/ironlake: Do not call collect_system_info twice 
Move wait for TXT and early ME init out of `collect_system_info`, and
then drop the first call to it. Also drop a useless register read.

Tested on out-of-tree HP 630, still boots.

Change-Id: I9b167f44cbd96864bf1e8b616576af19cbbfd90c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49581
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-22 07:25:37 +00:00
Patrick Georgi
6b688f5329 src: use ARRAY_SIZE where possible 
Generated with a variant of
https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci

Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 11:30:40 +00:00
Angel Pons
ee7fb34dcb nb/intel/ironlake: Use RCBA macros 
Use defined RCBAx macros over readX/writeX calls.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I87cae75268ef5f329001706e4771e98653d40cd1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50037
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-30 23:07:55 +00:00
Angel Pons
244f455bd9 nb/intel/ironlake: Drop constant parameter 
All callsites of `rmw_1d0` use the same `flag` value.

Change-Id: I84fab5d3fd270ce684cd6ca892c213b0d8610283
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2021-01-25 09:09:59 +00:00
Angel Pons
b600d41c3f nb/intel/ironlake: Print MCH dev/revision IDs and CAPID 
Given the lack of documentation for this platform, having this info
in coreboot logs (e.g. from board_status) can be pretty useful.

Change-Id: I6a743c1efc1b6da71589460a69bfe4785e3e77a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2021-01-19 08:58:17 +00:00
Kyösti Mälkki
e1aa9833c1 lib/ramtest: Fix ram_check() declarations 
For a long time, second parameter 'stop' has been
ignored. The tested range is within 1 MiB above 'start'.

Change-Id: Icbf94cd6a651fbf0cd9aab97eb11f9b03f0c3c31
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48561
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-18 07:26:32 +00:00
Angel Pons
c2d6f5f4da nb/intel/ironlake: Add comment about MCH scan chains 
Change-Id: I3e60cfc1fd3352b8b0c7460503179425cc593d36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-12-14 08:24:12 +00:00
Angel Pons
71e4545e5a nb/intel/ironlake: Remove unused constant 
Change-Id: I0a32295e72270cde2e9bd2f8f00358b47ffd3e33
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48562
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-12-14 08:24:04 +00:00
Angel Pons
3b264d0074 nb/intel/ironlake: Clean up DMIBAR/EPBAR registers 
Several registers have been copy-pasted from i945 and do not exist on
Ironlake. Moreover, other register definitions were missing. Use the
newly-added definitions in existing code, in place of numerical offsets.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I8ac99166a8029dcdbb59028b4a7ee297249de5db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-10-10 19:30:56 +00:00
Patrick Rudolph
819c206742 ironlake: Fix compilation on x86_64 
Use correct datasize to compile on x86_64.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: I213b2b1c5de174b5c14b67d1b437d19c656d13fd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-09-26 17:31:08 +00:00
Angel Pons
aaea66aca8 nb/intel/ironlake: Use MSAC definition 
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I479fd701f992701584d77d43c5cd5910f5ab7632
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-09-22 17:36:42 +00:00
Angel Pons
d071c4d3c3 nb/intel/ironlake: Use DMIBAR/EPBAR macros 
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: Ie0198a44589271de0335a51937e95662db891d98
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-09-22 17:36:14 +00:00
Angel Pons
eb53793fdb nb/intel/ironlake: Clean up cosmetics of early ME functions 
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: Ic766345b58c59f3d3c3570741c0eb0ad4e53ed79
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-09-21 08:05:22 +00:00
Angel Pons
55f11e29e4 nb/intel/ironlake: Clean up send_heci_uma_message signature 
The only raminfo field it needs is `memory_reserved_for_heci_mb`. So,
pass in that value directly. As it's read-only, make it const as well.

Change-Id: Ib5d4604e6c1c9bc77df9adfead93b6028d536a3d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45365
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-09-21 08:04:57 +00:00
Angel Pons
36592bfe40 nb/intel/ironlake: Reduce the scope of heci_uma_addr 
There's no need to have it in raminfo. Also, bump MRC_CACHE_VERSION.

Change-Id: Ida48ec4f50c880fe48d88d016acd3737a0650f80
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45364
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-09-21 08:04:43 +00:00
Angel Pons
298d34d8ff nb/intel/ironlake: Do not re-read ME UMA size 
It has been read twice already, so don't read it a third time.

Change-Id: I56ec3a10246f6ebe8074e7b8c164bda6b90eee87
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-09-17 19:59:29 +00:00
Angel Pons
8690746efb nb/intel/ironlake: Drop some unused function parameters 
Some of the HECI functions do not need raminfo at all.

Change-Id: If0720fa87e5e18820db77a1b61bcdb42ecc538fb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-09-17 19:59:13 +00:00
Angel Pons
d02f3303d9 nb/intel/ironlake: Drop heci_bar field from raminit 
This field is only written to, never read. Drop it from raminfo.
Also, bump MRC_CACHE_VERSION as the saved data layout has changed.

Change-Id: I83d6e69addff996e2f18472d3e1d4f7b9ba974fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-09-17 19:59:04 +00:00
Patrick Rudolph
a1ef21301b nb/intel/ironlake/raminit: Work around compiler bug 
This fixes commit e1d1fe454c
initialize 'reply.command'.

The compiler now optimized away the final condition, that checks
the result of heci message, resulting in a binary that always
calls die().

Fix that behaviour by using volatile.
Tested on Lenovo T410: Boots again into Linux.

Change-Id: I63cffc8812bd22695c01bf57283ca593b12e3d87
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2020-09-15 18:03:26 +00:00
Shelley Chen
ad9cd687b8 mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms 
Create two new functions to fetch mrc_cache data (replacing
mrc_cache_get_current):

- mrc_cache_load_current: fetches the mrc_cache data and drops it into
  the given buffer.  This is useful for ARM platforms where the mmap
  operation is very expensive.

- mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a
  given buffer.  This is useful for platforms where the mmap operation
  is a no-op (like x86 platforms).  As the name mentions, we are not
  freeing the memory that we allocated with the mmap, so it is the
  caller's responsibility to do so.

Additionally, we are replacing mrc_cache_latest with
mrc_cache_get_latest_slot_info, which does not check the validity of
the data when retrieving the current mrc_cache slot.  This allows the
caller some flexibility in deciding where they want the mrc_cache data
stored (either in an mmaped region or at a given address).

BUG=b:150502246
BRANCH=None
TEST=Testing on a nami (x86) device:
     reboot from ec console.  Make sure memory training happens.
     reboot from ec console.  Make sure that we don't do training again.

Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-08-24 23:30:50 +00:00
Angel Pons
9addda3c41 nb/intel/ironlake: Add Generic Non-Core register definitions 
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I4d878b5dbb5a5617143240b8f5bc5b6f5a754511
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:32:20 +00:00
Angel Pons
c642a0d894 nb/intel/ironlake: Add Generic Non-Core PCI device definition 
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I8feff0d71ad70ac994e29b238d35e2c73aa92ecd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:32:12 +00:00
Angel Pons
a457e35237 nb/intel/ironlake: Add QPI Physical Layer registers 
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I44db564c757647f493e92d35602178ef8b722517
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:31:59 +00:00
Angel Pons
10993c4ad4 nb/intel/ironlake: Add QPI Physical Layer device definition 
Like the QPI Link device, there can be more of these devices on
multi-socket platforms. So, name it Physical Layer 0.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: Ia5f6e42a742bc69237de38f1833e56c8da7c4f7e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:31:47 +00:00
Angel Pons
0814357646 nb/intel/ironlake: Add QPI Link register definitions 
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: Id226a2fdcbd0fe48822c4f65746e14fb00db6b2e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:31:36 +00:00
Angel Pons
93d9517795 nb/intel/ironlake: Add definition for QPI Link PCI device 
On multi-socket platforms, there can be two QPI buses, each with its own
PCI device. We only have one QPI link on Arrandale, though. In case
support for multi-socket processors ever gets added, name it Link 0.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I6481154a2d1cc1c84c1f167a374a62af3b2cf3d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:31:22 +00:00
Angel Pons
67573371d5 nb/intel/ironlake: Add SAD DRAM register definitions 
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I66b87d15f6b741c6fc935106c35b201fbd9ab2c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:31:11 +00:00
Angel Pons
3ab19b32a2 nb/intel/ironlake: Add definition for SAD PCI device 
Let's hope this cheers up the poor System Address Decoder device.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: Ia62c05abb07216dc1ba449c3a17f8d53050b5af1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:30:50 +00:00
Angel Pons
16fe1e0246 nb/intel/ironlake: Drop D0F0_ prefix from register names 
Only some registers have such a prefix. Drop it for consistency.

Change-Id: I1ef7307d10a06db8f3c1a05bd9184f21fceb9d90
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:28:57 +00:00
Angel Pons
9333b74229 nb/intel/ironlake: Rename memory map variables 
Uppercase variable names can be confused with register definitions. Use
lowercase names instead, conforming to the coding style guidelines.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I61a28bf964ea8c2c662539825ae9f2c88348bdba
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:28:42 +00:00
Angel Pons
8bf160a9a6 nb/intel/ironlake/raminit.c: Drop unused define 
This is the only instance of `BETTER_MEMORY_MAP` in the tree.

Change-Id: I118e5b5a0f10da56e2335828477caed81c5bf855
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:28:30 +00:00
Elyes HAOUAS
e1d1fe454c nb/intel/ironlake/raminit.c: initialize 'reply.command' 
This to silent a bug found using gcc-10.
src/northbridge/intel/ironlake/raminit.c: In function 'setup_heci_uma':
src/northbridge/intel/ironlake/raminit.c:1805:11: error: 'reply.command' may be used uninitialized in this function [-Werror=maybe-uninitialized]
 1805 |  if (reply.command != (MKHI_SET_UMA | (1 << 7)))
      |      ~~~~~^~~~~~~~
cc1: all warnings being treated as errors

Change-Id: I0d13de549b6d428ac3675ee3f91eb5e42aeb25e8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42461
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-25 01:23:49 +00:00
Angel Pons
ea1953f492 nb/intel/ironlake/raminit.c: Drop dead code 
This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I36500c1f0eb3c37d08c691d22382ceca732d1355
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
 2020-07-09 23:47:13 +00:00
Kyösti Mälkki
1a1b04ea51 device/smbus_host: Declare common early SMBus prototypes 
Change-Id: I1157cf391178a27db437d1d08ef5cb9333e976d0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-06-22 11:53:31 +00:00
Patrick Georgi
6b5bc77c9b treewide: Remove "this file is part of" lines 
Stefan thinks they don't add value.

Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)

The exceptions are for:
 - crossgcc (patch file)
 - gcov (imported from gcc)
 - elf.h (imported from GNU's libc)
 - nvramtool (more complicated header)

The removed lines are:
-       fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-#  This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */

Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-05-11 17:11:40 +00:00
Patrick Georgi
ac9590395e treewide: replace GPLv2 long form headers with SPDX header 
This replaces GPLv2-or-later and GPLv2-only long form text with the
short SPDX identifiers.

Commands used:
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist)

perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)

perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)

perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)

Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2020-05-06 22:20:57 +00:00