sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
57,125 Commits 47 Branches 30 Tags
e60989db3670d02a6d67bcaa76d00b00ef593f68
Commit Graph

57125 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Martin Roth
22e16db4c5 acpi/soundwire.[ch]: Fix dpn entry array overrun 
In soundwire.h, SOUNDWIRE_DPN MIN  & MAX are set to 1 and 14. When
creating the dpn array, the length was set to MAX - MIN or 13, numbered
0 to 12.

When accessing the array, the code was bailing out if a value greater
than MAX was trying to be accessed, so the array was able to be overrun
by two structure lengths.

Fix this problem by:
1) Not subtracting the MIN value when creating the array, which does
waste a little space. If anyone wants to refactor the code to fix that,
please feel free.
2) Breaking out of the loop when the port is equal to the MAX port
number instead of just when it's greater than the max port number.

Reported-by: Coverity (CID:1429766 & CID:1429771)
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0841bb8c9869fe9f53958f05614848785a98b766
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
 2023-09-13 15:26:01 +00:00
Leo Chou
3c4e0ad561 mb/google/nissa/var/pujjo: Select VBT based on FW_CONFIG for pujjo1e 
Select pujjo1e vbt bin files based on PANEL_IVO_BOE field of FW_CONFIG.

BUG=b:299852789
TEST=emerge-nissa coreboot

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I344f97331e79e713af47ad743e27794e21be4ca3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2023-09-13 13:16:16 +00:00
Leo Chou
1db8f13bb6 mb/google/brya/var/pujjo: modify fw_config to separate pujjo1e wifi sar table 
Use fw_config for a dedicated pujjo1e intel wifi sar table.

BUG=b:293360900
Test=emerge-nissa coreboot

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I635d3d23384cc4efd85b0c420817dd18a65d2872
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77648
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-13 13:15:36 +00:00
Sean Rhodes
c7cd4a6334 soc/intel/{alderlake,meteorlake}: Remove the dummy PS0 and PS3 methods 
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8515407eb10e1a74f37ea5a80fa31533c38badec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77455
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-13 13:14:35 +00:00
Sean Rhodes
2e10a6d6f3 soc/intel/{tigerlake,meteorlake}: Check ITBT FW version 
The ensures that ITBT is ready to operate.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If60404a88208c632cd60e8aaa6ba70494eefbed2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77454
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-09-13 13:14:03 +00:00
Sean Rhodes
53048c2a54 soc/intel/{tigerlake,alderlake,meteorlake}: Start to unify the TCSS ACPI 
The ACPI used for Tiger Lake, Alder Lake and Meteor Lake are very
similar, so can be moved to shared code.

This commit aligns minor difference between then, such as comments and
tabs/spaces.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If6554c7ef9e83740d7ec5dcca6a9d7e32fb182db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77453
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-13 13:13:21 +00:00
Mario Scheithauer
90e1346d51 mb/siemens/mc_ehl5: Enable PWM passthrough mode on PTN3460 
The connected panel on this mainboard gets the PWM frequency directly
from the Elkhart Lake CPU. The PWM controls the brightness of the
backlight. Therefore, it is necessary to activate the PWM passthrough
mode in the PTN3460 eDP-to-LVDS bridge (see PTN3460 Programming Guide -
5. Configuration Registers).

Link to PTN3460 Programming Guide:
https://web.archive.org/web/20230908074244/https://www.nxp.com/docs/en/application-note/AN11128.pdf

BUG=none
TEST=Boot into Linux and change the brightness of the screen

Change-Id: Iec9d8ae22fced40c45e5bfa8989ad655a722d7ef
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77702
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-13 13:12:38 +00:00
Stefan Reinauer
b8a71b46fb Switch scripts over to use main branch 
This will be needed to switch over to main branch in coreboot

Change-Id: I90fadf2352d56074ce8b58d559a73b0c53fac14b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75782
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-13 05:44:56 +00:00
Felix Held
d30e081295 soc/amd/*/Makefile: drop wrong EFS diagrams 
The EFS data structure diagrams in the Makefiles of Picasso and newer
SoCs were wrong, since the BIOS directory table pointer is in a
different location than shown in the diagram. Since the diagram also
wasn't that easy to understand and amdfwtool does all of that handling,
drop the wrong diagram from the Makefiles.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5f86fea29f956ff10746d35dbe967a4a89e11cca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
 2023-09-12 17:57:32 +00:00
Patrick Rudolph
f372c40b90 x86/tables: Upgrade error to critical 
When more ACPI tables are written than space is available in CBMEM, the
buffer overflow corrupts other CBMEM tables and a successful boot is unlikely.

Upgrade the error message to critical and be more precise what to do.

Change-Id: I152842945f552905729265f7d623cd581dd0a8d0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
 2023-09-12 16:26:54 +00:00
Jeremy Compostella
ba7a9eefcf soc/intel/common: Fix invalid MADT entries creation 
commit f8ac3dda02 ("soc/intel/common:
Order the CPUs based on their APIC IDs") sort algorithnm walks all the
`cpu_info' entries without discarding empty ones.  Since `cpu_info' is
not initialized, the data that is used is undefined and it generally
results in the creation of invalid `Local x2APIC' entries in the
MADT ("APIC") ACPI table.

Depending on the X2APIC ID value the Linux kernel behavior
changes (cf. arch/x86/kernel/acpi/boot.c::acpi_register_lapic()):
1. If (int)ID >= MAX_LOCAL_APIC (32768), the Linux kernel discards the
   entry with the "skipped apicid that is too big" INFO level
   message.
2. If (int)ID < MAX_LOCAL_APIC (32768) (including negative) this data
   is taken into account and it can lead to undesirable behavior such
   as core being disabled as (cf. "native_cpu_up: bad cpu" ERROR
   kernel message).

TEST=Verified the MADT does not contain any invalid entries on rex.

Change-Id: I19c7aa51f232bf48201bd6d28f108e9120a21f7e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77615
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
 2023-09-12 16:08:57 +00:00
Ruihai Zhou
2a6a79c706 drivers/mipi: sta_himax83102: Completely pull GPW to VGL before TP term 
The sta_himax83102 panel sometimes shows abnormally flickering
horizontal lines. The front gate output will precharge the X point of
the next pole circuit before TP term starts, and wait until the end of
the TP term to resume the CLK. For this reason, the X point must be
maintained during the TP term. In abnormal case, we measured a slight
leakage at point X. This is because during the TP term, the GPW does not
fully pull the VGL low, causing the TFT to not be closed tightly.

To fix this, we completely pull GPW to VGL before entering the TP term.
This will ensure that the TFT is closed tightly and prevent the abnormal
display.

BUG=b:299249186
BRANCH=corsola
TEST=FW Screen display normally

Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I5dddaaa38917a65990c1474b657db5eb551940b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77692
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-12 14:40:01 +00:00
Jeremy Compostella
1eff77bc59 arch/x86: Reduce max phys address size for Intel TME capable SoCs 
On Intel SoCs, if TME is supported, TME key ID bits are reserved and
should be subtracted from the maximum physical addresses available.

BUG=288978352
TEST=Verified that DMAR ACPI table `Host Address Width` field on rex
     went from 45 to 41.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I9504a489782ab6ef8950a8631c269ed39c63f34d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-12 08:12:02 +00:00
Jeremy Compostella
a6a5b25ce4 cpu/intel: Move is_tme_supported() from soc/intel to cpu/intel 
It makes the detection of this feature accessible without the
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU dependency.

BUG=288978352
TEST=compilation

Change-Id: I005c4953648ac9a90af23818b251efbfd2c04043
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77697
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-12 08:11:17 +00:00
Elyes Haouas
e099176412 mb/packardbell: Remove space between function name and '(' 
Change-Id: Ied86fb05a3930f1bd900d106b5f3c79466a81a6d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-11 21:39:45 +00:00
Elyes Haouas
c54a967147 soc/intel: Remove space between function name and '(' 
Change-Id: I1dbfca33c437c680118eb3a92e60b5607c93e565
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77768
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-11 21:39:08 +00:00
Elyes Haouas
d3bb087360 mb/lenovo: Remove space between function name and '(' 
Change-Id: I9b1e3ad668c332bebdaf48a2e95f1f9e2131d598
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-11 21:38:13 +00:00
Elyes Haouas
fb39a2f91a mb/google: Remove space between function name and '(' 
Change-Id: I0909f24844fab3dfc859ea8c5325344a9872799f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-11 21:35:10 +00:00
Elyes Haouas
b024e23cfd arch/arm64: Remove space between function name and '(' 
Change-Id: I0cba99070f251d86679c068bb737c05178f4a7c5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77771
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-11 21:31:16 +00:00
Elyes Haouas
a4c74578ec soc/cavium: Remove space between function name and '(' 
Change-Id: I25e3cf15a77cf61a60bd31519eae019742842389
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-11 15:57:58 +00:00
Elyes Haouas
0f3075ea63 sb/intel: Remove space between function name and '(' 
Change-Id: I2e8eb3632c93b4449f108cb690f9bfd8e1ea3776
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77767
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-11 15:57:35 +00:00
Elyes Haouas
9d450b2248 nb/intel: Remove space between function name and '(' 
Change-Id: Ibffaf86f9e32d747c8f2f7a3643df8935fb00047
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-11 15:52:56 +00:00
Elyes Haouas
98a9b34854 soc/nvidia: Remove space between function name and '(' 
Change-Id: I5b0cdb7b8484080db6571d70ddef145bbaf2e87d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77769
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-11 15:51:44 +00:00
Elyes Haouas
78d2469f05 drivers: Remove space between function name and '(' 
Change-Id: I42e995952a72a23a5f3aeadf428ad13f25546854
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-11 15:51:04 +00:00
Stefan Reinauer
0d3a1fb93f Switch release scripts over to use main branch 
In preparation for switching over coreboot.

Change-Id: Id66f0def84b913fc8fdd4ee77fef996e45dbd4f5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75780
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-11 15:45:41 +00:00
Stefan Reinauer
38d8a6a570 Switch jenkins node over to use encapsulate main branch 
This is only needed once we want to recreate the docker

Change-Id: I493acb4de615508b08826f814ef6ac1b37cbdf0c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75781
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-11 06:57:26 +00:00
Stefan Reinauer
16672cab7d Switch gitconfig.sh over to use main branch 
Change-Id: Iea1a7e61b60c4bf04be2fed9c503eaf7e20fe462
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75783
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-11 06:56:59 +00:00
Stefan Reinauer
5db03ed14c Switch board_status.sh to use main branch 
... so we can switch coreboot over.

Change-Id: Ib0487014fd49829e0d021533b04df9e8bd1a757a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75779
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
 2023-09-11 06:35:43 +00:00
Elyes Haouas
dc75d3e6c1 security/intel/stm: Remove __attribute__(()) 
Change-Id: Id35a0a589128ea2dfb2f0e5873d4fa087b0886a9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-09 04:45:57 +00:00
Elyes Haouas
2dc5c6e2cc soc/amd/common: Remove __attribute__(()) 
Change-Id: I2866dcdd6900c98310b4b3736b40ebe4eaa77ea2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77719
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-09 04:45:33 +00:00
Elyes Haouas
25a7af18a5 drivers/net/ne2k: Remove space before semicolon 
Also move the semicolon on next line.

Change-Id: I68412407ec8c8f99c15f39b0ec08d4fb33eb1b3f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-09 04:44:44 +00:00
Jon Murphy
cbe975d8d8 vendorcode/eltan/security: update attribute use 
Update the use of __attribute__((weak)) to the preferred __weak

BUG=None
TEST=Builds
BRANCH=None

Change-Id: I75a0e7c03e537be2d38b7f9c6b81eafbb5fb8018
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-08 15:22:44 +00:00
Jonathon Hall
89709da1fc mb/purism/librem_cnl: Enable HDMI1 output for Mini native graphics init 
Enable HDMI1 output, which corresponds to the physical DisplayPort
connector, so passive adapters to DVI or HDMI will work with native
graphics init.

Change-Id: I95a147978697f4af092fe61ceacd2e725155d489
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2023-09-08 12:47:08 +00:00
Cliff Huang
cb362cf2bb mb/google/rex: Fix ACPI MPTS method for non-5G board SKUs 
MPTS method should only be generated for the board sku with 5G.

BUG=NA
TEST=Check kernel messages when going to S3. The following errors
should not be seen:
ACPI BIOS Error (bug):
	Could not resolve symbol [\_SB.PCI0.RP06.RTD3._STA]
ACPI Error:
	Aborting method \_SB.MPTS due to previous error (AE_NOT_FOUND)
ACPI Error:
	Aborting method \_PTS due to previous error (AE_NOT_FOUND)

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I78f434c9049773cf5229d3a1f3934ae82d1fe46d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77690
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-08 12:46:45 +00:00
Sean Rhodes
9796d4ce4f mb/starlabs/starbook/rpl: Enable the PD interrupt GPIO 
Enable the PD interrupt GPIO, GPP_B11, so that HPD works when
Thunderbolt is disabled.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie37976d58921b7a12dff16d93d7ac9bdd92edbea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-08 12:45:35 +00:00
Sean Rhodes
1e0d0a721e mb/starlabs/starbook/rpl: Correct GPP_A19 
A19 was incorrectly labelled as TCP0 HPD. It is not connected
so configure it accordingly.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I5aea723c2e8c0758d413bbc4bfd0ce92b22d0c87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-08 12:45:15 +00:00
Sean Rhodes
59453aa763 mb/starlabs/starbook/{adl,rpl}: Remove unnecessary entries 
Certain devices are enabled in Alder Lakes chipset.cb, so remove
them from the devicetree.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I929af0bed6c2e1024b4787424a8fe466edce5a36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-08 12:44:54 +00:00
Subrata Banik
3ff6b2ff9e mb/google/rex: Require VBOOT_LID_SWITCH for Chromebook design 
This patch ensures that platforms with lids, such as Chromebooks, only
select the VBOOT_LID_SWITCH configuration option.

Only samples the LID GPIO if VBOOT_LID_SWITCH config is enabled,
otherwise fake LID is open to avoid shutdown after reaching
depthcharge.

Tested by building and booting Google/Rex with the VBOOT_LID_SWITCH
configuration option enabled, and verifying that google/ovis does not
required VBOOT_LID_SWITCH config.

Change-Id: Ic5123b822a5a7021023319cb08a3f9e5225961ba
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77693
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2023-09-08 09:21:35 +00:00
Felix Singer
79503ef515 vc/intel/fsp2/alderlake_n: Drop unused header files 
Change-Id: I870fa65ff05cf5907d62b3af1b2f9c4334b62603
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77260
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-08 02:46:01 +00:00
Felix Singer
1e889d8082 soc/intel/alderlake_n: Hook up the FSP repository 
Change-Id: I57b54653bd29a728825210403c8f426eb1c9cc48
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2023-09-08 02:45:53 +00:00
Felix Singer
f957d29254 Update fsp submodule to upstream master 
Updating from commit id 3beceb0:
2023-06-30 14:45:10 +0800 - (IoT ADL-S MR5 (4081_05) FSP)

to commit id a727948:
2023-09-07 10:50:08 +0800 - (IoT ADL-N MR1 (4172_00))

This brings in 6 new commits:
a727948 IoT ADL-N MR1 (4172_00)
5030738 IoT RPL-S MR1 (4115_04) FSP
46a88ff IoT ADL-N MR1 (4172_00)
1fdadea IoT ADL-PS MR3 (4081_07) FSP
3054701 Add New Fsp, IoT ArizonaBeach MR2 (4202_00)
b5bbf8d IoT ADL-N MR1 (4172_00)

Change-Id: I90bebdc5c15c96303d88a7bc362f534397471e06
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77443
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-08 02:45:43 +00:00
Martin Roth
74f18777a2 arch to drivers/intel: Fix misspellings & capitalization issues 
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic52f01d1d5d86334e0fd639b968b5eed43a35f1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77633
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-08 00:53:57 +00:00
Elyes Haouas
cef239675b drivers/pc80/vga/vga_io: Remove unnecessary parentheses 
Parentheses are not required.

Change-Id: Iad1f766a3eb569af39030e43365e8a0a609f5944
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77706
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-07 17:35:38 +00:00
Elyes Haouas
db3e16e73c security/intel: Remove unnecessary blank line after '{' 
Change-Id: I0d2a9c30d332b16efd548433a54f974067bd281e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-09-07 17:35:19 +00:00
Elyes Haouas
19b4e6487f drivers/siemens/nc_fpga/nc_fpga: Remove space before '++' 
Change-Id: I6ff11df45ddc396391efd651f9938e04646dc0d3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77707
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-09-07 17:34:53 +00:00
Elyes Haouas
ad0b3fa83d ec/lenovo/h8/h8.c: Use sizeof() 
Use 'sizeof(ecfw)' instead of 'sizeof ecfw'.
sizeof operator should only be used for types and variables require sizeof().

Change-Id: Ifae1680917bb0ce610e6ba753741aae233a71103
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-09-07 17:34:22 +00:00
Matt DeVillier
7542ab94df mb/google/myst: Set i2c2 to hidden in devicetree 
Allows ACPI SSDT generator to hide the device from Windows via _STA

Change-Id: I41fc7f847ef08138cb0f430bfd1a170f209163f1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77681
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-07 15:59:03 +00:00
Matt DeVillier
5445d4c021 mb/google/zork: Set i2c3 to hidden in devicetree 
Allows ACPI SSDT generator to hide the device from Windows via _STA

Change-Id: I19f0a5a72ec409b306be7bc4bb53425870fc6298
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2023-09-07 15:58:44 +00:00
Matt DeVillier
95b614c0b8 3rdparty/amd_blobs: update submodule pointer 
Update submodule pointer to pull in release binaries for Mendocino SoC.

TEST=build/boot google/skyrim (frostflow)

Change-Id: Ie30415c0b47ef1302a29f8392958bb2cd1d0bda9
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77627
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-07 15:14:09 +00:00
Matt DeVillier
6695256e69 mb/google/skyrim: Set i2c3 to hidden in devicetree 
Allows ACPI SSDT generator to hide the device from Windows via _STA

Change-Id: Idb5d2cd6eca2a2746e89a371005332e9f621df83
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77675
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-07 15:13:37 +00:00