Update memory parameters based on memory type supported by Tiger lake RVP
1. Update dq/dqs mappings
2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory
3. Add SPD data bin files for supported memory types
4. Update other FSPM UPDs as part of memory initialization
BUG=none
BRANCH=none
TEST= build tglrvp flash and boot to kernel
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Correct the offset for the Topstar driver enable/disable bit,
which was off by 2 bits compared to a dump of the AMI UEFI ACPI.
This prevents the fan mode (FANM) from being inadvertently changed
and hopefully fixes some intermittent issues with fan speed on
resume from suspend.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: Ibc3c39d5b14c753eed6d1ed8cbf161717f8d04e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39105
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The indirection of names is exceedingly confusing for ultimately the single
interrupt trace of EC_PCH_WAKE_ODL between the EC gpio#74 to GPD2/LAN_WAKE# on
the PCH side.
This helps folks chase this indirection down through the code.
BUG=b:147026979
BRANCH=none
TEST=builds
Change-Id: I35d746a202dae06d2f6f1edfaa3889864b09f50d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
WWAN wake event is routed to GPP_D0 GPIO and Pen Detect wake event is
routed to GPP_C12 GPIO. Update the GPE configuration accordingly.
BUG=None
TEST=Build the mainboard.
Change-Id: Id36d2c8265a0b7ea241565f6bb723df6b37446fa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch makes all legacy 8254 FSP UPDs (Enable8254ClockGating and
Enable8254ClockGatingOnS3) depend on CONFIG_USE_LEGACY_8254_TIMER to
avoid discrepancy between S0 and S3 resume flow.
TEST=Able to boot to TianoCore without any hangs and errors, also
verified S3 resume path doesn't clock gate 8254 timer using FSP-S UPD.
Change-Id: Id6fe74a51537abbb9ff48db925e37a64e5b21f78
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39110
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The specified PNP registers PNP_MSC0-E (F0-FE) are part of the iLPC2AHB
bridge's index/value interface. They are no one-time config registers
so we can't specify a sane value in the devicetree.
Thus, drop them to stop coreboot from complaining about the missing
entries.
Change-Id: I7d7f16845c755592317f140cca66cca12032f7a6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
When specifying _PAD_CFG_STRUCT with raw hex values, a logical reset
value of 0x0 is only defined for GPD pads. For any other GPIOs this maps
to 0x3.
On the Supermicro X11 boards a value of 0x0 is set for GPP_D22 and
GPP_F23, triggering the error "gpio_pad_reset_config_override: Logical
to Chipset mapping not found".
Set the right value (0x3<<30) for the affected GPIOs.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I3ae17dfc4d90f88f5b8bc5bee49740745778a91a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch cleans soc/intel/{cnl, icl, tgl} by moving common
soc code into common/block/cse.
Supported SoC can select existing HECI_DISABLE_USING_SMM option to
select common cse code block to make heci function disable using
sideband interface during SMM mode at preboot envionment.
BUG=b:78109109
TEST=Able to make HECI disable in SMM mode successfully without any hang
or errors in CNL, ICL and TGL platform.
Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26133
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The coverity project is done, for the most part, so drop it. Expand
a bit on the scope of the toolchain binary project, and point out
that the Ghidra project already has code from GSoC 2019 but could be
developed further.
Change-Id: I7342cc3133494f69b175b11b1f8342a0f40840e7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
When compiling with GCC, use the special wrappers around ar and nm that
provide the path to the plugin they need to understand LTO object files.
These wrappers forward all other functionality to the underlying
programs, so they should otherwise be equivalent.
Change-Id: Ibdae4faabf67bf6a4bb8c38970f6189646ee74b3
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38290
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Default FSP values for "GtFreqMax" and "CdClock" UPDs are "Auto", hence
related FSP-S UPD override can be avoided from coreboot.
As per FSP-S UPD Header (FspsUpd.h)
/** Offset 0x020E - GT Frequency Limit
0xFF: Auto(Default)
**/
UINT8 GtFreqMax;
/** Offset 0x0209 - CdClock Frequency selection
0: (Default) Auto
**/
UINT8 CdClock;
TEST=Able to get Pre-OS display on ICLRVP and Dragonegg platform.
Change-Id: Ie500dd5fad5cd358ea3fad4d5c0be1b0c148584b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
