The patch defines the following helper functions:
get_cpu_scaling_factor(): Returns scaling factors of big and small core.
cpu_is_nominal_freq_supported(): Returns true if CPU supports Nominal
Frequency, otherwise false.
cpu_is_nominal_freq_supported(): Check CPU supports nominal frequency or
not.
The patch also enables CPPCv3 support for Intel Alder Lake which is
based on hybrid core architecture.
TEST=Verified Nominal Frequency and Nominal Performance are getting
updated for ADL-P small and big cores correctly.
Signed-off-by: Sridahr Siricilla <sridhar.siricilla@intel.com>
Change-Id: I963690a4fadad322095d202bcc08c92dcd845360
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The patch implements ACPI CPPCv3 package. It implements and updates the
following methods:
generate_cppc_entries(): Updates method to support CPPCv3 package
acpi_get_cpu_nominal_freq(): Calculates CPU's nominal frequency
acpi_get_cpu_nomi_perf(): Calculates nominal performance for big and
small cores.
acpigen_write_CPPC_hybrid_method(): It generates ACPI code to implement
_CPC method.
acpigen_cppc_update_nominal_freq_perf(): It updates CPPC3 package if cpu
supports Nominal Frequency. It generates ACPI code which sets Nominal
Frequency and updates Nominal Performance. It uses below calculation to
update the Nominal Frequency and Nominal Performance:
Nominal Frequency = Max non-turbo ratio * cpu_bus_frequency
Nominal Performance = Max non-turn ratio * cpu scaling factor
CPU scaling factor varies in the hybrid core environment. So, the
generated ACPI code updates Nominal Performance based on the CPU's
scaling factor.
TEST=Verified CPPCv3 package is getting created in the SSDT table.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: ravindr1 <ravindra@intel.com>
Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Don't assume that libpayload is built from a fully checked
out coreboot tree.
There's already an override when building vboot, so reuse
that override when referring to its header files.
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I503c69a593dd68b3a974fbdbb64d7bb25d6c7f63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Currently only PLD group is used to check USB port number. In the
future, we want to use custom PLD fields, so custom PLD should also be
considered when checking USB port number.
BUG=b:216376040
TEST=emerge-brya coreboot & SSDT dump in Brya test device
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Id8076a2a952de61a6f38fbdecd76e991487bf696
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Compared to Cezanne there are 3 more UARTs controllers. The PCI
interrupt index table in the new SoC's PPR #57243 Rev 1.50 doesn't
contain a PIRQ mapping for UART4. The reference code has a mapping for
this and it uses PIRQ mapping index 0x77 for UART4 and not for I2C5.
Since the I2C5 controller isn't owned by the x86 side and I didn't see
any mapping of the I2C5 controller into the x86 MMIO space, this seems
very plausible. Also add the corresponding fields to the ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I44780f5bc20966e6cc9867fca609d67f2893163d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
- Handle older CrOS firmware which lacks a COREBOOT FMAP region
- Add support for all blobs used in CrOS firmware 2013 to current
- Put extracted blobs in their own directory
Change-Id: Idaa39eca3be68a9327cead9b21c35a6c7a3a8166
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Without acpi name, acpi_device_path will return NULL.
<NULL>: Intel USB4 Retimer at GENERIC: 0.0
Replace with usb4_retimer_scope for the identify.
BUG=b:215742472
TEST=show below meaasge in coreboot log
\_SB.PCI0.TMD0.HR : Intel USB4 Retimer at GENERIC: 0.0
\_SB.PCI0.TMD1.HR : Intel USB4 Retimer at GENERIC: 0.0
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idfa8b204894409b11936e5f221c218daa206cc02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
A simple GUI to change settings in coreboot's CBFS, via the nvramtool utility.
Test on the StarBook Mk IV running coreboot 4.15 with:
* Ubuntu 20.04
* Ubuntu 21.10
* MX Linux 21
* elementary OS 6
* Manjaro 21
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I491922bf55ed87c2339897099634a38f8d055876
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
When using the default initial core display clock frequency, Metaknight
has a rare stability issue where the startup of Chrome OS in secure mode
may hang. Slowing the initial core display clock frequency down to
172.8 MHz as per Intel recommendation avoids this problem.
The CdClock=0xff is set in dedede baseboard,and we overwrite it as 0x0
(172.8 MHz) for metaknight.
BUG=None
BRANCH=dedede
TEST=Build firmware and verify on fail DUTs.
Check the DUTs can boot up in secure mode well.
Change-Id: I987277fec2656fe6f10827bc6685d3d04093235e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Commit b67c5ed [3rdparty/fsp: Update submodule pointer to newest master]
updated the FSP binaries/headers for Comet Lake, which included a change
moving PcieRpHotPlug from FSP-S to FSP-M. Unfortunately the existing
UDP in FSP-S was left in and deprecated, which allowed the change to go
unnoticed until it was discovered that hotplug wasn't working.
Since other related platforms (WHL, CFL) share the SoC code but use
different FSP packages, add the setting of the PcieRpHotPlug UPD to
romstage/FSP-M and guard it with '#if CONFIG(SOC_INTEL_COMETLAKE)'.
Test: build/boot Purism Librem 14, verify WiFi killswitch operates
as expected / WiFi is re-enabled when turning switch to on position.
Change-Id: I4e1c2ea909933ab21921e63ddeb31cefe1ceef13
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
