That vendor firmware still works after applying `me_cleaner` doesn't
mean that coreboot will also work with the same broken ME firmware.
Instead, one should first test coreboot with the original, unmodified ME
firmware to make sure coreboot works properly, and only then consider
using `me_cleaner` with coreboot. Otherwise, one would end up with a
non-booting or otherwise misbehaving system when trying to use coreboot
and `me_cleaner` without having tested coreboot with the original ME
firmware beforehand, which is hard to diagnose as the problem may only
happen when the ME isn't running normally.
Change-Id: I1626d747a99969faf7db37c10cf7d87e3977744a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Updating from commit id 4c21b57eb:
2021-07-19 11:36:07 +0000 - (pd: Fix missing polarity_rm_dts in some conditions)
to commit id e486b388a:
2022-01-12 21:11:11 +0000 - (zephyr: Update power policy for API change)
This brings in 2212 new commits.
Signed-off-by: zhixingma <zhixing.ma@intel.com>
Change-Id: I4437f09c3193ec7c89f7f9550940a0fa5464a511
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Thejaswani Putta <theja427@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Turns out 150ms isn't enough in the worst reset conditions. On guybrush
the TPM is reset in S0i3 and the CR50 is allowed to hibernate. The CR50
is woken up and initialized early during S0i3 resume. Occasionally the
CR50 isn't ready before the probe times out.
BUG=b:213828947
BRANCH=None
TEST=suspend_stress_test -c 1000
Change-Id: Ifda438080cf1ad2796c7061223a6a97b8e6e9987
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
FSP 2.3 specification introduces following changes:
1. FSP_INFO_HEADER changes
Updated SpecVersion from 0x22 to 0x23
Updated HeaderRevision from 5 to 6
Added ExtendedImageRevision
FSP_INFO_HEADER length changed to 0x50
2. Added FSP_NON_VOLATILE_STORAGE_HOB2
Following changes are implemented in the patch to support FSP 2.3:
- Add Kconfig option
- Update FSP build binary version info based on ExtendedImageRevision
field in header
- New NV HOB related changes will be pushed as part of another patch
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ica1bd004286c785aa8a431f39d8efc69982874c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Along with commit f94405219c (soc/intel/alderlake: Hook up FSP-S CPU
PCIe UPDs), we need to set cpu pcie rp flags in devicetree now.
This CL is to add proper cpu pcie flags (PCIE_RP_LTR and PCIE_RP_AER) in
all intel projects or system will be blocked at PKGC2R with root port
LTR not enable.
BUG=b:214009181
TEST=Build and DUT (Kano) can enter deeper PKGC state normally.
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: I0d8721bf1454448b7fc14655f0e4513001469a18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When using the default initial core display clock frequency (648MHz),
Jasper Lake board might have a rare stability issue where the startup
of Chrome OS in secure mode may hang during re-initializing display in
kernel graphic driver.
Bugzzy didn't show this problem so far, but Intel recommends slowing
the initial core display clock frequency down to 172.8 MHz to prevent
this potential problem.
Depend on CL: https://review.coreboot.org/c/coreboot/+/60009
The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0
(172.8 MHz) for bugzzy.
BUG=None
BRANCH=dedede
TEST=Build firmware and check the DUTs can boot up in secure mode well.
Change-Id: I592b2d7c814881074bd2fef9906f2450326c1fcd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Cannon Lake
and ensures disable_heci1() is guarded against this config.
Also, makes dt CSE PCI device `on` by default.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This reverts commit bcd7873ea8.
Reason for revert: It makes beadrix can't boot to os without depthcharge change. The depthcharge change related with fw_config and will effect other variants.
================ error log ================
...
Starting depthcharge on Beadrix...
src/vboot/util/flag.c:50 flag_install(): Gpio already set up for flag 5.
===========================================
BUG=b:204882915
BRANCH=None
TEST=Build and boot into OS.
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Id5e76fc78a56d30caf9f805a8a430f176a653bbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60849
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Pre-bootblock stages (i.e., VBOOT_STARTS_BEFORE_BOOTBLOCK) might not
have the ability to log to the UART, so their console messages are
inaccessible until the boot processes gets into the payload or OS.
This makes it difficult to debug verstage.
This feature will dump the pre-bootblock CBMEM console immediately
after the bootblock console is initialized. I chose to do this in
console_init instead of bootblock_soc_init because I wanted to have the
pre-bootblock contents dumped before the coreboot bootblock starting
message is printed.
BUG=b:213828947
TEST=Boot guybrush with PSP verstage and verify verstage logs are dumped
to the UART.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I363c93ef3ee6c5c303a6a68f88a622e2aa62594c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61012
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This function is similar to cbmem_dump_console_to_uart except it uses
the normally configured consoles. A console_paused flag was added to
prevent the cbmem console from writing to itself.
BUG=b:213828947
TEST=Boot guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3fe0f666e2e15c88b4568377923ad447c3ecf27e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Make dt CSE PCI device `on` by default.
4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1
function disable at pre-boot instead of the dt policy that uses
`HeciEnabled = 0`.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The existing Sideband access is with the PCH P2SB. There will be future
platforms which access the TCSS registers through SBI other than the PCH
P2SB. This change abstracts the SBI with common API.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia6201762fe92801ce6b4ed97d0eac23ac71ccd37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Each time the spinlock is acquired a byte is decreased and then the
sign of the byte is checked. If there are more than 128 cores the sign
check will overflow. An easy fix is to increase the word size of the
spinlock acquiring and releasing.
TEST: See that serialized SMM relocation is still serialized on
systems with >128 cores.
Change-Id: I76afaa60669335090743d99381280e74aa9fb5b1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60539
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
New CBFS API uses commonlib/bsd/cbfs_serialized.h, which includes
vboot's vb2_sha.h. And, because vboot's includes are not available
in libpayload's installation directory nor in lpgcc paths, it was
causing compilation errors. This patch fixes this issue.
lpgcc will look for `vboot` directory like it is doing for `include`
directory to create correct paths. However, if payload will be built
using libpayload's build dir as a base, then vboot headers from
3rdparty/vboot will be used, as there is no way to pass VBOOT_SOURCE
from makefile to lpgcc.
Moreover, this patch moves VBOOT_SOURCE to the main Makefile to
make it available for installation target, to install headers from
vboot directory provided by caller.
Change-Id: I68dd7e1545cfcaf24547d8a9fe289447c79da222
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reported-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This also uncouples cbfstool from being overly Chromium
specific. However the main objective is to not subprocess
flashrom any more and instead use the programmatic API.
BUG=b:207808292
TEST=built and ran `elogtool (list|clear|add 0x16 C0FFEE)`.
Change-Id: I79df2934b9b0492a554a4fecdd533a0abe1df231
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
The redrix thermal team has determined that the TCC circuit trip
temperature should be set to 97C, therefore, because the offset
is subtracted from 100C, set the `tcc_offset` register in the
devicetree to 3.
BUG=b:200134784
TEST=build and verified by thermal team
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Ifb63d63bc741b2a402328f256b43bc83e0a88a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The anahera thermal team has determined that the TCC circuit trip
temperature should be set to 97C, therefore, because the offset
is subtracted from 100C, set the `tcc_offset` register in the
devicetree to 3.
BUG=b:214088543
TEST=build and verified by thermal team
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I25b8a3d9e5fe28e9497b735c50a09994092b2243
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch applies clang-format settings to most of tests files. Some
files were fixed "by-hand" to exclude some lines, which whould be less
readable after automatic style fixing.
Moreover, some comments (mostly in tests/lib/edid-test.c) were adjusted
to match coreboot coding style guidelines.
Change-Id: I69f25a7b6d8265800c731754e2fbb2255f482134
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
DDR interfaces emit electromagnetic radiation which can couple to the
antennas of various radios that are integrated in the system, and cause
radio frequency interference (RFI). The DDR Radio Frequency Interference
Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband
RFI from DDR4/5 and LPDDR4/5 technologies for the Wi-Fi high and
ultra-high bands (~5-7 GHz). This patch sets CnviDdrRfim UPD and enables
CNVI DDR RFIM feature for brya0 variant.
Refer to Intel doc:640438 and doc:690608 for more details.
BUG=b:201724512
BRANCH=None
TEST=Build and boot with debug FSP and verify CnviDdrRfim UPD value.
Change-Id: I6ad826d0039e400f219c2d407c51762c1751a909
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
The goal when adding the new CBFS API in CB:59497 was that the old CBFS
code would be left completely untouched and just moved to the side a
bit, so that it could continue to work for the payloads that use it
until they all have time to transition to the new CBFS API.
Unfortunately, between the different iterations of the patch something
went wrong with that and the final committed version of cbfs_legacy.c
does differ in some parts from the original code, including a changed
macro definition that breaks decompression support. This patch restores
all the legacy CBFS files to exactly what they used to be (other than
the necessary changes in cbfs_core.h to avoid double definition
clashes).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ic7fd428acb03d3830f66f807cd1d7cdbd652f409
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4a81fd58df468e2711108a3243bf116e02986316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
CBFS_VERIFICATION was depending on the VBOOT instead of on VBOOT_LIB,
which made enabling CBFS_VERIFICATION impossible. VBOOT is not
available, like in the main coreboot, but is was changed to VBOOT_LIB,
and was not correctly adjusted in patch instroducing CBFS_VERIFICAITON
option.
Change-Id: Ie23bad5f0ed3faf17a2ed7a3ad99310ee803edd2
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The call to genbuild_h needs to happen after xcompile is imported so
that genbuid_h can use iasl as chosen by xcompile. Move the entire
section down to keep things together.
TEST=no more error that util/crossgcc/xgcc/bin/iasl isn't found.
Change-Id: Ia7afd32bd120e5405e65825144b0c30d69931a22
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI
bit set for any slots of already existing boards, add set the option
PcieRpSlotImplemented=1 where appropriate.
Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The patch adjusts CSE region's internal partitions' (CSE RO and Data
partition) sizes to match with sizes of MFIT generated CSE Region's
internal partitions.
BUG=b:213993778
TEST=Generate coreboot for Brya and verify with MFIT generated
coreboot.
Cq-Depend: chrome-internal:4452789
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I5418c02f83134814e3f9959ee8c8da32ce8c7bec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60951
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
