Commit Graph

55828 Commits

Author SHA1 Message Date
Tim Crawford
e96476dd65 mb/system76: Enable S0ix for darp8/darp9
The newer batch of these boards do not de-assert VW PLTRST# on S3
resume, causes the units to not power on in the EC code. Switch them to
S0ix by default, but leave S3 available.

Change-Id: I95337c1391102db9e020e82bdd938659c1a4f905
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-02-20 08:25:25 -07:00
Tim Crawford
9113e145db mb/system76: Enable EC lockdown on TGL+
Change-Id: I4b07846c404eb93ab4baf0a78a4bbffcc5d8afca
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-02-20 08:25:25 -07:00
Tim Crawford
bb54e49a54 ec/system76: Support lockdown based on EC security state
Change-Id: I202c0607c2cdac1df59f42fb41735704dd5bd95c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-02-20 08:25:25 -07:00
Tim Crawford
be0dfcd68a mb/system76: Enable dGPUs
Change-Id: I28fe45afaccd60621f2f2456af14306e18df2657
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-02-20 08:25:25 -07:00
Jeremy Soller
ed92a6d587 drivers/gfx/nvidia: Add driver for NVIDIA GPU
Add a driver for laptops with NVIDIA Optimus (hybrid) graphics. The
driver provides ACPI support for dynamically powering on and off the
GPU, NVIDIA Dynamic Boost support, and a function for enabling the GPU
power in romstage.

References:
- DG-09845-001: NVIDIA GN20/QN20 Hardware Design Guide
- DG-09954-001: NVIDIA GN20/QN20 Software Design Guide

Change-Id: I2dec7aa2c8db7994f78a7cc1220502676e248465
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-02-20 08:25:25 -07:00
Tim Crawford
b21bd87af0 soc/intel/alderlake: Add IRQ for non-existent CPU PCIe device
Device 0:01.1 does not exist on ADL-P. I assume this works because the
bridged device has function 1.

Fixes the following error in Linux:

    pcieport 0000:00:01.0: can't derive routing for PCI INT B
    snd_hda_intel 0000:01:00.1: PCI INT B: no GSI - using ISA IRQ 10

Which in turn resolves the conflict with the PCH HDA device...again:

    irq 10: nobody cared (try booting with the "irqpoll" option)
    <snip>
    [<00000000bf549647>] azx_interrupt [snd_hda_codec]
    Disabling IRQ #10

Change-Id: I9d9a0003764a1e031be578c1f406b2a5d7512de7
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-02-20 08:25:25 -07:00
Tim Crawford
f224ddbc78 mb/system76/bonw14: Enable TAS5825M smart amp
The Bonobo has 2 AMPs: one for the speakers and one for the subwoofer.

Smart AMP data was collected using a logic analyzer connected to the IC
during system start on proprietary firmware. This data is then used to
generate a C file [1].

[1]: https://github.com/system76/smart-amp

Change-Id: I5389a9890563ebd3adb20096b6225f474bc006f9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-02-20 08:25:25 -07:00
Tim Crawford
e3033b56fe mb/system76/rpl: Enable discrete TBT device
The HX board, using PCH-S, use a discrete Thunderbolt device (Intel
Maple Ridge), as opposed to a built-in one like the boards using PCH-P.

Fixes Thunderbolt on RPL-HX boards using the Maple Ridge controller.

Change-Id: I53d18f3ec5a084431e1113782c791bcb42728350
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-02-20 08:25:25 -07:00
Jeremy Soller
cfa8635d03 drivers/intel/dtbt: Add discrete Thunderbolt driver
Add a new driver for discrete Thunderbolt controllers. This allows using
Maple Ridge devices on Raptor Point PCH.

Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-02-20 08:25:25 -07:00
Jeremy Soller
868c102d2f lib,soc/intel/common/block/smbus: Use a SPD length of 512 bytes for DDR5
Change-Id: I8bdc4c676a0f571fd8f34e078f6a1c73a2e90a87
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-02-20 08:25:25 -07:00
Jeremy Soller
f6ed8684a5 soc/intel/adl: Fill in SPD data on both channels of DDR5 memory
CB:52731 introduced support for reading SPD from the EEPROM via SMBus.
Replace the now unneeded workaround for DDR5 with filling in the correct
channels for DDR5.

Change-Id: I5a92199a7cd2718e9396f0dac8257df40e4f834c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-02-20 08:25:25 -07:00
Meera Ravindranath
920d350c9f soc/common/smbus: Add support for reading spd data via smbus for DDR5
DDR5 uses a Serial Presence Detect EEPROM with hub function
(SPD5 hub device) to store the spd data.
This CL adds support to read the spd5 hub device via smbus.

BUG=b:180458099
TEST=Boot adlrvp DDR5 board to kernel

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe
2024-02-20 08:25:25 -07:00
Jeremy Soller
d241bc97c9 soc/intel/alderlake: Hack to preserve SBREG
Change-Id: Ie70905d34a4050aeff4b5cda116eb700f19a18ea
2024-02-20 08:25:25 -07:00
Tim Crawford
70657e373f security/tpm/tspi: Do TPM Restart if TPM Resume fails
The Infineon SLB 9672 on newer Clevo machines regularly fails TPM Resume
on S3 with the error `TPM_RC_VALUE`.

Per TPM2 spec, handle the failure by performing a TPM Restart.

> The startup behavior defined by this specification is different than
> TPM 1.2 with respect to Startup(STATE). A TPM 1.2 device will enter
> Failure Mode if no state is available when the TPM receives
> Startup(STATE). This is not the case in this specification. It is up
> to the CRTM to take corrective action if it the TPM returns
> TPM_RC_VALUE in response to Startup(STATE).

Fixes the following error from being repeatedly logged in Linux:

> kernel: tpm tpm0: A TPM error (256) occurred attempting get random

Ref: Trusted Platform Module Library, Part 1: Architecture, rev 1.59
Change-Id: I3388007d4448c93bd0dda591c8ca7d1a8dc5306b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-02-20 08:25:25 -07:00
Jeremy Soller
8d5df37c79 intel/block/pcie/rtd3: Also implement _PR3
Change-Id: Id7f4373989dffe8c3bc68a034f59a94d2160dd15
Signed-off-by: Jeremy Soller <jeremy@system76.com>
2024-02-20 08:25:25 -07:00
Jeremy Soller
ed35db9071 intel/block/pcie/rtd3: ACPI debug messages
Change-Id: Icc4a882ff73f62a134b92f1afb0dc298ea809189
Signed-off-by: Jeremy Soller <jeremy@system76.com>
2024-02-20 08:25:25 -07:00
Tim Crawford
f2182a3f95 submodules: Use absolute paths
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: If03415f80a6028e263e76a9e3cc10df0cde5cc3c
2024-02-20 08:25:25 -07:00
Martin Roth
4845b69db2 Documentation: Release notes for the 24.02 release
These will be updated and finalized after the release to capture any
final changes, remove "upcoming release", and finalize all stats.

Change-Id: Idc224c43f2459faabf91a9ef282bb9eaeba42240
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80617
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
24.02
2024-02-20 01:50:51 +00:00
Matt DeVillier
be23f04ce7 soc/intel/cannonlake: select SOC_INTEL_COMMON_BLOCK_DTT
Select this at the SoC level (like other modern Intel SoCs), and drop
it from individual boards which selected it.

Change-Id: I838ada7dfe948c58a5bb9805ade289b07368aa63
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-19 18:09:20 +00:00
Matt DeVillier
320adcbe35 mb/purism/librem_cnl: Drop selection of USE_LEGACY_8254_TIMER
It's not needed other than for booting w/SeaBIOS, where it is already
selected by default, and enabling it with edk2 payload prevents Linux/
Windows from fully entering S0ix.

TEST=build/boot purism/librem_cnl (Mini v2), verify Win11/Linux able
to enter and exit S0ix properly.

Change-Id: I974a82bedc4e06f48ce801f2bc0c29afbd80ffcf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80602
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-19 18:06:30 +00:00
Sean Rhodes
60acd827b3 mb/starlabs/starbook: Always include the tcss.asl
The tcss.asl doesn't just relate to tcss, it is required for core
scheduling, so include it for all platforms.

Change-Id: I781ba8756e06133799e8d6d91302968cc3ea0a56
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80485
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-19 17:45:48 +00:00
Sean Rhodes
00b81adfed soc/intel/alderlake: Include ADL-N ID 5 0x4618
This patch adds support for using ADL N 4-core MCH ID 0x4618.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3e4855ce93666c54ab35def9b58e4b13bc9a8672
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-19 17:42:44 +00:00
Sean Rhodes
ccd18d1bb4 soc/intel/common: Add ADL_N ID 5 0x4618
This patch adds ADL N 4-core MCH ID 0x4618.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I47bd8fa991a48d30be4975b7965f2c3c859836dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80487
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-19 17:42:20 +00:00
Felix Singer
17e48e8530 util/liveiso/nixos: Install lm_sensors package
Change-Id: I6b027ed39d3ee81878e069142c2d7212f3dc0a6f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
2024-02-19 14:46:34 +00:00
Nico Huber
2bc4b934c3 soc/intel/tigerlake: Drop redundant PcieRpEnable
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.

Thanks to Nicholas for doing all the mainboard legwork!

Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79920
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-19 13:19:26 +00:00
Nico Huber
3d80d14cd4 soc/intel/jasperlake: Drop redundant PcieRpEnable
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.

Thanks to Nicholas for doing all the mainboard legwork!

Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-19 13:18:17 +00:00
Kevin Yang
9bf38c7d67 mb/google/dedede/var/beadrix: Disable un-used C1 port by daughterboard
Probe usb ports by FW_CONFIG setting to disable C1 port on
beadrix poin2 new daughterboard without C1 port.

BUG=b:316365055
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot

Change-Id: I494a922d2b04dcf7bd35680f5d95f8463e225f2d
Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
2024-02-19 13:15:33 +00:00
Kevin Yang
3ebe14f3b6 mb/google/dedede/var/beadrix: Generate SPD ID for supported memory part
Add beadrix supported memory parts in mem_parts_used.txt, generate
SPD id for this part.

1. CXMT CXDB4CBAM-ML-A

BUG=b:321830738
TEST=Use part_id_gen to generate related settings

Change-Id: I3a6925395b52dc7aa5c0f93b8820099369db4dbf
Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
2024-02-19 13:15:03 +00:00
Patrick Georgi
7691e96ab1 cbfstool: Support 64bit addresses for flat images
SELF has the fields wired up for 64bit, but adding flat images cuts the
upper half.

Change-Id: I3b48b8face921e942fb0e01eace791ad3e1669a0
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80576
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18 21:36:08 +00:00
Maximilian Brune
6270e74025 arch/riscv/Makefile.mk: Fix OpenSBI compilation
1. romstage.S should only be included if we have a separate romstage
2. FW_JUMP and FW_DYNAMIC are opposing options and we only support
   FW_DYNAMIC

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic14fa77d2f223664b9faba048b759e03efffcde8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79952
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-18 07:53:27 +00:00
Maximilian Brune
732134932b util/crossgcc/buildgcc: Compile RISC-V GCC with medany
currently the HiFive Unmatched mainboard produces the following error:
```
util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/rv64imafdc/lp64d/libgcc.a
(_clzsi2.o): in function `__clzdi2':
util/crossgcc/gcc-13.2.0/libgcc/libgcc2.c:690:(.text+0x1e): relocation
truncated to fit: R_RISCV_HI20 against symbol `__clz_tab' defined in
.rodata section in util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/
rv64imafdc/lp64d/libgcc.a(_clz.o)
```

This is due to the fact that the libgcc.a library is compiled with the
medlow code model but the mainboards are compiled with the medany code
model.

Changing the code model of the GCC libraries to the medany code model
fixes the issue.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: If5f07ce034686dd7fec160ea76838507c0ba7fa0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80139
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18 07:53:09 +00:00
Patrick Rudolph
8bbc07ef23 soc/intel/xeon_sp/spr: Don't leak memory
Only call fill_pds() once to prevent leaking memory. Previously it was
called for every active stack on every socket.

Only call dump_pds() once to prevent spamming the console with the same
information.

Drop the return value since it's always returning success.

Change-Id: Ifa9609e9da086dc9731556014ea9b320b270d776
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-18 07:51:51 +00:00
Patrick Rudolph
eba383c20c soc/intel/xeon_sp/uncore: Don't print uninitialized memory
The struct map_entry has two zero'd entries due to the ifdef
being used. Do not read those entries and do not print those
entries.

Fixes a NULL string being printed along as the vendor and device
ID of the PCI device.

Change-Id: Id87ced76af552c0d064538f8140d1b78724fb833
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80546
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-18 07:51:00 +00:00
Patrick Rudolph
7d4155e6e6 util/cbfstool/linux_trampoline: Support more e820 entries
Since linux commit f9ba70535dc12d9eb57d466a2ecd749e16eca866
"[PATCH] Increase number of e820 entries hard limit from 32 to 128"
made in 2005 the number of e820 entries passed from the bootloader
is 128. Use the boot protocol version to check for support of
128 entries and use them if necessary.

Tested on IBM/SBP1:
Fixes booting a Linux payload when more than 32 entries are present
in the memory table, which can easily happen on a 4 socket platform.

Change-Id: Iec0a832fff091b6c3ae7050ef63e743a30618f25
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-18 07:50:28 +00:00
Matt DeVillier
29f7c4f0a6 mb/purism_librem_cnl/var/*: Drop redundant entries in overridetrees
Now that the baseboard uses chipset devicetree references, remove
all references whose value is identical to the chipset devicetree
default or the baseboard default, since they are pointless clutter.

TEST=build/boot purism/librem_cnl (Mini v2), verify output of lspci
and lsusb unchanged before and after patch.

Change-Id: I12498e7261dafd7ee59fe79926532399392d1b09
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80600
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18 05:34:07 +00:00
Matt DeVillier
3d638a19fd mb/purism/librem_cnl: Drop devicetree entries identical to chipset.cb
Now that the board uses chipset devicetree references, remove all
references whose value is identical to the chipset devicetree default,
since they are pointless clutter.

TEST=build/boot purism/librem_cnl (Mini v2), run lspci and verify output
unchanged before and after patch.

Change-Id: I6c656d227962548cebde61f1d82333837adbbf56
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80599
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18 05:34:01 +00:00
Subrata Banik
e29c3e748d soc/intel/mtl: Skip RW CBFS ucode update if RO is locked
This patch eliminates coreboot from loading microcode from RW CBFS
(when the RO descriptor is locked, which indicates a fixed RO image)
because the kernel can already patch the microcode on BSPs and APs
while booting to OS.

This may be a chance to lower the burden on the AP FW side because
patching microcode on in-field devices is subject to firmware updates,
which are rarely published and, if required, must go through the
firmware qualification testing procedure (which is costly, unlike
kernel updates for ucode updates).

1. The FIT loads the necessary microcode from the RO during reset.
2. Reloading microcode from RW CBFS impacts boot time
   (~60ms, core-dependent).
3. The kernel can still load microcode updates.

ChromeOS devices leverage RO+RW-A/RW-B booting. The RO's microcode is
sufficient for initial boot, and the kernel can apply updates later.

BUG=none
TEST=Verified boot optimization; in-field devices skip RW-CBFS microcode
loading when RO is locked.

Change-Id: Ia859809970406fca3fa14e6fa8e766ab16d94c8a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
2024-02-18 03:13:45 +00:00
Matt DeVillier
c9c88fb598 soc/intel/jasperlake: select SOC_INTEL_COMMON_BLOCK_DTT
Select this at the SoC level (like other modern Intel SoCs), and drop
it from individual boards which selected it.

Change-Id: I8ebb915fbc21f82e39304473b0fcaa620559b5d5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80558
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18 02:29:36 +00:00
Matt DeVillier
88d5807314 mb/intel/tglrvp: Drop selection of SOC_INTEL_COMMON_BLOCK_DTT
It's already selected at the SoC level, so selecting at the board
level is redundant.

Change-Id: Ifbe7f88858b9e5e8e5185dbff5853186fd3c66cb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80557
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-18 02:29:15 +00:00
Matt DeVillier
76c7176e59 soc/intel/common/block/dtt: Add ACPI stub for TCPU device
Add an ACPI stub containing the TCPU device in proper scope, along with
the device status, on boards not using the DPTF driver, so that there
exists an ACPI device to be referenced from the PEPD LPI constraint
list.

Adding the stub fixes an AE_NOT_FOUND ACPI error under Linux for
_SB.PCI0.TCPU on boards with the SA thermal device enabled but which do
not use the Intel DPTF driver.

TEST=build/boot Linux,Win11 on purism/librem_cnl (Librem Mini v2).

Change-Id: I926d0461e5e0dfaf606102575c2be555a6bfb695
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-18 02:28:41 +00:00
Matt DeVillier
8c1bcb7fcb soc/intel/alderlake/acpi: Drop ACPI stub for SATA device
This is now generated by acpigen in the common/block/sata module.

Change-Id: Ic45a059f47a090aa1993e83884408a82826b30cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-18 02:28:12 +00:00
Matt DeVillier
1f250767ed soc/intel/common/block/sata: Fix scope for SATA ACPI device
acpi_device_path() includes the device name, so we end up with:
Scope (\_SB.PCI0.SATA) {
    Device (SATA) {
...

Fix this by using acpi_device_scope() instead.

TEST=build/boot purism librem_cml (Mini v2), dump ACPI and verify
SATA device scope correct.

Change-Id: Ibbc8890d93b22f0ecba4b3a9b0531994574b3d55
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80554
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18 02:28:05 +00:00
Martin Roth
e623845df6 mb/*: Add SPDX headers for cmos.default files
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib7beed7218f317bc2352b65a6191ef1cdaa0742d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2024-02-18 02:04:03 +00:00
Martin Roth
7d86f34398 soc: Add SPDX license headers to Kconfig files
Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18 02:03:37 +00:00
Martin Roth
9712f10f75 mb/samsung to mb/up: Add SPDX license headers to Kconfig files
Change-Id: Ied455ff29b151fb5f4bca26a189b1d4104d8cede
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80595
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18 02:03:13 +00:00
Martin Roth
39065ef5f7 mb/opencellular to mb/roda: Add SPDX license headers to Kconfig files
Change-Id: Ia2100d26027a7f71739d5445f781b52c517ed966
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80594
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18 02:02:44 +00:00
Martin Roth
af6616fd86 mb/inventec to mb/ocp: Add SPDX license headers to Kconfig files
Change-Id: Ib1bbf22480783f63fc2d729b94251e755d2f1720
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80593
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18 02:02:15 +00:00
Martin Roth
41a8997357 mb/getac to mb/intel: Add SPDX license headers to Kconfig files
Change-Id: Id859c981d0bf5dcf90bf6858607a9fe726516309
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18 02:01:52 +00:00
Martin Roth
26bcee0a21 mb/cavium to mb/foxcomm: Add SPDX license headers to Kconfig files
Change-Id: Ib100a677935cf3309a380952c35e9060e64433cb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18 02:01:17 +00:00
Martin Roth
e9af73d419 mb/51nb to mb/bytedance: Add SPDX license headers to Kconfig files
Change-Id: I71dc3dd270b9a61c86b59031f898af37f0fea345
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80590
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18 02:00:56 +00:00