stapm_time passed to smu via agesa is in msec. With earlier value
smu was getting stapm_time as 2.5 sec instead of 2500 sec and thus
causing issue in S3, and audio in PsppBalanceLow state.
BUG=b:117569918, b:117252463
TEST=
1.) audio works with PsppBalanceLow
2.) S3 cycles
Change-Id: I673e7e673d042918dff47141f37bbca354f5c45c
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/29027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Bounce buffers used to be used in those cases where the payload
might overlap coreboot.
Bounce buffers are a problem for rampayloads as they need malloc.
They are also an artifact of our x86 past before we had relocatable
ramstage; only x86, out of the 5 architectures we support, needs them;
currently they only seem to matter on the following chipsets:
src/northbridge/amd/amdfam10/Kconfig
src/northbridge/amd/lx/Kconfig
src/northbridge/via/vx900/Kconfig
src/soc/intel/fsp_baytrail/Kconfig
src/soc/intel/fsp_broadwell_de/Kconfig
The first three are obsolete or at least could be changed
to avoid the need to have bounce buffers.
The last two should change to no longer need them.
In any event they can be fixed or pegged to a release which supports
them.
For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the
value needed in 1999 for the 32-bit Linux kernel, the original ramstage)
to 0xe00000 (14 Mib) which will put the non-relocatable x86
ramstage out of the way of any reasonable payload until we can
get rid of it for good.
14 MiB was chosen after some discussion, but it does fit well:
o Fits in the 16 MiB cacheable range coreboot sets up by default
o Most small payloads are well under 14 MiB (even kernels!)
o Most large payloads get loaded at 16 MiB (especially kernels!)
With this change in place coreboot correctly still loads a bzImage payload.
Werner reports that the 0xe00000 setting works on his broadwell systems.
Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tune I2C params for I2C buses 0, 5, 6, and 7 to ensure that the
frequency does not exceed 400KHz.
BUG=b:117298114
TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency
under 400 KHz
Change-Id: Id608aae7edf54a24f364606dd7952521d1d67c1a
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/29021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
A colon usually indicates that something related follows. But in
Documentation/releases/index.md, nothing followed. Fix this by swapping
two lines.
Change-Id: I3e2750c208a2b725145b94615f64381ac763f0dc
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change sets PCIEXPWAK_DIS in PM1_EN register if WAKE# pin is not
enabled on the platform. This is required to prevent unnecessary wakes
if the WAKE# pin remains not connected on the platform. Function to
set PCIEXPWAK_DIS gets called in normal boot path (BS_PAYLOAD_LOAD) as
well as S3 resume path (BS_OS_RESUME).
BUG=b:117284700
TEST=Verified that no spurious wakes are observed on nocturne.
Change-Id: Iea93baffc9bb703c0ffedacafc6a9a9410c7ebfe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Need to tune I2C bus 0 clock frequency under the 400KHz
since this bus attached the Stylus EMR pen and need meet the spec.
Bug=b:117297214
TEST=flash coreboot to the DUT and measure I2C bus 0 clock
frequency whether under 400KHz
Change-Id: I06d9d25f52d7f641d937de0d6b7df3d7a076fbf9
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28973
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The dimm_info and memory_info structs are used in devices that
don't strictly use DIMMs. Those platforms have the DRAM soldered
down so there's no DIMM part number that encapsulates the DRAMs
used in the DIMM. The full part number is desired to be exposed in
the SMBIOS tables. As such extend DIMM_INFO_PART_NUMBER_SIZE to 33
to accommodate longer part numbers
'MT53B256M32D1NP-053 WT:C' is one of the longer part numbers that
are desired to be maintained.
BUG=b:115697578
Change-Id: I0c39dd1d1c2f0776d70d8c4d8d56719779ff82ae
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/28978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use the new I2C slave reset function and reset all slaves connected to all
4 I2C. Do this in all boards.
BUG=b:114479395
TEST=Added debug code. Build and boot grunt. Examined output, confirmed
GPIO pins changing as required. Removed debug code.
Change-Id: Ia78ee5d5319d3c1a7daa9c56c81d435999b3a359
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28575
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD's SOC do not wait for I2C transactions to complete before executing
a reset. Because of this, it's possible for the reset to happen in the
middle of a transaction, resulting on a slave hang. There are 2 possible
solutions:
If the slave has a reset pin connected to a GPIO pin, it can be used to
reset the slave, else the only solution is to bang SCL 9 times. Create
code that makes it easy to implement SCL bang, using a devicetree
register to define which I2C SCL lines needs to be reset.
BUG=b:114479395
TEST=Build and boot grunt. Look at transactions on a scope.
Change-Id: I7f74b7e45c509044825355874753969f074e2382
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28574
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clean up Kconfig file in order to support variants for fizz. Add
BOARD_GOOGLE_BASEBOARD_FIZZ that can be set by various fizz variants
to use the common baseboard configs.
BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
Change-Id: I9c89f1dc526a9d623e1ae4d4b52a923489b389d3
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There is no datasheet available for this SuperIO, but dumping all
possible registers on a Dell Optiplex GX520 resulted in data that was
similar to other supported chips. Data also matches what is set in the
BIOS, e.g. the parallel and serial ports' addresses.
Change-Id: I768e4b5ec1e73c53e1a2355e0a0657b7a5ccbb89
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Legacy PME are enabled by default in FSP-S UPD. This policy sets
PME Interrupt Enable (PIE) bit of RCTL register to trigger interrupt
generation when RSTS.PS state has changed (either due to 0->1 transition
or due to this bit being set with RSTS.PS already set). Due to this
interrupt generation, system wakes from sleep immediately it enters.
This patch overrides root port legacy pme upd policy from coreboot to
ensure no false SCI is triggerd when system is in S3/S0ix state.
BUG=b:113083354
BRANCH=none
TEST=Able to make S3 resume using wake on wifi connect/disconnect usecase
without any failure.
Change-Id: I779fac711eeeed65ea379fad1cc400052d8a00eb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The SCH3112, SCH3116 and SCH5127 were lacking a pin dump. Since their
datasheets are available, add their pin dumps.
The SCH3112, SCH3114 and SCH3116 are almost identical, they only differ
in the number of serial ports. Some values in the SCH3114 dump were
inaccurate, that has been fixed as well.
Datasheets used:
- SCH311X: DS00001872A
- SCH5127: DS00002081A
Change-Id: Ic985526be9b09e0452eaf883904dfaf709b7e907
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Setting default PSPP setting to BalancedLow was causing audio
playback issue in most of the units. With BalancedLow either there
was no sound or noise on playback.
Switching to BalancedHigh as default option.
BUG=b:116553085, b:112020107
TEST=Test playback and hear proper audio.
Change-Id: Ibf64d7b8e58e60ce931ddc85f11b135708cdb1ee
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/28967
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Wifi wake register is incorrectly set in devicetree.
Set wifi wake to its correct wake source, GPE0_DW2_01.
BUG=b:117330593
TEST='emerge-nocturne coreboot chromeos-bootimage', flash nocture,
connect wifi to a hotspot, suspend device, echo freeze >
/sys/power/state, and then shutdown the hotspot and verify device
wakes.
Change-Id: Iafa865ca79d33541d7f47b69d2fb209e7f9c98af
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28938
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The WAKE# signal has moved to LAN_WAKE, so WAKE# is now
floating and must be disabled. This change disables WAKE#.
BUG=b:117284700
TEST=none
Change-Id: I1c25e4ba28cd2b8807cd155d47c29c0d3ee9e8a5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
* Convert PNG to JPG and reduce image quality.
* Mark flash IC and USB serial connector.
* Mark SPI programming header.
* Add programming header pinout.
Change-Id: Ica5958545ed23573a0d48dfa422ad1a822d06b47
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* Add Makefile dependency to source file
* Add argument support
* Add help support
* Print usage on wrong arguments
* Add support for parsing VBT binary file
* Add support for parsing PCI Option ROM
* Add support for writing VBT binary file
* Add support for patching PCI Option ROM
* Keep support for accessing legacy VGA area Option ROM
* Keep support for dumping VBT contents to stdout
Allows to extract VBT, analyse VBT and patch PCI Option ROMs as needed.
The required arguments have been changed:
./intelvbttool --<SOURCECMD> [filename] --<DESTCMD> [filename]
SOURCECMD set the VBT source. Supported:
inlegacy : Legacy BIOS area at phys. memory 0xc0000
invbt : Read raw Intel VBT file
inoprom : Read VBT from Intel Option ROM file
DESTCMD set the VBT destination. Supported:
outdump : Print VBT in human readable form
outvbt : Write raw Intel VBT file
patchoprom: Patch existing Intel Option ROM
Any combination of SOURCECMD and DESTCMD is possible.
Change-Id: I8cbde042c7f5632f36648419becd23e248ba6f76
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
RISC-V is not a project of the University of California, Berkeley,
anymore; it stands on its own feet now.
Remove the "UCB" component from the RISC-V mainboards in the "emulation"
directory, and don't set MAINBOARD_VENDOR to UCB, either.
Change-Id: I301d9d0091a714e62375052e5af06a9197876688
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
