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Author SHA1 Message Date
Elyes HAOUAS
6c78420bcb soc/intel/braswell/romstage/romstage.c: Use __func__ 
Change-Id: I07d36fb9b499e64eaba8829073c040792a2fee6e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-26 20:52:35 +00:00
Elyes HAOUAS
f984aecc02 device/pci_device.c: Use __func__ 
Change-Id: Ia6c7de99164682dcbcc375969403d2bfb9675f3c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-26 20:52:10 +00:00
Angel Pons
aded1d7fd0 arch/x86/car.ld: Fix up blob reserved regions 
Drop duplicated assignment that rewound `.` back, and broke platforms
using MRC.bin and DCACHE_RAM_MRC_VAR_SIZE.

Tested on out-of-tree Acer E5-573 (Broadwell), fixes booting.
Also tested on Asrock B85M Pro4 (Haswell), also fixes booting.

Change-Id: I3f0153f776c07acf7cf92808b677b118c60507c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49909
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-26 18:01:16 +00:00
Angel Pons
aaa4a0d39e cpu/intel/common/fsb.c: Add Broadwell CPUID models 
Like Haswell, Broadwell has a "FSB" speed of 100 MHz. Add the IDs for
both the traditional and ULT variants of Broadwell, because the CPU
driver for Haswell already contains CPUIDs for both Broadwell types.

Without this patch, Broadwell CPUs would hang when trying to print the
first console log message, but only if flashconsole was not enabled.

This was missed in commit f542b7bcef (cpu/intel/haswell: Add Broadwell
CPUIDs and microcode) and went unnoticed until now because the tests
were done with flashconsole enabled, which somehow boots properly even
though the console time tracking would not work (depends on TSC).

Tested on out-of-tree Acer E5-573, fixes booting without flashconsole.

Change-Id: I78a1696771d4d6d2138ec432dc0d8e030f14293b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49939
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-26 17:29:20 +00:00
Zheng Bao
64d0ad347b soc/amd: Add an option to select if SOC supports ESPI sub decode 
Cezanne doesn't have eSPIx00034 register define in PPR. Currently only
Picasso need this option.

Change-Id: Icb8e8a1a59393849395125108bfaa884839ce10f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-01-26 15:51:36 +00:00
Eric Lai
56868b8045 mb/google/brya: Add memory DQ map 
Add memory DQ map based on latest schematic.

BUG=b:174266035
TEST=Build Test

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I94102240b13d2b95e0295f41bc2c0ba078faf242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48446
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-26 10:38:49 +00:00
Felix Held
3ebfd3fb1c mb/google/zork/Kconfig.name: remove double space in board variant names 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If0bc153cd3a3391b1607848436f0ab5fcd54ce7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-26 10:37:27 +00:00
Johnny Lin
38cb7c1615 mb/ocp/deltalake: Replace space with underscore in Locator string 
Per Facebook BIOS requirements 'Locator' field should not
have any space between words.

Tested=On OCP Delta Lake, dmidecode -t 17 to verify.

Change-Id: I2f6f1b2590c55d6da4ca32aef2f50eb332f441dc
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-26 10:37:10 +00:00
David Wu
1f7a39eaf6 mb/google/volteer/var/voema: Add camera ACPI configuration 
Add camera ACPI configuration for Voema

BUG=b:169551066
TEST=Build and boot Voema. Start camera app and able to
capture images.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I903e5e0b5f85718c7c9cbb6d5cafb8fc9ad5814e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jim Lai <jim.lai@intel.com>
 2021-01-26 10:36:49 +00:00
Marc Jones
05a480acea ocp/deltalake: Set C-State config 
Set the supported C-State to C1 and C6. This matches the states in
CPUID(5).

Change-Id: If32b8256097b5b2bee7fb074fab105e4b54d14b3
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49803
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-26 10:35:04 +00:00
Marc Jones
31ed8856f9 soc/intel/xeon_sp/acpi.c: Add ACPI C-State table 
Add the soc ACPI _CST table.
The table may be customized to support the different state
combinations and set by the mainboard config.

Tested on deltalake with acpi_idle driver.
Note, intel_idle may not use ACPI _CST table.

Change-Id: I359daa9556edbe263ab0a7f1849c96c8fe1a0da0
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
 2021-01-26 10:34:56 +00:00
Marc Jones
08de06ad6d soc/intel: Move c-state resource define 
De-duplicate the MWAIT_RES define. Move it to intel/common/block.

Change-Id: I43903e4f02a549f53101e79f6febd42f2e54f98f
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49802
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-26 10:34:52 +00:00
Kyösti Mälkki
3c18186e76 sb,soc/intel: Refactor power_on_after_fail option 
It's only necessary to call get_option() with SLP_TYP S5.

Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49251
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-26 09:14:27 +00:00
Kyösti Mälkki
22236a580d cpu/x86/smm: Remove unused APMC for C-state and P-state 
Change-Id: I7a3a1b63c0ef14b1e24ecce2df66f7970e5eb669
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-26 09:14:15 +00:00
Kyösti Mälkki
9e591c409a soc/amd: Refactor some ACPI S3 calls 
Do not pass ACPI S3 state as a parameter, by locally
calling acpi_is_wakeup_s3() compiler has better chance
for optimizing HAVE_ACPI_RESUME=n case.

Test for acpi_s3_allowed() is already included in the
implementation of acpi_is_wakeup_s3() and is removed
as redunandant.

For ramstage, acpi_is_wakeup_s3() evaluates to
romstage_handoff_if_resume().

Change-Id: I6c1e00ec3d5be9a47b9d911c73965bc0c2b17624
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49838
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-26 00:17:38 +00:00
Angel Pons
f9acd37d7f mb/google/auron: Use get_gpios function 
Change-Id: I91424a45ae67186987630b7686102f467f57e7ee
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-25 23:43:40 +00:00
Raul E Rangel
75f6ab35ff soc/amd/picasso: Change GPIO _HID to AMDI0030 
This matches the _HID used in the picasso UEFI bios.

BUG=none
BRANCH=zork
TEST=boot linux and verify peripherals still work

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ieb441696cbe67a772632990347c12d1d15cfaf13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-01-25 23:09:58 +00:00
Raul E Rangel
8ace387090 soc/amd/picasso/acpi: Change I2C _HID to AMDI0010 
This is the new _HID that was used for Raven. It matches the _HID used
by the picasso UEFI bios.

This does change the fixed clock used by linux from 133 MHz to 150 MHz.

BUG=none
BRANCH=zork
TEST=boot linux and verify touch screen and touchpad still function

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I37fcb4a4f0148f4843d026902d694c03aeed3c3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-01-25 23:09:38 +00:00
Raul E Rangel
4389bbc55d soc/amd/picasso/acpi: Change UART _HID to AMDI0020 
This is the new _HID that was used for Raven. It matches the _HID used
by the picasso UEFI bios.

BUG=none
BRANCH=zork
TEST=boot linux and verify UART still works

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I138cb445c84997f4a4006cbb4f6617dac25a61b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-01-25 23:09:22 +00:00
Angel Pons
e53534eead soc/intel/denverton_ns: Drop unused pattrs.h 
Change-Id: I78ff11a56b38c4bc4f4f00115de1af4b73d4448c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-25 19:32:28 +00:00
Furquan Shaikh
a1c247b55d soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driver 
This change uses the newly added meminit block driver and updates ADL
SoC and mainboard code accordingly.

BUG=b:172978729

Change-Id: Ibcc4ee685cdd70eac99f12a5b5d79fdbaf2b3cf6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2021-01-25 19:14:19 +00:00
Zheng Bao
13d6a4647d soc/amd/picasso: Use makefile variable to locate UCODE 
Change the hardcoded location of microcode patches to using
FIRMWARE_LOCATION.

Change-Id: Iae3d159aa5413a416c54935ab7a809d0f4ff776f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49734
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 17:08:24 +00:00
Kyösti Mälkki
08bd2077bf soc/amd/common: Refactor ACPI wake source 
Change-Id: I5cb65e131bf2a35c4305ea971812d9799b964c4d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49837
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 17:05:43 +00:00
Kyösti Mälkki
b0db813523 soc/amd: Refactor ACPI power state and ELOG 
Change-Id: Ib7423c8d80355871393c377ebaffdfe2846d8852
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-25 17:01:12 +00:00
Kyösti Mälkki
b218c20c00 sb,soc/intel: Remove no-op APMC for C-state and P-state 
Change-Id: I3c1aa7f68eb03f04ddb9c1a5e960e3e2050a029c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49250
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 10:37:13 +00:00
Kyösti Mälkki
c1d524b8c6 sb/intel/common: Change some SMI logging 
Change-Id: Ief0c3d36e6de6e18b7f2613f043ac4d31a193f9d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49249
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 10:35:46 +00:00
Kyösti Mälkki
9a1620f4ed cpu/x86/smm: Use common APMC logging 
Unify the debug messages on raised SMIs.

Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49248
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 10:35:23 +00:00
Wisley Chen
5e6e5c11c7 mb/google/dedede/var/drawcia: Add support to handle pen detection 
For board version 6 afterward, it will have external pull-up for
GPP_C12, and remove internal pull-up.

BUG=b:177618684
TEST=emerge-dedede coreboot, check evtest if SW_PEN_INSERTED event
(value:1/0) when insert/eject pen, and eject pen to wake system from s0ix

Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I503873afb48384168dcd8a822c7246655898356e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
 2021-01-25 09:11:57 +00:00
chenzanxi
8130959d01 mb/google/kukui: Add panel for Katsu 
Declare the following panel for Katsu:
- BOE_TV105WUM_NW0
- STA_2081101QFH032011_53G

BUG=b:176523929
TEST=build Katsu image passed
BRANCH=kukui

Change-Id: I59a02198bc0e13f2760677ae4ea3eb05eb883464
Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2021-01-25 09:11:31 +00:00
Chris Wang
5e0db41602 mb/google/zork: adjust the eDP panel power sequence 
set pwron_varybl_to_blon to 0x5, which means fw will delay 20ms between backlight
on and vary backlight.

BUG=b:171269338
BRANCH=zork
TEST=Build; Verify the UPD was passed to system integrated table; measure
the power on sequence on dalboz

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2021-01-25 09:11:17 +00:00
Chris Wang
3ec3cb82f9 soc/amd/picasso: Add UPDs for support eDP power sequence adjust 
Add UPDs for eDP power sequence adjust
all pwr sequence numbers below are in uint of 4ms.

BUG=b:171269338
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48864
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 09:11:03 +00:00
Chris Wang
27b149c30b soc/amd/picasso: Add UPDs for support eDP power sequence adjust 
Add UPDs for eDP power sequence adjust.

BUG=b:171954512
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ic4bafd86ffb7804c4739f9d30beb67549b71d289
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2021-01-25 09:10:51 +00:00
Chris Wang
027b8b2ab9 mb/google/zork: add eDP tuning parameter to fix the eDP noise 
needs to adjust the eDP phy setting to fix the eDP noise for WWAN.

DP_VS_LEVEL0_PREEMPH_LEVEL0, = 0x00 (0.4v 0db) swing 0, pre-emphasis 0)
COMMON_MAR_DEEMPH_NOM = 0x004B
COMMON_SELDEEMPH60 = 0x0
CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80

BUG=b:171269338
BRANCH=none
TEST=Build; Verify the UPD was passed to system integrated table

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ibe720e26d2257e05a989eaa1fd85d542005cf6a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48734
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 09:10:40 +00:00
Chris Wang
4e66d932c7 soc/amd/picasso: Set UPDs for tuning eDP phy 
Add UPDs for edp phy tuning adjust.

BUG=b:171269338
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I389bc4b5726f70bb1edfd858dba1c575cf68050b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2021-01-25 09:10:27 +00:00
Angel Pons
244f455bd9 nb/intel/ironlake: Drop constant parameter 
All callsites of `rmw_1d0` use the same `flag` value.

Change-Id: I84fab5d3fd270ce684cd6ca892c213b0d8610283
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2021-01-25 09:09:59 +00:00
Elyes HAOUAS
9c19a4fae8 mb/google/auron: Convert to ASL 2.0 syntax 
Built google/auron (Lulu) provides identical 'dsdt.dsl' files.

Change-Id: I5728b220e88d4105fcf6e5cee78662bc80fa01d7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-25 09:09:43 +00:00
Idwer Vollering
f0712795b0 util/board_status/board_status.sh: invoke md5 on FreeBSD 
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I8d9493ce0c3fa97ea9c3c2f60a0106bb98bd8315
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49309
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 09:08:53 +00:00
Idwer Vollering
a3c44d843c util/board_status/board_status.sh: improve mktemp behaviour on non-linux OSes 
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I763b0e7c7c81a2447ed20db0a25047d106e30606
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49308
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 09:08:35 +00:00
Idwer Vollering
3c70774629 util/board_status/board_status.sh: improve getopt detection and usage on 
non-linux OSes

Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: Iba50d8a8609eda974f12b0d9802e04d7371aed5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49307
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 09:08:22 +00:00
Idwer Vollering
22bcb5643b util/board_status/board_status.sh: select the right gnu make binary 
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I4523b1b235064f89c01530b47c9cb4c3c11c9761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49306
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 09:08:08 +00:00
Angel Pons
64b88623cb nb/intel/sandybridge: Only run DMI recipe on Ivy Bridge 
Reference code does not run any DMI recipe for Sandy Bridge. Create a
helper function and exit early for Sandy Bridge. The CPUID value will
be used in a follow-up, since DMI setup has stepping-specific steps.

Change-Id: I5d7afb1ef516f447b4988dd5c2f0295771d5888e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48413
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 09:07:30 +00:00
Angel Pons
77516ca792 nb/intel/sandybridge: Correct late DMI init sequence 
Based on reference code, update the DMI ASPM setup steps.

Change-Id: I1248305b2f76f48f4e6910de1a6980e942f16945
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48536
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 09:07:24 +00:00
Elyes HAOUAS
e515515e2e mb/libretrend/Kconfig: Remove duplicated string 
Change-Id: Iab19538e1f5a74b714cb2a34855d9717315b9018
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
 2021-01-25 09:07:02 +00:00
Elyes HAOUAS
6807204919 mb/51nb/Kconfig: Remove duplicated string 
Change-Id: Ib184dbfef05608bbf18d49fee5cbc9dd12ed6751
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49883
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 09:06:51 +00:00
Elyes HAOUAS
2266b33935 src/lib/: Remove "this file is part of" line 
Change-Id: I9031dad52581e77aa56014b1fede884f2cdeb6de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49882
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 09:06:37 +00:00
Michael Niewöhner
d2c57f2a0c soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroring 
Drop the old, redundant code for mirroring LPC registers to DMI and make
use of the new common code.

Select the new Kconfig option for LPC DMI mirroring by the option
SOC_INTEL_COMMON_PCH_BASE, which is selected by platforms starting with
SPT, except APL and Xeon-SP. For Xeon-SP, select DMI and the new Kconfig
directly.

APL, even though it's younger than SPT, does not need mirroring.

Test: Set LGMR address by calling `lpc_open_mmio_window` and check that
      both the PCI cfg and DMI LGMR register get written correctly.

Tested successfully on clevo/cml-u.

Change-Id: Ibd834f1474d986646bcebb754a17db97831a651f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-01-25 09:06:10 +00:00
Michael Niewöhner
f7e91d22d4 soc/intel/lpc_lib: mirror LPC registers to DMI when required 
Starting with SPT, LPC registers IOD, IOE, LGIR* and LGMR need to be
mirrored to their corresponding DMI registers. Add the required writes
to DMI registers, where the PCI config registers get written.

This is already done in soc code for IOD, IOE and LGIR* by mirroring
the registers later, during PCH init. Also the code mostly matches
accross the platforms. This common implementation will avoid delayed
mirroring of the registers and also deduplicate the code.

This change also adds a new Kconfig that will be selected by platforms
requiring mirroring of LPC IO/MMIO registers to their corresponding DMI
registers.

For making use of this common code, the redundant soc code needs to be
dropped and the newly introduced Kconfig option has to be selected. This
is done in the follow-up change.

Change-Id: I39f3bf4c486a1bbc112b2b453381de6da4bbac4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-01-25 09:00:12 +00:00
Kevin Chang
2efd6441c4 mb/google/dedede/var/boten: Add custom SAR values for Boten 
Add Boten customized SAR table.

BUG=b:175931508
BRANCH=dedede
TEST=build and test no Boten

Change-Id: I3b00f56c8b890979cbf2155c97a3a064d8b0ba1a
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2021-01-25 08:58:09 +00:00
Tim Chen
1da9e35bc9 mb/google/dedede/var/magolor: Enable EC keyboard backlight 
BUG=b:177288782
TEST=emerge-dedede coreboot chromeos-bootimage

Change-Id: I98f741da4a22494883939c4efe7960c66e71c6a7
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2021-01-25 08:58:02 +00:00
Martin Roth
0ad5fbd48d util: Update all shebangs to use /usr/bin/env 
Instead of hardcoding paths to the executables, use the version in the
path.  This allows the scripts to work on more systems, and allows the
binary version to be changed more easily if needed.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ifcc56aa21092cd3866eacb6a02d198110ec6051d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-25 08:57:40 +00:00