d67cf181bf
soc/intel/quark/gpio_i2c.c: Use __func__
...
Change-Id: Id84a88933d32f60dd8d864d9a10d84a2b3c365ff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 21:28:19 +00:00
7dbc4a4658
soc/intel/denverton_ns/pmc.c: Use __func__
...
Change-Id: I06134e48b2d33c178883fc2047bcfbad417c6d02
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 21:27:07 +00:00
f9e18520c9
soc/intel/denverton_ns/npk.c: Use __func__
...
Change-Id: Ib0f425d74bc219ef518394526b51f2756eb95d61
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2021-01-24 21:26:23 +00:00
e98dbf31f2
soc/intel/denverton_ns/lpc.c: Use __func__
...
Change-Id: Ic83a6a5db3b3d8a08c92064f8039d1bac825ffc3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 21:25:56 +00:00
9cf49da224
mainboard/lenovo/s230u/smihandler.c: Use __func__
...
Change-Id: If46ef5ffbd3de82d793a095b011e5740b776ff14
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 21:24:28 +00:00
e167c38775
mainboard/intel/strago/ec.c: Use __func__
...
Change-Id: Ifa30e9d2a71eae9a438e84367fd8b4f8bd920983
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 21:24:05 +00:00
038dc4535c
mainboard/intel/emeraldlake2/ec.c: Use __func__
...
Change-Id: I75f534245d37f401357b611efc5c190e8a872d02
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 21:23:44 +00:00
1ad0f6d90b
ec/acpi/ec.c: Use __func__
...
Change-Id: I4823b84d851d7d1f0f48be44ab28e7365b553b6f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 21:23:30 +00:00
75d19d740b
drivers/intel/gma/opregion.c: Use __func__
...
Change-Id: Ia45825ade0c9d24d5b87882e21bfc6df82a693e6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 21:23:17 +00:00
36f9ea6f2a
drivers/elog/elog.c: Use __func__
...
Change-Id: I024a0c2d7c53634c58d5d80522933ecad554d7c9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 21:22:58 +00:00
0c1d660263
device/pci_rom.c: Use __func__
...
Change-Id: I24c40d511eeaa5073acd2b47b20b4ec2f85bb69e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 21:22:34 +00:00
433bc3eed3
mb/lenovo/t400: Convert to ASL 2.0 syntax
...
Change-Id: I4e6d5048ca9e949a70f3619f05b74870c1f1fe30
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 21:18:01 +00:00
c23ec645d3
mb/lenovo/s230u: Convert to ASL 2.0 syntax
...
Generated 'build/dsdt.dsl' are identical.
Change-Id: I8843d418bd9c34a4f079444bc6ce8ecd4559e36d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 21:17:20 +00:00
67e3365eb0
ec/purism/librem/acpi/ec.asl: Convert to ASL 2.0 syntax
...
Change-Id: Ic773f8404c24fc886e8420a5f4b3e00b2d752ba2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 21:16:09 +00:00
944cf91fd9
soc/samsung/exynos5250/dp-reg.c: Use __func__
...
Change-Id: I572ee7faaa4453d32852eea2b83b0b27c549abf2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2021-01-24 21:15:31 +00:00
0be419947e
arch/x86: Use wildcard for mb/smihandler.c
...
Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49247
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-24 21:06:22 +00:00
37eb24be15
ACPI: Clean up GNVS initialisation
...
With the common <soc/nvs.h> approach platform does not
need to implement the common accessors or sizeof() function.
Change-Id: I1050a252f765c763c1ae2d1610cbfb0d973ba026
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-01-24 19:57:17 +00:00
cc975c5c65
soc/amd/cezanne/Kconfig: select missing SSE2 option
...
This will set the corresponding enable bit in CR4 in bootblock_crt0.S
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I648a83fbcb71456bf1e5b11c491e7cadc8e0e281
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
2021-01-24 18:16:17 +00:00
f09221c033
soc/amd/cezanne/Kconfig: select X86_AMD_FIXED_MTRRS
...
This option will make the ramstage MTRR core set the additional bits in
the fixed MTRRs that need to be set on AMD CPUs to enable caching.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I94bca61acfc6e38a6d808eb5020537b4e8596178
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
2021-01-24 18:16:09 +00:00
57419de187
soc/amd/cezanne: add basic romstage
...
This currently only initializes the console, calls into the FSP driver
that then calls into FSP-M and then jumps to ramstage after the FSP-M
returns. Right now, this mainly unblocks the FSP-M development.
Change-Id: I9f3cdaac573e365bb4d59364d44727677f53e91b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
2021-01-24 18:15:59 +00:00
8d0a609e6d
soc,vendorcode/amd/cezanne: add basic FSP integration
...
This is a trimmed-down version of the Cezanne FSP integration code, so
for example the UPD definitions are empty, which will be addressed
later. Since coreboot just leaves the UPD values at their default, this
is not a problem during the initial platform bring-up.
Change-Id: Ie0fc30120c2455aa2160708251e9d2f229984305
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
2021-01-24 18:15:46 +00:00
45b0714c89
soc/amd/picasso: Remove some empty strings
...
Change-Id: If1ff88010f8bf941ec6a76019c4b6a4cb9b31093
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2021-01-24 18:10:31 +00:00
f51738ddab
soc/amd/cezanne: Add PSP integration for cezanne
...
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48528
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-24 18:09:19 +00:00
7a5c369614
soc/intel/xeon_sp/cpx: Account for 'rc' heap manager
...
The xeon_sp/cpx has a second 'rc' heap inside FSP-M that is statically
allocated at the start of CAR. This breaks FSP 2.0 specification. This
can be worked around in the linker scripts to make sure coreboot and
FSP-M don't fight over the same memory.
Tested
- on ocp/deltalake: boot and the "Smashed stack detected in
romstage!" message at the end of romstage is gone.
- qemu/i440fx: BUILD_TIMELESS=1 results in the same binary.
Change-Id: I6d02b8a46a2a8ef00f34d8f257595d43f5d3d590
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Jonathan Zhang <jonzhang@fb.com >
2021-01-24 15:54:22 +00:00
9789689e41
arch/x86/car.ld: Account for FSP-T reserved area
...
Tested
- on ocp/deltalake: boots (with FSP-T).
- qemu/i440fx: BUILD_TIMELESS=1 results in the same binary.
Change-Id: I7e364ab039b65766eb95538db6b3507bbfbfb487
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-01-24 15:54:13 +00:00
aaa69b621b
soc/intel/lpc_lib: drop dead code
...
Change-Id: I7cf5f97c3229fe6a72d70a36e8cff49ff3cf611b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2021-01-24 14:46:15 +00:00
0fc6bec763
soc/intel/icl: drop wrong, unused code
...
The ids used in function `soc_get_pch_series()` are not valid for
Icelake. Since it's not even used, instead of fixing it, drop it.
Change-Id: I4a1ee4b84f11ea314cb666ce4506ff90168da0ca
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49875
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-24 14:03:44 +00:00
89fe2f34b4
soc/intel/cnl: use Kconfig to determine PCH type
...
We already know the PCH type at build time, so there is no need to do
runtime detection. Thus, use Kconfig and drop `get_pch_series()`.
Change-Id: I470871af5f5954e91a8135fddf4a2297a514d740
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49874
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-24 14:03:33 +00:00
d0d528a92a
soc/intel/broadwell: Align raminit with Haswell
...
Rename and split functions to match what Haswell does.
Change-Id: I4f3e997dd934bdf7717a70603d9413eae93cf181
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 12:07:55 +00:00
24e4edb376
soc/intel/broadwell: Drop struct romstage_params
...
It is no longer necessary.
Change-Id: Ib37c9de83badc6339dca6916aec8c34a43797652
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 12:07:07 +00:00
65f81a7b90
broadwell: Flatten mainboard_pre_raminit
...
All Broadwell boards only use the `mainboard_pre_raminit` function to
call `mainboard_fill_pei_data` and optionally `mainboard_fill_spd_data`.
Move the declaration and weak definition of `mainboard_fill_spd_data` to
platform code, replace the call to `mainboard_pre_raminit` in romstage.c
with calls to `mainboard_fill_pei_data` and `mainboard_fill_spd_data`,
and delete all other instances of `mainboard_pre_raminit` for Broadwell.
Finally, delete now-empty romstage.c and spd.h files from mainboards.
Change-Id: I3334b20bd7138bb753b996a137ff106e87c6e8a5
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 12:06:55 +00:00
ac1c9bb5cd
broadwell: Clean up mainboard_post_raminit
...
Make it optional and change its signature.
Change-Id: I4b5f3fb08e8954514ebf39e72c95aa62d66856d7
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 12:06:39 +00:00
d626e554aa
soc/intel/broadwell/chip.h: Drop unused fields
...
Broadwell boards now use the CPU code for Haswell. Therefore, these
devicetree options are no longer used anywhere and can be removed.
Change-Id: Ib0d1b6eecc11a70d1a2614669353a8040c860535
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-24 12:05:07 +00:00
3f0a95ac4c
soc/intel/broadwell: Select CPU_INTEL_HASWELL
...
This allows us to drop many now-redundant Kconfig options.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
The default configuration file also remains identical, as expected.
Change-Id: I20b0200550508679bf2533342ce918b221dcf81e
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2021-01-24 12:04:40 +00:00
e751a101c0
soc/intel/broadwell: Move romstage.c to Haswell
...
Broadwell no longer has CPU code.
Change-Id: I9c9717439a702dddaa613a30e6f3da29887ec4bd
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46951
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-24 12:04:25 +00:00
b89c8bb135
soc/intel/broadwell: Drop now-unused CPU code
...
All boards now use Haswell's CPU code, which also supports Broadwell.
Change-Id: Ia0b8f7bf64334dd965baad0a30a7bb0ed81c4cac
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46950
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-24 12:04:09 +00:00
9d733def59
soc/intel/broadwell: Use Haswell CPU headers
...
Now that the boards use Haswell's CPU code, Broadwell can be updated.
Change-Id: If07e5272f07edb59bb18eef1f80d7d5807b26e66
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46949
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-24 12:03:55 +00:00
739a6ad1ac
mb/google/auron: Use Haswell CPU code
...
The VR config and S0ix options are now specified for the CPU chip.
Change-Id: I75e405d41b4a0605e786fe761c92535e62d0cfce
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46945
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-24 12:03:08 +00:00
d0b7a534ce
mb/google/jecht: Use Haswell CPU code
...
Change-Id: I6c106b152bb2824e000232d23c2991898b2c4475
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46946
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-24 12:02:43 +00:00
b7fe448575
mb/intel/wtm2: Use Haswell CPU code
...
Change-Id: I478576afa3b390cf5480298aafe6e049b5e90bff
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46947
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-24 12:02:34 +00:00
ba78fce868
mb/purism/librem_bdw: Use Haswell CPU code
...
Change-Id: I736bff90305952d279a10dfe90a2ee3a533220b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46948
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-24 12:02:25 +00:00
a3288b38e1
soc/intel/broadwell: Allow to use Haswell CPU code instead
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This allows individual boards to be adapted to use Haswell CPU code.
Also rename the CPU_SPECIFIC_OPTIONS symbol to avoid any collisions.
Change-Id: I65e878dacf0a0d53fd8d4defce6684f4ceb92588
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46944
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-24 12:02:15 +00:00
417a6da449
soc/intel/broadwell: Select INTEL_LYNXPOINT_LP
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This allows the correct Haswell and Lynxpoint code to be used.
Change-Id: Icbfc5bb11b1ea755a143fa340a3971376f4e5e91
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46958
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-24 12:01:31 +00:00
f542b7bcef
cpu/intel/haswell: Add Broadwell CPUIDs and microcode
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Broadwell can now use the Haswell CPU driver.
Change-Id: I36138cab72b1e3ad0ff7f6434996f5ce00de9d0d
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46942
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-24 12:01:24 +00:00
1c7ba62eb7
cpu/intel/haswell: Set C9/C10 vccmin
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Backport commit ab7586fa26th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46922
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-24 12:01:09 +00:00
c86b119495
cpu/intel/haswell: Add fast ramp voltage for Broadwell
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Backport commit 55228ba4b4th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46921
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-24 12:00:59 +00:00
8b043c058c
lib/edid_fill_fb: Relax bits_per_pixel constraint
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The Picasso VBIOS is not setting the reserved_mask_size correctly. This
change relaxes the constraint to allow bpp_mask <= bits_per_pixel. This
is how the code previously used to work before CB:39002.
BUG=b:177094598, b:177422379
TEST=boot zork and see depthcharge working
Signed-off-by: Raul E Rangel <rrangel@chromium.org >
Change-Id: I2e67532fa949fbd673269d8d7f1c0d8af6124ac9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
2021-01-24 11:18:23 +00:00
d4b58259c4
soc/intel/baytrail,broadwell: Use bootstate for save_wake_source()
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Change-Id: I01be1b9dfefcfcf037de4153e9540c7258dc160f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49818
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-23 20:32:01 +00:00
2787237dd5
ACPI: Add helpers for CBMEM_ID_POWER_STATE
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Create uniform logging for the (unlikely) case of a CBMEM
entry disappearing.
Change-Id: I7c5414a03d869423c8ae5192a990fde5f9582f2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-01-23 20:31:09 +00:00
10f7f997ad
soc/amd: Rename chipset_state to chipset_power_state
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To implement some common helpers for CBMEM_ID_POWER_STATE
allocation use the same struct name as soc/intel.
Change-Id: I5d2c06a2a7b4602374562197c99b0ad7bcf50afb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-01-23 20:21:14 +00:00
