AMDFW tool stores bios dir entry to bios1_entry in picasso but
bios3_entry in cezanne. Separate getting bios_dir_addr into a function
and implement it on each platforms.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ie18ed7979a04319c074b9b251130d419dc7f22dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52964
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move all platform-specific code except direct svc calls to chipset.c.
There will be differences between each platforms and we can't put
everything into svc.c.
TEST=build firmware for zork
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ie7a71d1632800072a17c26591e13e09e0269cf75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52963
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To configure and enable the IOAPIC in the graphics and northbridge (GNB)
container, FSP needs to write an undocumented register, so pass the GNB
IOAPIC MMIO base address to make it show up at that address.
BUG=b:187083211
TEST=Boot guybrush and see IO-APIC initialized
IOAPIC[0]: apic_id 16, version 33, address 0xfec00000, GSI 0-23
IOAPIC[1]: apic_id 17, version 33, address 0xfec01000, GSI 24-55
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1e127ce500d052783f0a6e13fb2ad16a8e408b0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52905
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PIC IRQs are required so we can correctly set up the PCI_INT
registers. This only matters when booting in PIC mode. We don't need to
set the IO-APIC registers since the linux kernel will auto-assign those
to reduce conflicts.
BUG=b:184766519
TEST=Boot guybrush with `pci=nomsi,noacpi amd_iommu=off noapic` and
verify xhci and graphics continue to work.
$ cat /proc/interrupts
12: 285064 XT-PIC nvme0q0, nvme0q1, rtw88_pci
13: 100000 XT-PIC xhci-hcd:usb1
14: 4032 XT-PIC amdgpu, xhci-hcd:usb3
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1d66ccd08a86a64242dbc909c57ff9685828f61f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52915
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This uses the new FSP PCI methods to pull the routing table and populate
the pirq data structure.
BUG=b:184766519
TEST=Boot guybrush and verify we get Got IRQ 0x1F (disabled) messages
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie21229cc2fb4fd5b85c0b9e933f7b43af24864b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is loosely based off of picasso/pcie_gpp.c. This version uses the
acpigen_write_PRT_X methods to write the actual records. There are also
two functions, 1 for using the GNB, and one for using the FCH. The FCH
one is useful when the GNB IO-APIC has not been initialized.
BUG=b:184766519
TEST=Dump guybrush ACPI and verify it looks correct
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This allows us to use the common get_pci_routing_info and
pci_calculate_irq. The IRQ field in the struct was also filled in from
the PPR.
BUG=b:184766519
TEST=Boot ezkinil and verify SSDT table is identical.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I16d90d8c89bfcf48878c0741154290ebc52a4120
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53923
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This struct is similar to `struct pci_routing` defined in
picasso/pcie_gpp.c. It additionally contains the irq used for the bridge
and is structured in a way that the FSP can provide via HOB.
The next set of CLs will migrate the pci routing functions used by
picasso into common and enable pci routing table generation for cezanne.
BUG=b:184766519
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1a8d988d125f407f0aa7bc1722d432446aa9aff8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
These parameter IDs are defined in the AGESA Interface specification
#55483. This patch also adds a ALIB_DPTC_ prefix to the IDs and makes
the names more consistent.
TEST=Timeless build for Mandolin results in identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I75e0504f6274ad50c53faa8fcbde4d6821d85a04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53917
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The other enum entries are control IDs for the
ALIB_FUNCTION_DYNAMIC_POWER_THERMAL_CONFIG ALIB function while
DPTC_TOTAL_UPDATE_PARAMS is the total number of configuration settings
that will get passed as parameter in the ALIB call, so it shouldn't be
part of that enum.
TEST=Timeless build for Mandolin results in identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0cb9e9d2ba579a74d916011b4ead71cc86d69a24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53916
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ACPI ALIB function numbers are defined in the AMD Generic
Encapsulated Software Architecture (AGESA™) Interface Specification
(document #55483).
TEST=Timeless build stays the same for Mandolin (Picasso) and Gardenia
(Stoneyridge).
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I290ef0db32c65ebb2bbbe4f65db4df772b884161
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53915
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mcache is overflowed in the latest build. In order
to fix the mcache overflow, we increase the mcache size
to 0x4000 and adjust the percentage to 50% for the ro/rw
mcache. This change is for all of the volteer variants
as we see many of the volteer variants which use the
latest bios having the mcache overflow issue.
BUG=b:187095474, b:187095765, b:187234881, b:162052593
TEST=no mcache overflow in the bios log
Change-Id: If9552bc9fa5d36b1ca662c9da030ae7b137b60a8
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The SN65DSI86 eDP bridge supports two ways to read the EDID: for now
we've been using "direct mode", which works by basically making the
bridge I2C device listen to another chip address besides its own and
proxy all requests received there directly to the eDP AUX channel. The
great part about that mode is that it is super easy and hassle-free to
use. The not so great part about it is that it doesn't work: for EDID
extensions, the last byte (which happens to contain the checksum) is
somehow always read as zero. We presume this is a hardware bug in the
bridge part.
The other, much more annoying way is "indirect mode", where each byte
transmitted over the AUX channel has to be manually set up in the I2C
registers of the bridge, just like we're already doing with DPCD
transactions. Thankfully, we can reuse most of the DPCD code for this so
it's not a lot of extra code. It's a bit slower but not as much as you'd
expect (26ms instead of 18ms on my board), and the difference is not
very relevant compared to common total times for display init.
Also, some of the (previously unused) enum definitions for the AUX_CMD
mode field of the bridge had just been plain wrong for some reason, and
needed to be fixed to make this work.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I65f80193380d3c3841f9f5c26897ed672f45e15a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52959
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the volet variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:186334008
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_VOLET
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ic6ca9a78494e3819b0fb39c0bcc70fed95c2c589
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Bank interleaving does not work on this platform, disable it.
Additionally enable ECC feature on SKUs supporting it. AmdIntPost
returns success thanks to these settings.
TEST=boot apu2 4GB ECC and apu3 2GB no ECC and see AGESA_SUCCESS after
AmdInitPost
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I010645f53b404341895d0545855905e81c89165e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We need to configure CPU PCIE root port related gpios in early
boot block stage for CPU root ports to work. Since we're removing
this programming from FSP, coreboot needs to take care of programming
this GPIOs. Also we need to enable virtual wire messaging for native
gpios for CPU PCIE root ports.
Change-Id: Ieda6b6c31ce5bd5e84e4efe544bfc659283ce6f1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52270
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
