Because the FSP interface for PCI IRQs only includes the PCH devices,
this function is the complement to that, taking the list of irq entries,
and programming the PCI_INTERRUPT_LINE registers.
BUG=b:130217151, b:171580862, b:176858827
TEST=boot brya with patch train, verify with `lspci -vvv` that for all
the north PCI devices, their IRQ was either the one programmed by this
function, or an MSI was used.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I81cf7b25f115e41deb25767669b5466b5712b177
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55817
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Intel FSP provides a default set of IO-APIC IRQs for PCI devices, if
the DevIntConfigPtr UPD is not filled in. However, the FSP has a list of
rules that the input IRQ table must conform to:
1) One entry per slot/function
2) Functions using PIRQs must use IOxAPIC IRQs 16-23
3) Single-function devices must use INTA
4) Each slot must have consistent INTx<->PIRQy mappings
5) Some functions have special interrupt pin requirements
6) PCI Express RPs must be assigned in a special way (FIXED_INT_PIN)
7) Some functions require a unique IRQ number
8) PCI functions must avoid sharing an IRQ with a GPIO pad which routes
its IRQ through IO-APIC.
Since the FSP has no visibility into the actual GPIOs used on the board
when GpioOverride is selected, IRQ conflicts can occur between PCI
devices and GPIOs. This patch gives SoC code the ability to generate a
table of PCI IRQs that will meet the BWG/FSP rules and also not conflict
with GPIO IRQs.
BUG=b:130217151, b:171580862, b:176858827
TEST=Boot with patch series on volteer, verify IO-APIC IRQs in
`/proc/interrupts` match what is expected. No `GSI INT` or
`could not derive routing` messages seen in `dmesg` output.
Verified TPM, touchpad, touchscreen IRQs all function as expected.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0c22a08ce589fa80d0bb1e637422304a3af2045c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49408
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To set the Fibocom 850-GL module to USB mode, it needs to be disabled
when PCIe training happens, or it will automatically switch to PCIe
mode. This patch makes sure it's shut down when training happens in
FSP-M. It will be brought up in ramstage and will be available for USB
enumeration later.
BUG=b:187316460
TEST=Run lsusb from the OS and see that the Fibocom module is present
on USB.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I153eb6cd7c3a0e2cc3b71c99f76db3e565173cfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This configures the romstage portion of the PCIe GPIOs in the correct
sequence to meet the power-on timings.
The PCIe_RST line is anded with the Aux reset lines, so to take the PCIe
devices out of reset, both need to be brought hign.
BUG=b:184796302, b:184598323
TEST=Verify timings between GPIO init sections. All available modules
are present after training.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ib1990bba31c84827467d4ff8a15f1e0682501e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54741
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This configures the bootblock portion of the PCIe GPIOs in the correct
sequence to meet the power-on timings.
Setting the PCIE Reset happens in coreboot instead of in the FSP.
The Aux reset lines are anded with the PCIe RST line, so both have
to be brought up together. On v1 of guybrush, the PCIe reset line
also resets EC communication, so it must be brought up immediately on
that version.
BUG=b:184796302, b:184598323
TEST=Verify timings between GPIO init sections. All available modules
are present after training.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I2d0b812b654b0cd317a2c8c1ce554e850c96be44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add configs for Herobrine variants. Also enable ec sw sync as this
should not be disabled by default.
BUG=b:182963902
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_SENOR -x -a -B
./util/abuild/abuild -p none -t GOOGLE_PIGLIN -x -a -B
Change-Id: Ide4e375aa0236dce65a954a2f68455d05fa841eb
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
When initializing eSPI early, guybrush has requirements to configure the
bus properly. Those are normally run in bootblock_mainboard_early_init,
but when setting up eSPI early, those have not run yet.
BUG=192100564
TEST=Build along with previous patch, eSPI works on guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ifec6113d48aea0bb5efe47909e4faf0161148a99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55864
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To reduce power load, set unused GPIOs to NC and close
unused interface in devicetree. GPIOs and
interfaces are as below:
GPIO: GPP_C18/C19/D12/D14/D15/D19/D20/D21/E00/E02/H06/H07
Interface: I2C1/I2C3/I2C5
USB: port2_3/2_4/2_6
BUG=b:185044041
BRANCH=dedede
TEST=Built bios and test, it reduces power load without affecting
device function.
Change-Id: Ib5999f0e129bf3e660fe293eda7af3e8e1426151
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ben Kao <ben.kao@intel.com>
The `soc_read_pmc_base()` function returns an `uintptr_t`, which is then
casted to a pointer type for use with `read32()` and/or `write32()`. But
since commit b324df6a54 (arch/x86: Provide
readXp/writeXp helpers in arch/mmio.h), the `read32p()` and `write32p()`
functions live in `arch/mmio.h`. These functions use the `uintptr_t type
for the address parameter instead of a pointer type, and using them with
the `soc_read_pmc_base()` function allows dropping the casts to pointer.
Change-Id: Iaf16e6f23d139e6f79360d9a29576406b7b15b07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Introduce a macro retry(attempts, condition, expr) for retrying a
condition, which is extensively used in coreboot.
Example usage:
if (!retry(3, read32(REG) == 0, mdelay(1))
printk(BIOS_ERR, "Error waiting for REG to be 0\n");
BUG=none
TEST=make tests/commonlib/bsd/helpers-test
TEST=emerge-cherry coreboot
BRANCH=none
Change-Id: I421e4dcab949616bd68b3a14231da744b9f74eeb
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Vboot's Makefile is controlled by a ${DEBUG} environment variable.
As the name is very generic, it may be set by accident without any
intention to change the build. Having it set would break reproduci-
bility at least but it also turns out that the hostlib build would
be incomplete so that linking cbfstool fails due to internal calls
to vb2api_fail() which is not built in.
Change-Id: I2a9eb9a645c70451a320c455b8f24bfed197117c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
FirmwareVersionInfoHob.h is removed in JSL FSP v2376 so
remove it from Jasper Lake vendorcode.
BUG=b:153038236
BRANCH=None
TEST=Verify JSLRVP build with all the patch in relation chain
and verify the version output prints no junk data observed.
couple of lines from logs are as below.
Display FSP Version Info HOB
Reference Code - CPU = 8.7.16.10
uCode Version = 0.0.0.1
Change-Id: Iad0429630665f50dbc1541487c9061dd1a19907c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45908
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select DISPLAY_FSP_VERSION_INFO_2 for Jasper Lake soc.
BUG=b:153038236
BRANCH=None
TEST=Verify JSLRVP build with all the patch in relation chain
and verify the version output prints no junk data observed.
couple of lines from logs are as below.
Display FSP Version Info HOB
Reference Code - CPU = 8.7.16.10
uCode Version = 0.0.0.1
Change-Id: If68b704c4304357b0046a510545fc213d7ed5887
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45907
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CB:55452 uses FMAP instead of "cbfs master header".
The flash size statement in vboot-rw.fmd does not contain the start
address, resulting in a non-booting system.
Add start address to FLASH statement.
BUG = N/A
TEST = Boot Facebook FBG1701
Change-Id: Id05ad33babb416a37c657b25cdb1e98d47c1a56d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
0xf7f000 - 0x1000 = 0xf7e000, not 0xf6f000.
This fixes build failure when selecting the option to validate the
layout using the flash descriptor (CONFIG_VALIDATE_INTEL_DESCRIPTOR)
Test: build google/casta successfully with IFD validation selected
Change-Id: I6df67f76f5d766a9f4f85ffc3e1f0de4a241f509
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55815
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `xdci_can_enable()` function is called earlier to configure FSP-S
UPDs. If it returned false, then the xDCI device will be disabled and
the second `xdci_can_enable()` call will never be evaluated.
Change-Id: I4bd08e3194ffccc79c8feaf8f34b2bb4077f760a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55789
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The null-termination of `filetypes` was added after the code was
written, obviously resulting in NULL dereferences. As some more
code has grown around the termination, it's hard to revert the
regression, so let's update the code that still used the array
length.
This fixes commit 7f5f9331d1 (util/cbfstool: fix buffer over-read)
which actually did fix something, but only one path while it broke
two others. We should be careful with fixes, they can always break
something else. Especially when a dumb tool triggered the patching
it seems likely that fewer people looked into related code.
Change-Id: If2ece1f5ad62952ed2e57769702e318ba5468f0c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Error Could not add [key.vbpubk]: too big occurs, when Eltan verified boot is enabled.
Update value of VENDORCODE_ELTAN_VBOOT_KEY_LOCATION.
BUG = N/A
TEST = Boot Facebook FBG1701 with Eltan verified boot enabled.
Change-Id: I1faecd189915985df633ac74627fd872ce8867f0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
BUG=b:191213716
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I2d5738442d2c173fd5b4802d8b5dff76b428c6f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55564
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
