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Author SHA1 Message Date
Sumeet R Pawnikar
3657187789 drivers/intel/dptf: Add OEM variables support 
This adds OEM variables feature under DPTF as per BWG doc #541817. Using
this, platform vendors can expose an array of OEM-specific values as OEM
variables to be used in determining DPTF policy. These are obtained via
the ODVP method, and then simply exposed under sysfs. In addition, these
gets updated when a notification is received or when the DPTF policy is
changed by userspace.

BRANCH=None
BUG=b:187253038
TEST=Built and tested on dedede board

Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2021-07-01 12:12:33 +00:00
Kyösti Mälkki
b2287718ef device: Clean up resource utility function signatures 
Drop extern declarations from functions.
Declare resource arguments as const.

Change-Id: I7684cc7813bad805c39a762892636818279ac134
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55475
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-07-01 09:46:09 +00:00
Iru Cai
3ab408c698 toolchain.inc: copy architecture specific CFLAGS to GCC_ADAFLAGS 
This fixes building with libgfxinit in x86_64 mode, which can
generates unsupported R_X86_64_32S relocations without -mcmodel=large.

Change-Id: If5162fae475f3e70c856d9664a8cfc6a89d82283
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55549
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-07-01 09:43:54 +00:00
Angel Pons
c76c59aa6a QEMU: Only call pci_assign_irqs with non-NULL dev 
Do not call `pci_assign_irqs` with a NULL device pointer.

Change-Id: Ide9ae38dedd881ed673ba1838a1e29529b306937
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-07-01 09:43:09 +00:00
Angel Pons
5124c131ba mb/emulation/qemu-i440fx: Tidy up PAM register writes 
Tidy up the code that programs the PAM (Programmable Attribute Map)
registers. Introduce the `D0F0_PAM` macro and use it to replace the
magic `0x59` and `0x5a` values in the code. Adjust the range of the
for-loop to work with the `D0F0_PAM` macro, and properly indent the
loop's body.

Change-Id: I9036425d726ffb69737ea6ed36c7a8f61d9d040a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-07-01 09:42:55 +00:00
Bill XIE
3b1a9944aa mb/asus/p8x7x-series: Add P8C WS as a variant of P8X7X series 
Mainboard information can be found in the included documentation.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Idb696193e5a67c42adf45e54d455d2dff7681ca7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-07-01 09:42:34 +00:00
Patrick Rudolph
7b45920804 mb/prodrive/hermes: Implement smbios_mainboard_version 
Return the HSI version read from BMC in smbios_mainboard_version.

Change-Id: If907d598c9e05d35f8898d294678f61d075f935a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-07-01 09:42:05 +00:00
Sunway
917785a3bb mb/google/dedede: Create cappy2 variant 
Create the cappy2 variant of the waddledee reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:192035460
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_CAPPY2

Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I772801152b9ca9c2c6afe76a353cb2b62d6210ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2021-07-01 09:41:54 +00:00
Casper Chang
9ce8cb1629 mb/google/brya/variants/primus: Update mainboard properties for BB retimer upgrade 
This changes updates mainboard properties by adding DFP number and
power_gpio for each DFP.

Reference CB:55348

BUG=b:191897776

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I63c912980530e5c9f341bdbab18c07685fd77abf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2021-07-01 09:41:22 +00:00
Kevin Chiu
58ff2acb7e mb/google/dedede/var/drawcia: Add LTE modem support for drawper 
Add LTE modem to devicetree.
Configure GPIO control for LTE modem by fw_config.

Update LTE USB port configuration at run-time after probing FW_CONFIG.
By default the concerned USB port takes the Type-A port configuration.

BUG=b:186393848
TEST=Build image and check with command modem status

Change-Id: I20450ae37e5047dba67211316515994bd2a09600
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2021-07-01 09:41:12 +00:00
Tony Huang
856b579fe5 mb/google/dedede/var/kracko: Update LTE USB port configuration 
Update LTE USB port configuration at run-time after probing FW_CONFIG.
By default the concerned USB port takes the Type-A port configuration.

BUG=b:178092096
BRANCH=dedede
TEST=Build and boot to OS to check LTE by modem status

Change-Id: If12cc29ddda6d5c32c0bda840a3680e7bf932f89
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54671
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-07-01 09:41:04 +00:00
Angel Pons
ceca5dedbc device/pci_device.c: Reuse irq variable 
The `irq` variable has the same value as `pIntAtoD[line - 1]`.

Change-Id: Iabf760adbc3014b32cfe6f908dc04c38b71bd980
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2021-07-01 09:39:56 +00:00
Subrata Banik
34237863ff soc/intel/alderlake: Select VBOOT_X86_SHA256_ACCELERATION config 
By enabling the flag alderlake platform will use hardware sha
instruction instead of software implementation for sha256.

This will speed up firmware verification especially on low-performance
device.

Change-Id: Ie8ab02360fdceafab257e9a301e6a89d3a22c3ae
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-07-01 09:38:31 +00:00
Subrata Banik
9479037f38 vboot: add VBOOT_X86_SHA256_ACCELERATION config 
Add Kconfig option for VBOOT_X86_SHA256_ACCELERATION, which will
use x86-sha extension for SHA256 instead of software implementation.

TEST=Able to call vb2ex_hwcrypto_digest_init() and perform SHA
using HW crypto engine.

Change-Id: Idc8be8711c69f4ebc489cd37cc3749c0b257c610
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2021-07-01 09:38:19 +00:00
Subrata Banik
bf487e46d7 Update vboot submodule to upstream main 
Updating from commit id b38e3a63:
    cros_ec: Use boot mode to check if EC can be trusted

to commit id ccc56f4:
    vboot: add x86 SHA256 ext support

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I4e170e84a12646386d3fd84ae97add6c19f23809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-07-01 09:38:12 +00:00
Angel Pons
b554b7c51f SMBIOS: Drop now-unnecessary unions 
Now that the refactoring is complete, the unions for the table header
are no longer needed. Therefore, drop them.

Change-Id: I4e170e84a12646386d3fd84ae973dd6c18f25809
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-07-01 07:38:32 +00:00
Angel Pons
fff1b2f547 mb/emulation/qemu-i440fx/fw_cfg.c: Use smbios_header 
Replace uses of `smbios_type0` with `smbios_header` for correctness.

Change-Id: I2479984f5322f0fb474ff1707c1dd1f5885f30e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-07-01 07:38:18 +00:00
Angel Pons
a37701afa3 SMBIOS: Introduce smbios_full_table_len function 
Introduce the `smbios_full_table_len` function to consolidate table
length calculation. The case where the length of a table equals the
length of the structure happens when a table has no strings.

Change-Id: Ibc60075e82eb66b5d0b7132b16da000b153413f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
 2021-07-01 07:38:00 +00:00
Angel Pons
b977c1ade3 arch/x86/smbios.c Move calculation next to usage 
Change-Id: I949da86605e76b186ef2fdbfbc112b71544b694a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-07-01 07:37:41 +00:00
Angel Pons
d62a5012d6 SMBIOS: Introduce smbios_carve_table function 
Factor out some boilerplate code into a helper `smbios_carve_table`
function, which zeroes out the table memory and fills in the header
fields common to all tables.

Change-Id: Iece2f64f9151d3c79813f6264dfb3a92d98c2035
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
 2021-07-01 07:37:21 +00:00
Angel Pons
ca01baa065 SMBIOS: Introduce struct for SMBIOS table header 
All SMBIOS `type X` tables start with the same 4-byte header. Add a
struct definition for it, and use it where applicable. The union is
temporary and allows doing the necessary changes in smaller commits.

Change-Id: Ibd9a80010f83fd7ebefc014b981d430f5723808c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-07-01 07:37:04 +00:00
Angel Pons
631cd29efb mb/pcengines/apuX: Refactor to avoid dead assignment 
The initial value of `len` is never used. Declare and initialise all
local variables in a single statement to avoid this problem.

Change-Id: Ieb96758f4cd19d9d3f8fdc543e8ca17db06a2123
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-07-01 07:36:49 +00:00
Angel Pons
35b99c64e6 SMBIOS: Avoid sizeof on struct type 
Where applicable, use the size of the associated variable.

Change-Id: Ibbac2a82893232a6f87182a6a965b84a599d633e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
 2021-07-01 07:35:02 +00:00
Angel Pons
c6dab80b1c arch/x86/smbios.c: Trim some len variables 
Reduce the scope or remove some `len` variables. This is done to ease
replacing `sizeof` on struct types in a follow-up commit, by ensuring
that all to-be-replaced appearances follow the variable declarations.

Change-Id: Ied38fcaf87ef5b1e4f93076b4ba2898ad1f98a72
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-07-01 07:26:56 +00:00
Angel Pons
808692b4f4 drivers/mrc_cache: Avoid sizeof on struct type 
Where applicable, use the size of the associated variable.

Change-Id: Icf4f1c8fe9f54c44b041a65eb46d6ec9f9fd6367
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-07-01 07:26:33 +00:00
Tim Wawrzynczak
a8dac049b1 commonlib: Add Intel-specific timestamps for before/after sending EOP 
Change-Id: I11daebbfc44959f1e498ddac2ee7633e31a1a7d5
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
 2021-06-30 22:20:32 +00:00
Tim Wawrzynczak
82eaa21945 soc/intel/jasperlake: Send End-of-Post message to CSE 
This is done to ensure the CSE will not execute any pre-boot commands
after it receives this command. Verified EOP and error recovery sequence
from Intel doc#619830.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I36fe448ff279ba054ad5e79e71c995dc915db21e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55633
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-06-30 22:20:20 +00:00
Tim Wawrzynczak
25d2452388 soc/intel/tigerlake: Send End-of-Post message to CSE 
This is done to ensure the CSE will not execute any pre-boot commands
after it receives this command. Verified EOP and error recovery sequence
from Intel doc#612229

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iae6b2eac11c065749e57c5337d81ed20044fc903
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2021-06-30 22:20:06 +00:00
Tim Wawrzynczak
c0e82e705d soc/intel/alderlake: Send End-of-Post message to CSE 
This is done to ensure the CSE will not execute any pre-boot commands
after it receives this command. Verified EOP and error recovery sequence
from Intel doc#627331.

TEST=on brya, autotest firmware_CheckEOPState confirms ME is in
post-boot state

Change-Id: Iee8c29f81d5d04852ae3f16dc8a9ff0fa59f056a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2021-06-30 22:19:35 +00:00
Tim Wawrzynczak
9fdd2b264b soc/intel/common/block/cse: Add BWG error recovery to EOP failure 
This patch adds functionality to attempt to allow booting in a secure
configuration (albeit with potentially reduced functionality) when the
CSE EOP message fails in any way. These steps come from the CSME BWG
(13.5, 15.0, 16.), and tell the CSE to disable the MEI bus, which
disables further communication from the host. This is followed by
requesting the PMC to disable the MEI devices. If these steps are
successful, then the boot firmware can continue to boot to the
OS. Otherwise, die() is called, prefering not to boot over leaving the
insecure MEI bus available.

BUG=b:191362590
TEST=Set FSP UPD to disable sending EOP; called this function from a
BS_PAYLOAD_LOAD, ON_ENTRY entry; observed that with just
cse_mei_bus_disable() called, Linux can no longer communicate over MEI:
[   16.198759] mei_me 0000:00:16.0: wait hw ready failed
[   16.204488] mei_me 0000:00:16.0: hw_start failed ret = -62
[   16.210804] mei_me 0000:00:16.0: H_RST is set = 0x80000031
[   18.245909] mei_me 0000:00:16.0: wait hw ready failed
[   18.251601] mei_me 0000:00:16.0: hw_start failed ret = -62
[   18.257785] mei_me 0000:00:16.0: reset: reached maximal consecutive..
[   18.267622] mei_me 0000:00:16.0: reset failed ret = -19
[   18.273580] mei_me 0000:00:16.0: link layer initialization failed.
[   18.280521] mei_me 0000:00:16.0: init hw failure.
[   18.285880] mei_me 0000:00:16.0: initialization failed.
Calling both error recovery functions causes all of the slot 16 devices
to fail to enumerate in the OS

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I06abf36a9d9d8a5f2afba6002dd5695dd2107db1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55675
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-06-30 22:19:23 +00:00
Mark Hsieh
a96e9cb0b4 mb/google/brya/variants/gimble: init overridetree for gimble 
init overridetree.cb based on the schematic carbine_adl-p_proto_20210618_proto final.pdf

BUG=b:191213263
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I3f6875ef438b147436605629445d346a56896a87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-06-30 19:25:30 +00:00
Casper Chang
4b3ad7d677 mb/google/brya/variants/primus: update gpios 
set GPP_C3 and GPP_C4 as NC since LAN function removal.

BUG=b:190643562

Change-Id: I21214d0a2904ba4347fbbbc74237aca6db22c345
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55933
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-06-30 15:53:25 +00:00
Lean Sheng Tan
58ec51cc0a soc/intel/elkhartlake: Enable PCH GBE 
Enable PCH GBE with following changes:
1. Configure PCH GBE related FSP UPD flags
2. Use EHL own GBE ACPI instead of common code version due to
   different B:D.F from the usual GBE
3. Add kconfig PMC_EPOC to use the PMC XTAL read function

Due to EHL GBE comes with time sensitive networking (TSN)
capability integrated, EHL FSP is using 'PchTsn' instead of the
usual 'PchLan' naming convention across the board.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-06-30 07:35:32 +00:00
Lean Sheng Tan
bed1b602d0 soc/intel/common: Refine pmc_get_xtal_freq function 
1. Remove 'PCH_EPOC_XTAL_FREQ(__epoc)' macro since it only be used
   in 1 place.

2. Transform macro into more readable C code.

3. Add additional case check to make sure the returned value is
   defined in the 'pch_pmc_xtal' enum.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: If57a99bf8e837a6eb8f225297399b1f5363cfa85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-06-30 07:35:09 +00:00
Lean Sheng Tan
508dc163f1 soc/intel/common: Move PMC EPOC related code to Intel common code 
Move PMC EPOC related code to intel/common/block because it is
generic for most Intel platforms and ADL, TGL & EHL use it.

Add a kconfig 'PMC_EPOC' to guard this common EPOC code.

The PMC EPOC register indicates which external crystal oscillator is
connected to the PCH.  This frequency is important for determining the
IP clock of internal PCH devices.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ib5fd3c4a648964678ee40ed0f60ca10fe7953f56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-06-30 07:34:44 +00:00
Rob Barnes
f1ade489c8 ec/google: Use EC_HOST_EVENT_NONE 
google_chromeec_get_event returns 0 for no event. Return
EC_HOST_EVENT_NONE=0 to improve readability.

BUG=b:184074997
TEST=Build and boot guybrush without error

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ic08ed9ccdd7c0023d0fe8b641fcf60dca495a242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-06-30 04:57:16 +00:00
Rob Barnes
8bc5fa9f0a ec/google: Sync ec_commands.h 
This change syncs the coreboot version of google ec_commands.h with the
ec_commands.h from the google ec repository. This is a straight copy
except for the the copyright header.

BUG=b:184074997
TEST=Build and boot guybrush
BRANCH=None

Change-Id: I095c3316d720328cb7b8dd1b72ffc108208b14bd
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-06-30 04:55:38 +00:00
Tao Xia
2ffd1bff2f mb/google/dedede/var/storo: Add USB2 PHY parameters for LTE USB2.0 
This change adds fine-tuned USB2 PHY parameters for storo.

BUG=191089827
TEST=Built and verified USB2 eye diagram test result

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I38dd8ad59b32f635e641765e0a1bd13651180d23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2021-06-30 04:53:15 +00:00
Tao Xia
9d05cf11b5 mb/google/dedede/var/storo: Enable Wifi SAR for storo 
BUG=b:190027970,b:178175837
BRANCH=dedede
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I7084f9b7be2b66adda2d9d5a83ce5dd9c31d01b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2021-06-30 04:51:30 +00:00
Angel Pons
8e035e3c13 src: Move select ARCH_X86 to platforms 
To generalise the choice of 32-bit or 64-bit coreboot on x86 hardware,
have platforms select `ARCH_X86` directly instead of through per-stage
Kconfig options, effectively reversing the dependency order.

Change-Id: If15436817ba664398055e9efc6c7c656de3bf3e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2021-06-30 04:48:59 +00:00
Nikolai Vyssotski
c839b37049 soc/amd/common/fsp/dmi.c: Fix Type 17 DMI reporting 
With two versions of *speed_mhz_to_reported_mts() we need to call the
correct one based on the reported memory type.

BUG=b:184124605
TEST="dmidecode --type 17" in OS on Guybrush

Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Change-Id: I92e834097546e3ef7130830444a80f818bdea3d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55852
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-06-30 04:47:13 +00:00
Angel Pons
5f406d9cb3 device/pci_device.c: Drop redundant guard 
This guard is nested inside an identical guard already.

Change-Id: I2b315ee6620865429097041035ad493ddcc51884
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2021-06-30 04:45:10 +00:00
Eric Lai
7ade3435df mb/google/brya: Set GPP_B3 to APIC mode 
Set GPP_B3 to APIC mode to avoid PCI IRQ conflict.

BUG=b:181555900
TEST=check dmesg there are no IRQ request errors like below.
genirq: Flags mismatch irq 27. 00002008 (sx932x_event) vs. 00000080 (idma64.1)

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idf88fae9e244858445c45e66e26715cebe0c93ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-06-30 02:46:26 +00:00
Rex-BC Chen
9c098e27db vc/mediatek/mt8195: Fix license headers 
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: If5e72b36242e1aff7ce2609ea6bdbaea53683bd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-06-30 02:22:56 +00:00
Tim Wawrzynczak
ed042a9687 soc/intel/tigerlake: Enable support for common IRQ block 
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch
allows tigerlake boards to dynamically assign PCI IRQs. This means not
relying on FSP defaults, which eliminates the problem of PCI IRQs
interfering with GPIO IRQs routed to the same IRQ, when both have
selected IO-APIC routing.

BUG=b:171580862
TEST=on delbin, grep 'IO-APIC' /proc/interrupts (compressed to fit)
   0:     6     0     0   0  IO-APIC    2-edge      timer
   1:     0    35     0   0  IO-APIC    1-edge      i8042
   8:     0     0     0   0  IO-APIC    8-edge      rtc0
   9:     0   601     0   0  IO-APIC    9-fasteoi   acpi
  14:     1     0     0   0  IO-APIC   14-fasteoi   INT34C5:00
  20:     0     0     0 516  IO-APIC   20-fasteoi   idma64.6, ttyS0
  28:     0   395     0   0  IO-APIC   28-fasteoi   idma64.0, i2c_design
  29:     0     0  1654   0  IO-APIC   29-fasteoi   idma64.1, i2c_design
  30:     0     0     0   0  IO-APIC   30-fasteoi   idma64.2, i2c_design
  31:     0     0     0   0  IO-APIC   31-fasteoi   idma64.3, i2c_design
  32:     0     0     0   0  IO-APIC   32-fasteoi   idma64.4, i2c_design
  33:     0     0 14469   0  IO-APIC   33-fasteoi   idma64.5, i2c_design
  35:     0 18494     0   0  IO-APIC   35-edge      cr50_spi
  36: 95705     0     0   0  IO-APIC   36-fasteoi   idma64.7, pxa2xx-spi
  37:     0     0  1978   0  IO-APIC   37-fasteoi   idma64.8, pxa2xx-spi
  51:  1865     0     0   0  IO-APIC   51-fasteoi   ELAN9008:00
  59:     0     0   422   0  IO-APIC   59-fasteoi   ELAN0000:00
 116:     0     0     0  23  IO-APIC  116-fasteoi   chromeos-ec
abbreviated _PRT dump:
Method (_PRT, 0, NotSerialized)  // _PRT: PCI Routing Table
  If (PICM)
    Package () {0x0002FFFF, 0x00, 0x00, 0x10},
    Package () {0x0004FFFF, 0x00, 0x00, 0x11},
    Package () {0x0005FFFF, 0x00, 0x00, 0x12},
    Package () {0x0006FFFF, 0x00, 0x00, 0x13},
    Package () {0x0007FFFF, 0x00, 0x00, 0x14},
    Package () {0x0007FFFF, 0x01, 0x00, 0x15},
    Package () {0x0007FFFF, 0x02, 0x00, 0x16},
    Package () {0x0007FFFF, 0x03, 0x00, 0x17},
    Package () {0x000DFFFF, 0x00, 0x00, 0x10},
    Package () {0x000DFFFF, 0x01, 0x00, 0x11},
    Package () {0x000DFFFF, 0x02, 0x00, 0x12},
    Package () {0x0010FFFF, 0x00, 0x00, 0x13},
    Package () {0x0010FFFF, 0x01, 0x00, 0x14},
    Package () {0x0011FFFF, 0x00, 0x00, 0x18},
    Package () {0x0012FFFF, 0x00, 0x00, 0x19},
    Package () {0x0012FFFF, 0x01, 0x00, 0x1A},
    Package () {0x0013FFFF, 0x00, 0x00, 0x1B},
    Package () {0x0014FFFF, 0x00, 0x00, 0x15},
    Package () {0x0015FFFF, 0x00, 0x00, 0x1C},
    Package () {0x0015FFFF, 0x01, 0x00, 0x1D},
    Package () {0x0015FFFF, 0x02, 0x00, 0x1E},
    Package () {0x0015FFFF, 0x03, 0x00, 0x1F},
    Package () {0x0016FFFF, 0x00, 0x00, 0x16},
    Package () {0x0016FFFF, 0x01, 0x00, 0x17},
    Package () {0x0016FFFF, 0x02, 0x00, 0x10},
    Package () {0x0016FFFF, 0x03, 0x00, 0x11},
    Package () {0x0017FFFF, 0x00, 0x00, 0x12},
    Package () {0x0019FFFF, 0x00, 0x00, 0x20},
    Package () {0x0019FFFF, 0x01, 0x00, 0x21},
    Package () {0x0019FFFF, 0x02, 0x00, 0x22},
    Package () {0x001CFFFF, 0x00, 0x00, 0x10},
    Package () {0x001CFFFF, 0x01, 0x00, 0x11},
    Package () {0x001CFFFF, 0x02, 0x00, 0x12},
    Package () {0x001CFFFF, 0x03, 0x00, 0x13},
    Package () {0x001DFFFF, 0x00, 0x00, 0x10},
    Package () {0x001DFFFF, 0x01, 0x00, 0x11},
    Package () {0x001DFFFF, 0x02, 0x00, 0x12},
    Package () {0x001DFFFF, 0x03, 0x00, 0x13},
    Package () {0x001EFFFF, 0x00, 0x00, 0x14},
    Package () {0x001EFFFF, 0x01, 0x00, 0x15},
    Package () {0x001EFFFF, 0x02, 0x00, 0x24},
    Package () {0x001EFFFF, 0x03, 0x00, 0x25},
    Package () {0x001FFFFF, 0x01, 0x00, 0x17},
    Package () {0x001FFFFF, 0x02, 0x00, 0x14},
    Package () {0x001FFFFF, 0x03, 0x00, 0x15},
    Package () {0x001FFFFF, 0x00, 0x00, 0x16},
  Else
    Package () {0x0002FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0004FFFF, 0x00, 0x00, 0x0A},
    Package () {0x0005FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0006FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0007FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0007FFFF, 0x01, 0x00, 0x0B},
    Package () {0x0007FFFF, 0x02, 0x00, 0x0B},
    Package () {0x0007FFFF, 0x03, 0x00, 0x0B},
    Package () {0x000DFFFF, 0x00, 0x00, 0x0B},
    Package () {0x000DFFFF, 0x01, 0x00, 0x0A},
    Package () {0x000DFFFF, 0x02, 0x00, 0x0B},
    Package () {0x0010FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0010FFFF, 0x01, 0x00, 0x0B},
    Package () {0x0014FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0016FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0016FFFF, 0x01, 0x00, 0x0B},
    Package () {0x0016FFFF, 0x02, 0x00, 0x0B},
    Package () {0x0016FFFF, 0x03, 0x00, 0x0A},
    Package () {0x0017FFFF, 0x00, 0x00, 0x0B},
    Package () {0x001CFFFF, 0x00, 0x00, 0x0B},
    Package () {0x001CFFFF, 0x01, 0x00, 0x0A},
    Package () {0x001CFFFF, 0x02, 0x00, 0x0B},
    Package () {0x001CFFFF, 0x03, 0x00, 0x0B},
    Package () {0x001DFFFF, 0x00, 0x00, 0x0B},
    Package () {0x001DFFFF, 0x01, 0x00, 0x0A},
    Package () {0x001DFFFF, 0x02, 0x00, 0x0B},
    Package () {0x001DFFFF, 0x03, 0x00, 0x0B},
    Package () {0x001EFFFF, 0x00, 0x00, 0x0B},
    Package () {0x001EFFFF, 0x01, 0x00, 0x0B},
    Package () {0x001FFFFF, 0x01, 0x00, 0x0B},
    Package () {0x001FFFFF, 0x02, 0x00, 0x0B},
    Package () {0x001FFFFF, 0x03, 0x00, 0x0B},
    Package () {0x001FFFFF, 0x00, 0x00, 0x0B},

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ieb241f2b91af52a7e2d0efe997d35732882ac463
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49409
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-06-29 21:54:17 +00:00
Tim Wawrzynczak
43607e4751 soc/intel/alderlake: Enable support for common IRQ block 
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch
allows ADL boards to dynamically assign PCI IRQs. This means not relying
on FSP defaults, which eliminates the problem of PCI IRQs interfering
with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC
routing.

BUG=b:176858827
TEST=brya0, grep 'IO-APIC' /proc/interrupts (compressed to fit)
   0:   36     0  0  0     0    0    0   0   IO-APIC    2-edge      time
   1:    0     0  9  0     0    0    0   0   IO-APIC    1-edge      i804
   8:    0     0  0  0     0    0    0   0   IO-APIC    8-edge      rtc0
   9:    0 21705  0  0     0    0    0   0   IO-APIC    9-fasteoi   acpi
  14:    0     0  0  0     0    0    0   0   IO-APIC   14-fasteoi   INTC
  18:    0     0  0  0     0    0    0   0   IO-APIC   18-fasteoi   inte
  20:    0     0  0  0     0    0    0 394   IO-APIC   20-fasteoi   idma
  23: 2280     0  0  0     0    0    0   0   IO-APIC   23-fasteoi   idma
  26:    0     0 26  0     0    0    0   0   IO-APIC   26-fasteoi   idma
  27:    0     0  0  6     0    0    0   0   IO-APIC   27-fasteoi   idma
  28:    0     0  0  0     0    0    0   0   IO-APIC   28-fasteoi   idma
  29:    0     0  0  0 25784    0    0   0   IO-APIC   29-fasteoi   idma
  30:    0     0  0  0     0    0    0   0   IO-APIC   30-fasteoi   idma
  31:    0     0  0  0     0    0  226   0   IO-APIC   31-fasteoi   idma
  77:    0     0  0  0     0 2604    0   0   IO-APIC   77-edge      cr50
 100:    0     0  0  0     0    0    0   0   IO-APIC  100-fasteoi   ELAN
 103:    0     0  0  0     0    0    0   0   IO-APIC  103-fasteoi   chro
abbreviated _PRT dump:
    If (PICM)
          Package (){0x0002FFFF, 0, 0, 0x10},
          Package (){0x0004FFFF, 0, 0, 0x11},
          Package (){0x0005FFFF, 0, 0, 0x12},
          Package (){0x0006FFFF, 0, 0, 0x13},
          Package (){0x0006FFFF, 1, 0, 0x14},
          Package (){0x0007FFFF, 0, 0, 0x15},
          Package (){0x0007FFFF, 1, 0, 0x16},
          Package (){0x0007FFFF, 2, 0, 0x17},
          Package (){0x0007FFFF, 3, 0, 0x10},
          Package (){0x000DFFFF, 0, 0, 0x11},
          Package (){0x0012FFFF, 0, 0, 0x18},
          Package (){0x0012FFFF, 1, 0, 0x19},
          Package (){0x0014FFFF, 0, 0, 0x12},
          Package (){0x0014FFFF, 1, 0, 0x13},
          Package (){0x0015FFFF, 0, 0, 0x1A},
          Package (){0x0015FFFF, 1, 0, 0x1B},
          Package (){0x0015FFFF, 2, 0, 0x1C},
          Package (){0x0015FFFF, 3, 0, 0x1D},
          Package (){0x0016FFFF, 0, 0, 0x14},
          Package (){0x0016FFFF, 1, 0, 0x15},
          Package (){0x0016FFFF, 2, 0, 0x16},
          Package (){0x0016FFFF, 3, 0, 0x17},
          Package (){0x0017FFFF, 0, 0, 0x10},
          Package (){0x0019FFFF, 0, 0, 0x1E},
          Package (){0x0019FFFF, 1, 0, 0x1F},
          Package (){0x0019FFFF, 2, 0, 0x20},
          Package (){0x001CFFFF, 0, 0, 0x10},
          Package (){0x001CFFFF, 1, 0, 0x11},
          Package (){0x001CFFFF, 2, 0, 0x12},
          Package (){0x001CFFFF, 3, 0, 0x13},
          Package (){0x001DFFFF, 0, 0, 0x10},
          Package (){0x001DFFFF, 1, 0, 0x11},
          Package (){0x001DFFFF, 2, 0, 0x12},
          Package (){0x001DFFFF, 3, 0, 0x13},
          Package (){0x001EFFFF, 0, 0, 0x14},
          Package (){0x001EFFFF, 1, 0, 0x15},
          Package (){0x001EFFFF, 2, 0, 0x16},
          Package (){0x001EFFFF, 3, 0, 0x17},
          Package (){0x001FFFFF, 1, 0, 0x15},
          Package (){0x001FFFFF, 2, 0, 0x16},
          Package (){0x001FFFFF, 3, 0, 0x17},
          Package (){0x001FFFFF, 0, 0, 0x14},
    Else
          Package (){0x0002FFFF, 0, 0, 0x0B},
	  Package (){0x0004FFFF, 0, 0, 0x0A},
	  Package (){0x0005FFFF, 0, 0, 0x0B},
	  Package (){0x0006FFFF, 0, 0, 0x0B},
	  Package (){0x0006FFFF, 1, 0, 0x0B},
	  Package (){0x0007FFFF, 0, 0, 0x0B},
	  Package (){0x0007FFFF, 1, 0, 0x0B},
	  Package (){0x0007FFFF, 2, 0, 0x0B},
	  Package (){0x0007FFFF, 3, 0, 0x0B},
	  Package (){0x000DFFFF, 0, 0, 0x0A},
	  Package (){0x0014FFFF, 0, 0, 0x0B},
	  Package (){0x0014FFFF, 1, 0, 0x0B},
	  Package (){0x0016FFFF, 0, 0, 0x0B},
	  Package (){0x0016FFFF, 1, 0, 0x0B},
	  Package (){0x0016FFFF, 2, 0, 0x0B},
	  Package (){0x0016FFFF, 3, 0, 0x0B},
	  Package (){0x0017FFFF, 0, 0, 0x0B},
	  Package (){0x001CFFFF, 0, 0, 0x0B},
	  Package (){0x001CFFFF, 1, 0, 0x0A},
	  Package (){0x001CFFFF, 2, 0, 0x0B},
	  Package (){0x001CFFFF, 3, 0, 0x0B},
	  Package (){0x001DFFFF, 0, 0, 0x0B},
	  Package (){0x001DFFFF, 1, 0, 0x0A},
	  Package (){0x001DFFFF, 2, 0, 0x0B},
	  Package (){0x001DFFFF, 3, 0, 0x0B},
	  Package (){0x001EFFFF, 0, 0, 0x0B},
	  Package (){0x001EFFFF, 1, 0, 0x0B},
	  Package (){0x001EFFFF, 2, 0, 0x0B},
	  Package (){0x001EFFFF, 3, 0, 0x0B},
	  Package (){0x001FFFFF, 1, 0, 0x0B},
	  Package (){0x001FFFFF, 2, 0, 0x0B},
	  Package (){0x001FFFFF, 3, 0, 0x0B},
	  Package (){0x001FFFFF, 0, 0, 0x0B},
dmesg shows no GSI or PCI errors, TPM & touchpad IRQs still work

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1e7a708183ac4170b28da9565137fa2f5088a7eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54683
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-06-29 21:54:00 +00:00
Tim Wawrzynczak
f9bb1b46a2 soc/intel/cannonlake: Use new IRQ module 
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch
allows cannonlake boards to dynamically assign PCI IRQs. This means not
relying on FSP defaults, which eliminates the problem of PCI IRQs
interfering with GPIO IRQs routed to the same IRQ, when both have
selected IO-APIC routing.

Also prodrive/hermes (intel/cannonlake) was the only user of
uart_acpi_write_irq(), therefore use the allocated IRQ instead of the
fixed IRQ number in that function to preserve behavior.

BUG=b:130217151
TEST=on dratini, grep 'IO-APIC' /proc/interrupts (compressed to fit)
   0:     11     0    0 0 IO-APIC    2-edge      timer
   1:      0   661    0 0 IO-APIC    1-edge      i8042
   8:      0     0    0 0 IO-APIC    8-edge      rtc0
   9:      0   874    0 0 IO-APIC    9-fasteoi   acpi
  14:      0     0    1 0 IO-APIC   14-fasteoi   INT34BB:00
  17:      0 10633    0 0 IO-APIC   17-fasteoi   mmc1
  19:      0     0    0 0 IO-APIC   19-fasteoi   mmc0
  22:      0     0    0 0 IO-APIC   22-fasteoi   i801_smbus
  26: 153738     0    0 0 IO-APIC   26-fasteoi   idma64.0, i2c_designwar
  27:      0     8    0 0 IO-APIC   27-fasteoi   idma64.1, i2c_designwar
  30:      0     0  227 0 IO-APIC   30-fasteoi   i2c_designware.2
  33:      0     0    0 0 IO-APIC   33-fasteoi   idma64.3
  35:  43107     0    0 0 IO-APIC   35-fasteoi   idma64.4, pxa2xx-spi.4
  36:      0     0 2039 0 IO-APIC   36-fasteoi   idma64.5, pxa2xx-spi.5
  45:      0     0 9451 0 IO-APIC   45-edge      ELAN0000:00
  85:      0     0    0 0 IO-APIC   85-fasteoi   chromeos-ec
  93:      0  7741    0 0 IO-APIC   93-edge      cr50_spi
abbreviated _PRT dump:
If (PICM)
  Package () {0x0001FFFF, 0x00, 0x00, 0x10},
  Package () {0x0001FFFF, 0x01, 0x00, 0x11},
  Package () {0x0001FFFF, 0x02, 0x00, 0x12},
  Package () {0x0002FFFF, 0x00, 0x00, 0x13},
  Package () {0x0004FFFF, 0x00, 0x00, 0x14},
  Package () {0x0005FFFF, 0x00, 0x00, 0x15},
  Package () {0x0008FFFF, 0x00, 0x00, 0x16},
  Package () {0x0012FFFF, 0x01, 0x00, 0x17},
  Package () {0x0012FFFF, 0x02, 0x00, 0x10},
  Package () {0x0012FFFF, 0x00, 0x00, 0x18},
  Package () {0x0013FFFF, 0x00, 0x00, 0x19},
  Package () {0x0014FFFF, 0x00, 0x00, 0x11}
  Package () {0x0014FFFF, 0x01, 0x00, 0x12},
  Package () {0x0014FFFF, 0x02, 0x00, 0x13},
  Package () {0x0014FFFF, 0x03, 0x00, 0x14},
  Package () {0x0015FFFF, 0x00, 0x00, 0x1A},
  Package () {0x0015FFFF, 0x01, 0x00, 0x1B},
  Package () {0x0015FFFF, 0x02, 0x00, 0x1C},
  Package () {0x0015FFFF, 0x03, 0x00, 0x1D},
  Package () {0x0016FFFF, 0x00, 0x00, 0x15},
  Package () {0x0016FFFF, 0x01, 0x00, 0x16},
  Package () {0x0016FFFF, 0x02, 0x00, 0x17},
  Package () {0x0016FFFF, 0x03, 0x00, 0x10},
  Package () {0x0017FFFF, 0x00, 0x00, 0x11},
  Package () {0x0019FFFF, 0x00, 0x00, 0x1E},
  Package () {0x0019FFFF, 0x01, 0x00, 0x1F},
  Package () {0x0019FFFF, 0x02, 0x00, 0x20},
  Package () {0x001AFFFF, 0x00, 0x00, 0x12},
  Package () {0x001CFFFF, 0x00, 0x00, 0x10},
  Package () {0x001CFFFF, 0x01, 0x00, 0x11},
  Package () {0x001CFFFF, 0x02, 0x00, 0x12},
  Package () {0x001CFFFF, 0x03, 0x00, 0x13},
  Package () {0x001DFFFF, 0x00, 0x00, 0x10},
  Package () {0x001DFFFF, 0x01, 0x00, 0x11},
  Package () {0x001DFFFF, 0x02, 0x00, 0x12},
  Package () {0x001DFFFF, 0x03, 0x00, 0x13},
  Package () {0x001EFFFF, 0x00, 0x00, 0x21},
  Package () {0x001EFFFF, 0x01, 0x00, 0x22},
  Package () {0x001EFFFF, 0x02, 0x00, 0x23},
  Package () {0x001EFFFF, 0x03, 0x00, 0x24},
  Package () {0x001FFFFF, 0x01, 0x00, 0x15},
  Package () {0x001FFFFF, 0x02, 0x00, 0x16},
  Package () {0x001FFFFF, 0x03, 0x00, 0x17},
  Package () {0x001FFFFF, 0x00, 0x00, 0x14},
Else
  Package () {0x0001FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0001FFFF, 0x01, 0x00, 0x0A},
  Package () {0x0001FFFF, 0x02, 0x00, 0x0B},
  Package () {0x0002FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0004FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0005FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0008FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0012FFFF, 0x01, 0x00, 0x0B},
  Package () {0x0012FFFF, 0x02, 0x00, 0x0B},
  Package () {0x0014FFFF, 0x00, 0x00, 0x0A},
  Package () {0x0014FFFF, 0x01, 0x00, 0x0B},
  Package () {0x0014FFFF, 0x02, 0x00, 0x0B},
  Package () {0x0014FFFF, 0x03, 0x00, 0x0B},
  Package () {0x0016FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0016FFFF, 0x01, 0x00, 0x0B},
  Package () {0x0016FFFF, 0x02, 0x00, 0x0B},
  Package () {0x0016FFFF, 0x03, 0x00, 0x0B},
  Package () {0x0017FFFF, 0x00, 0x00, 0x0A},
  Package () {0x001AFFFF, 0x00, 0x00, 0x0B},
  Package () {0x001CFFFF, 0x00, 0x00, 0x0B},
  Package () {0x001CFFFF, 0x01, 0x00, 0x0A},
  Package () {0x001CFFFF, 0x02, 0x00, 0x0B},
  Package () {0x001CFFFF, 0x03, 0x00, 0x0B},
  Package () {0x001DFFFF, 0x00, 0x00, 0x0B},
  Package () {0x001DFFFF, 0x01, 0x00, 0x0A},
  Package () {0x001DFFFF, 0x02, 0x00, 0x0B},
  Package () {0x001DFFFF, 0x03, 0x00, 0x0B},
  Package () {0x001FFFFF, 0x01, 0x00, 0x0B},
  Package () {0x001FFFFF, 0x02, 0x00, 0x0B},
  Package () {0x001FFFFF, 0x03, 0x00, 0x0B},
  Package () {0x001FFFFF, 0x00, 0x00, 0x0B},

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I914ac65470635f351d6311dc9b65e8e4d8d8ecfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55968
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-06-29 21:53:49 +00:00
Tim Wawrzynczak
664c58ab95 soc/intel/cannonlake: Add some missing DEVFN macros 
BUG=b:130217151

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If535ad0bdd46d3315493155e64968d305aa34799
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55967
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-06-29 21:53:34 +00:00
Tim Wawrzynczak
61005c8eb5 soc/intel/common/irq: Add function to return IRQ for PCI devfn 
The IRQ for a single device may be required elsewhere, therefore provide
get_pci_devfn_irq.

BUG=b:130217151, b:171580862, b:176858827

Change-Id: Ibebd821767a2698c9e60b09eeeff3bb596359728
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55826
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-06-29 21:52:44 +00:00
Tim Wawrzynczak
e9ee919fac soc/intel/common/irq: Internally cache PCI IRQ results 
The results of the PCI IRQ assignments are used in several places, so
it makes for a nicer API to cache the results and provide simpler
functions for the SoCs to call.

BUG=b:130217151, b:171580862, b:176858827

Change-Id: Id79eae3f2360cd64f66e7f53e1d78a23cfe5e9df
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55825
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-06-29 21:52:20 +00:00