Tim Wawrzynczak ed042a9687 soc/intel/tigerlake: Enable support for common IRQ block
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch
allows tigerlake boards to dynamically assign PCI IRQs. This means not
relying on FSP defaults, which eliminates the problem of PCI IRQs
interfering with GPIO IRQs routed to the same IRQ, when both have
selected IO-APIC routing.

BUG=b:171580862
TEST=on delbin, grep 'IO-APIC' /proc/interrupts (compressed to fit)
   0:     6     0     0   0  IO-APIC    2-edge      timer
   1:     0    35     0   0  IO-APIC    1-edge      i8042
   8:     0     0     0   0  IO-APIC    8-edge      rtc0
   9:     0   601     0   0  IO-APIC    9-fasteoi   acpi
  14:     1     0     0   0  IO-APIC   14-fasteoi   INT34C5:00
  20:     0     0     0 516  IO-APIC   20-fasteoi   idma64.6, ttyS0
  28:     0   395     0   0  IO-APIC   28-fasteoi   idma64.0, i2c_design
  29:     0     0  1654   0  IO-APIC   29-fasteoi   idma64.1, i2c_design
  30:     0     0     0   0  IO-APIC   30-fasteoi   idma64.2, i2c_design
  31:     0     0     0   0  IO-APIC   31-fasteoi   idma64.3, i2c_design
  32:     0     0     0   0  IO-APIC   32-fasteoi   idma64.4, i2c_design
  33:     0     0 14469   0  IO-APIC   33-fasteoi   idma64.5, i2c_design
  35:     0 18494     0   0  IO-APIC   35-edge      cr50_spi
  36: 95705     0     0   0  IO-APIC   36-fasteoi   idma64.7, pxa2xx-spi
  37:     0     0  1978   0  IO-APIC   37-fasteoi   idma64.8, pxa2xx-spi
  51:  1865     0     0   0  IO-APIC   51-fasteoi   ELAN9008:00
  59:     0     0   422   0  IO-APIC   59-fasteoi   ELAN0000:00
 116:     0     0     0  23  IO-APIC  116-fasteoi   chromeos-ec
abbreviated _PRT dump:
Method (_PRT, 0, NotSerialized)  // _PRT: PCI Routing Table
  If (PICM)
    Package () {0x0002FFFF, 0x00, 0x00, 0x10},
    Package () {0x0004FFFF, 0x00, 0x00, 0x11},
    Package () {0x0005FFFF, 0x00, 0x00, 0x12},
    Package () {0x0006FFFF, 0x00, 0x00, 0x13},
    Package () {0x0007FFFF, 0x00, 0x00, 0x14},
    Package () {0x0007FFFF, 0x01, 0x00, 0x15},
    Package () {0x0007FFFF, 0x02, 0x00, 0x16},
    Package () {0x0007FFFF, 0x03, 0x00, 0x17},
    Package () {0x000DFFFF, 0x00, 0x00, 0x10},
    Package () {0x000DFFFF, 0x01, 0x00, 0x11},
    Package () {0x000DFFFF, 0x02, 0x00, 0x12},
    Package () {0x0010FFFF, 0x00, 0x00, 0x13},
    Package () {0x0010FFFF, 0x01, 0x00, 0x14},
    Package () {0x0011FFFF, 0x00, 0x00, 0x18},
    Package () {0x0012FFFF, 0x00, 0x00, 0x19},
    Package () {0x0012FFFF, 0x01, 0x00, 0x1A},
    Package () {0x0013FFFF, 0x00, 0x00, 0x1B},
    Package () {0x0014FFFF, 0x00, 0x00, 0x15},
    Package () {0x0015FFFF, 0x00, 0x00, 0x1C},
    Package () {0x0015FFFF, 0x01, 0x00, 0x1D},
    Package () {0x0015FFFF, 0x02, 0x00, 0x1E},
    Package () {0x0015FFFF, 0x03, 0x00, 0x1F},
    Package () {0x0016FFFF, 0x00, 0x00, 0x16},
    Package () {0x0016FFFF, 0x01, 0x00, 0x17},
    Package () {0x0016FFFF, 0x02, 0x00, 0x10},
    Package () {0x0016FFFF, 0x03, 0x00, 0x11},
    Package () {0x0017FFFF, 0x00, 0x00, 0x12},
    Package () {0x0019FFFF, 0x00, 0x00, 0x20},
    Package () {0x0019FFFF, 0x01, 0x00, 0x21},
    Package () {0x0019FFFF, 0x02, 0x00, 0x22},
    Package () {0x001CFFFF, 0x00, 0x00, 0x10},
    Package () {0x001CFFFF, 0x01, 0x00, 0x11},
    Package () {0x001CFFFF, 0x02, 0x00, 0x12},
    Package () {0x001CFFFF, 0x03, 0x00, 0x13},
    Package () {0x001DFFFF, 0x00, 0x00, 0x10},
    Package () {0x001DFFFF, 0x01, 0x00, 0x11},
    Package () {0x001DFFFF, 0x02, 0x00, 0x12},
    Package () {0x001DFFFF, 0x03, 0x00, 0x13},
    Package () {0x001EFFFF, 0x00, 0x00, 0x14},
    Package () {0x001EFFFF, 0x01, 0x00, 0x15},
    Package () {0x001EFFFF, 0x02, 0x00, 0x24},
    Package () {0x001EFFFF, 0x03, 0x00, 0x25},
    Package () {0x001FFFFF, 0x01, 0x00, 0x17},
    Package () {0x001FFFFF, 0x02, 0x00, 0x14},
    Package () {0x001FFFFF, 0x03, 0x00, 0x15},
    Package () {0x001FFFFF, 0x00, 0x00, 0x16},
  Else
    Package () {0x0002FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0004FFFF, 0x00, 0x00, 0x0A},
    Package () {0x0005FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0006FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0007FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0007FFFF, 0x01, 0x00, 0x0B},
    Package () {0x0007FFFF, 0x02, 0x00, 0x0B},
    Package () {0x0007FFFF, 0x03, 0x00, 0x0B},
    Package () {0x000DFFFF, 0x00, 0x00, 0x0B},
    Package () {0x000DFFFF, 0x01, 0x00, 0x0A},
    Package () {0x000DFFFF, 0x02, 0x00, 0x0B},
    Package () {0x0010FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0010FFFF, 0x01, 0x00, 0x0B},
    Package () {0x0014FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0016FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0016FFFF, 0x01, 0x00, 0x0B},
    Package () {0x0016FFFF, 0x02, 0x00, 0x0B},
    Package () {0x0016FFFF, 0x03, 0x00, 0x0A},
    Package () {0x0017FFFF, 0x00, 0x00, 0x0B},
    Package () {0x001CFFFF, 0x00, 0x00, 0x0B},
    Package () {0x001CFFFF, 0x01, 0x00, 0x0A},
    Package () {0x001CFFFF, 0x02, 0x00, 0x0B},
    Package () {0x001CFFFF, 0x03, 0x00, 0x0B},
    Package () {0x001DFFFF, 0x00, 0x00, 0x0B},
    Package () {0x001DFFFF, 0x01, 0x00, 0x0A},
    Package () {0x001DFFFF, 0x02, 0x00, 0x0B},
    Package () {0x001DFFFF, 0x03, 0x00, 0x0B},
    Package () {0x001EFFFF, 0x00, 0x00, 0x0B},
    Package () {0x001EFFFF, 0x01, 0x00, 0x0B},
    Package () {0x001FFFFF, 0x01, 0x00, 0x0B},
    Package () {0x001FFFFF, 0x02, 0x00, 0x0B},
    Package () {0x001FFFFF, 0x03, 0x00, 0x0B},
    Package () {0x001FFFFF, 0x00, 0x00, 0x0B},

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ieb241f2b91af52a7e2d0efe997d35732882ac463
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49409
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29 21:54:17 +00:00
2021-06-26 10:09:06 +00:00
2019-09-10 12:52:18 +00:00
2012-11-01 23:13:39 +01:00
2006-08-12 22:03:36 +00:00
2021-05-19 19:56:02 +00:00

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.

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