This patch adds support for the Kontron mAL10 COMe module with the
Apollo Lake SoC together with Kontron T10-TNI carrierboard.
Working:
- UART console and I2C on Kontron kempld;
- USB2/3
- Ethernet controller
- eMMC
- SATA
- PCIe ports
- IGD/DP
- SMBus
- HWM
Not tested:
- IGD/LVDS
- SDIO
TODO:
- HDA (codec IDT 92HD73C1X5, currently disabled)
Tested payloads:
- SeaBIOS
- Tianocore, UEFIPayload - without video, EFI-shell in console only
Tested on COMe module with Intel Atom x5-E3940 processor (4 Core,
1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS
(5.0.0-32-generic linux kernel)
Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
If AGESA is added as a raw binary (and not a stage), then cbfstool
does not perform relocation. In this case, it should be added only to
COREBOOT (i.e. default) CBFS since the binary needs to be present only
in one specific location that is present in the default CBFS.
Change-Id: I7a7edc217663f9d1d36b05308bbd35f56a28b9b1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This register needs to be updated differently depending on the CPU
generation and stepping. Handle this as per reference code. Further,
introduce a bitfield for the register to make the code easier to read.
Change-Id: I51649cb2fd06c5896f90559f59f25d49a8e6695e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Values differ between Sandy and Ivy Bridge. Remove the lookup table,
since it contains duplicated values and is hard to see which values
correspond to which frequencies. New values come from reference code.
Change-Id: I3b28568f0053f1b39618e16bdffc24207547d81f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This is actually aggressive write training, similar to aggressive read
training. Rename it accordingly and refactor it to improve clarity.
Enabling IOSAV_n_SPECIAL_COMMAND_ADDR optimizations must only be done
for later Ivy Bridge steppings. Therefore, guard the code accordingly.
Change-Id: Ia3331b95c265113d94cb5d66c57a97cb77fc3dc9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
When memory is running at fast frequencies, power-down modes can lessen
system stability. Check tXP and tXPDLL values and use safer power down
modes if their values are high. Do not use APD with DLL-off on mobile:
vendor firmware does not use it, and it can influence system stability.
Change-Id: Ic8e98162ca86ae454a8c951be163d58960940e0e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This is actually an (incomplete) aggressive read training algorithm.
Rename functions and variables accordingly, and tidy up declarations.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I8a4900f8e3acffe4e4d75a51a2588ad6b65eb411
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The byte-wise error mask only needs to be set for certain corner cases
in read MPR training. Thus, minimize writes to this register.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I0bb8d99ad60c4964f896d303878e5982ae1dcdbe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Create and rename a few functions to contain the entire JEDEC write
leveling algorithm. Not all write training is JEDEC write leveling.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: Ie9c6315340164029e30354723b4103d906633602
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There's no need to reprogram the exact same sequence over a hundred
times. Move it out of the timB loop, and drop the `test_timB` function.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I375e325cf8b5369889b9cb059c3675cd00bdbb3f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Given that it sets the receive enable mode bit in the GDCRTRAININGMOD
register, it's clear that this is about receive enable calibration.
Remove a potentially-outdated comment. Proper documentation will be
written once code refactoring and various improvements are complete.
Change-Id: Iaefc8905adf2878bec3b43494dc53530064a9f5d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47576
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to run a write leveling test, one needs to unset the Qoff bit
in MR1, then run the test, and finally set Qoff again. The current IOSAV
sequence uses two subsequences to perform the test, while the other two
are unused. It is possible to perform the two necessary MR1 updates in
the same sequence, which can potentially improve runtime (not measured).
Since `write_mrreg` is no longer used, it is necessary to handle address
mirroring explicitly. This can be accomplished with the recently-added
`ddr3_mirror_mrreg` function, which is also used in `write_mrreg`.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I65ca1aa32cdb177d2a9e27c3b02e74ac0c882794
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47614
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD family 17h and newer don't use cache as RAM, since the RAM is
already initialized by the PSP when the x86 cores are released from
reset. Therefore they use a different linker script as the rest of the
x86 chips in coreboot do. Since there will be support for newer
generations than Picasso will be added, move those linker scripts from
soc/amd/picasso to soc/amd/common/block/cpu/noncar.
TEST=Timeless build of amd/mandolin and amd/gardenia result in identical
binaries.
Change-Id: Ie60372aa498b6e505708f97213b502c9d0b3534b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
