22ad95394e
sb/intel/x/lpc.c: Drop commented-out gpio_init call
...
Change-Id: I4255c63f87e8243237204ac86eb85e34b5aaa225
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2021-02-12 07:56:57 +00:00
6324759784
sb/intel/x/lpc.c: Drop pch_disable_smm_only_flashing
...
The southbridge common SPI support already does this.
Tested on Asrock B85M Pro4, internal flashing and MRC cache still work.
Change-Id: I7ce0ca584cd3d42a10cdb74f45742f1eadc01bfa
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2021-02-12 07:56:48 +00:00
9382f0c251
sb/intel/lynxpoint: Do not mask out TCO status bits
...
Not all TCO status bits have a corresponding enable bit. Masking out the
status register with the enable register causes these events to be lost.
Tested on Asrock B85M Pro4, BIOSWR_STS events are now detected.
Change-Id: I49abb5a4a99e943e57e0aaa6f06ff63bdf957cd3
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2021-02-12 07:56:33 +00:00
04f1de3e14
sb/intel/lynxpoint: Only generate SerialIO SSDT for PCH-LP
...
Lynxpoint PCH-H does not have SerialIO, so do not generate its SSDT.
Change-Id: Ie816ebd470df93a45826498bf21be59ff0a813bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
2021-02-12 07:56:04 +00:00
1afe46913a
sb/intel/lynxpoint/pch.h: Guard macro parameters
...
Guard against unintended operator precedence and associativity issues.
Tested on Asrock B85M Pro4, still boots.
Change-Id: I2b22af17816e5383c7eb215a773eb6750d4ed9bc
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
2021-02-12 07:55:24 +00:00
06f1fed3a1
sb/intel/common: Move named packages out of method
...
IASL complains that creation of named objects within a method is highly
inefficient. Avoid this by moving these named objects out of the method.
Change-Id: Iabfb20dcb3f655658844d99ab7a3b479684d9d19
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
2021-02-12 07:54:55 +00:00
3529024071
nb/intel/common/fixed_bars.h: Add casts to uintptr_t
...
64-bit builds need this, as the Kconfig values fit in a 32-bit integer.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I570374f92394f839a97e28fabc8fa07a7e673e83
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2021-02-12 07:52:37 +00:00
f95b9b4b09
nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors
...
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I3ff4577ce662697cb3d8fb34003217fd6275dd42
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2021-02-12 07:52:25 +00:00
ea573b04d8
sandybridge MRC boards: Drop channel disable masks
...
Platform code will overwrite these values anyway, so do not program them
in mainboards.
Change-Id: I7571d336a1402c6cfae5835a95dc706a28106271
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49751
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-12 07:52:01 +00:00
64c6a746ac
soc/intel/broadwell: Use southbridge common RCBA
...
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I94953bed3f331848271464bee829f8209167f150
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2021-02-12 07:51:22 +00:00
75439de2d9
util/superiotool: Add ITE IT8616E/IT8656E support
...
Datasheet is not publicly available. Derive which registers to dump from
IT8625E, since there are mainboards that can use either chip depending
on BOM configuration. Default values are taken from an HP 280 G2 running
a coreboot build that does not configure the Super I/O.
Change-Id: Icc8c56e9cd19e940e85176ac51b8ef978275eb71
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-02-12 07:49:43 +00:00
86afb171b6
util/superiotool: Add ITE IT8625E support
...
Values as per "IT8625E Preliminary Specification V0.3 (For D Version)".
Change-Id: Ic3ff13d93f66d09a1f2ea953736336b201a7114c
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-02-12 07:49:33 +00:00
e49dfb6c44
mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID over I2C
...
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ifdc3f061d919c8db9001c7a4cc26eb21117958d7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2021-02-12 07:48:54 +00:00
6bcaf6f908
mb/system76/lemp9: Configure IRQs as level triggered for HID over I2C
...
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ice096777077bd2e9cfbaf744371fc372c0c05606
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2021-02-12 07:48:42 +00:00
b3a7c84b43
tests: Add lib/stack-test test case
...
Signed-off-by: Jakub Czapiga <jacz@semihalf.com >
Change-Id: Icf0cceac290618a50ecc4e65f1f9551dbf31bd32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
2021-02-12 07:48:24 +00:00
e22eef7c51
soc/amd/*/Kconfig: remove redundant SMM_TSEG condition
...
Since SMM is in TSEG on the platforms which is the default, drop the
SMM_TSEG condition for the default of SMM_TSEG_SIZE.
Change-Id: I7bd965c0794efa12ea4886a55522cc5193a1d3ac
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50498
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-12 00:42:32 +00:00
8c80d9e612
3rdparty/blobs: advance submodule pointer.
...
This adds the apcb binary for Bilby.
Change-Id: I1487369bc72734e875c5a701f27ed2d6af41cd01
Signed-off-by: Ritul Guru <ritul.bits@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-02-11 21:34:52 +00:00
fe5cf51258
util/abuild: Ensure that non-Chrome OS builds are non-Chrome OS
...
Sometimes boards enable it by default, making the Kconfig option
impossible to disable without messing with the Kconfig files. This
shouldn't happen, so report on such occurrences early.
TEST=Tried building GOOGLE_KOHAKU through abuild with -x, without
-x and both cases after having added a "select CHROMEOS" for testing
and it failed in the "without -x with select" scenario while properly
configuring and passing all other builds.
Change-Id: Ieb6bcbf3e9ca8cd4ced85c7c9ffaa39505f5a9b7
Signed-off-by: Patrick Georgi <pgeorgi@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-11 20:49:27 +00:00
373769f103
soc/amd/common/block/acpi/pm_state: don't rely on undefined behavior
...
Change-Id: I5a76a38f8d84666f6b9c0bfffecca064fa82d593
Found-by: Coverity CID 1445994
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2021-02-11 19:00:44 +00:00
5dd52c77f7
soc/amd/picasso/fch: remove comment about ForceStpClkRetry
...
The corresponding bit is marked as reserved in the PPR. Also there's no
BKDG for Picasso any more; the BKDG was mostly replaced by the PPR. Also
fix the style of the comment.
Change-Id: Iffdbb9e951cb140e4352ab0f198f72a71ba798dc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50495
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-11 17:01:11 +00:00
ea120f96c9
soc/amd/common: Fix missing header in amd_pci_utils.h
...
This was causing a build error because size_t wasn't defined.
Signed-off-by: Raul E Rangel <rrangel@chromium.org >
Change-Id: Ia467c7d6cc0f71580d0b323cb560c444d53bd7f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2021-02-11 16:45:04 +00:00
ffdf1f9503
sb/intel/ibexpeak: Drop Global NVS support
...
Was copy-pasted from bd82x6x and no mainboard actually needs it.
The few globals moved outside the GNVS will be removed, relocated or
replaced with acpigen later.
Change-Id: I590a355f1bd1e54365b2e329cfdc62384446a15c
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49280
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-11 16:38:44 +00:00
00f11c0290
sb/intel/i82801jx: Drop Global NVS support
...
Was copy-pasted from i82801ix and no mainboard actually needs it.
Change-Id: I400424540b52dc5d43aba15720b18ad57ea2ebda
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49279
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-11 16:38:15 +00:00
aa969e887a
ACPI: Move PICM declaration
...
Variable PICM was not inside GNVS region and can use a static
initialisation value.
For most AMD platforms PICM default changes from 1 to 0.
Fix comments about PICM==0 used to indicate use of i8259 PIC for
interrupt delivery.
Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-11 16:37:28 +00:00
f6f1215cdb
sb,soc/intel: Drop OSYS from GNVS
...
The value should be set by OSPM using some combination of
_OSI() queris in the \_SB._INI() method.
To maintain previous behaviour with this commit, boards where
GNVS osys initialisation was removed now do the same in ASL.
Change-Id: Id4957b12a72fbf7fa988e7ff039e47abcc072e1c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49353
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-11 16:36:15 +00:00
d6ccbb9d48
mainboards: Drop PWRS from GNVS
...
Initialize variable to 1 to indicate AC power supply.
If platform has EC it will set this correctly based on
whether plugged on the charger or not.
Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-11 16:35:32 +00:00
e0936a56ec
mb/amd/majolica: Add chromeos support
...
This change enables vboot support. To use it add CHROMEOS=y to your
config.
TEST=Boot majolica and see verstage run, and then see depthcharge load.
coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 verstage starting (log level: 8)...
Phase 1
FMAP: area GBB found @ 805000 (458752 bytes)
VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
Phase 2
Phase 3
FMAP: area GBB found @ 805000 (458752 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
VB2:vb2_verify_keyblock() Checking keyblock signature...
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
VB2:vb2_verify_fw_preamble() Verifying preamble.
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
Phase 4
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
VB2:vb2api_init_hash() HW crypto forbidden by TPM flag, using SW
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
Saving secdata firmware
Saving secdata kernel
Saving nvdata
Slot A is selected
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
CBFS: mcache @0x02017000 built for 9 files, used 0x1ec of 0x800 bytes
CBFS: Found 'fallback/romstage' @0x0 size 0x753c in mcache @0x02017000
BS: verstage times (exec / console): total (unknown) / 116 ms
coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 romstage starting (log level: 8)...
Family_Model: 00a50f00
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
CBFS: Found 'fspm.bin' @0x15440 size 0x2257d in mcache @0x02017138
Signed-off-by: Raul E Rangel <rrangel@chromium.org >
Change-Id: I43f0c6e33649332057f41f8813a86571b06032f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martinroth@google.com >
2021-02-11 16:35:13 +00:00
be35a3a012
soc/amd/cezanne/smihandler: add basic SMI APMC and sleep handler
...
Only the ACPI enable/disable functionality is implemented and sleep is
also not implemented yet. This will be added in future patches.
Change-Id: I7701944023ce2e86586679c32c4138d4488768a1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50488
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-11 16:18:48 +00:00
bb4bee8572
soc/amd/cezanne: select soc-specific ACPI functionality
...
This doesn't select HAVE_ACPI_TABLES, so no ACPI tables will be
generated for now. There's also no globalnvs.asl that corresponds to
nvs.h yet. The added nvs.h has some currently unused fields, but still
having them in the struct aligns it with Picasso and also might reduce
the noise in future ACPI patches a bit. When most of the ACPI code for
Cezanne has landed, we need to do a cleanup though.
Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2021-02-11 16:18:01 +00:00
2e97897ea3
soc/amd/*/smihandler: use size_t and unsigned int
...
signed int should only be used when we need negative values and in those
cases the value shouldn't became negative.
Change-Id: Iefac021260ff363c76bf5cd3fe3619ea1dbabdba
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50486
Reviewed-by: Martin Roth <martinroth@google.com >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-11 16:17:15 +00:00
a2db88eb5a
soc/amd/*/smihandler: remove replace southbridge references with fch
...
Change-Id: I96fc8082263800b731f1d4d9ecdc8a99c28bff32
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50485
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Reviewed-by: Martin Roth <martinroth@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-11 16:17:01 +00:00
c3ce09cdac
soc/amd/cezanne/chip: set device operations for UART MMIO devices
...
Change-Id: I5df3a61741f05364e2c20725b0b85164b197dbdc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50484
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Reviewed-by: Martin Roth <martinroth@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-11 16:16:47 +00:00
b2d8a5c017
soc/amd/cezanne: add empty mp_init_cpus
...
Change-Id: I845a7e2cfea58ca08cd2a6f0d884dbbbe1a7bdef
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50483
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Reviewed-by: Martin Roth <martinroth@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-11 16:16:37 +00:00
aa77d1364f
soc/amd/cezanne/cpu: add basic zen_2_3_init functionality
...
The MCA MSRs aren't getting cleared and no microcode update gets applied
for now. Both will be added later.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I38ce5d11787ffefdd0183c5540ae2683158cbee8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50482
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Reviewed-by: Martin Roth <martinroth@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-11 16:16:29 +00:00
68bcc083bd
util/msrtool: teach the configure script to use clang
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Signed-off-by: Idwer Vollering <vidwer@gmail.com >
Change-Id: I5d0cbbb0c415df0d7b899cf5eb1a9a52dd98bef9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
2021-02-11 14:32:02 +00:00
ad581984a6
src: Remove unused <cpu/intel/model_206ax/model_206ax.h>
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Change-Id: I67862a6a5110e2cab4f77388caa702494e4d71c9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-11 10:25:44 +00:00
45ce5d8973
src: Remove unused <arch/cpu.h>
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Change-Id: I1112aa4635a3cf3ac1c0a0834317983b4e18135a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-11 10:25:23 +00:00
d152837d34
soc/intel/broadwell: Remove _ADR from SerialIO ACPI devices
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SerialIO is in ACPI mode for google/auron and intel/wtm2, and is
disabled for google/jecht and purism/librem_bdw. Since Broadwell
SerialIO is never used in PCI mode, _ADR can safely be dropped.
Change-Id: I9a99b8209b5c139146012aa4a92f563692b62c5e
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-02-11 10:24:43 +00:00
4f880b9ab8
sb/amd/agesa/hudson/acpi/fch.asl: Sync whitespace
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Make it look more like the file under amd/pi/hudson.
Change-Id: I5b40dc5b6f54bf68113826e693ca5963fec83d38
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2021-02-11 10:24:03 +00:00
a03058a22a
soc/intel/xeon_sp; Remove unneeded whitespace before tab
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Change-Id: I56f0d4aa627155ee318362f626347d7990571dcb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-11 10:23:45 +00:00
f4f2132c64
src/mainboard: Remove unneeded whitespace before tab
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Change-Id: I37f12f5cb35ea1a6ad33edb114688ce1619030a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-11 10:23:17 +00:00
388aaf734b
security/intel/txt/Makefile.inc: Use tab for indent
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Change-Id: Ic85a3b6cfb462f335df99e7d6c6c7aa46dc094e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-11 10:23:04 +00:00
c2dd4c7a6b
mb/google/volteer/variants: Remove unneeded whitespace before tab
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Change-Id: I4c991e6119f14d949a2e103024132d70674f29a1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-11 10:22:34 +00:00
e2856be098
mb/amd/mandolin/Kconfig: Remove unneeded whitespace before tab
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Change-Id: I2b52c32a607386cdc1ca00531eda4dfc0bfaab1e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-11 10:22:25 +00:00
f26b2e5c91
arch/x86/id.S: Remove unneeded whitespace before tab
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Change-Id: I053a2a8cff3fda1a1074f74e4d4c174a0cb24d86
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-11 10:22:07 +00:00
89c05c56c0
src/superio: Fix typo in comment
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Change-Id: I2e5cac310af824eb9756b2aa9459239e0b5784da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-11 10:21:54 +00:00
4dc85f11d1
sb/intel/common/rtc.c: Define __SIMPLE_DEVICE__
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Change-Id: Ie11fffdf907227ab315bfd4887aaa5de3602bd24
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2021-02-11 10:19:31 +00:00
6f4dc8f7a4
lib/selfboot.c: Fix indentation and drop one newline
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Change-Id: Ica4254297f5d05e75f852d7e9a9e7bb833dfcea7
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50397
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-11 10:19:17 +00:00
56a676e5d0
cpu/intel/microcode: Fix typo in function parameter
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Change-Id: I9b03105a6808a67c2101917e1822729407271627
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2021-02-11 10:19:04 +00:00
f843e0a8ef
nb/intel/{haswell,sandybridge}/*/mchbar.h: Fix typo in comment
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Change-Id: Ie41433ed8fcadec25007c436ec12163d729a2afe
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-11 10:18:54 +00:00
