sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
41,820 Commits 47 Branches 30 Tags
f28dcbcfc971f7159c853e206933c07f57d3f17c
Commit Graph

41820 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Angel Pons
b53dfc727e sb/amd/agesa/hudson/amd_pci_int_defs.h: Fix comments 
Change-Id: Iff701d8e6d672b3ca97d9d6361ba48736c06c6c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
 2021-02-11 10:18:37 +00:00
Angel Pons
39a223724d sb/amd/agesa/hudson: Drop setting ACPI_FADT_RESET_REGISTER 
It is already set in `src/arch/x86/acpi.c` function `arch_fill_fadt`.

Change-Id: Ica7e112ca253d1332ed2ea414948c8f1970d0a69
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
 2021-02-11 10:18:28 +00:00
Angel Pons
73c73dded6 sb/amd/agesa/hudson/sm.c: Drop unused BITx macros 
Tested with BUILD_TIMELESS=1, Lenovo G505s remains identical.

Change-Id: I759bdef44f7ca0f35350901998f6820820005b38
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-02-11 10:18:21 +00:00
Angel Pons
c64465f212 sb/amd/pi/hudson/pci.c: Remove empty init operation 
Change-Id: I5620867b3044936be8ad1bf95255be5a3565bb51
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
 2021-02-11 10:17:58 +00:00
Angel Pons
c3d88eee64 sb/amd/pi/hudson/imc.c: Remove duplicated comment 
Change-Id: Ie2de3948a78352bbb68c9215222b8489cacb91ce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
 2021-02-11 10:17:55 +00:00
Kevin Chiu
788eb99448 mb/google/zork: modify ELAN TP i2c IRQ to LEVEL active for dirinboz 
configure IRQs as level triggered to prevent TP lost.

BUG=None
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
     2. power on, suspend DUT to check TP is functional

Change-Id: I81ffa889fbdfb01bf3057a8258fb4dd4ad7e88d5
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50420
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-11 10:17:35 +00:00
Patrick Georgi
d510b60f5b Revert "mb/intel/shadowmountain: Add the ASL code" 
This reverts commit 2151f7561d.

Reason for revert: It depends on the shadowmountain ramstage patch.

Error on the builder:

    IASL       /cb-build/coreboot.0/default/INTEL_SHADOWMOUNTAIN/dsdt.aml
src/mainboard/intel/shadowmountain/dsdt.asl:4:10: fatal error: baseboard/ec.h: No such file or directory
 #include <baseboard/ec.h>
          ^~~~~~~~~~~~~~~~
compilation terminated.

Change-Id: I9fa5e8cc2ad485bf82bfbda151bc46d26faef7ab
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-11 10:15:41 +00:00
V Sowmya
2151f7561d mb/intel/shadowmountain: Add the ASL code 
This patch includes the DSDT ASL code for shadowmountain board.

BUG=b:175808146
TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49733
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-11 07:43:16 +00:00
Felix Held
a90854d429 soc/amd: fully commonize clear_tvalid 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I90526a566a5fbc19a7368f90421067a6c716614e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50466
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-11 02:49:34 +00:00
Felix Held
3c4fd70d61 soc/amd/cezanne/smihandler: add missing southbridge_io_trap_handler 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4140fbf93e84a2620ffb88e5c65df17b23135553
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50465
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-11 02:47:49 +00:00
Felix Held
574b1b9674 soc/amd: include cpu/x86/smm directory in common SMM Makefile 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id6be7aa7f295e61f873bfae1fca42260d3b0db78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50464
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-11 02:46:41 +00:00
Felix Held
a3a66b6e68 soc/amd: move southbridge_smi_handler to common code 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I650498321736eee3d33af51216eda1b650f11744
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50463
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-11 02:45:48 +00:00
Felix Held
bc134812c3 soc/amd: factor out common SMM relocation code 
The common code gets moved to soc/amd/common/block/cpu/smm, since it is
related to the CPU cores and soc/amd/common/block/smi is about the SMI/
SCI functionality in the FCH part. Also relocation_handler gets renamed
to smm_relocation_handler to keep it clear what it does, since it got
moved to another compilation unit.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I45224131dfd52247018c5ca19cb37c44062b03eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50462
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-11 01:44:24 +00:00
Felix Held
a6fc2125e7 soc/amd*/smihandler: factor out and rename clear_smi_sci_status 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd6c3bebee1ccf7e7e7987d8ae3d9fa654019791
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50460
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-11 00:50:52 +00:00
Felix Held
4f69ab729a soc/amd*/smihandler: factor out and rename clear_all_smi_status 
The old name was misleading, since it doesn't disable the generation of
SMIs, but clears the status registers.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iddadbec013091c2e5993a6303e291451c3d1e7ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50459
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-11 00:50:14 +00:00
Felix Held
ee2a365872 soc/amd/cezanne: add empty SMM-handler 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I95908fac3b1e17a16542e5d80001fac3d22d839a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50455
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-11 00:49:23 +00:00
Felix Held
a8d4a718e3 soc/amd/stoneyridge: drop empty sb_enable 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9b6e0bd5c7358e2f18f929d5b098d95acbf59a5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50437
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-11 00:46:12 +00:00
Felix Held
e094b1f137 soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7bab29ae8d0e28c392210f8dcbaa4441ca61114
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50454
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 23:25:21 +00:00
Paul Fagerburg
259cccd7e7 mb/google: order matters in mem_parts_used.txt 
* Add comments to mem_parts_used.txt to point out that the order of
the entries matters when assigning IDs, so always add a new part
to the end of the file.
* Update existing mem_parts_used.txt to add the same comment.
* No updates to Zork variants, because they use an optional ID, so
the order actually doesn't matter there.

BUG=b:175898902
TEST=create a new variant of dalboz, trembyle, volteer, waddledee,
or waddledoo, and observe that mem_parts_used.txt has the new
verbiage.

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Iffbd8e69a89b1b7c810c5d25c7a6148d459d8b02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
 2021-02-10 22:15:52 +00:00
Felix Held
237bc2efaa soc/amd/stoneyridge/chip: rewrite enable_dev as switch case statement 
This also aligns Stoneyridge with Picasso and Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I35bf9915e3502c22e9dd9efa80b00a1ce70f187d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50436
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 21:50:36 +00:00
Raul E Rangel
72616b3813 soc/amd/cezanne: Add verstage support 
Setup the config required to support verstage.
The offsets are the same as picasso.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
 2021-02-10 21:46:54 +00:00
Felix Held
a634257f13 soc/amd/common/psp_gen2: print error for uninitialized MSR_PSP_ADDR 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8b6362a9eb2344293dad22357651f646774af789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50448
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 21:11:09 +00:00
Felix Held
583d531bd6 soc/amd/common/block/psp: factor out soc_get_psp_base_address 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib73ac92e69f1be5852a1406ba714acb6a8a04989
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-02-10 21:10:11 +00:00
Elyes HAOUAS
517453a6cc src/ec/quanta/ene_kb3940q/acpi/battery.asl: Convert to ASL 2.0 
Change-Id: I7cc47536b0c1e2c903df29402090abfccde82406
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-02-10 19:18:09 +00:00
Elyes HAOUAS
81d55cf6d6 src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0 
Change-Id: I5de6c7da2440d682378a4ceb89b4bedd689dad60
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-02-10 19:17:34 +00:00
Raul E Rangel
5461662c66 soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPI 
Required so we pass SPI information down to depthcharge.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4ce819b537333c28d394c925331e3dbf260b7732
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-10 19:01:22 +00:00
Raul E Rangel
466edb51b4 soc/amd/common/blocks/lpc: Remove common SPI registers 
Use the SoC versions instead.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia0b8129b165f8a2e6be6706ab2e3f2d39e1025a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-02-10 19:00:49 +00:00
Raul E Rangel
6ba1fcac34 soc/amd/cezanne: Add SPI registers 
These are identical to picasso.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3ef4c51ef6d656b3b035d97a56b1875b40e89210
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-02-10 19:00:34 +00:00
Raul E Rangel
4f1147b541 soc/amd/picasso: Add SPI registers 
The picasso SPI registers are different than the ones defined in
amdblocks/lpc.h. The BASE_ALIGNMENT has changed and the
PSP_SPI_MMIO_SEL bit has been added.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0b5a0c88c6dbb95cdbc62b949a7d30bfad1fa725
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-02-10 19:00:22 +00:00
Raul E Rangel
f87427f1a4 soc/amd/stoneyridge: Add SPI registers 
This is a copy/paste of amdblocks/lpc.h. The registers are different for
picasso and cezanne, so I'm moving them to soc.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4dfadcdc025d3581cb1423e9793a9b2181742b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-02-10 19:00:17 +00:00
Elyes HAOUAS
78452a584a sb/intel/bd82x6x/acpi: Convert to ASL 2.0 
Change-Id: Ib587d7a982852e7123e43337407ef20d96811719
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-02-10 18:04:48 +00:00
Elyes HAOUAS
93329d8189 soc/intel/xeon_sp/include/soc/acpi_asl.h: Convert to ASL 2.0 
Change-Id: Ie1d31b9d02584b97b85afe970894cfe557174733
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-02-10 18:02:42 +00:00
Elyes HAOUAS
9edeb31d4a mb/google/poppy/var/baseboard: Convert to ASL 2.0 
Change-Id: Ic3d0ea9893c3c25305e2da94681cb5ac466782fc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50321
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 18:01:42 +00:00
Elyes HAOUAS
fc29afbdd4 soc/intel/skylake: Convert to ASL 2.0 syntax 
Change-Id: Iea915b60d8ec9a1a7a2aa5926b0277cae58113a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-02-10 17:52:29 +00:00
Elyes HAOUAS
b4b4fa5b2f mb/intel/wtm2: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' files are same.

Change-Id: Id68623cfb57e889e60d66cd465612336cd8298ca
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-02-10 17:46:38 +00:00
Benjamin Doron
e166cb38bf soc/intel/skylake/acpi: Add PEP table 
PEP table is applicable to Skylake platform as well. It is required to
make the kernel load `intel_pmc_core`. Skylake boards can also use S0ix
hooks.

Tested on an out-of-tree Acer Aspire VN7-572G (Skylake-U),
intel_pmc_core kernel module is loaded and reports statuses predictably
via debugfs.

Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49140
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 17:45:15 +00:00
Raul E Rangel
d86db1ca8e soc/amd/common/block: Fix guards for PSP transfer buffer 
The transfer buffer is only required when using
VBOOT_STARTS_BEFORE_BOOTBLOCK.

The VBOOT workbuffer is only required when VBOOT_STARTS_BEFORE_BOOTBLOCK
or VBOOT_STARTS_IN_BOOTBLOCK.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I444bede3f2b716e1900e7621453351d7fddadaa3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-02-10 16:23:56 +00:00
Kevin Chiu
1deca23f0a mb/google/zork: modify ELAN TS i2c IRQ to LEVEL active for dirinboz 
EDGE IRQ from TS might be invalid to HOST, configure IRQs
as level triggered to prevent TS lost.

BUG=b:179594439
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
     2. power on, suspend DUT to check TS is functional

Change-Id: Ibbbc73b37932ba1359ffe6f572a15564bb341025
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50416
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 16:21:00 +00:00
Elyes HAOUAS
6dd2e7b926 soc/amd/common/block/cpu/noncar: Remove unneeded whitespace before tab 
Change-Id: Ib88358ca26876cd25247cd9619fb2b70f6859ac2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-10 16:20:13 +00:00
Kane Chen
0967d78490 mb/google/zork/var/shuboz: Adjust touchscreen settings 
Modify GPIO_140 delay time and add "disable_gpio_export_in_crs"
to meet touchscreen controller power on sequence.

BUG=b:174442484
BRANCH=master
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I36a7055b7be0963479f8a0f4dc49c92bc8fbdc9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50228
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 16:19:12 +00:00
Felix Held
37fbbfd3bf soc/amd/picasso/smihandler: replace southbridge.c in comment with fch.c 
southbridge.c was renamed and split into early_fch.c and fch.c.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie439e746fb3dfe9ec865481a76a09eab378242bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50458
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 16:17:57 +00:00
Felix Held
c8a0faab5c soc/amd/cezanne/chip: add empty set_mmio_dev_ops 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2ac5fcd17b6aed464a0d1e55f2860574501f7a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-02-10 16:09:32 +00:00
Felix Held
fd05601eb0 soc/amd/cezanne/chip: add empty cpu_bus_ops 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I658294c84d64c7de0ccfa74b0e830d787a3a42fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50438
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 16:09:19 +00:00
Kane Chen
c023839a84 mb/google/zork/var/shuboz: Modify touchpad setting for Jelboz 
Since Jelboz support number pad,
due to one single coreboot for both Jelboz and Shuboz,
modify "overridetree.cb" setting to number pad support for Jelboz.

BUG=b:174964012
BRANCH=master
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie0219419834b34b6eac589f28d3604f5f1b65679
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
 2021-02-10 16:03:08 +00:00
Felix Held
35b3cc9b6d soc/amd/block/psp/psp: raise log level of PSP failure messages 
If the PSP didn't like a command this should be at least a warning on
the console and not just a debug message.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7e5f6320631cca86813e98f82b8c0c21bf18af1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-10 14:45:21 +00:00
Elyes HAOUAS
6564842857 sb/amd/cimx/sb800/acpi: Convert to ASL 2.0 syntax 
Also, fix typo on "success".
Built gizmosphere/gizmo generate identical 'build/dsdt.dsl'.

Change-Id: I6fd7056d8053f0097b5c9de6b4e2e6db38910a2e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-10 09:25:49 +00:00
Elyes HAOUAS
b5a237d911 sb/amd/pi/hudson/acpi/fch.asl: Convert to ASL 2.0 syntax 
Change-Id: Ie413f36ef11a42a23d7d265d7a66f5e0d088892e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-10 09:25:35 +00:00
Angel Pons
6b486e1588 soc/intel/broadwell/pch: Simplify PCI RMW operations 
This reduces the differences between Lynx Point and Broadwell.

Change-Id: Ib53d73e3f89c538ba0f052a98c7aabe815a59472
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46891
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 07:33:35 +00:00
Angel Pons
4299cb4829 nb/intel/i945: Use common {DMI,EP,MCH}BAR accessors 
Tested with BUILD_TIMELESS=1, Getac P470 remains identical.

Change-Id: If6d6cba76bdd1134372ab2faa475e574fdc5fddf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-02-10 07:30:05 +00:00
Angel Pons
e88f705946 nb/intel/x4x: Use common {DMI,EP,MCH}BAR accessors 
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.

Change-Id: I33c17f56eac0277a12b32af777e2e1ceb086685f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-02-10 07:29:54 +00:00