In newer AMD SoCs, the image slot header is used in the AMD A/B recovery
scheme, so set recovery_ab to true when need_ish is true. Also move the
block of code before the process_config call, since that call will
already use the recovery_ab field of the cb_config struct.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I65903765514f215bf5cc9b949d0b95aff781eb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63184
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the specific SPD hex file for the Samsung memory part with
updating the part number into the SPD table. The ABL needs to
identify the part by checking SPD data to do the proper tuning.
BUG=b:224884904
TEST=Build, validate the SPD data has been applied.
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ia54726ce8c1bae46dcd4fed3df509ef184914e94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Some solutions require readable form of timestamps, which does not
contain spaces. Current descriptive timestamp names do not meet this
criteria. Also, mapping enums to their text representation allows for
quick grepping (use of grep command) to find relevant timestamps in the
code.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ifd49f20d6b00a5bbd21804cea3a50b8cef074cd1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
On FreeBSD, every build target would show warnings from its
builtin printf().
Change the regexp to be compatible with BSD sed.
This will avoid noise like "printf: 4.14-1278-g5d74ccf1c3: not
completely converted".
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Change-Id: I1c0c260fd8d42e23a612a353a288e472cc068c8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We don't want to enable the speaker on init. It will be enabled while
using GPIO AMP codec in depthcharge.
BUG=b:223289882
TEST=boot guybrush and verify the devbeep and gpio value in kernel
Change-Id: Ic949cc95556913a2afef4a683a49eaa1e07e6147
Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Only Cr50 versions starting at 0.5.5 support long IRQ pulses, so this
feature is enabled based on the value of the board_cfg register (see
CB:61722).
However, Ti50 versions below 0.0.15 don't support the board_cfg
register, and trying to access it will cause I2C errors (see CB:63011).
Also, all Ti50 versions only support long IRQ pulses. Therefore, add a
workaround to force enable long IRQ pulses for boards using Ti50
versions under 0.0.15, instead of enabling it based on board_cfg. This
workaround will be removed once all Ti50 stocks are updated to 0.0.15 or
higher.
BUG=b:225941781
TEST=Boot nivviks and nereid to OS with Ti50 0.0.14 and check there are
none of these I2C errors:
[ERROR] I2C stop bit not received
[ERROR] cr50_i2c_read: Address write failed
[ERROR] cr50_i2c_tis_status: Failed to read status
Change-Id: Iaba71461d8ec79e8d6efddbd505339cdf1176485
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63160
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move WWAN power on sequence from OS to coreboot. This can save the
WWAN initial time about 10S. Another purpose is power resource be
removed because we don't power off the LTE in S0ix.
BUG=b:223490884
TEST=FM101-GL work as expected.
Enumerate time from
[ 17.747145] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd
[ 17.760192] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04
[ 17.760210] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 17.760215] usb 4-2: Product: Fibocom FM101-GL Module
[ 17.760220] usb 4-2: Manufacturer: Fibocom Wireless Inc.
[ 17.760224] usb 4-2: SerialNumber: 9c88998f
to
[ 3.936409] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd
[ 3.966695] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04
[ 3.989989] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 4.003813] usb 4-2: Product: Fibocom FM101-GL Module
[ 4.019760] usb 4-2: Manufacturer: Fibocom Wireless Inc.
[ 4.019762] usb 4-2: SerialNumber: 9c88998f
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I0f3fe999ae3a109b739629948b619a389a9059b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig for
ADL RVP board. The flag updates PMC settings in the IFD for Alder Lake
A0 silicon. As Alder Lake A0 is intermediate stepping, and the IFD is
locked in the production systems, so the Kconfig is deselected.
TEST=Build the coreboot for adlrvp
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I966be42ba662861f4a6933d7275ecc13860220f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
coreboot.pre doesn't follow the standard Make conventions. It gets
modified by multiple rules, and thus we can't compute the dependencies
correctly. This means we need to manually delete it before starting the
dependency calculations.
i.e., Building firmware with the seabios payload now works correctly.
Fixes: dd6efce934 ("Makefile: Add .SECONDARY")
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If5fa3f0b8d314369a044658e452bd75bc7709397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Change the DXIO descriptors to match the default PCIe lane mapping on
the chausie board. With this configuration and a board-level rework to
bypass the EC control of the NVMe SSD power supply rail, this
configuration results in the SSD being detected on the root port on bus
0 device 2 function 3 and usable as boot device. This was also validated
against the schematics revision B.
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib74988b741f748d240ef09fa0dba8885bdc5e706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63161
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow the Moli GPIO Table_20220324.xlsx to update it.
1.Set A15 as the default value.
2.Set A14, A19 NC.
3.Set C3, C4 as the default value.
4.Set D9 as the default value.
5.Set E5, E13 as the default value.
6.Set R4, R5 as the default value.
7.Update E14.
8.Set E12 as the default value.
9.Set D16 as the default value.
BUG=b:220821454
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ia54256244111a99cb130b74f78c37815099a021a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This patch adds an option to disable loglevel prefixes. This patch helps
to achieve clear messages when low loglevel is used and very few
messages are displayed on a terminal. This option also allows to
maintain compatibility with log readers and continuous integration
systems that depend on fixed log content.
If the code contains:
printk(BIOS_DEBUG, "This is a debug message!\n")
it will show as:
[DEBUG] This is a debug message!
but if the Kconfig contains:
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
the same message will show up as
This is a debug message!
Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com>
Change-Id: I911bb601cf1933a4c6498b2ae1e4cb4d4bc85621
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
ESPI is not initialized in PSP. Hence any attempt to write to port80
causes failure to boot. Disable PSP postcodes for now and re-enable it
later after ESPI is initialized in PSP.
BUG=b:224618411
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I73b7ddec50936f7836f915f459ca0bdc0777cb22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is done to work around a hang when SMU writes to port80. Remove it
after the issue is fixed.
BUG=b:224618411
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63122
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the PCIe CEM specification, the deassertion of PERST#
should occur at least 100ms after the assertion. To ensure the 100ms
delay requirement is met, calculate the elapsed time since assertion. If
it is smaller than 100ms, do an extra delay.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the measured PERST# time:
[DEBUG] mtk_pcie_domain_enable: 432517 us elapsed since assert PERST#
[INFO ] mtk_pcie_domain_enable: PCIe link up success (17 tries)
And the SSD information in boot log is as follows:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be
delayed 100ms (TPVPERL) for the power and clock to become stable.
Instead of asserting PERST# right before PCIe initialization and waiting
for 100ms, which is currently the only function of 'mtk_pcie_pre_init',
so that the extra 100ms delay in ramstage is avoided.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add early init support for MT8195 platform.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I4eb7da53ff76c385cab18bbf84970e96b61662ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add support for "early_init_data" region, which can be used to store
data initialized in an early stage (such as bootblock), and retrieve it
in later stages (such as ramstage).
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
SMU locks up sometimes if the port80 enable bit is cleared in the ESPI
Decode register. Add a config to choose between clearing the entire ESPI
Decode Register vs retaining the port80 enable bit.
BUG=None
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The memory initialization reference code didn't support returning
DRAM information in the old platforms, for example MT8192 and MT8195.
So we have to add a new configuration USE_CBMEM_DRAM_INFO to make
sure the common code will try to get DRAM information on new
platforms supporting that.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Iebe9ea0c1d01890b09fdf586813d85adde9702e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The current pmif register setting for low power mode is incorrect,
which is causing suspend failure. The issue of suspend failure is that
SRCLKENA0 will not be pulled down. EC will not be informed AP is
suspending now becuase of this. Therefore, add pmif_spmi_set_lp_mode()
to correct the setting.
This implementation is based on chapter 3.7 in MT8186 Functional
Specification.
BUG=b:215639203
TEST=test of suspend and resume pass.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Change-Id: I2d02198f19f9cb052fba612c02404a6af1a10adb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The Cherry follower projects may choose Max98390 for audio output
so we have to add a new config CHERRY_USE_MAX98390. Also, the
'dojo' device is the first one to use it.
BUG=b:204391159
BRANCH=cherry
TEST=emerge-cherry coreboot
TEST=Verify beep function through CLI in depthcharge successfully
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Change-Id: I9b6bc5a5520292dd502b0389217f5062479b4490
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63083
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch moves `pmc_clear_pmcon_sts` function into common code and
remove SoC specific instances.
Accessing PMC GEN_PMCON_A register differs between different Intel
chipsets. Typically, there are two possible ways to perform GEN_PMCON_A
register programming (like `pmc_clear_pmcon_sts()`) as:
1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration
register.
2. Using MMIO access when GEN_PMCON_A is a memory mapped register.
SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to
perform GEN_PMCON_A register programming using PMC MMIO.
BUG=b:211954778
TEST=Able to build brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeff Daly <jeffd@silicom-usa.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
