Commit Graph

26080 Commits

Author SHA1 Message Date
274dabd7a0 src/northbridge: Remove unneeded include <arch/io.h>
Change-Id: I52ace93ae6f802723823955ac349ed54dc064aaa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-15 17:58:59 +00:00
45b79be9c0 src/soc: Remove unneeded include <arch/io.h>
Change-Id: I5a7b53a07fe6fd6121067dcec004e81eb284edbb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-15 17:58:49 +00:00
5bc493a8a2 src/southbridge: Remove unneeded include <arch/io.h>
Change-Id: If358e221021466f0058bfc84a322750b34a36d5f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-15 17:58:41 +00:00
caae269032 soc/intel/broadwell/romstage: Clean up unused bist variable
Checking BIST is done in the bootblock.

Change-Id: I3ea2eb6a37c038f7348f0abd2056eee5c07bdb9d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32757
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-15 17:57:57 +00:00
e43972474c soc/intel/broadwell: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock and enables
bootblock console by default.

Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-05-15 17:57:33 +00:00
4d56a06255 nb/intel/broadwell: Add an option for where verstage starts
Previously broadwell used a romcc bootblock and starting verstage in
romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also
possible to have a separate verstage.

This selects using a separate verstage by default but still keeps the
option around to use verstage in romstage.

With a separate verstage the romstage becomes an RW stage.
The mrc.bin however is only added to the RO COREBOOT fmap region as it
requires to be run at a specific offset. This means that coreboot will
have to jump from a RW region to the RO region for that binary and
back to that RW region after that binary is done initializing the
memory.

Change-Id: I900233cadb3c76da329fb98f93917570e633365f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30384
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-15 17:57:18 +00:00
5bb15f1a4d soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
This puts the cache-as-ram init in the bootblock.
Before setting up cache as ram the microcode updates are applied.

This removes the possibility for a normal/fallback setup although
implementing this should be quite easy.

Setting up LPC in the bootblock to output console on SuperIOs is not
done in this patch, therefore BOOTBLOCK_CONSOLE is not yet selected.

Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-15 17:56:56 +00:00
56f768774a soc/intel/broadwell: Use the common cpu/intel/car romstage entry
The only functional difference is the use of stack guards.

Change-Id: I95645271e0d93a97f544a1cc4e9a4320738e6a20
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-15 17:56:36 +00:00
807803afa2 vboot: remove OPROM-related code
As of CL:1605641, vboot2 code should be used for setting and
checking display init state.  Remove all vboot1 OPROM-related
code, and use the vboot2 display init code which has already
been added in previous commits.

coreboot should not be reading vboot NVRAM flags directly.
Remove the function vboot_wants_oprom(), and instead rely on
display_init_required(), which uses the
VBOOT_WD_FLAG_DISPLAY_INIT value stored in
vboot_working_data.flags, initialized during verstage.
Note that this means in the case of CONFIG_VBOOT=y, the return
value of display_init_required() can only be trusted after
verstage has been executed.  This should not be a problem
assuming that all display initialization occurs in ramstage.

BUG=b:124141368, b:124192753, chromium:948529
TEST=Build locally
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: Ic8f9dc5a3c7f1546a8fed82bde02be4d04568f8d
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:1605641, chromium:1605525
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32723
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-15 17:50:08 +00:00
18b51b7315 vboot: rename BOOT_OPROM_NEEDED to BOOT_DISPLAY_REQUEST
Verified Boot OPROM code is being refactored.  OPROM is being
generalized into "display initialization".  As such, the NVRAM
request flag is being renamed from OPROM_NEEDED to
DISPLAY_REQUEST.

BUG=b:124141368, b:124192753, chromium:948529
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: I74374abf7d1deb594c073f7a4a76c9de46092143
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:1605640
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-15 17:49:24 +00:00
caef7f837a mb/packardbell/ms2290/acpi: Serialize Control Method
IASL reports remarks 'Control Method should be made Serialized'.

Change-Id: I5606c6e435da17f7d4732148f6ddcedb1fde4ab0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-15 17:48:14 +00:00
111f9a9bcd mb/google/poppy/variants/atlas: Remove B0D4 _PSV
Per Intel, the internal thermal protection is working better
than putting B0D4 _PSV in dptf.

BUG=b:131251533
TEST=Get ~10% better Octane score.
Correct TCC and TCC offset in MSR register.

Change-Id: If85afdc673687477ec85a47efcb264a7e5d6ae45
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
2019-05-15 17:48:01 +00:00
2968c9d6c7 mb/google/poppy/variants/rammus: Support new onboard Hynix memory
Add hynix_dimm_H9CCNNNCLGALAR-NVD for new onboard memory support.

BUG=b:130337306
BRANCH=firmware-rammus-11275.B
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure system boots up.

Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ibd02953d0c6ac62fa4d7751fd8b103b74433aa73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-15 17:47:39 +00:00
0d4200fef3 soc/intel/cannonlake: Support different SPD read type for each slot
Also clean up cannonlake_memcfg_init.

The major changes include:
(1) Add enum 'mem_info_read_type' to spd_info.
(2) Add per-dimm-slot spd_info to cnl_mb_cfg.
(3) Setup memory config for each slot independently.
(4) Squash meminit_memcfg_spd().

BUG=chromium:960581, b:124990009
BRANCH=none
TEST=boot hatch, hatch_whl, and kohaku

Change-Id: I686a85996858204c20fd05ef24787a0487817c34
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32513
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-15 17:47:13 +00:00
72f6fbb1bc superio/ite: Add IT8786E-I
Based on IT8786E-I V0.4.1 datasheet with following remark:

  "Please note that the IT8786E-I V0.4.1 is
   applicable only to the D version."

Signed-off-by: Kyösti Mälkki <kyosti.malkki@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I7317da6a72db64f95f9a790ef96ed7a5f93b3aea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-05-15 17:45:41 +00:00
dcfff3739b src/superio/ite/common: Prepare for ITE IT8786E SuperIO
Introduce 7bit Slope PWM registers. New ITE SuperIO may have contiguous
7bit values for PWM slope.

Add option to enable External Sensor SMBus Host.

Update/add registers macros for IT8786E-F which are not backwards
compatible.

Change-Id: I68fbfe62dfa05d0c166abaefbdc2ab873114b236
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-15 17:45:14 +00:00
29150c83df soc/amd/stoneyridge: Add ACPI D3Cold support for SD Controller
We need to support entering D3Cold from the OS to work around a bug in
the SDHC where the data lines get stuck always reading zeros.

BUG=b:122749418
TEST=Verified the linux kernel can transition between D3 and D0. Also
verified that the device can suspend and resume and continue to have a
functioning SD controller after.

Change-Id: Ifbf48f20c03a752ce3ff773296b536e92db16a62
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-15 16:01:48 +00:00
cd51d7ced5 mb/google/poppy/variant/atlas: Add SPDs for Samsung D-die chips
This adds the SPDs for Samsung D-die 16Gbit and 32Gbit LPDDR3-2133
chips.

BUG=b:132206809
TEST=boots on atlas with C-die and D-die memory chips

localhost ~ # mosys memory spd print all
0 | LPDDR3 | SO-DIMM
1 | LPDDR3 | SO-DIMM
0 | 1-78: Samsung | 00000000 | K4EBE304ED-EGCG
1 | 1-78: Samsung | 00000000 | K4EBE304ED-EGCG
0 | 8192 | 2 | 64
1 | 8192 | 2 | 64
0 | LPDDR3-800, LPDDR3-1066, LPDDR3-1333, LPDDR3-1600, LPDDR3-1866, LPDDR3-2133
1 | LPDDR3-800, LPDDR3-1066, LPDDR3-1333, LPDDR3-1600, LPDDR3-1866, LPDDR3-2133
localhost ~ #

Change-Id: I8ba000aeeb77f07d7f18bda86b3c07f5b50478b8
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-14 23:33:54 +00:00
d1ad37847d mb/google/poppy/vr/atlas: Add a W/A for Samsung memory init error
This patch adds a workaround for Samsung C-die 2G/4G memory chips.
For unknown reasons, some boards with Samsung LP3 memory chips
could not pass early CS/CMD training. MRC has to change the
granularity from 16 ticks to 8 ticks, which implies bad margin
with this memory chip. Another way is to enhance the drive
strength for CS. This patch is to enhance the drive strength for CS
and CMD. Enhancing the drive strength for CMD could gain margin abaout
3 more ticks. Root cause needs to be further investigated with memory
vendor.

BUG=b:131177542
BRANCH=None
TEST=USE=fw_debug emerge-atlas chromeos-mrc coreboot chromeos-bootimage
     & check the MRC log to ensure correct Rcomp values are passed to
     MRC. Tested with board ID #8 and #11.

Change-Id: I9ea3ceda8dc8bf781063d3c16c7c2d9b44e5ddd6
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
2019-05-14 23:33:45 +00:00
97e9e5622d soc/intel/broadwell: Clean up the bootflow
Call the raminit from a common location instead of from the mainboard
specific code.

Change-Id: I65d522237a0bb7b2c032536ede10e2cf93c134d8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32760
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-14 23:22:51 +00:00
325865db56 soc/intel/broadwell: Don't use a pointer for pei_data
To improve the bootflow, the scope of the pei_data needs to be
extended.

Change-Id: Ic6d91692a7bf9218b81da5bb36b5b26dabac454e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-05-14 23:22:26 +00:00
cadc70f797 soc/intel/broadwell: Move GPIO init to a common place
This also links the gpio configuration instead of including it as a
header.

Change-Id: I9309d2b842495f6cff33fdab18aa139a82c1959c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-05-14 23:22:02 +00:00
57459dbeac mb/{lenovo/x201,packardbell/ms2290}: Remove superfluous TS init
Timestamps are initialized in cpu/intel/car/romstage.c.

Change-Id: Ia2b762667be17aa5b482cd585dd6f6198cf50d9e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32758
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-14 06:59:48 +00:00
55cb5f8de5 Remove unnecessary ENV_RAMSTAGE guard
TEST=Able to build coreboot for CML.

Change-Id: Ic0f473e04ffc1de50dee871af52eacf0b328b376
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32764
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-14 06:56:59 +00:00
11a5b6b577 i82801gx/bootblock: Use macro instead of magic number
Change-Id: I2556c150f53d9580bc3b70ab49b3a2c8477c18ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:31:28 +00:00
8dd518969c soc/intel/{cannonlake,icelake}: Drop unused cbmem.c file
Change-Id: Ib9444f7797289c9b8250cfb16eb1c12dff867ec3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-13 09:31:14 +00:00
0c22d2fe46 {bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macro
Use BIOS_CNTL defined macro instead of magic number.

Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:30:54 +00:00
9005071c5f nb/intel/sandybridge: Move boot_count_increment()
Move boot_count_increment() to romstage.c, drop preprocessor code and
only increase counter once on regular boot.

Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to OS, no errors visible in dmesg.

Change-Id: I6aa52b75edf19953405b70284c7e7db30f607cd6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32067
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-13 09:29:33 +00:00
5709e03613 nb/intel/sandybridge: Migrate MRC settings to devicetree
* Add more chip register to move PEI data to devicetree.cb.
* Set northbridge/southbridge and runtime detectable settings.
* Fill in values from devicetree.

This change is still a noop as the pei structure is completely overwritten
with the exsting mainboard pei structure.

The followup commit will migrate to devicetree.cb.

Tested on Lenovo T520, boots MRC path with the new devicetree settings.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13 09:28:39 +00:00
59b4255c63 mb/samsung/lumpy: Move onboard SPD to second channel
Move the onboard SPD to second channel as native raminit does and workaround
mrc expecations in northbridge code.

Required to move pei data to devicetree and to use the same code for mrc and
native raminit.

Tested on Lenovo T520:
Other fields then spd_data[0] are ignored.

Change-Id: If1910e82a4bd178c2a6c2991c91e09782122888e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13 09:28:11 +00:00
44105942df nb/intel/sandybridge: Update pei_data comments
Update outdated comments.

Change-Id: I100f71345281a1dc52e99d2395f528d60a9a1f58
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13 09:27:21 +00:00
60ab1d8c52 src/ec/lenovo/h8/acpi: Serialize Control Method
IASL reports warning 'Control Method should be made Serialized'.

Change-Id: I034f2c00e912e8f9ef87b9918de1db06fade38b9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:26:58 +00:00
2f0bbbfe9f mb/lenovo/s230u: Rewrite trigger inversion ACPI code
The GPIO invert registers are already defined in the PCH code, so
just use the 8-bit versions of the registers instead of creating
a new GPIO field for the single bits.

This allows us to get rid of the Field(GPIO...) code that's causing
problems with IASL version 20190509.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iac5dfb71b3a2b5a25c05a403cf5f403c7acecaaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-13 09:26:45 +00:00
ef9e85bbfd mb/t400/acpi: Update ATPR buffer to fit all entries
Error spotted using acpica version 20190509 (Change-Id: I6779a20).

Change-Id: Ic9cf16a7494667f6dab156c697fb8f8e9966051e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-13 09:25:28 +00:00
7528f83444 soc/intel: Geminilake Refresh feature request support
Add 0x706a8 for GLK Refresh CPU stepping ID.

BUG=b:132414963
BRANCH=None
TEST=Image built successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I4641d9bd4c82211e7200f617cae9043b0f2f38d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-13 09:23:13 +00:00
2cb399625e mainboard: remove "recovery" gpio, selectively add "presence" gpio.
The gpio table is only used by depthcharge, and depthcharge rarely
has a need for the "recovery" gpio.  On a few boards it does use the
gpio as a signal for confirming physical presence, so on that boards
we'll advertise the board as "presence".

All these strings probably should have been #defines to help avoid
typos (e.g., the "ec_in_rw" in stout seems questionable since everybody
else uses "EC in RW").

Cq-Depend: chromium:1580454
BUG=b:129471321
BRANCH=None
TEST=Local compile and flash (with corresponding changes to depthcharge)
to 2 systems, one with a "presence" gpio and another without.  Confirmed
that both systems could enter dev mode.

Change-Id: Id6d62d9e48d3e6646cbc1277ea53f0ca95dd849e
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-13 09:21:51 +00:00
f2d173a554 mb/google/sarien: config ISH_GP6 with NF2
A12 is not current set for ISH_GP6 so the ISH_LID_CL#_TAB
signal is not making it to the ISH properly. Enable the second native
function instead of the first.

BRANCH=none
BUG=b:131785573
TEST=gpioget on ISH now shows the correct gpio level

Change-Id: Ib3a654ae659037263aa9aa29d45b42ca67b7955b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32738
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-13 09:16:43 +00:00
ac6bf7dc12 lib/hexdump: Drop redundant isprint() implementation
Change-Id: I23e2d89274553cbc75e42f0420a1a84d4cec4340
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-13 09:14:55 +00:00
cb6f6a10b3 soc/intel/braswell: Remove unused include <timestamp.h>
Change-Id: Ied645a583f78bc47c8358240acd639132fd499db
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-05-13 09:13:29 +00:00
9d6f645908 mainboard: Remove unused include <timestamp.h>
Change-Id: Id05fc39c0c0d0560e34e55f793060d29df82d026
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-05-13 09:13:19 +00:00
9c90609331 soc/intel/braswell: Add tsc_freq.c and pmutil.c in verstage
Systems with C_EVIRONMENT_BOOTBLOCK and VBOOT enabled requires functions
tsc_freq_mhz(), vbnv_cmos_failed() and vboot_platform_is_resuming()
in verstage.
Add tsc_freq.c and pmutil.c to verstage.

BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701 + Building Google Banon

Change-Id: Ia509eda6bf415aaa63be71013249493aa472289d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:13:06 +00:00
e091d0efc4 lapic/lapic_cpu_init: Add cpu_add_map_entry() to store default_apic_id
This patch ensures start_cpu() function to store default_apic_id using
common cpu_add_map_entry() function to make cpu_index() implementation
generic.

BRANCH=none
BUG=b:79562868

Change-Id: Iac4d6e9e6e6f9ba644335b4b70da8689c405f638
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13 02:07:09 +00:00
095c931cf1 src/arch/x86: Use core apic id to get cpu_index()
This cpu_index() implementation assumes that cpu_index() function
might always getting called from coreboot context (ESP stack
pointer will always refer to coreboot).

This might not be true in case of proposed PI spec MP_SERVICES_PPI
implementation, where FSP context (stack pointer refers to fsp)
will request to get cpu_index(), natural alignment logic will
use ESP and retrieve struct cpu_info *ci from (stack_top - 8 byte).
This is not the place where cpu_index is actually stored by
ramstage c_start.S

Hence this patch tries to remove those dependencies while retrieving
cpu_index(), rather it uses cpuid to fetch lapic id and matches with
cpus_default_apic_id[] variable to return correct cpu_index().

BRANCH=none
BUG=b:79562868
TEST=Ensures functions can be run on APs without any failure and
cpu_index() also provides correct index number.

Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26346
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-13 02:06:46 +00:00
a6d401c193 mb/asrock/h81m-hds: Drop now obsolete libgfxinit override
CPU type is detected at runtime now.

Change-Id: I5e54176e235e43ca28e4baf43dbb9860e7fc3dbd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-05-12 15:03:15 +00:00
772a154d39 nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGE
We keep the support, though. Just now that `libgfxinit` is fixed, we
don't need the distinction anymore. Causally, we also don't need
CPU_INTEL_MODEL_306AX any more.

TEST=Played tint on kontron/ktqm77. Score 606

Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-12 15:03:03 +00:00
47953d0ae0 3rdparty/libgfxinit: Update for runtime CPU detection
Beside one tiny fix for framebuffer scaling, this contains a major
refactoring of libgfxinit's configuration infrastructure. With this,
we are finally able to detect CPUs at runtime and only have to confi-
gure a CPU/GPU generation.

Change-Id: Iccf4557453878536f527e4a1902439a1961ab701
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32736
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-12 15:02:23 +00:00
f77eb44433 mb/lenovo/*: Add MAINBOARD_FAMILY
The Kconfig MAINBOARD_FAMILY sets the family field of SMBIOS entry 1.
Match what vendor firmware does and use the same value as in the
version field.

Required for fwupd which uses the family field to generate a GUID.

Change-Id: I0033c42c5eac6b9d47d0acd16c67467b6d419534
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-12 07:48:18 +00:00
2be0b50be5 boot_device: Constify argument
Add const qualifier to first argument.

Change-Id: I6655e04401b6a7aa5cafb717ff6f46b80b96646e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-12 07:47:45 +00:00
2d7a52c784 lib/timestamp: Make timestamp_sync_cache_to_cbmem() in postcar
This patch ensures to have correct timestamp value in postcar.

Change-Id: I3ba3a54c20dfcdaf5b87818cc5da9a812f5f2edf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-12 03:11:20 +00:00
7e893a02c0 Kconfig: Create RAMPAYLOAD kconfig
This patch enables coreboot flow to skip ramstage as
individual stage to load payload. Instead it is expected
to load payload from postcar stage.

Change-Id: I839f2d34a93b69ca6bf3de6594e2ad9f66ee7135
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
2019-05-12 03:10:24 +00:00