Traditionally, we have always allocated 1 DRAM ID per part number.
However, on nami, we have run out of DRAM IDs because we have
supported so many different parts. We are now adopting the use of
generic SPD files that are feature-based rather than specific to each
part, allowing us to support multiple parts with a single SPD.
The common SPDs were created by taking current SPDs in Nami (which is
using the same DDR4 parts as Hatch) and zeroing out all the
manufacturer information and part names. Additionally, we zeroed out
bytes 128 (raw card extension, module nominal height), 129 (module
maximum thickness), and 130 (reference raw card used) after verifying
that they are not used in FSP. We verified with these fields zeroed
out, all nami devices could boot up without errors. We also verified
on the two Hatch skus that we have (4G 2400, 8G 2666) that the generic
SPDs boot properly.
BUG=b:122959294
BRANCH=None
TEST=Make sure that we can boot up on both 4G Samsung and 8G Hynix DDR4
devices that we currently have.
Change-Id: I14d9e6b13975b6a65b506e6cd475160711b8f6d4
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
df7aecd "cpu/intel: Configure IA32_FEATURE_CONTROL for alternative
SMRR" introduced a regression because it unconditionally writes to
IA32_FEATURE_CONTROL, which if it is already locked results in an
unhandled exception. The lock bit is already set on a system reboot.
Change-Id: I7d2df9e1b9d767809da7a61ccd877c6c40f132eb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31255
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
"is_wakeup_source" flag is used to indicate if the concerned device can
trigger a wakeup. This flag is redundant with the "wake" GPE event
definition. So remove the redundant flag and use the "wake" GPE event to
mark the wakeup source.
BUG=None
BRANCH=None
TEST=Boot to ChromeOS. Ensure that the device is marked as wakeup-source
in SSDT if wake GPE is configured. Ensure that the system can suspend
and the device acts as a wakeup source
Change-Id: I99237323639df1cb72e3a81bcfed869900a2eefa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change uses cnl_configure_pads to configure GPIOs in ramstage so
that cannonlake SoC code can re-configure the GPIOs after FSP-S is
run. This is just adding a workaround until FSP-S is fixed.
BUG=b:123721147
BRANCH=None
TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch.
Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
FSP-S is currently configuring GPIOs that it should not. This results
in issues where mainboard devices don't behave as expected e.g. host
unable to receive TPM interrupts as the pad for the interrupt is
re-configured as something else.
Until FSP-S is fixed, this change adds a workaround by reconfiguring
GPIOs after FSP-S is run.
All mainboards need to call cnl_configure_pads instead of
gpio_configure_pads so that SoC code can maintain a reference to the
GPIO table and use that to re-configure GPIOs after FSP-S is run.
BUG=b:123721147
BRANCH=None
TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch.
Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch performs below tasks
1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig.
2. Allow required SoC to select this kconfig to extend CANNONLAKE
SoC support and add incremental changes.
3. Select correct SoC support for hatch, sarien, cflrvps
and whlrvp.
* Hatch is WHL SoC based board
* Sarien is WHL SoC based board
* CFLRVP U/8/11 are CFL SoC based board
* WHLRVP is based on WHL SoC
4. Add correct FSP blobs path for WHL SoC based designs.
Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change enables I2C bus 2, 3 and 4 in devicetree and configures
GPIO pads for the same. It also configures pads for I2C5 as
no-connect.
BUG=b:123711244
TEST=Verified that i2c shows up in "i2cdetect -l" after booting to OS.
Change-Id: Ib4714a670d73228332115415e4393f82802c6475
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31237
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current coreboot size is not adequate for adding new features.
Note for cros: This change is for merge to ToT only and should not be
cherry-picked into reef's firmware branch.
BUG=chromium:903833
TEST=emerge-reef coreboot
Change-Id: Ie7a25c4638c474e81fb34b57de0dfc1bf393ea67
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add maximum width and height options and set the default to 2560x1600
(WQXGA). The framebuffer will be scaled up to the displays' native
resolutions. So this should help with tiny fonts on high-DPI displays.
For laptops, reasonable defaults can be set at the mainboard level.
Change-Id: I47fba063629260c3a2854caf7a73f1a1e933d063
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We generate a $(obj)/cb-config.ads once and copy it per stage that uses
it to $(obj)/<stage>/cb-config.ads (to simplify the gnat-bind step). The
Ada package is called `CB.Config`. As there was no `CB` package yet, add
that too.
Change-Id: I963a6517ef4bcf84f2c8e9ae8d24a0d6b971d2b0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This moves a lot of the common romstage boilerplate code to a common
location, while adding a few mainboard specific hooks.
Another difference is that the settings for enable_igd and enable_peg
are now based on the static devicetree settings.
Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
his either sets unwanted or unnecessary settings.
Also this RCBA replay did not even originate from the T400 as this
code was copied from the Thinkpad x200 code on which this replay was
already removed in 7bcd062 'mb/lenovo/x200: Remove RCBA replay'
Change-Id: Iac6846d43395e342897e03c1ad31387638bcac64
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch ensures to select chromeos kconfig only for required
CFL-U and WHL-U RVPs supported by Intel client team.
TEST=Ensure CONFIG_GBB_FLAG_FORCE_MANUAL_RECOVERY is only selected
for CFL-U and WHL-U boards.
Change-Id: Ib61409402a948f8d5f91130e200c45320ea13d3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31214
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select the appropriate system type for the different variants of
the Sarien board.
This will allow the Arcada variant to use the tablet mode feature
of the Intel Virtual Button driver.
Change-Id: I8a829aab012256ec196c8ec0fa298fd2bc77f2e1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add an ACPI device that is compatible with the Intel Virtual
Button kernel driver for reporting tablet mode state and various
virtual button events that may come from the EC.
This driver is used in Windows and in the Linux kernel at
drivers/platform/x86/intel-vbtn.c
Because of a check in the kernel driver it expects the board to
define the SMBIOS enclosure type as convertible for the check at
driver load time for tablet/laptop and dock/undock to work.
The virtual tablet mode button will proxy the tablet mode state
sent from the Sensor Hub to a SW_TABLET_MODE event in the kernel.
The virtual power button is used during S0ix for the EC to wake
the system with an SCI. There are separate press and release
events which are sent for completeness, although the kernel driver
will ignore the release event.
BUG=b:73137291
TEST=Test that the power button can wake the system from S0ix.
Also verify that the device is reported as laptop mode at boot.
Change-Id: I0d5dc985a3cfb1d01ff164c4e67f17e6b1cdd619
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31208
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are more common system types and in some cases it is important
to know when a device is a convertible or a tablet or detachable
instead of just a laptop.
This change will select the appropriate SMBIOS enclosure type based
on the selected system type.
This is important for the Intel Virtual Button driver as it does a
check on the SMBIOS enclosure type and only enables the tablet mode
events if it is set to convertible:
https://patchwork.kernel.org/patch/10236253/
Change-Id: I148ec2329a1dd38ad55c60ba277a514c66376fcc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The ACPI spec has an asl example for _PLD in the form:
Name (_PLD, Package (0x01) { ToPLD (PLD_Revision = 0x2) })
When I ported this to acpigen and diffed the results I noticed that
the binary blob was no longer provided within a package. The ACPI
spec (section 6.1.8 in version 6.2) defines _PLD as "a variable-length
Package containing a list of Buffers". This commit changes
acpigen_write_pld to use a package (the one existing caller I found
isn't wrapping the result in a package so it doesn't look like
it was intended for the callers of acpigen_write_pld to be responsible
for using a package.
BUG=none
BRANCH=none
TEST=Verified that after this change a package is use and the result
of acpigen matches what was used in the original asl.
Change-Id: Ie2db63c976100109bfe976553e52565fb2d2d9df
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
If an acpi_dp table has children but no properties then acpi_dp_write()
will write out a properties UUID and package that contains no properties.
The existing function will avoid writing out a UUID and empty package
when no children exist, but it seems to assume that properties will
always be used. With this change properties are handled in a manner
akin to children so that a UUID and package are only written if
properties exist.
BUG=none
BRANCH=none
TEST=Confirmed that prior to this change a UUID and empty package was
present for a device that had children but no properties. Verified that
after this change the UUID and empty package are no longer present but
the child UUID and package are still present.
Change-Id: I6f5597713a1e91ca26b409f36b3ff9eb90a010af
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The allocation is not required before romstage,
so it can be just another CAR_GLOBAL instead of
polluting the linker script.
Change-Id: I0738a655f6cc924fbed92ea630f85406e3f58c0b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31191
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The default state of the HOSTSW_OWN register in the PCH is zero, which
configures GPIO pins for ACPI ownership. The board variabt GPIO tables
can request specific pins to be configured for GPIO driver ownership.
This change sets the HOSTSW_OWN ownership bit when requested and
explicitly clears the ownership bit if not requested.
BUG=b:120884290
BRANCH=none
TEST=Build coreboot on sarien. Verified UEFI to coreboot transition
boots successfully.
Change-Id: Ia82539dbbbc7cf5dfb9223902d563cafec1a73e5
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This reconfigures the GPP_D1 GPIO pin as a no-connect. It really
doesn't go anywhere today or on previous revs of the board.
BUG=b:110614620
BRANCH=none
TEST=atlas still boots
Change-Id: Iea53cf909f8f060c4e0f14e8b4ad579b838b7caa
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This reverts commit 7696290004.
We're seeing trackpad problems on some units with the I2C bus running
at 1MHz but not at 400KHz. So, revert back to 400KHz until we
understand how to make 1MHz operation more robust.
BUG=b:123650686
Change-Id: Ifb06afece9eee0c153240d35e6c3001f5b74f310
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use memory map from fw_cfg e820 map to find cbmem_top in romstage to
avoid conflicts with CMOS option table. Keep qemu_gwt_memory_size() as
fallback.
Change-Id: I6465085020125fc790257f09eb157030c6ceabcb
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The FSP has a parameter to enable or disable the VTD feature
(Intel's Virtualization Technology for Directed I/O). In current header
files for FSP-S (Apollo Lake and Gemini Lake) this parameter is set to
disabled per default. Therefore, if the FSP was not modified via BCT,
this feature is most likely disabled on all mainboards.
Add a chip parameter so that VTD can be enabled on mainboard level in
devicetree and therefore this feature can be activated if needed.
Change-Id: Ic0bfcf1719e1ccc678a932bf3d38c6dbce3556bc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31194
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables exporting the reset GPIO for CNVi Bluetooth module to
the kernel for use in an rf-kill operation.
BUG=b:123296264
BRANCH=octopus
TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset
gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured
that the kernel btusb driver is able to find the exported GPIO in the
devices with CNVi BT module.
Change-Id: I10f28bfe705da5104d709ae2ed91a8ae003fa639
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
GLK has a dedicated USB2 port that is used specifically for CNVi
BT. This requires that the ACPI tables define an additional USB 2 port
which results in _ADR for USB 3 ports being different for GLK than
APL.
This change splits the ports in xhci.asl into APL and GLK specific
ports.asl and selects the appropriate file based on
CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK
if ACPI name is requested for that port.
BUG=b:123670712
BRANCH=octopus
TEST=Verified that generated DSDT for octopus (GLK) includes HS09 and
for reef (APL) does not include HS09 definition.
Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31172
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This implementation adds support to create ACPI package for USB port
capability (_UPC) and physical location of device (_PLD) for USB2 port 10.
BUG🅱️123375275
TEST:Verify _UPC and _PLD ACPI packages gets published for USB2 Port 10
in SSDT and BT is functional in discrete and integrated mode.
Change-Id: Ifeab24505a700e8e4677be20074c7d0400769cec
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/31197
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
