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Author SHA1 Message Date
David Wu
872079656b mb/google/brya/var/kuldax: Add wifi sar table 
Add wifi sar table for kuldax

BUG=b:248367859
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot
chromeos-bootimage

Change-Id: I5ade590c739aae391e47e8bb66ee03c086e8d56e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71270
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-28 00:56:00 +00:00
Dinesh Gehlot
d910fec9a6 soc/intel/alderlake: Use common gpio.h include 
Replace the intelblocks/gpio.h and soc/gpio.h includes with the
common gpio.h which will include soc/gpio.h which will include
intelblocks/gpio.h

BUG=b:261778357
TEST=Able to build and boot Google/brya.

Change-Id: Ia90a8ea7b4ee125657c7277e3e14018cfe5423a9
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71266
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2022-12-27 15:23:11 +00:00
David Wu
a1b9f0588b mb/google/brya/var/kano: Enable Fast VMode for kano 
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.

BUG=b:252966799
BRANCH=firmware-brya-14505.B
TEST=Verify that the feature is enabled by reading from fsp log

Change-Id: I15c3eea6ebb7f104bce0ba8cb544ecde7f488343
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-27 15:21:15 +00:00
Harsha B R
a256bd6fe5 mb/intel/mtlrvp: Configure devicetree and GPIOs for MTL-RVP 
Add devicetree and GPIO configuration for MTL-RVP
Changes include,
1. Add initial devicetree to support MTL-RVP board & variant
2. Add initial setup for ramstage gpio config

BRANCH=none
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp to chromeOS
using subsequent patches in the train.

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I3173c3f32b36d24467431df3652badd70efeab93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-12-27 10:42:55 +00:00
Harsha B R
bd91aa7609 mb/intel/mtlrvp: Add bootblock and early gpio for MTL-RVP 
This patch adds initial bootblock code. This also configures required
GPIOs for early board initialization.

1. Add bootblock file for MTL-RVP
2. Add early gpio config for MTL-P variant in gpio.c

BRANCH=none
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform to
ChromeOS with the subsequent patches in the train

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I9c0893e52036147c5f6bbfafc6d818e9d3460bed
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-12-27 10:42:07 +00:00
Subrata Banik
b052683d46 mb/google/rex: Enable PMC IPC config 
TEST=Able to build and boot Google/Rex.

Device (PMC)
{
    Name (_HID, "INTC1026")  // _HID: Hardware ID
    Name (_DDN, "Intel(R) Meteor Lake IPC Controller")  // _DDN: DOS Dev
ice Name
    Method (_STA, 0, NotSerialized)  // _STA: Status
    {
         Return (0x0B)
    }
    ...
}

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I28c0153a770b36cde0653ac92d2e5ad1b8dd3449
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71268
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-27 10:05:46 +00:00
Felix Singer
9df60d36b2 tree/acpi: Replace constant "Zero" with actual number 
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-27 09:06:47 +00:00
Felix Singer
42efd7f593 {superio,ec}/acpi: Replace constant "Zero" with actual number 
Change-Id: I449ec5b0bbf3f24d51688efef151d3018d2848b2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71524
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-27 09:06:29 +00:00
Felix Singer
fa06bcba06 mainboard/acpi: Replace constant "Zero" with actual number 
Change-Id: I4f2f02623b060ef0ebefc5aceb713c77a8b1e9a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71523
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-27 09:05:56 +00:00
Felix Singer
7b8ac0030c {acpi,arch,soc}/acpi: Replace constant "One" with actual number 
Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-27 09:05:15 +00:00
Felix Singer
dfbb634ae1 mainboard/acpi: Replace constant "One" with actual number 
Change-Id: Id1078b14a805eea53d2a7c5a8183a5413f26e115
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71521
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-27 09:04:02 +00:00
Felix Singer
ca4b587f95 {superio,ec}/acpi: Replace constant "One" with actual number 
Change-Id: I5c77b6d1e1dc1134f62dcb3e93df01dc9c2f386c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71520
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-27 09:03:34 +00:00
Subrata Banik
b4767ce169 mb/google/brya/var/marasov: Add DmaProperty for ISH 
On Marasov, the ISH is running closed source firmware, so the ChromeOS
security requirements specify it must be behind an IOMMU. Add
DmaProperty to the ISH _DSD on Marasov.

TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the
IOMMU group type to "DMA". Also, device still goes to S0i3.

Before:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
0

After:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
1

Change-Id: I4b65b8909c41b06852fe7771375029bd2e76e111
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71263
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-27 04:41:33 +00:00
Subrata Banik
3a60e5c827 drivers/intel/ish: Add ADL-P ISH DID 
This patch adds ISH ID for ADL-P to ensure dynamic ASL code is
added into SSDT.

With this patch:
   Scope (\_SB.PCI0.ISHB)
    {
        Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
        {
            ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
            Package (0x01)
            {
                Package (0x02)
                {
                    "DmaProperty",
                    One
                }
            }
        })
    }

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I48dc6056155824239bb88eda2b0ff5bcd36ced15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71262
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-27 04:41:12 +00:00
Subrata Banik
11e1950d26 mb/google/brya/var/marasov: Remove ISH firmware-name 
For marasov, the ISH main firmware will be included in the CSE region in
flash instead of loading it from rootfs. So remove the ISH
firmware-name.

TEST=Boot to OS on Marasov UFS SKUs. Check ISH firmware is not
loaded by kernel, and device still goes to S0i3.

Change-Id: I278e5d403ef9515e538a527f43949e505d750bb1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71261
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
 2022-12-27 04:40:56 +00:00
Elyes Haouas
1e9344481a sio/winbond/w83627hf/acpi: Replace Divide(a,b,c,d) with ASL 2.0 syntax 
Replace Divide (a,b,c,d) with:
  c = a % b
  d = a / b

Change-Id: I0e9fdabbb4b5bd9698968cd8acb497dcde14e433
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71508
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-26 20:43:25 +00:00
Felix Singer
8171364d06 tree/acpi: Replace Divide(a,b,c,d) with ASL 2.0 syntax 
Replace `Divide (a, b, c, d)` with these instructions:

  c = a % b
  d = a / b

Change-Id: I44366be5b5145a5d19f85df7a2f338866cb9c8b0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2022-12-26 19:57:44 +00:00
Felix Singer
eaa31d95c2 mb/lenovo/s230u/acpi: Replace Not(a, b) with ASL 2.0 syntax 
Replace `Not (a, b)` with `b = ~a`.

Change-Id: I0f18119c8e91222e59a56b8509f12c6ece6d04ce
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71514
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-26 19:57:09 +00:00
Felix Singer
c87c1abffb tree/acpi: Replace Not(a) with ASL 2.0 syntax 
Replace `Not (a)` with `~a`.

Change-Id: I53993fb7b46b3614d18ee001323f17efacbf04c1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71513
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-26 19:56:04 +00:00
Subrata Banik
25b717ad84 drivers/pc80/vga: Add NULL check for vga_line_write() 
This patch ensures vga_line_write() returns if the argument 1
(aka output string) is NULL.

TEST=Able to build and boot Google/Taeko.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I716ce82c0afe21f7fe2f6d7bdc5229f8087242fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
 2022-12-26 15:55:28 +00:00
Elyes Haouas
cfdd488440 sio/acpi/pnp.asl: Replace Not(a) with ASL 2.0 syntax 
Change-Id: Icbd2ab736b9fc3300ee82896c31b373fe92e1d54
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71509
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-26 11:45:10 +00:00
Elyes Haouas
e007893a8e nb/intel/ironlake/acpi: Replace Index(a, b) with ASL 2.0 syntax 
Change-Id: I6af7131e151700569d50e8bc42bfaeb7a58fa7d3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71507
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-26 08:53:07 +00:00
Elyes Haouas
2369818c3d nb/intel/sandybridge/acpi: Replace Index(a, b) with ASL 2.0 syntax 
Change-Id: I75bc048d9e04be8d0cab25f6aad1c71d3e7a4008
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71506
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-26 08:52:19 +00:00
Elyes Haouas
9ede493c73 nb/intel/haswell/acpi: Replace Index(a, b) with ASL 2.0 syntax 
Change-Id: I1ff0132e17b08f492828eb13d66e167eae45250d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71505
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-26 08:51:55 +00:00
Elyes Haouas
f451bfb1a5 soc/intel/baytrail/acpi: Replace Index(a, b) with ASL 2.0 syntax 
Change-Id: Iab611cda1083da4378a6e509d11ea26bdbb45edd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71503
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-26 08:51:39 +00:00
Elyes Haouas
ffc0d2455c soc/intel/braswell/acpi: Replace Index(a, b) with ASL 2.0 syntax 
Change-Id: I7da6ee3c5bce6b32874e59ad46290b86db8f97c6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71502
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-26 08:50:46 +00:00
Dinesh Gehlot
14a0876de8 soc/intel/meteorlake: Make use of is_devfn_enabled() function 
1. Replace all pcidev_path_on_root() and is_dev_enabled()
functions combination with is_devfn_enabled().
2. Remove unused local variable of device structure type
(struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with
is_devfn_enabled() call.

TEST=Able to build and boot without any regression seen on MTL.

Port of 'commit 50134eccbd ("soc/intel/alderlake: Make use
of is_devfn_enabled() function")'

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I54bbd2bdba69a19e0559738035916fa7ac60faaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-12-25 15:26:03 +00:00
Dinesh Gehlot
d4f2d14d52 soc/intel: Move max speed API to common 
This patch moves API "smbios_cpu_get_max_speed_mhz()"
to common code from board specific. This API was made
generic in 'commit d34364bdea ("soc/intel/alderlake:
Utilize `CPU_BCLK_MHZ` over dedicated macro")'

BUG=NONE
TEST=Boot and verified that SMBIOS max speed value is
correct on brya and rex.
(brya) dmidecode -t : "Max Speed: 4400 MHz"
(rex) dmidecode -t : "Max Speed: 3400 MHz"

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I87040ab23319097287e191d7fc9579f16d716e62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70879
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-25 15:24:36 +00:00
Elyes Haouas
2179c7fdb7 arch/riscv: Use 'enum cb_err' 
Change-Id: I5a589a43b1e92cca6b531ca161174eefb5592569
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
 2022-12-25 15:09:48 +00:00
Elyes Haouas
9523e3b790 arch/x86: Use 'enum cb_err' 
Change-Id: I38e4b8c6adfaaa45377b2fbe0644285d21841cd1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
 2022-12-25 15:09:16 +00:00
Martin Roth
70191da272 util/docker: Update setuptools to get dtc building 
python3-setuptools installed via apt-get is not currently working to
build dtc from git.kernel.org.  Falling back to setuptools version
58.2.0 allows it to build again.

The failure message was:
/usr/lib/python3/dist-packages/setuptools/installer.py:27:
SetuptoolsDeprecationWarning: setuptools.installer is deprecated.
Requirements should be satisfied by a PEP 517 installer.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I04cb6d776c3748f9a4b0cfc4ffd4f46458560d3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71500
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-25 13:22:13 +00:00
Subrata Banik
265dc1d793 util/mb/google: Add support for rex 
Add the file templates for creating a new variant of Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4abca1f999accc008eb2549fcc13199b8d9bdc7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2022-12-24 23:39:08 +00:00
zhaojohn
92d49da163 mb/google/rex: Enable DPTF functionality for Rex 
Enable DPTF functionality for Meteor Lake Rex board.

BUG=b:262498724
TEST=Booted to OS and verified DPTF entries in ACPI SSDT on Rex board.

Change-Id: I87b2d71650be9ce940d9452bf4a76d4cd1ddba52
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70884
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-24 23:37:56 +00:00
Tracy Wu
387ec919d9 soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE 
With enabling FSP Notify Phase APIs, it has chance to issue a global
reset in FSP after CSE EOP (with selecting SOC_INTEL_CSE_SEND_EOP_EARLY
), which CSE already in idle mode and cause failure. For this reason we
should drop SOC_INTEL_CSE_SEND_EOP_EARLY in all ADL sku and select
SOC_INTEL_CSE_SEND_EOP_LATE instead.

BUG=b:261544011
BRANCH=firmware-brya-14505.B
TEST=tested and verified on Marasov, make sure this kind of global
reset can be executed successfully.

Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: I29736ca8efee64dd03feb48404241ee6295b7c72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-12-24 23:36:59 +00:00
Johnny Li
2a12b6a9a4 mb/google/volteer/eldrid: Correct DDR4 SPDs for Eldrid 
Correct DDR4 SPDs from H5AG36EXNDX019 to H5AG36EXNDX017.

DRAM Part Name    ID to assign
H5AG36EXNDX017    0 (0000)

BUG=b:236739240
BRANCH=Volteer
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully.

Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: If248714088835eb5dd48fa12223c273199297228
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71160
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-24 23:35:44 +00:00
Johnny Li
7866193eee spd/ddr4: Correct Hynix ddr4 part number from H5AG36EXNDX019 to H5AG36EXNDX017 
Correct Hynix ddr4 part number H5AG36EXNDX019 to H5AG36EXNDX017 by Hynix Memory spec.

BUG=b:236739240
BRANCH=Volteer
TEST="util/spd_tools/bin/spd_gen memory_parts.json ddr4" and verify it builds successfully.

Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I6195fa1402691afc303f5223de48f552660cd97f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71159
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-24 23:35:31 +00:00
David Wu
cedd4d14f4 mb/google/brya/var/zydron: Use SSFC for mipi instead of fw_config 
Kano didn't use SSFC in mass production, however
Zydron needs SSFC for 2rd source mipi instead of fw_config.

BUG=b:262939431
TEST=Boot to OS and check functional with ov2740/hi556 camera.

Change-Id: Idb2a35d67af0b5a7dedc66b0f7eccd8a3b4612d1
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
 2022-12-24 19:11:22 +00:00
Karthikeyan Ramasubramanian
716c8f0711 soc/amd/mendocino: Split the EFS from the AMDFW body 
Contents of unsigned AMDFW in RW sections are verified twice in PSP
verstage - first time by vboot verifying the firmware body, second time
by CBFS verification while the file is loaded to update PSP about the
boot region. This redundant verification adds to boot time. Minimize the
redundancy by splitting the EFS header from the AMDFW body and keep them
as 2 separate CBFS files. This helps to improve the boot time by another
25 ms.

BUG=None
TEST=Build Skyrim BIOS image and boot to OS. Observe boot time
improvement of ~25ms.
Before:
   6:end of verified boot              363,676 (16)
  11:start of bootblock                641,392 (277,716)
After:
   6:end of verified boot              361,655 (16)
  11:start of bootblock                616,967 (255,312)

Change-Id: Ib18a4f5c6781e5a7868e9395c0f1212da0823100
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70839
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-24 19:10:17 +00:00
Karthikeyan Ramasubramanian
ecb4e31531 util/amdfwtool: Write EFS and AMDFW body in separate files 
Add support to write EFS and AMDFW body to separate files. This is done
through passing an optional --body-location parameter to the amdfwtool.
If that option is not passed, then EFS will be written in the same file
as the AMDFW body. This will help to keep the minimum data to be
loaded/mapped from CBFS in PSP verstage.

BUG=None
TEST=Build and boot to OS in Skyrim.

Change-Id: I79325c81394cf8a0c663752d094adf6660896127
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-24 19:09:59 +00:00
Subrata Banik
7c55aab199 mb/google/rex: Use GPP_C15 as WWAN_DPR_SAR_ODL 
BUG=b:263413949
TEST=Able to build and boot Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I453fe8e1f4b4b8d4730ade259899d76aec949a44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71231
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2022-12-24 13:25:41 +00:00
Subrata Banik
9a97df3010 mb/google/rex: Rename GPP_D07 to FPMCU_UWB_MUX_SEL 
BUG=b:263412235
TEST=Able to build and boot Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia444cc8e3666fe15479ece81d068f9e8f1d339ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71228
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2022-12-24 13:25:27 +00:00
Eric Lai
beb2826ffd mb/google/nissa/var/craask: Use get_wifi_sar_fw_config_filename 
Use get_wifi_sar_fw_config_filename to remove the duplicate code.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I04176fee373e534d42c72506df73a092ad55e65b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-12-24 05:51:39 +00:00
Eric Lai
3c53300002 mb/google/volteer/var/lindar: Use get_wifi_sar_fw_config_filename 
Use get_wifi_sar_fw_config_filename to remove the duplicate code.
WIFI_SAR_CBFS_DEFAULT_FILENAME is not exist, so return the non-exist
id has the same outcome.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib34e6b4f435880d62936ae54f19ba2ec752eced2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-12-24 05:51:15 +00:00
Eric Lai
bffa9066fa mb/google/brya/var/taeko: Use get_wifi_sar_fw_config_filename 
Use get_wifi_sar_fw_config_filename to remove the duplicate code.
WIFI_SAR_CBFS_DEFAULT_FILENAME is not exist, so return the non-exist
id has the same outcome.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib7a764d8cc3160c26abad9c1757812b955bef066
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-12-24 05:50:54 +00:00
Eric Lai
51f1822421 mb/google/nissa/var/pujjo: Use get_wifi_sar_fw_config_filename 
Use get_wifi_sar_fw_config_filename to remove the duplicate code.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ifde714c19f7ab9fe08f870060037db190a80dbd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-12-24 05:50:25 +00:00
Eric Lai
8cb2f185d1 vc/google/chromeos: use fw_config field to return sar filename 
Use fw_config field to return sar filename instead of fw_config probe.
Return filename unconditionly because the sar_id must be valid in
CBI. If invalid sar_id, the file won't exist in CBFS by design.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I7b75c5d4fd3c459ad7232bb16c6218a6218f1f77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-12-24 05:50:13 +00:00
Eric Lai
9f2faca246 lib: add stub for fw_config_get_field 
Return UNDEFINED_FW_CONFIG with disabled fw_config.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I0d31ff3ba7706039c622bd1ec825d216a0f21fe4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-12-24 05:50:00 +00:00
Sergii Dmytruk
4ee03170e0 Revert "security/tpm/: turn tis_{init,open} into tis_probe" 
This reverts commit d43154486d.

From CB:68991: This causes CraterLake boot up process to die.
Investigation in progress.

Change-Id: I4a6c11b0e638a891108fe230bdaea92d5fbca020
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: siemens-bot
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-12-23 21:31:11 +00:00
Sergii Dmytruk
025d20eaeb Revert "drivers/pc80/tpm: probe for TPM family of a device" 
This reverts commit 907a81e2a7.

This reportedly breaks TPM and measured boot flow completely.

Change-Id: Id0d98ecc7807faa1617ad16dc9a24343c5a66b06
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-12-23 21:30:54 +00:00
Matt DeVillier
86425c81af mb/google/poppy: Use runtime detection for touchscreens/digitizers 
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens/digitizers.
This removes non-present devices from the SSDT and relieves the OS of
the burden of probing.

BUG=b:121309055
TEST=build/boot Windows/linux on all poppy variants, verify all
touchscreens functional in OS, dump ACPI and verify only i2c devices
actually present on the board have entries in the SSDT.

Change-Id: I4c1d8ae8c41c1f4283718a86fccbf5ae4fc399b6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70921
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-23 20:58:57 +00:00