5be0b2e03d
rockchip/rk3399: fix rk_mipi_dsi_phy_init err
...
This patch fix rk_mipi_dsi_phy_init error return.
Change-Id: Ie260975ad6ed26c37aa8bb65dfcef4db2407a2da
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com >
Reviewed-on: https://review.coreboot.org/19903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Julius Werner <jwerner@chromium.org >
2017-05-26 23:47:17 +02:00
6b697ef207
util/hugo: no need to enable an interactive terminal
...
Change-Id: Iac4cdb003b2fe967b303c1f8e0eeb61673a02858
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de >
Reviewed-on: https://review.coreboot.org/19930
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
Tested-by: Patrick Georgi <pgeorgi@google.com >
2017-05-26 18:36:47 +02:00
dc5eea1cfa
util/hugo: mark source mounts read-only
...
hugo has no need to write there, it should only write to the
output directory.
Change-Id: Ie320f5017feccfa2e9ecba3c802e040487b44d67
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de >
Reviewed-on: https://review.coreboot.org/19929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
2017-05-26 18:36:19 +02:00
73108ded48
mainboard/google/poppy: Add PowerResource for touchscreen device
...
1. Do not enable touchscreen device by default in gpio configuration.
2. Select use of PowerResource for touchscreen device in devicetree so
that the ACPI subsystem can take care of powering on/off the
device. When system enters suspend, touchscreen device is powered off
and on resume, it is powered back on.
BUG=b:62028489
TEST=Verified 100 cycles of suspend-resume. Touchscreen still works on
poppy.
Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e
Signed-off-by: Furquan Shaikh <furquan@chromium.org >
Reviewed-on: https://review.coreboot.org/19829
Reviewed-by: Duncan Laurie <dlaurie@chromium.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2017-05-26 04:41:53 +02:00
04edaefad7
util/hugo: Add framework to build www.coreboot.org/Documentation
...
www.coreboot.org/Documentation is now built with hugo (www.gohugo.io)
based on files in this repo's /Documentation directory.
Also clarify that new additions to Documentation are under CC-BY 4.0 terms.
Change-Id: I000e15b29a182bb88b40de3d0178bf8cc54ba8af
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de >
Reviewed-on: https://review.coreboot.org/19881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com >
2017-05-25 23:04:36 +02:00
9ec25f7678
util/lint: ignore some more binary file types
...
Namely png (images) and eot, ttf, woff (fonts)
Change-Id: I41e773c0adab796876a3b1e91e089ae89cbb04df
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de >
Reviewed-on: https://review.coreboot.org/19880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com >
2017-05-25 23:04:29 +02:00
a6f0b2754b
soc/intel/skylake: Implement GPIO ACPI AML generating functions
...
Implement GPIO ACPI AML generating functions that can be called by
coreboot drivers to generate GPIO manipulation code in AML. Following
API functions are implemented:
1. acpigen_soc_read_rx_gpio
2. acpigen_soc_get_tx_gpio
3. acpigen_soc_set_tx_gpio
4. acpigen_soc_clear_tx_gpio
In addition to the API functions above, helper functions are added to
gpio.asl to set/clear/get Tx value of GPIO.
BUG=b:62028489
Change-Id: I77e5d0decd8929a922d06b02312378f092551667
Signed-off-by: Furquan Shaikh <furquan@chromium.org >
Reviewed-on: https://review.coreboot.org/19828
Reviewed-by: Duncan Laurie <dlaurie@chromium.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2017-05-25 18:37:33 +02:00
d635506fa7
detachables: Add invert parameter
...
Instead of storing inverted-colored bitmaps,
invert drawing of text bitmap on the fly by adding
an invert parameter down to libpayload. Merging
pivot and invert fields into flags field.
BUG=b:35585623
BRANCH=None
TEST=Make sure compiles successfully
CQ-DEPEND=CL:506453
Change-Id: Ide6893a26f19eb2490377d4d53366ad145a9e6e3
Signed-off-by: Shelley Chen <shchen@chromium.org >
Reviewed-on: https://review.coreboot.org/19698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2017-05-25 18:23:56 +02:00
000cc598cb
mb/lenovo/*60: Remove not existing DIMMs from SPD map
...
Should result in a tiny speed bump in raminit since those addresses
are not checked for present DIMMs.
Checked in schematics of both Thinkpad X60 and T60 and tested to
configure raminit correctly for all DIMMs populated on X60.
Change-Id: I56c4f3176541bc75a8de3aac9f87526a77fc819b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/19862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2017-05-25 17:37:52 +02:00
36dafd88bc
mb/lenovo/x200/blc: Add LTD121EQ3B panel at 447Hz
...
Change-Id: Ia44097f32f74ffd749219415984224ce33d9252b
Signed-off-by: Nico Huber <nico.h@gmx.de >
Reviewed-on: https://review.coreboot.org/19816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2017-05-25 17:04:14 +02:00
41f937382d
mainboard/google/eve: Update VR config settings
...
Update Psi2Threshold, IccMax, AcLoadline, DcLoadline
VR config settings as per board design.
BUG=b:38415991
BRANCH=none
TEST=Build and boot eve.
Change-Id: I274245821f68fb3151e5563ea0c75eaa1ad32c08
Signed-off-by: V Sowmya <v.sowmya@intel.com >
Reviewed-on: https://review.coreboot.org/19826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-by: Duncan Laurie <dlaurie@chromium.org >
2017-05-25 16:14:49 +02:00
34dba35831
rk3399: Reshuffle memlayout to move PRERAM_CBMEM_CONSOLE further back
...
It seems that the BootROM on the RK3399 overwrites some of the earlier
parts of SRAM, including the PRERAM_CBMEM_CONSOLE area. Now that we have
a persistent CBMEM console we want that area to survive in case of an
early (pre-CBMEM) reboot, so shuffle the layout around a bit to move it
further back. (This reduces the stack size to 12KB which should still be
way more than enough.)
Change-Id: Ifc1e568cda334394134bba9eba75088032d2ff13
Signed-off-by: Julius Werner <jwerner@chromium.org >
Reviewed-on: https://review.coreboot.org/19784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
2017-05-24 16:30:39 +02:00
b25b2329a9
mb/google/soraka: Update camera sensor for soraka
...
Soraka uses OV 13858 sensor. Hence update the same.
Change-Id: I4dd39a25da47e379cca3f8748250b3ce1ff61e50
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com >
Reviewed-on: https://review.coreboot.org/19639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2017-05-24 16:29:14 +02:00
37689fae38
nb/intel/x4x/raminit: Initialise async variable
...
It could end up not initialized which causes it not to build with
clang.
Change-Id: I3be9477d836123aaa87c9bebb41c1ec34689a771
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/19736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Martin Roth <martinroth@google.com >
2017-05-24 16:28:19 +02:00
1d407cceaf
mb/google/poppy: Update SPD data
...
Though SPD is rightly selected (i.e., H9CCNNNBKTALBR-NUD),
it displays wrong part number during boot in coreboot logs.
So correct part number info within the SPD.
TEST= Build for Soraka & make sure part number is rightly printed.
Change-Id: I67f676fb6ee9d685fa7aa41fdc4b00355e6d33c7
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com >
Reviewed-on: https://review.coreboot.org/19692
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2017-05-24 08:02:19 +02:00
dd8d24759d
drivers/spi/spi-generic: Make spi_setup_slave strong symbol
...
Now that all platforms are updated to provide spi bus map, there is no
need to keep the spi_setup_slave as a weak symbol.
BUG=b:38430839
Change-Id: I59b9bbb5303dad7ce062958a0ab8dee49a4ec1e0
Signed-off-by: Furquan Shaikh <furquan@chromium.org >
Reviewed-on: https://review.coreboot.org/19781
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2017-05-24 04:43:46 +02:00
53bbf87a4c
soc/marvell/armada38x: Remove unused SoC armada38x
...
No mainboard is actually using this SoC. Remove the code for this SoC
for now.
BUG=b:38430839
Change-Id: Ia35986dffda8bbd76305ef5abab6ae81cc154b0f
Signed-off-by: Furquan Shaikh <furquan@chromium.org >
Reviewed-on: https://review.coreboot.org/19824
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2017-05-24 04:43:23 +02:00
12eca76469
southbridge/amd: Move spi driver to use spi_bus_map
...
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I2a789cff40fb0e6bd6d84565531d847afb3f8bed
Signed-off-by: Furquan Shaikh <furquan@chromium.org >
Reviewed-on: https://review.coreboot.org/19780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
2017-05-24 04:43:04 +02:00
2cd03f1696
southbridge/intel: Move spi driver to use spi_bus_map
...
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I23c1108c85532b7346ff7e0adb0ac90dbf2bb2cc
Signed-off-by: Furquan Shaikh <furquan@chromium.org >
Reviewed-on: https://review.coreboot.org/19779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
2017-05-24 04:42:40 +02:00
2d9a99535d
soc/intel: Move spi driver to use spi_bus_map
...
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: Id3f05a2ea6eb5e31ca607861973d96b507208115
Signed-off-by: Furquan Shaikh <furquan@chromium.org >
Reviewed-on: https://review.coreboot.org/19778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
2017-05-24 04:41:21 +02:00
f8662ca3bc
soc/samsung/exynos5420: Move spi driver to use spi_bus_map
...
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: Ic937cbf93b87f5e43f7d70140b47fa97bcd7757e
Signed-off-by: Furquan Shaikh <furquan@chromium.org >
Reviewed-on: https://review.coreboot.org/19777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
2017-05-24 04:40:28 +02:00
e424a59729
soc/qualcomm/ipq*: Move spi driver to use spi_bus_map
...
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I6cc8c339e008e16449fa143c1d21e23534bdaf0b
Signed-off-by: Furquan Shaikh <furquan@chromium.org >
Reviewed-on: https://review.coreboot.org/19776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2017-05-24 04:39:52 +02:00
56c88ebc02
soc/broadcom/cygnus: Move spi driver to use spi_bus_map
...
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I48b242dd6226e392ed0f403051843b3ae02cd9a4
Signed-off-by: Furquan Shaikh <furquan@chromium.org >
Reviewed-on: https://review.coreboot.org/19773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
2017-05-24 04:39:30 +02:00
e173ee8f01
soc/imgtec/pistachio: Move spi driver to use spi_bus_map
...
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: Ie4ec74fccaf25900537ccd5c146bb0a333a2754c
Signed-off-by: Furquan Shaikh <furquan@chromium.org >
Reviewed-on: https://review.coreboot.org/19772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2017-05-24 04:39:07 +02:00
23d5d99098
soc/rockchip: Move spi driver to use spi_bus_map
...
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I66b1b9635ece2381f62f2a9d6f5744d639d59163
Signed-off-by: Furquan Shaikh <furquan@chromium.org >
Reviewed-on: https://review.coreboot.org/19771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Julius Werner <jwerner@chromium.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
2017-05-24 04:38:50 +02:00
02c0743a24
soc/mediatek/mt8173: Move spi driver to use spi_bus_map
...
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: Ib0d6e4e8185ce1285b671af5ebcead1d42e049bc
Signed-off-by: Furquan Shaikh <furquan@chromium.org >
Reviewed-on: https://review.coreboot.org/19770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Julius Werner <jwerner@chromium.org >
2017-05-24 04:38:33 +02:00
b46e9f6029
soc/nvidia/tegra*: Move spi driver to use spi_bus_map
...
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I873b96d286655a814554bfd89f899ee87302b06d
Signed-off-by: Furquan Shaikh <furquan@chromium.org >
Reviewed-on: https://review.coreboot.org/19769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Julius Werner <jwerner@chromium.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
2017-05-24 04:38:04 +02:00
250715eb2f
soc/marvell/bg4cd: remove cosmos mainboard and bg4cd soc
...
The SoC code was never completed. It's just a skeleton that gets
in the way of refactoring other code. Likewise, the mainboard was
never completed either. Just remove them both.
Change-Id: I8faaa9bb1b90ad2936dcdbaf2882651ebba6630c
Signed-off-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-on: https://review.coreboot.org/19823
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
2017-05-24 00:28:22 +02:00
0fb6568444
sb/intel/common: Add common EC fw support
...
Add support to the Intel common firmware Kconfig and Makefile.inc to
allow the embedded controller (EC) blob to be added to the final
binary through ifdtool.
TEST=Add ec.bin and enable in config, build is successful.
Change-Id: Ib14732b4d263dde4770bf26b055c005de2540338
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com >
Reviewed-on: https://review.coreboot.org/19719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
2017-05-23 00:53:27 +02:00
4a907c79a2
soc/intel/skylake: Display FPF status of CSME
...
Field Programmable Fuses (FPF) status maintained by
CSME in bits 30:31 of FWSTS6 for Skylake and Kabylake.
FPF committed means CSME has blown the fuses.
Change-Id: If63c7874e6c894749df8100426faca0ad432384b
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com >
Reviewed-on: https://review.coreboot.org/19747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
2017-05-22 23:38:17 +02:00
f714965e8d
soc/intel/common/block/uart: Add GLK UART pci ids
...
Change-Id: I08dd7a8c0d42d4ec7c6ff65a82553fe1efbcc424
Signed-off-by: Hannah Williams <hannah.williams@intel.com >
Reviewed-on: https://review.coreboot.org/19687
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2017-05-22 21:37:09 +02:00
3038e9bd08
soc/intel/common/block: Add GLK I2C PCI IDs
...
Add GLK PCI IDs for I2C to use common I2C code.
Change-Id: I2144199345e6382984c367f6a77f0cbb0a93daea
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com >
Reviewed-on: https://review.coreboot.org/19782
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2017-05-22 21:30:28 +02:00
240409a5f6
include/device: Add pci ids for Intel GLK
...
Change-Id: Ifbca20a0c38cc1fb8ee4b4e336d59e834fcaf57a
Signed-off-by: Hannah Williams <hannah.williams@intel.com >
Reviewed-on: https://review.coreboot.org/19686
Reviewed-by: Brenton Dong <brenton.m.dong@intel.com >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2017-05-22 21:29:55 +02:00
7941c96f8e
soc/intel/skylake: Add entry for deep Sx wake
...
If deep Sx is enabled and prev sleep state was not S0, then if SUS
power was lost, it means that the platform had entered deep Sx. Add an
elog entry for deep Sx variant in this case.
BUG=b:38436041
TEST=Verified that elog entries are updated correctly:
Deep S5:
59 | 2017-05-19 10:39:08 | Kernel Event | Clean Shutdown
60 | 2017-05-19 10:39:09 | ACPI Enter | S5
61 | 2017-05-19 10:39:17 | System boot | 22
62 | 2017-05-19 10:39:17 | EC Event | Power Button
63 | 2017-05-19 10:39:17 | ACPI Deep Sx Wake | S5
64 | 2017-05-19 10:39:17 | Wake Source | Power Button | 0
65 | 2017-05-19 10:39:17 | Chrome OS Developer Mode
Deep S3:
66 | 2017-05-19 10:40:11 | ACPI Enter | S3
67 | 2017-05-19 10:40:16 | EC Event | Power Button
68 | 2017-05-19 10:40:16 | ACPI Deep Sx Wake | S3
69 | 2017-05-19 10:40:16 | Wake Source | Power Button | 0
Normal S3:
77 | 2017-05-19 10:43:22 | ACPI Enter | S3
78 | 2017-05-19 10:43:39 | EC Event | Power Button
79 | 2017-05-19 10:43:39 | ACPI Wake | S3
80 | 2017-05-19 10:43:39 | Wake Source | Power Button | 0
Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac4
Signed-off-by: Furquan Shaikh <furquan@chromium.org >
Reviewed-on: https://review.coreboot.org/19798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2017-05-22 18:47:32 +02:00
75ef6ec29e
elog: Add a new elog type for deep Sx variant
...
This is useful for debugging based on eventlog to identify if platform
entered normal or deep Sx.
BUG=b:38436041
Change-Id: Ic7d8e5b8aafc07aed385fe3c4831ab7d29e1f890
Signed-off-by: Furquan Shaikh <furquan@chromium.org >
Reviewed-on: https://review.coreboot.org/19797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2017-05-22 18:47:21 +02:00
fd8e00092a
soc/intel/skylake: Use Intel SATA common code
...
Use SATA common code from soc/intel/common/block/sata
and clean up code.
Change-Id: Ib5d65f1afda6b2f8098f1c006623a48cf2690593
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com >
Reviewed-on: https://review.coreboot.org/19735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
2017-05-22 18:12:27 +02:00
1b1ecae0a4
soc/intel/common: Add Intel SATA common code support
...
Add SATA code support in intel/common/block to initilalize
SATA controller, allocate resources and configure SATA port
status.
Change-Id: I42ec0059f7e311a232c38fef6a2e050a3e2c0ad3
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com >
Reviewed-on: https://review.coreboot.org/19734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
2017-05-22 18:12:16 +02:00
5196642870
soc/intel/skylake: Use Intel PCIe common code
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Change-Id: Ia9fa22c30fffb1907320667ac37f55db9f3cb7b3
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com >
Reviewed-on: https://review.coreboot.org/19666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
2017-05-22 18:12:05 +02:00
2d689f9e0d
soc/intel/common: Add Intel PCIe common code
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Add PCIe code support under soc/intel/common/block
to initialize PCIe controller, allocate resources
and configure L1 substate latency.
Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com >
Reviewed-on: https://review.coreboot.org/19665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
2017-05-22 18:11:56 +02:00
4bbfe57959
Kconfig: Move and clean up CONFIG_VGA
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Change-Id: I6e710b95cade0ea68f787f33c0070613d64b6da6
Signed-off-by: Nico Huber <nico.h@gmx.de >
Reviewed-on: https://review.coreboot.org/19743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2017-05-22 12:24:43 +02:00
afa9aefce0
include/console: Use IS_ENABLED() macro
...
Change-Id: I3d0c61c37399e96c1d154c1d3af5c47db967a07a
Signed-off-by: Nico Huber <nico.huber@secunet.com >
Reviewed-on: https://review.coreboot.org/19763
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
2017-05-22 11:07:57 +02:00
7b811d5e36
device/oprom/include: Use IS_ENABLED() macro
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Change-Id: Ibc3bf2f4f1e1bf1ffe9632aa150d549fcd6c201d
Signed-off-by: Nico Huber <nico.huber@secunet.com >
Reviewed-on: https://review.coreboot.org/19762
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
2017-05-22 11:07:43 +02:00
1b2d95feb3
arch/x86/include: Use IS_ENABLED() macro
...
Change-Id: I0f9a92e595ec765d47f89f0023ff69636ee406af
Signed-off-by: Nico Huber <nico.huber@secunet.com >
Reviewed-on: https://review.coreboot.org/19761
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
2017-05-22 11:07:31 +02:00
746aa054e2
drivers/intel/gma: Drop unused INTEL_DP
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Change-Id: I786848cd48c6fcfecf9b72c60623cadcfcbb7db7
Signed-off-by: Nico Huber <nico.h@gmx.de >
Reviewed-on: https://review.coreboot.org/19803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2017-05-22 10:26:11 +02:00
0df9a01009
nb/intel/haswell: Fix up C NGI remnants
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Change-Id: I3cd5e99b9954a68837de85b49b4389b668e00cf4
Signed-off-by: Nico Huber <nico.h@gmx.de >
Reviewed-on: https://review.coreboot.org/19802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2017-05-22 10:25:42 +02:00
10326ba889
mb/intel/wtm2: Drop unsupported native graphics init
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Since the conversion of this board to soc/broadwell in 0aa06cbf18nico.h@gmx.de >
Reviewed-on: https://review.coreboot.org/19801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2017-05-22 10:25:04 +02:00
bb72852baf
sb/via/k8t890: Clean up CONFIG_VGA usage
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Remove guards and let the linker take care of it.
Change-Id: I96ad8002845082816153ca5762543768998a5619
Signed-off-by: Nico Huber <nico.h@gmx.de >
Reviewed-on: https://review.coreboot.org/19744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2017-05-22 10:21:34 +02:00
27f0ca18bc
nb/intel/x4x: Use a struct for dll settings instead of an array
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This makes the code more readable since it avoids messing with two
dimensional arrays and needing remember what the indices mean.
Also introduces an unused coarse element which is 0 for all default
DLL settings on DDR2.
Change-Id: I28377d2d15d0e6a0d12545b837d6369e0dc26b92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/19767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2017-05-22 09:06:36 +02:00
93eac6a89d
mb/lenovo/*/romstage: Remove COM IO port
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All those boards do not have a serial port.
Don't attempt to decode the COMA/COMB IO range.
Change-Id: Ide7e818f87e70e3f559d0769ccde89c35da961d6
Signed-off-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-on: https://review.coreboot.org/19571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2017-05-21 16:39:30 +02:00
c670a41ca7
mb/lenvovo/*: Clean mainboard.c and devicetree
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* Move board specific SPI registers to devicetree
* Remove unused headers
* Remove obsolete methods
* Fix coding style
* Fix Thinkpad L520 SPI lvscc register
Except for Thinkpad L520, no functional change has been done,
just moving stuff around.
Change-Id: I692a5632030fe2fedbe9a90f86251000f1360fb2
Signed-off-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-on: https://review.coreboot.org/19494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2017-05-21 16:38:52 +02:00
