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96 Commits
4.21 ... master

Author SHA1 Message Date
Martin Roth
a4e1066ca7 util/kconfig: Update toada to halt on errors 
The tool 'toada' which converts the Kconfig output to ada syntax keeps
running even when it can't parse something. Change that behavior to
halt, and update the error message to show where the error is coming
from.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I29807a054581060d04b9ecbe02f2ba666c46bcf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-27 11:23:28 +00:00
Martin Roth
67448c33f1 util/kconfig: Allow toada to handle negative integers 
Any builds using ADA were getting a message saying:
`couldn't parse value '-1' for 'SEABIOS_DEBUG_LEVEL'`

This change allows toada to parse negative integers.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6507c54976b67f1ad70846b6bd6c54c861130d3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77421
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-27 11:22:13 +00:00
Martin Roth
ab46c18afd Docs/acronyms.md: Fix build warnings & update some links 
- Change all links to wikipedia to https.
- Update some links to wikipedia that were incomplete.
- Update a few links that are now broken.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If780e15997c499d1df975b436fd9af530f324eba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77488
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-27 11:15:33 +00:00
Felix Singer
7f50bcca93 doc/mainboard/index: Deduplicate menu points for T530 and W530 
Both mainboards have the same documentation. Instead of having two list
items referring to the same document, just merge the two items.

This fixes the following Sphinx warning:

  WARNING: duplicated entry found in toctree: mainboard/lenovo/w530

Change-Id: I4140b34db01b1d5f47a39b9c1e33405e7789de63
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77503
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-27 11:15:00 +00:00
Felix Singer
ead437f143 doc/mb/asus/{p2b-ls,p3b-f}: Remove reference to non-existing document 
The document for northbridge/intel/i440bx doesn't exist and it didn't
exist at the time of introduction of these two mainboard documents. So
replace the reference with just the northbridge name.

This fixes the following Sphinx warning:

  WARNING: unknown document: '../../northbridge/intel/i440bx/index'

Change-Id: Iaa67399f9d0e62d5d54ae08f5ebb8c70073c601f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
 2023-08-27 11:14:35 +00:00
Felix Singer
471de17fd5 doc,util: Regenerate documentation files 
Add new documentation generated by util/util_readme/util_readme.sh.

This also fixes the following Sphinx warning:

  util/abuild/index.md: WARNING: document isn't included in any toctree

Change-Id: I26c33af3c5a5853f6bcce23e982a6b192b01f1d7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
 2023-08-27 11:14:02 +00:00
Felix Singer
facdfe4622 doc/releases/4.22: Remove transitions from sections 
Sections may not start with transitions. Remove them.

This fixes the following Sphinx error:

  ERROR: Document or section may not begin with a transition.

Change-Id: I519af83df14e44b0709dee7e338dba1ee6413f0a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77440
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-27 11:13:51 +00:00
Elyes Haouas
139cb06b77 acpi/acpi.h: Use __packed over __attribute__((packed)) 
Change-Id: Iabbb637c797a361a2cbc55505002774ff4f774e1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77526
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-27 07:14:47 +00:00
Jeremy Soller
3d7a5bdf58 mb/system76: Enable DRIVERS_GENERIC_BAYHUB_LV2 to fix LTR issue 
Clevo started using OZ711LV2 for the SD card reader around the time of
making its TGL boards. Without the driver, CPUs don't go to power states
lower than C2 due to LTR not being programmed. After enabling the driver
the CPU will go to C8 while the system is idle, giving significant power
savings if the system is left on battery power.

There is another issue with RPL where it only goes to C6 instead of C8.
This may be due to the intel_idle driver in Linux (as of 6.5-rc6
mainline and 6.4.6 stable) not supporting RPL C-states.

- tgl: Started being used with the Gazelle 3060 variant
- adl: Used on all models
- rpl: bonw15 does not have an SD card reader

Change-Id: I85c60feb6dcae7d877e70a6c6f2d3a7b3296fa0e
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-26 22:26:59 +00:00
Martin Roth
8fc68816a9 soc/amd: Move psp_transfer.h out of each SOC into common 
The psp_transfer.h file was the same under all SoCs, and is really
tied to the file common/vboot/transfer.c, not the SOC.

This patch makes an include directory under vboot to put the header into
and sets it to be included for all SoCs using SOC_AMD_COMMON. This makes
the header file available to all platforms, so that new chips that don't
use the psp_verstage don't have to make a psp_transfer.h file just to
satisfy the compiler.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5b9f2adee3a1d4d8d32813ec0a850344b7d717b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77303
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-26 21:39:22 +00:00
Martin Roth
7687e7767f vc/amd/pi: Add SPDX headers to all files that don't have them 
License classifiers are much better about classifying files with SPDX
headers than they are at classifying the general text licenses due to
minor variations in the text. To help with classification, add the
SPDX headers to the files.

To see the current state of coreboot's licensing, see:
https://coreboot.org/fossology/

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If490f6705e7862d9ad02c925104113b355434101
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2023-08-26 21:38:58 +00:00
Michał Żygowski
d627f7b4f7 soc/intel/common/block/oc_wdt: Add OC watchdog common block 
Add new block for handling overclocking watchdog. The watchdog is
present since Skylake or maybe even earlier so it is safe to use with
most of the microarchitectures utilizing intelblocks.

The patch adds the common block for initializing and feeding the
watchdog. Timeout is defined statically in Kconfig and should be set
high enough by the board or SoC Kconfig to let the board boot with
full memory training and avoid reset loops. Full training of 128GB
DDR5 DIMM memory on AlderLake takes about 5 minutes. Newer SoCs
with newer memory technologies and higher RAM capacity may take more.
The default has been set to 10 minutes.

The patch also adds support for feeding watchdog in driverless mode,
i.e. it utilizies periodic SMI to reload the timeout value and restart
the watchdog timer. This is optional and selectable by Kconfig option
as well. If the option is not enabled, payload and/or software must
ensure to keep feeding the watchdog, otherwise the platform will
reset.

TEST=Enable watchdog on MSI PRO Z690-A and see the platform resets
after some time. Enable the watchdog in driverless mode and see the
platform no longer resets and periodic SMI keeps feeding the watchdog.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ib494aa0c7581351abca8b496fc5895b2c7cbc5bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68944
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-26 21:32:11 +00:00
Tyler Wang
ee15c2ead8 mb/google/rex/var/karis: memory: Add Micron MT62F512M32D2DR-031 
Add new memory part in the mem_parts_used.txt and generate the
SPD ID.

1. MICRON MT62F512M32D2DR-031 WT:B

BUG=b:291018417
TEST=emerge-rex coreboot

Change-Id: I6e05c0d41a4899ed64dbab7efd8904cd361cb50e
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77426
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-26 21:23:44 +00:00
Sheng-Liang Pan
a1459caa88 mb/google/dedede/var/taranza: Add Wifi SAR for taranza 
BUG=b:297276380
BRANCH=dedede
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot
chromeos-bootimage

Cq-Depend: chrome-internal:6373154

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: If21c7a7d329b0b1cc2c73dadb0c5b8a5b8ab27e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77399
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
 2023-08-26 21:22:05 +00:00
Tyler Wang
d97bd1574b mb/google/rex/var/karis: Remove WWAN module 
According to the schematic, karis does not have a WWAN module, remove
related settings.

BUG=b:294155897
TEST=emerge-rex coreboot

Change-Id: I653e3b4fae8a53018a6004528d1cfb3a6c883687
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77427
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-26 21:19:11 +00:00
Elyes Haouas
ce655f5bd5 vendorcode/intel/edk2: Use C99 flexible arrays 
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: If093dc08c70c521cbef96ac5b5a7a46b37169bcd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-26 21:17:24 +00:00
Subrata Banik
0c602b614d mb/google/rex/var/rex0: Use FW_CONFIG to select the correct SAR table 
This patch changes the SAR table selection logic to use FW_CONFIG which
will eventually help to support different WiFi SAR tables.

TEST=Able to build and boot google/rex.

Change-Id: I8f1244e3c3715bc3fbe6be1ade87817ff19836de
Signed-off-by: YH Lin <yueherngl@google.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77428
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-26 21:16:45 +00:00
Martin Roth
09202cce26 vc/intel: Remove unnecessary Kconfig options 
These Kconfig options were being used basically as #define statements,
which is unnecessary. This isn't a good use of Kconfig options and would
be better just as #defines if actually needed.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If987b50d8ec3bb2ab99096e5e3c325e4d90a67a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2023-08-26 21:14:45 +00:00
Martin Roth
8b703954c3 vc/siemens: Only add the include path for hwlib when needed 
This patch moves the line adding hwlib to the include path to the inner
makefile so that it doesn't get added to every build, but only when
CONFIG_USE_SIEMENS_HWILIB=y

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id668b76366a554efff560cec746e637487ebdbf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77417
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-26 21:13:50 +00:00
Martin Roth
81da643c13 vc/amd: Only pull in Makefiles & dirs that are needed 
This keeps the vc/amd/pi & pi/00670F00 Makefiles from getting pulled
into the build when they aren't needed.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If600c78c2ba74dd03cf493586dae037b96b7d623
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-26 21:13:20 +00:00
Martin Roth
c12b290c5d vc/eltan: Only pull in vc/eltan/security Makefile when enabled 
This change tells the build to only pull vc/eltan/security/Makefile.inc
into the overall build when USE_VENDORCODE_ELTAN is enabled in Kconfig.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1e462d8cc21c44716463c41cab598588cf4a22c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77418
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-26 21:12:17 +00:00
Wisley Chen
8e42ebeea2 mb/google/nissa/var/yaviks: Disable SUSCLK based on fw_config 
Disable SUSCLK for MT7922 based on FW_CONFIG to avoid power leakage.

BUG=b:296511904, b:294456574
BRANCH=firmware-nissa-15217.B
TEST=build and verified by EE

Change-Id: I9a6bf0ab7cc77f95e0d64f1380eac9e022fc08e4
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77383
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-26 21:11:00 +00:00
Felix Singer
b792f6a2b9 configs: Remove configs for unsupported boards 
Scaleway Tagada was removed with commit c013fa6234 and Intel Galileo was
removed with commit 037c25d4dd. So remove their configs.

Change-Id: I1c491f437b8a1104bdf31a34e3c7d2c4e5794301
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77415
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-26 21:09:14 +00:00
Cliff Huang
5790a05237 soc/intel/meteorlake: Add PMC GPIO GPE group mapping 
Add two missing mapping for GPIO GPE routes

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I3f0d13cf7c07201856e934f22efc4cc8c4ea5bf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77423
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-26 21:08:46 +00:00
Arthur Heymans
668b8ccad3 libpayload: Skip unknown arguments to clang 
This compiler argument only exists on gcc.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I10902517c86daedc9853e6f6cac8fcf513211bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77436
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-26 21:06:30 +00:00
Arthur Heymans
536ea50c53 libpayload: Remove unnecessary brackets 
This fixes compilation with clang.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I675056c8a15fe446bba81a144bfea64d106df293
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77435
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-26 21:05:54 +00:00
Arthur Heymans
ae57f1d2dc libpayload: Fix untyped function arguments 
This is necessary with clang.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Icc197fbd48b49bfa8770caf01727669b0ac59090
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2023-08-26 21:01:43 +00:00
Simon Glass
aacf35cca3 docs: Tidy up the English in the testing tutorial 
Tweak a few sentences noticed when reading this.

BUG=none
BRANCH=none
TEST=none

Change-Id: I0a072c83402bc551a6bbdb7cd7c55fc3505784b2
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77464
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: Patrick Georgi <patrick@coreboot.org>
 2023-08-26 20:57:37 +00:00
Simon Glass
d7c88c2308 docs: Mention add_intermediate and provide an example 
This is a useful feature, so add a note about it.

Change-Id: If29f6480f878bdaf877dc208cc4861b884e10840
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77465
Tested-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
 2023-08-26 20:57:11 +00:00
Simon Glass
f40f4a6e23 payloads/U-Boot: Use github mirror and latest version 
Update the U-Boot version to the latest release. Also switch to github
since it is typically much faster to download than the existing URL.

Drop the 'experimental' tag since this payload is pretty stable. It is
also tested regularly in U-Boot's CI.

Change-Id: I082130539c3474593a82e4b21cb995380f4db168
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77149
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77463
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2023-08-26 20:56:10 +00:00
Nico Huber
b2893e22e6 memrange: Honor limit in the last step of top-down stealing 
We only checked that the resource fits below the given `limit` in
memranges_find_entry(), but then accidentally placed it at the top
of the found memrange. As most resources have only a coarse limit,
e.g. the 4G barrier of 32-bit space, this became only visible when
artificially setting an unusual, lower limit on a resource.

So, for the final placement, use `MIN(limit, range end)` instead
of the range's end alone.

Change-Id: I3cc62ac3d427683c00ba0ac9f991fca62e99ce44
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
 2023-08-26 20:29:37 +00:00
David Wu
8a58483072 mb/google/brask/var/kuldax: Set customized_leds value for RTL8111K 
Set customized_leds value for RTL8111K to fix led can't work.

BUG=b:297093096
BRANCH=firmware-brya-14505.B
TEST=Verified RTL8125 and RTL8111K led can work normally.

Change-Id: Icb8624005e7e24398abdd242570970c6bfa8a09f
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77390
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-25 14:41:30 +00:00
Chen-Tsung Hsieh
c61be60b97 mb/google/brya: Create nokris variant 
Create the nokris variant of the nissa reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:285838647
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_NOKRIS

Change-Id: If7cb00ce978236746dfe4d097d1f20aeebb96a35
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
 2023-08-25 14:41:06 +00:00
Krishna Prasad Bhat
93be5d5d07 util/cbfstool: Add eventlog support for PSR data backup status 
In order to support logging of events for PSR data backup command
status during CSE firmware downgrade, add support for
ELOG_TYPE_PSR_DATA_BACKUP and ELOG_TYPE_PSR_DATA_LOST types.

BRANCH=None
BUG=b:273207144
TEST=Verify event shows in eventlog after CSE firmware downgrade

Change-Id: Ibb78ac8d420bb7a64328ce009ddcb99030519ec6
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77005
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
 2023-08-25 14:40:40 +00:00
Krishna Prasad Bhat
055b874658 commonlib: Add PSR backup eventlog types 
Add new eventlog types to support logging of Platform Service Record
(PSR) backup related messages. Eventlog entries are added on PSR data
backup success/failure and also when PSR data is lost.

BRANCH=None
BUG=b:273207144
TEST=Verify elog event added after PSR data backup command is sent
cse_lite: PSR_HECI_FW_DOWNGRADE_BACKUP command sent
...
ELOG: Event(B9) added with size 10 at 2023-07-27 06:44:49 UTC

Change-Id: I01ce3f7ea24ff0fdbb7a202ec3c75973b59d4c14
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77004
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-25 14:39:45 +00:00
Jakub Czapiga
1e3138fe0b mb/google/rex/var/ovis: Update PWM_BUZZER GPIO config 
BUG=b:271491845
TEST=Build and boot google/ovis on Rex P1 with buzzer added on GPP_B08

Change-Id: I44718ea15c93a075b6468f335a869a2cfa585273
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76049
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2023-08-25 14:38:48 +00:00
Sean Rhodes
6319ef9718 soc/intel/apollolake: Correct the logic for the legacy 8254 timer 
The `use_8254` should be flipped, the same as the other Intel
SOCs.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2d6c859c0910b796d2ae5874a560ff9974578106
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
 2023-08-25 14:38:31 +00:00
Mark Hsieh
2cd2263c32 mb/google/nissa/var/joxer: set the DB_USB field in FW_CONFIG 
Joxer will have SKUs with no type-c on daughter board, add fw_config
for EC control it.

BUG=b:297131468
TEST=USE="project_joxer emerge-nissa coreboot"

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie8098f72e29a10ebbaf3ba3b09d6a002d09fd35a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77394
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-25 14:37:45 +00:00
Nicholas Chin
80bd3ac5fe MAINTAINERS: Add Nicholas Chin for coreDOOM payload integration 
Change-Id: Idd3acd204c0809753b6f5534790e1dc81c10b761
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71859
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-25 13:28:18 +00:00
Anand Vaikar
2c3cded4bc mb/amd/birman: Enable two USB4 xHCI controller devices 
TEST: Boot to ubuntu OS and verify that USB4 devices are listed in lspci command
00:08.3/06:00.3 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c0
00:08.3/06:00.4 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c1

Change-Id: I6253a7694702179454bc1ca14825fd4f3b949c13
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
 2023-08-25 12:46:42 +00:00
Patrick Rudolph
354a2456ac payloads/external/LinuxBoot: Fix boot 
Fix regression introduced in I25e757108e0dd473969fe5a192ad0733f1fe6286
"payloads/external/LinuxBoot: Clean up".

Include the initrd into the payload. Allows to actually use LinuxBoot.

Change-Id: I5ab6b1a43a4100e83f4c188b9ea3451ab7b4ffe5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77412
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-25 12:27:09 +00:00
Felix Held
4ff1d63fc4 soc/amd/common/include/root_complex: add IOHC MISC SMN base addresses 
The Genoa server SoC has 4 IOHC PCI roots instead of the 1 the mobile
SoCs have, so add the additional 3 SMN base address definitions.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I72dba39bff7c7a739e1dfddd80e7f22e65b5f139
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77395
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-25 12:24:01 +00:00
Felix Singer
53a43f14da drivers/intel/fsp2/Makefile.inc: Deduplicate compression type checks 
When LZMA compression is selected, then it's not needed to check if LZ4
compression is selected in addition. So instead of handling both cases
separately, check for LZ4 only if LZMA is not selected.

This applies to the cases of both, FSP-M and FSP-S.

Change-Id: I4ea61a38baf4c29bf522a50a26c6b47292e67960
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77323
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-25 10:03:20 +00:00
Tyler Wang
fa17a9d03c mb/google/rex/var/karis: Add SOC_TCHSCR_INT settings to gpio table 
Karis use I2C touchscreen only, add SOC_TCHSCR_INT(GPP_C07) to ramstage
gpio table.

BUG=b:294155897
TEST=emerge-rex coreboot

Change-Id: Ie715cfbe1984dbe38cd933312304b42ce9088806
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2023-08-25 03:23:46 +00:00
Kapil Porwal
33a5722bd7 mb/google/rex/var/karis: Fix incorrect GPIO pad numbers 
Fix incorrect GPIO pad numbers. GPP_F19 was mistakenly used instead of
GPP_F14, GPP_F15 and GPP_F16 GPIOs.

BUG=none
TEST=none

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I219b78a5e92d9c56799964ea88615c27aed2e92e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77401
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-25 03:23:19 +00:00
Nico Huber
bfdefc2f9a Makefile: Fix typo in make help output 
Change-Id: I124e7d68198050616795a67df23b6481f6fe1276
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77407
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 22:19:07 +00:00
Nico Huber
4f014835e1 docs: Redirect top-level make targets to Documentation/ 
To avoid redundancy about how to call into `Makefile.sphinx`,
only do that from the `Documentation/Makefile` and call into
that from the top level.

Change-Id: I99c462cdaf83d711e4b7c07b713d304274db8cb4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77406
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
 2023-08-24 22:18:52 +00:00
Arthur Heymans
1312ef49b3 Kconfig: Add option to make clang the default compiler 
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ie910f654abdb8d79c686363d2bd8af4ceeea4087
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76436
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 22:08:59 +00:00
Riku Viitanen
1f9eadabbb docs/mb: update hp/compaq_elite_8300_usdt docs 
- Internal flashing possible
- Fix link
- Link here from the list of mainboards
- More consistent naming

Change-Id: Iaf6448c1e9f0dae9480fa9785a12f09d42f8cf7d
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77377
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 22:07:33 +00:00
Riku Viitanen
f442eadcad mb/hp/compaq_elite_8300_usdt: enable mSATA 
Tested with a Kingston UV500.
It works the same (3Gb/s) as with vendor FW.

According to smartctl -a /dev/sda:
SATA Version is:  SATA 3.1, 6.0 Gb/s (current: 3.0 Gb/s)

Change-Id: I5c714351586e6084029ce4c54fb47cbae4d3405b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77376
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-24 22:07:14 +00:00
Johannes Hahn
6117a2d296 mb/siemens/fa_ehl: Remove RTC RV3028C7 
Delete this RTC from the configuration as fa_ehl mainboard
uses a different real time clock.

Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Change-Id: Ifd6b68d05a094cb4c890f1ffce62d89b771e23c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
 2023-08-24 14:03:05 +00:00
Johannes Hahn
7f99551d5c mb/siemens/fa_ehl: Remove TPM 
The mainboard currently does not make use of a dedicated TPM.
Although it has one assembled. This TPM is not connected
via LPC hence it is turned off in the devicetree.

Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Change-Id: I96cc38c3812d76d654339ad5b2b7f88fd1327779
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77351
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
 2023-08-24 14:02:45 +00:00
Johannes Hahn
a9d8531c8c mb/siemens/fa_ehl: Remove NC_FPGA 
fa_ehl mainboard does not make use of the SIEMENS NC_FPGA
as it is not placed on this board.

Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Change-Id: I5f1f796e4339ba37d461d6818c2bb6ba028b89c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
 2023-08-24 14:02:24 +00:00
Martin Roth
b18726da2f Makefile: Update build for include-what-you-use 
This patch saves the output of the IWYU build into $(obj)/iwyu.txt. It
will also automatically adds -k to the MAKEFLAFGS when IWYU is selected,
so that the build doesn't halt after the first operation.

When IWYU is not selected, there is no change to the build.

This will allow us to create an automated IWYU build on jenkins.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0ea300d4c64bb923e9f7cc0e595885c3006ec3ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77192
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2023-08-24 13:58:51 +00:00
Stanley Wu
00e92f4538 mb/google/dedede/var/boxy: Enable 100M mode blink in RTL8111H LAN LED config 
Enable bit 9 for 100M mode green LED blink.

Reference: 
- RTL8111H-CG Datasheet 1.92 section 7.2 for customizable led configuration

BUG=b:293983804
TEST=emerge-dedede coreboot and verify LAN LED behavior

Change-Id: Ice5686affcc014a2dfd35b7f579c8eaa38c2d3fe
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
 2023-08-24 13:39:49 +00:00
Wisley Chen
d6c2e054f8 mb/google/nissa/var/yaviks: rename DB_NONE to DB_1A 
Yaviks doesn't have none DB sku, and rename to DB_1A for yahiko.

BUG=b:294928078, b:294456574
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: Icb952c0716d446d5feb5580f357120a27193284e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77384
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 13:37:20 +00:00
Thomas Heijligen
303a895d77 libpayload: Outsource delay function into own header 
For libflashrom we need the delay functions but when including the whole
libpayload.h it has conflicting symbols.

Change-Id: I6e4a669b8ba25836fb870d74c200985c1bfdb387
Signed-off-by: Thomas Heijligen <src@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2023-08-24 13:35:02 +00:00
Cliff Huang
711f84d177 soc/intel/metorlake: Fix PMC GPIO group assignment 
Those values need to match with the ones defined in PMC PWRM
GPIO CFG register.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I8e84df83caab794e2fe7186e89e78343c2b55fd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 13:33:50 +00:00
Johannes Hahn
377153d58d mainboard/siemens/fa_ehl: Add new mainboard based on mc_ehl2 
Add a new mainboard called fa_ehl which is based on Siemens's
'mc_ehl2'. This commit simply copies the mainboard directory and
adjusts the naming to match the new board's name. Moreover a variants
scheme is provided for possible alternative implementations. Follow-up
commits will introduce the needed changes for the new mainboard.

Change-Id: Ia389c8812d14db8b663547e6336e900becbc8be6
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76444
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
 2023-08-24 13:31:17 +00:00
Arthur Heymans
736d4d25df acpi: Add function to add ARM PL011 to ACPI DBG2 
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I3c3f7f579ec0ec4fdb72e1f6b785026daab17bac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76297
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 13:20:06 +00:00
Michał Żygowski
06cb997b0a soc/intel/apollolake: Move the PMC definitions to pmc.h file 
Add a pmc.h file, which is needed for OC watchdog compilation. The PMC
definitions from pm.h are moved to pmc.h.

TEST=Build UP Squared and Intel GLKRVP sucessfully.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I2726aaae1ce60d15a3944dadcf793def2dcb3a1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2023-08-24 12:59:48 +00:00
Subrata Banik
58a309a8f3 MAINTAINERS: Add Subrata and Nick for google/brya and hatch mbs 
Change-Id: I8308ac1d2f3c9a34b55c788797bccd4e7fcefd5c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77348
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
 2023-08-24 12:56:24 +00:00
Yidi Lin
eb6642d8e4 soc/mediatek/mt8188: Remove GPT timer init 
GPT timer init is no longer needed after DRAM blob is switching to ARM
arch timer.

BUG=b:229800119
TEST=boot to kernel

Change-Id: Iec1f93c96e791220feed4225959ef15c074ba577
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77388
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 12:55:41 +00:00
Yu-Ping Wu
c740c65fb9 Update vboot submodule to upstream main 
Updating from commit id 0c11187c:
2023-08-07 11:41:45 +0000 - (vboot_reference: Rename Cr50 to GSC when applicable)

to commit id 24cb127a:
2023-08-22 00:19:10 +0000 - (sign_uefi_unittest.py: Fix long-line lint)

This brings in 24 new commits:
24cb127a sign_uefi_unittest.py: Fix long-line lint
52ac0c71 dump_fmap: Rename format name from 'pretty' to 'parser'
068376d9 dump_fmap: Add description about formats
f67ae949 crossystem: stop supporting legacy chromeos_acpi driver
e6bd72f7 Revert "futility/cmd_vpd: Add vpd listing subcommand"
c7593acc futility: updater: fix build warning 'incompatible function pointer'
394fbfad crossystem: Binary search RW_NVRAM to find the active entry
a5b80353 keygeneration: drop ec_{data,root}_key
1c9b603d futility: updater: Refactor manifest generation
0a4be4a0 futility: updater: Use signer_config for all boards by default
f9d1f0b0 futility: Fix closing file in error path
4dbadfb3 vboot_reference: Remove VB2_RECOVERY_CR50_BOOT_MODE
11bdc1f5 futility: updater: Enable keyset in signer_config based manifest
35e69bcd futility: Change FLMSTR values set by --unlock_me
0ca8212b futility: updater: Use signer_config manifest instead of setvars
0e24a8ef scripts: use new fw updater pack/repack commands
4378179b futility/cmd_vpd: Add vpd listing subcommand
2fc252d8 futility: updater: Remove deprecated Glados platform quirks
3119182d x86/crossystem: Fix snprintf error for hostlib
06a0b9d0 sign_uefi: Remove exception catching
bcfd831e sign_uefi: Clarify comment for removing signatures
4cb7b0e5 crossystem: support new chromeos_acpi driver
eb37f19d vboot: remove trailing newline from sysfs
ec173ee4 vboot: rename ReadFileString() to ReadFileFirstLine()

Change-Id: I6c92791404dc1c6a3efc8bb9046fe5017ba794fb
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
 2023-08-24 12:55:11 +00:00
Won Chung
d597320d8e mb/google/brya/var/vell: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I62103563ec49769cd842fedf8c2c55118c55aa14
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:54:19 +00:00
Won Chung
4eaa0a929f mb/google/brya/var/taniks: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I12fa83987869b9a52940a49e9f7897d62abf59ff
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:54:02 +00:00
Won Chung
020d43e553 mb/google/brya/var/taeko: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I07e85f28c4f260d04317ec594e162db20f3d4ddd
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:53:50 +00:00
Won Chung
7f5c6d21c6 mb/google/brya/var/volmar: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Ie7982d1001c4a65322b4e6fdbd70b20c8eee6f0e
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:53:24 +00:00
Won Chung
d64da18c4a mb/google/brya/var/primus: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I78eee4c5f11b06fbc104182a4313c20be91b821b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76905
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 12:53:08 +00:00
Won Chung
f860d5aba0 mb/google/brya/var/osiris: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I6157894b96da2e9faed229a1f18c0c0b7c60897b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:52:57 +00:00
Won Chung
fb69c56971 mb/google/brya/var/omnigul: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Ie0304ea4343361ff0395c7204ebb76bffb5a6d97
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:52:33 +00:00
Won Chung
939d07ea35 mb/google/brya/var/mithrax: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Icdb8e9a20ab536f80fa7358472cca01996faf447
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:52:14 +00:00
Tyler Wang
34ce8c7377 mb/google/rex/var/karis: Disable GSPI0 
According to the schematic, karis does not have a SPI touchscreen,
remove related settings.

BUG=b:294155897
TEST=emerge-rex coreboot

Change-Id: I55eb9e3cebe426fcd023789831ce64a18d075d69
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2023-08-24 12:52:08 +00:00
Won Chung
d68bb7c84f mb/google/brya/var/marasov: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Ie2c089c0418f76ac7c8ce2e531dbbc91c66f34a0
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76901
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 12:51:52 +00:00
Won Chung
af1782cdcb mb/google/brya/var/kano: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I15888b4e5bd46c98e0864eaa6850e1a24b22fe65
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76900
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 12:51:38 +00:00
Won Chung
1c8f5c7f1b mb/google/brya/var/gimble: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Ief27cd6e32780683c53a88d73194c6d82c6c212b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:51:25 +00:00
Won Chung
7e00d51c39 mb/google/brya/var/felwinter: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I7be4a47ea2a8cb2b6f4a2d633252eec523807da6
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:50:55 +00:00
Won Chung
7fcdb9f902 mb/google/brya/var/crota: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Ic5343de88f5f089c9ec4a992f5a6383c08641568
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76897
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 12:50:40 +00:00
Won Chung
767ff9127b mb/google/brya/var/banshee: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Iced1061bab224d918fd5f0525423ac6858e1799b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:50:21 +00:00
Martin Roth
59d5092454 soc/nvidia: Fix incorrect SPDX license 
The SPDX license header for this file did not match the license text
in the file.

Update the SPDX header and remove the license text.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ifc0db79e43df6d14b80b0ad3061fe42de17ed90f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77379
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-24 05:30:10 +00:00
Martin Roth
d571a2f8a1 docs: Update with acronyms found in 4.20-4.21 commit messages 
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I19a69ffdf2c248223569153c00fbc76d5ceb7921
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-24 05:28:22 +00:00
Michael Strosche
8900323c4f soc/intel/jasperlake: Use boolean type where applicable 
Change-Id: If3c2e5bd9ee7e0f77d0c39ffe2ca9ad17b77d9bd
Signed-off-by: Michael Strosche <michael.strosche@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-24 05:15:18 +00:00
Anand Vaikar
1855cb4644 mb/amd/mayan: Enable the DT and M.2 SSD1 PCIE slots 
Program the EC GPIOs to enable the DT or M.2 SSD1
PCIe slots based on the config option selected.


Change-Id: Id141e5e55ef6e25722b411975a59c9764b86f624
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
 2023-08-23 16:09:00 +00:00
Naresh Solanki
40c740584b soc/intel/xeon/spr: Improve RMT configuration 
Set EnforceDdrMemoryFreqPor to 0 for RMT builds. This is needed
for proper functioning when EnforcePopulationPor is set to 1.

Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: Icf4fe01ac9b546830334717dbfa53782d2a85ba1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-08-23 12:14:09 +00:00
Sen Chu
8cc8b3c14b soc/mediatek/mt8188: Simplify pmif init flow 
Based on "MediaTek_EFUSE_MT8188_Confidential A_Technical Doc.docx",
MT8188G used in ChromeOS project does not support clock hardware
monitor. Thus, we can simplify the initialization flow by removing the
hardware default value check.

BUG=b:292866009
TEST=emerge-geralt coreboot
BRANCH=none

Change-Id: I07cd753f153da5b0aea1518a04a818214f986aeb
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77334
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2023-08-23 12:12:54 +00:00
Martin Roth
52354ea463 util/release: Update build-release script to pause for the PGP key 
When the script is run, it fetches a new copy of the repo, then creates
a tag, signed by GPG. When this signing step runs, a window pops up for
the user to enter their PGP key's passphrase. This window prevents the
user from doing anything else on their desktop, like looking up the
passphrase.  It also times out after a while, and causes the script to
fail at that point.

To prevent this annoyance, pause right before the step asking for the
passphrase until the user is ready.

Because the submodules aren't tagged, we can delay their update until
after the tag is created to lower the amount of time needed before the
tag & signing step.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I414dfc0f8944b4408881392278a2bce2a364992b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77366
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-23 12:11:47 +00:00
Martin Roth
11bd917ca4 util/release: Upload script to abandon patches older than 1 year 
This script allows any user with abandon rights to abandon patches that
haven't been touched (reviewed, commented on, rebased, etc) in over a
year.

As a part of the release process, we're now going to run the script to
abandon all of those patches so that we don't get to the point of
needing to abandon 1300 patches again in the future.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4a07c09edf02d9c1858a58322095eefbceb529d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-23 12:09:08 +00:00
Robert Chen
02295db726 mb/google/brya: Create quandiso variant 
Create the quandiso variant of the nissa reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)

BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_QUANDISO

Change-Id: I846c39260e2db504d7bec6e81a8317b6824c17f4
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-08-23 12:08:34 +00:00
Tyler Wang
b951bdc156 mb/google/rex/var/karis: Remove WWAN temperature sensor 
According to the schematic, karis does not have a WWAN temperature
sensor, remove related settings.

BUG=b:294155897
TEST=emerge-rex coreboot

Change-Id: Ic82c6cfec067faa37d452bed5c4977402a2139a5
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77284
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-08-23 07:38:05 +00:00
Daniel_Peng
3eed673659 mb/google/dedede/var/pirika: Add USB2 PHY parameters for Type-A/Type-C 
This change are added fine-tuned USB2 PHY parameters to improve the
USB2 eye diagram result.

BUG=b:296493887
BRANCH=firmware-dedede-13606.B
TEST=Local build bios successfully.
     And verified the USB2 eye diagram test result.

Change-Id: I915fe689883267901e8faba28632345d8c227c28
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77359
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-23 07:36:35 +00:00
Paul Menzel
16a01d9f34 Update intel-microcode submodule to tag microcode-20230808 
Updating from commit id 6f36ebd:
2023-06-13 16:09:19 -0600 - (microcode-20230613 Release)

to commit id 6788bb0:
2023-08-08 12:04:21 -0600 - (microcode-20230808 Release)

This brings in 1 new commits:
6788bb0 microcode-20230808 Release

https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20230808

Change-Id: I2885b0189c4b6e68dc5ae6b2a3f809280ed4507a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77132
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-23 06:27:41 +00:00
Subrata Banik
1ecba25d12 MAINTAINERS: Update Tarun Tuli’s email id for MTL and google/rex mbs 
Change-Id: I05c84cae5a050cc69f4d9eecaa0f82caacc85c2d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77345
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-23 04:15:35 +00:00
Morris Hsu
b6392ef4d7 mb/google/brask/var/constitution: Separate wifi sar table 
Separate constitution and intrepid wifi sar table in variant.c

BUG=b:291859402
BRANCH=firmware-brya-14505.B
TEST=emerge-constitution coreboot chromeos-bootimage

Change-Id: I0f89b3d5f5252a2b55bad4d91ad4ab9ec7519c50
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77242
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-23 04:13:36 +00:00
Felix Held
048c2f2ac0 Documentation/acpi: add Windows-specific documentation 
When using the Windows fast startup mechanism which is enabled by
default, Windows will use a cached version of the ACPI tables during
normal boots after a clean shutdown. Since I've run into this issue and
spent quite a bit of time debugging the wrong issue due to this, better
document this possibly unexpected behavior.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia9e65f6a3aff13fa54abe68c8f5fcbf9bc6efc1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
 2023-08-22 18:19:07 +00:00
Nick Vaccaro
eb08ae4ce1 mb/google/brya/var/bb/brask: enable HDMI gpios early 
Add some HDMI-related gpios that are needed for early sign-of-life
to the early_graphics_gpio_table array so that SOL will show up on
HDMI ports.

BUG=b:277861633
BRANCH=firmware-brya-14505.B
TEST=`emerge-brya coreboot chromeos-bootimage` and verify it builds
without error.

Change-Id: Ic36a636e68c2d457f40329a2e9c69dab5bbba41f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77353
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-22 16:11:06 +00:00
Yu-Ping Wu
fae1eb3e66 soc/qualcomm: Add missing newlines for logs 
Change-Id: Ifd2e0043122946211aceb5ff88db0314de720fb9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77336
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-08-22 02:28:57 +00:00
215 changed files with 2461 additions and 873 deletions
Expand all files Collapse all files

2
3rdparty/intel-microcode vendored

Submodule 3rdparty/intel-microcode updated: 6f36ebde45...6788bb07eb

2
3rdparty/vboot vendored

Submodule 3rdparty/vboot updated: 0c11187c75...24cb127a5e

3
Documentation/acpi/index.md
View File

@@ -11,6 +11,9 @@ upwards.
- [GPIO toggling in ACPI AML](gpio.md)
## Windows-specific ACPI documentation
- [Windows-specific documentation](windows.md)
## ACPI specification - Useful links

9
Documentation/acpi/windows.md Normal file
View File

@@ -0,0 +1,9 @@
# Testing ACPI changes under Windows
When testing ACPI changes in coreboot against Windows 8 or newer, beware that
during a normal boot after a clean shutdown, Windows will use the fast startup
mechanism which results in it not evaluating the changed ACPI code but instead
using some cached version which won't include the changes that were supposed to
be tested. In order for Windows to actually use the new ACPI tables, either
disable the fast startup or just tell Windows to do a reboot which will make it
read and use the ACPI tables in memory instead of an outdated cached version.

105
Documentation/acronyms.md
View File

@@ -1,7 +1,5 @@
# Firmware and Computer Acronyms, Initialisms and Definitions
** Note that this document even more of a work in progress than most **
** of the coreboot documentation **
## _0-9
@@ -20,24 +18,25 @@ Spec](https://uefi.org/specifications) for details, or run the tool
initialization that happens from the PSP. Significantly, Memory
Initialization.
* AC - Electricity: [**Alternating Current**](https://en.wikipedia.org/wiki/Alternating_current)
* Ack - Acknowledgment
* Ack - Acknowledgment / Acknowledged
* ACM – [**Authenticated Code Module**](https://doc.coreboot.org/security/intel/acm.html)
* ACP - [**Average CPU power**](https://en.wikipedia.org/wiki/Thermal_design_power)
* ACPI - The [**Advanced Configuration and Power
Interface**](http://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_Interface)
is an industry standard for letting the OS control power management.
* [http://www.acpi.info/](http://www.acpi.info/)
* [https://uefi.org/specifications](https://uefi.org/specifications)
* [http://kernelslacker.livejournal.com/88243.html](http://kernelslacker.livejournal.com/88243.html)
* ADC - [**Analog-to-Digital Converter**](https://en.wikipedia.org/wiki/Analog-to-digital_converter)
* ADL - Intel: [**Alder Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/alder_lake)
* AES - [**Advanced Encryption Standard**](https://en.wikipedia.org/wiki/Advanced_Encryption_Standard)
* AESKL - Intel: AES Key Locker
* AGESA - [**AMD Generic Encapsulated Software Architecture**](https://en.wikipedia.org/wiki/AGESA_)
* AGP - The [**Accelerated Graphics
Port**](http://en.wikipedia.org/wiki/Accelerated_Graphics_Port) is an
Port**](https://en.wikipedia.org/wiki/Accelerated_Graphics_Port) is an
older (1997-2004) point-to-point bus for video cards to communicate
with the processor.
* AHCI - The [**Advanced Host Controller
Interface**](http://en.wikipedia.org/wiki/Advanced_Host_Controller_Interface)
Interface**](https://en.wikipedia.org/wiki/Advanced_Host_Controller_Interface)
is a standard register set for communicating with a SATA controller.
* [http://www.intel.com/technology/serialata/ahci.htm](http://www.intel.com/technology/serialata/ahci.htm)
* [http://download.intel.com/technology/serialata/pdf/rev1_3.pdf](http://download.intel.com/technology/serialata/pdf/rev1_3.pdf)
@@ -51,10 +50,11 @@ Spec](https://uefi.org/specifications) for details, or run the tool
An open standard to connect and manage functional blocks in an SoC
(System on a Chip)
* AMD64 - Another name for [**x86-64**](https://en.wikipedia.org/wiki/X86-64)
* AMD-Vi AMD: The AMD name for their IOMMU implementation
* AMPL - AMD: [**Advanced Platform Management Link**](https://web.archive.org/web/20220509053546/https://developer.amd.com/wordpress/media/2012/10/419181.pdf) - Also referred to as
SBI: Sideband Interface
* AMT - Intel: [**Active Management Technology**](https://en.wikipedia.org/wiki/Intel_Active_Management_Technology)
* ANSI - [**American National Standards Institute**](American_National_Standards_Institute)
* ANSI - [**American National Standards Institute**](https://en.wikipedia.org/wiki/American_National_Standards_Institute)
* AOAC - AMD: Always On, Always Connected
* AP - Application processor - The main processor on the board (as
opposed to the embedded controller or other processors that may be on
@@ -63,7 +63,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* APCB - AMD: AMD PSP Customization Block
* API - [**Application Programming Interface**](https://en.wikipedia.org/wiki/API)
* APIC - [**Advanced Programmable Interrupt
Controller**](http://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt_Controller)
Controller**](https://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt_Controller)
this is an advanced version of a PIC that can handle interrupts from
and for multiple CPUs. Modern systems usually have several APICs:
Local APICs (LAPIC) are CPU-bound, IO-APICs are bridge-bound.
@@ -98,7 +98,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
## B
* BAR - [**Base Address Register**](http://en.wikipedia.org/wiki/Base_Address_Register) This generally refers to one of the
* BAR - [**Base Address Register**](https://en.wikipedia.org/wiki/Base_Address_Register) This generally refers to one of the
base address registers in the PCI config space of a PCI device
* Baud - [**Baud**](https://en.wikipedia.org/wiki/Baud) - Not an acronym - Symbol rate unit of symbols per second, named
after Émile Baudot
@@ -117,7 +117,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
the entire 4GiB of the 32-bit address space. Also known as flat mode
or [**Unreal mode**](https://en.wikipedia.org/wiki/Unreal_mode).
* BIOS - [**Basic Input/Output
System**](http://en.wikipedia.org/wiki/BIOS)
System**](https://en.wikipedia.org/wiki/BIOS)
* BIST - The [**Built-in Self Test**](https://en.wikipedia.org/wiki/Built-in_self-test) is a test run by the processor on
itself when it is first started. Usually, any nonzero value indicates
that the selftest failed.
@@ -183,7 +183,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
generally used to describe a section of NVRAM (Non-volatile RAM), in
this case a section battery-backed memory in the RTC (Real Time Clock)
that is typically used to store BIOS settings.
*[http://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory](http://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory)
*[https://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory](https://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory)
* CNL - Intel: [**Cannon Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/cannon_lake) (formerly Skymont)
* CNVi - Intel: [**Connectivity Integration**](https://en.wikipedia.org/wiki/CNVi)
* CPL - x86: Current Privilege Level - Privilege levels range from 0-3; lower numbers are more privileged.
@@ -191,14 +191,14 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* CPPC - AMD: Collaborative Processor Performance Controls
* CPS - Characters Per Second
* CPU - [**Central Processing
Unit**](http://en.wikipedia.org/wiki/Central_processing_unit)
Unit**](https://en.wikipedia.org/wiki/Central_processing_unit)
* CPUID - x86: [**CPU Identification**](https://en.wikipedia.org/wiki/CPUID) opcode
* Cr50 - Google: The first generation Google Security Chip (GSC) used on
ChromeOS devices.
* CRB - Customer Reference Board
* CRLF - Carriage Return, Line Feed - \\r\\n - The standard window EOL
(End-of-Line) marker.
* crt0 - [**C Run Time 0**](http://en.wikipedia.org/wiki/Crt0)
* crt0 - [**C Run Time 0**](https://en.wikipedia.org/wiki/Crt0)
* crt0s - crt0 Source code
* CRT - [**Cathode Ray Tube**](https://en.wikipedia.org/wiki/Cathode-ray_tube)
* CSE - Intel: Converged Security Engine
@@ -207,6 +207,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* CSME - Intel: Converged Security and Management Engine
* CTLE - Intel: Continuous Time Linear Equalization
* CVE - [**Common Vulnerabilities and Exposures**](https://en.wikipedia.org/wiki/Common_Vulnerabilities_and_Exposures)
* CXMT - ChangXin Memory Technologies
* CZN - AMD: [**Cezanne**](https://en.wikichip.org/wiki/amd/cores/cezanne) - CPU Family 19h, Model 50h
@@ -225,8 +226,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
still has power.
* D3 Cold - ACPI Device power state: Power is completely removed from
the device.
* DASH - [**Desktop and mobile Architecture for System Hardware**](Desktop_and_mobile_Architecture_for_System_Hardware)
* DASH - [**Desktop and mobile Architecture for System Hardware**](https://en.wikipedia.org/wiki/Desktop_and_mobile_Architecture_for_System_Hardware)
* DB - DaughterBoard
* DbC - USB: Debug Capability on the USB host controller
* DC - Electricity: Direct Current
* DCP - Digital Content Protection
* DCR - **Decode Control Register** This is a way of identifying the
@@ -242,7 +244,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* DIMM - [**Dual Inline Memory Module**](https://en.wikipedia.org/wiki/DIMM)
* DIP - [**Dual inline package**](https://en.wikipedia.org/wiki/Dual_in-line_package)
* DMA - [**Direct Memory
Access**](http://en.wikipedia.org/wiki/Direct_memory_access) Allows
Access**](https://en.wikipedia.org/wiki/Direct_memory_access) Allows
certain hardware subsystems within a computer to access system memory
for reading and/or writing independently of the main CPU. Examples of
systems that use DMA: Hard Disk Controller, Disk Drive Controller,
@@ -250,7 +252,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
computers, as it allows devices of different speeds to communicate
without subjecting the CPU to a massive interrupt load.
* DMI - Direct Media Interface is a link/bus between CPU and PCH.
* DMI - [**Desktop Management Interface**](Desktop_Management_Interface)
* DMI - [**Desktop Management Interface**](https://en.wikipedia.org/wiki/Desktop_Management_Interface)
* DMIC - Digital Microphone
* DMTF - [**Distributed Management Task Force**](https://en.wikipedia.org/wiki/Distributed_Management_Task_Force)
* DMZ - Demilitarized Zone
@@ -259,6 +261,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* DOS - Disk Operating System
* DP - DisplayPort
* DPM - Mediatek: DRAM Power Manager
* DPTC - AMD: Dynamic Power and Thermal Control
* DPTF - Intel: Dynamic Power and Thermal Framework
* DRAM - Memory: [**Dynamic Random Access Memory**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory)
* DRTM - Dynamic Root of Trust for Measurement
@@ -285,6 +288,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
vs Integrated TPMs or fTPMs (Firmware TPMs).
* DTS - U-Boot: Device Tree Source
* DUT - Device Under Test
* DvC - USB: Debug Capability on the USB Device (Device Capability)
* DVFS - ARM: Dynamic Voltage and Frequency Scaling
* DVI - [**Digital Video Interface**](https://en.wikipedia.org/wiki/Digital_Visual_Interface)
* DVT - Production Timeline: Design Validation Test
@@ -297,12 +301,13 @@ Spec](https://uefi.org/specifications) for details, or run the tool
## E
* EAPD - Intel: [**External Amplifier Power Down**](https://web.archive.org/web/20210203194800/https://www.eeweb.com/hd-audio-eapd/)
* EBDA - Extended BIOS Data Area
* EBG - Intel: Emmitsburg PCH
* ECC - [**Error Correction Code**](https://en.wikipedia.org/wiki/Error_correction_code) - Typically used to refer to a type of
memory that can detect and correct memory errors.
* EDID - [**Extended Display Identification Data**](https://en.wikipedia.org/wiki/Extended_Display_Identification_Data)
* edk2 - EFI Development Kit 2
* EDK2 - EFI Development Kit 2
* EDO - Memory: [**Extended Data
Out**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Extended_data_out_DRAM)
- A DRAM standard introduced in 1994 that improved upon, but was
@@ -324,6 +329,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* EOL - End of Life
* EPP - Intel: Energy-Performance Preference
* EPROM - Erasable Programmable Read-Only Memory
* EROFS - Linux: [**Enhanced Read-Only File System**](https://en.wikipedia.org/wiki/EROFS)
* ESD - Electrostatic discharge
* eSPI - Enhanced System Peripheral Interface
* EVT - Production Timeline: Engineering Validation Test
@@ -334,6 +340,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* FADT - ACPI Table: Fixed ACPI Description Table
* FAE - Field Application Engineer
* FAT - File Allocation Table
* FBVDDQ - Nvidia Power: Framebuffer Voltage
* FCH - AMD: Firmware Control Hub
* FCS - Production Timeline: First Customer Shipment
* FDD - Floppy Disk Drive
@@ -351,7 +358,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* FPDT - ACPI: Firmware Performance Data Table
* FPGA - [**Field-Programmable Gate Array**](https://en.wikipedia.org/wiki/Field-programmable_gate_array)
* Framebuffer - The
[**framebuffer**](http://en.wikipedia.org/wiki/Framebuffer) is a part
[**framebuffer**](https://en.wikipedia.org/wiki/Framebuffer) is a part
of RAM in a computer which is allocated to hold the graphics
information for one frame or picture. This information typically
consists of color values for every pixel on the screen. A framebuffer
@@ -363,12 +370,15 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* FPM - Memory: [**Fast Page Mode**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Page_mode_DRAM) - A DRAM standard introduced in 1990.
* FPU - [**Floating-Point Unit**](https://en.wikipedia.org/wiki/Floating-point_unit)
* FSB - [**Front-Side Bus**](https://en.wikipedia.org/wiki/Front-side_bus)
* FSM - Finite State Machine
* FSP - Intel: Firmware Support Package
* FSR - Intel: Firmware Status Register
* FTP - Network Protocol: [**File Transfer Protocol**](https://en.wikipedia.org/wiki/File_Transfer_Protocol)
* fTPM - Firmware TPM (Trusted Platform Module). This is a TPM that is
based in firmware instead of actual hardware. It typically runs in
some sort of TEE (Trusted Execution Environment).
* FWCM Intel: firmware Connection Manager
* FWID - Firmware Identifier
## G
@@ -389,6 +399,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* GMA - Intel: [**Graphics Media
Accelerator**](https://en.wikipedia.org/wiki/Intel_GMA)
* GNB - Graphics NorthBridge
* GND - Power: Ground
* GNVS - Global Non-Volatile Storage
* GPD - PCH GPIO in Deep Sleep well (D5 power)
* GPE - ACPI: General Purpose Event
@@ -405,23 +416,28 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* GSC - Google Security Chip - Typically Cr50/Ti50, though could also refer to the titan chips
* GSPI - Generic SPI - These are SPI controllers available for general
use, not dedicated to flash, for example.
* GTDT - ACPI: Generic Timer Description Table
* GTT - [**Graphics Translation Table**](https://en.wikipedia.org/wiki/Graphics_address_remapping_table)
* GUID - UEFI: [**Globally Unique IDentifier**](https://en.wikipedia.org/wiki/Universally_unique_identifier)
## H
* HBP - Graphics: [**Horizontal Back Porch**](https://en.wikipedia.org/wiki/Horizontal_blanking_interval) In the Horizontal blanking interval, this is the blank area past the end of the scanline
* HDA - [**High Definition Audio**](https://en.wikipedia.org/wiki/Intel_High_Definition_Audio)
* HDCP - [**High-bandwidth Digital Content Protection**](https://en.wikipedia.org/wiki/High-bandwidth_Digital_Content_Protection)
* HDD - Hard Disk Drive
* HDMI - [**High-Definition Multimedia Interface**](https://en.wikipedia.org/wiki/HDMI)
* HDR - [**High Dynamic Range**](https://en.wikipedia.org/wiki/High_dynamic_range)
* HECI - Intel: [**Host Embedded Controller Interface**](https://en.wikipedia.org/wiki/Host_Embedded_Controller_Interface) (Replaced by MEI)
* HFP - Graphics: [**Horizontal Front Porch**](https://en.wikipedia.org/wiki/Horizontal_blanking_interval) In the Horizontal blanking interval, this is the blank before the start of the next scanline.
* HID - [**Human Interface
Device**](https://en.wikipedia.org/wiki/Human_interface_device)
* HOB - UEFI: Hand-Off Block
* HPD - Hot-Plug Detect
* HPET - [**High Precision Event Timer**](https://en.wikipedia.org/wiki/High_Precision_Event_Timer)
* HSP - AMD: Hardware Security Processor
* HSPHY - USB: USB3 High-Speed PHY
* HSTI - Hardware Security Test Interface
* HSW - Intel: Haswell
* Hybrid S3 - System Power State: This is where the operating system
@@ -430,7 +446,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
resume quickly from S3 if the system stays powered, and resume from
the disk if power is lost.
* Hypertransport - AMD: The
[**Hypertransport**](http://en.wikipedia.org/wiki/Hypertransport) bus
[**Hypertransport**](https://en.wikipedia.org/wiki/Hypertransport) bus
is an older (2001-2017) high-speed electrical interconnection protocol
specification between CPU, Memory, and (occasionally) peripheral
devices. This was originally called the Lightning Data Transport
@@ -451,6 +467,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
- Also known as SenseWire
* IA - Intel Architecture
* IA-64 - Intel Itanium 64-bit architecture
* IAFC - RISC-V: [**RISC-V Base Integer instruction set**](https://en.wikipedia.org/wiki/RISC-V), plus atomic instructions, single precision floating point instructions, and compressed instructions
* IBB – Initial Boot Block
* IBV - Independent BIOS Vendor
* IC - Integrated Circuit
@@ -468,6 +485,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
Fabric**](https://en.wikipedia.org/wiki/HyperTransport#Infinity_Fabric)
is a superset of AMD's earlier Hypertransport interconnect.
* IFD - Intel: Intel Flash Descriptor
* IMAFC - RISC-V: [**RISC-V Base Integer instruction set**](https://en.wikipedia.org/wiki/RISC-V), plus integer multiply & divide, atomic instructions, single precision floating point instructions, and compressed instructions
* IMC - AMD: Integrated micro-controller - An 8051 microcontroller built
into some AMD FCHs (Fusion Controller Hubs) and Southbridge chips.
This never worked well for anything beyond fan control and caused
@@ -479,6 +497,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* IoC - Security: Indicator of Compromise
* IOC - Intel: I/O Cache
* IOE - Intel: I/O Expander
* IOHC - AMD: I/O Hub Controller
* IOM - Intel: I/O Manager
* IOMMU - [**I/O Memory Management Unit**](https://en.wikipedia.org/wiki/Input%E2%80%93output_memory_management_unit)
* IOMUX - AMD: The I/O Mux block controls how each GPIO is configured.
@@ -579,12 +598,14 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* MBR - Master Boot Record
* MCA - [**Machine Check Architecture**](https://en.wikipedia.org/wiki/Machine_Check_Architecture)
* MCR - Machine Check Registers
* MCTP - [**Management Component Transport Protocol**](https://en.wikipedia.org/wiki/Management_Component_Transport_Protocol)
* MCU - Memory Control Unit
* MCU - [**MicroController
Unit**](https://en.wikipedia.org/wiki/Microcontroller)
* MCTP - [**Management Component Transport Protocol**](https://en.wikipedia.org/wiki/Management_Component_Transport_Protocol)
* MCUPM - Mediatek: MCUPM is a hardware module which is used for MCUSYS Power Management. MCUPM firmware (mcupm.bin) is loaded into MCUPM SRAM at system initialization.
* MDFIO - Intel: Multi-Die Fabric IO
* MDN - AMD: Mendocino
* mDP - Mini DisplayPort connector
* ME - Intel: Management Engine
* MEI - Intel: ME Interface (Previously known as HECI)
* Memory training - the process of finding the best speeds, voltages,
@@ -601,7 +622,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* MKBP - Matrix Keyboard Protocol
* MMC - [**MultiMedia
Card**](https://en.wikipedia.org/wiki/MultiMediaCard)
* MMIO - [**Memory Mapped I/O**](http://en.wikipedia.org/wiki/MMIO)
* MMIO - [**Memory Mapped I/O**](https://en.wikipedia.org/wiki/MMIO)
allows peripherals' memory or registers to be accessed directly
through the memory bus. When the memory bus size was very small, this
was initially done by hiding any memory at that address, effectively
@@ -628,16 +649,17 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* MSB - Most Significant Bit
* MSI - Message Signaled Interrupt
* MSR - Machine-Specific Register
* MT/s - MegaTransfers per second
* MTS or MT/s - MegaTransfers per second
* MTL - Intel: Meteor Lake
* MTL - ARM: MHU Transport Layer
* MTRR - [**Memory Type and Range Register**](http://en.wikipedia.org/wiki/MTRR)
* MTRR - [**Memory Type and Range Register**](https://en.wikipedia.org/wiki/MTRR)
allows to set the cache behaviour on memory access in x86. Basically,
it tells the CPU how to cache certain ranges of memory
(e.g. write-through, write-combining, write-back...). Memory ranges
are specified over physical address ranges. In Linux, they are visible
over `/proc/mtrr` and they can be modified there. For further
information, see the [**Linux documentation**](https://www.kernel.org/doc/html/v5.19/x86/pat.html).
* MXM - PCIe: [**Mobile PCI Express Module**](https://en.wikipedia.org/wiki/Mobile_PCI_Express_Module)
## N
@@ -663,6 +685,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* NVME - Non-Volatile Memory Express - An SSD interface that allows
access to the flash memory through a PCIe bus.
* NVPCF - Nvidia Platform and Control Framework
* NVVDD - Nvidia Power: Core voltage
* NX - No Execute
@@ -708,17 +731,17 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* PCD - UEFI: Platform Configuration Database
* PCH - Intel: [**Platform Controller Hub**](https://en.wikipedia.org/wiki/Platform_Controller_Hub)
* PCI - [**Peripheral Control
Interconnect**](http://en.wikipedia.org/wiki/Peripheral_Component_Interconnect)
Interconnect**](https://en.wikipedia.org/wiki/Peripheral_Component_Interconnect)
- Replaced generally by PCIe (PCI Express)
* PCI Configuration Space - The [**PCI Config
space**](http://en.wikipedia.org/wiki/PCI_Configuration_Space) is an
space**](https://en.wikipedia.org/wiki/PCI_Configuration_Space) is an
[address space](https://en.wikipedia.org/wiki/Address_space) for all
PCI devices. Originally, this address space was accessed through an
index/data pair by writing the address that you wanted to read/write
into the I/O address 0xCF8, then reading or writing I/O Address 0xCFC.
This has been updated to an MMIO method which increases each PCI
function's configuration space from 256 bytes to 4K.
* PCIe - [**PCI Express**](http://en.wikipedia.org/wiki/Pci_express)
* PCIe - [**PCI Express**](https://en.wikipedia.org/wiki/Pci_express)
* PCMCIA: Personal Computer Memory Card International Association
* PCO - AMD: [**Picasso**](https://en.wikichip.org/wiki/amd/cores/picasso)
* PCR: TPM: Platform Configuration Register
@@ -732,8 +755,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* PEI - UEFI: Pre-EFI Initialization
* PEIM - UEFI: PEI Module
* PEP - Intel: Power Engine Plug-in
* PEXVDD - Nvidia Power: PCIExpress Voltage
* PHX - AMD: Phoenix SoC
* PHY - [**PHYsical layer**](http://en.wikipedia.org/wiki/PHY) - The
* PHY - [**PHYsical layer**](https://en.wikipedia.org/wiki/PHY) - The
hardware that implements the send/receive functionality of a
communication protocol.
* PI - Platform Initialization
@@ -752,7 +776,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* PIT - Generally refers to the 8253/8254 [**Programmable Interval
Timer**](https://en.wikipedia.org/wiki/Programmable_interval_timer).
* PLCC - [**Plastic leaded chip
carrier**](http://en.wikipedia.org/wiki/Plastic_leaded_chip_carrier)
carrier**](https://en.wikipedia.org/wiki/Plastic_leaded_chip_carrier)
* PLL - [**Phase-Locked
Loop**](https://en.wikipedia.org/wiki/Phase-locked_loop)
* PM - Platform Management
@@ -783,6 +807,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* PSF - Intel: Primary Sideband Fabric
* PSP - AMD: Platform Security Processor
* PSPP - AMD: PCIE Speed Power Policy
* PSR - Intel: Platform Service Record
* PSR - Graphics: Panel Self-Refresh - This is a power-savings feature specified in eDP
* PTT - Intel: Platform Trust Technology - Intel's firmware based TPM.
* PU - GPIOs: Pull-Up - Drives the pin to reference voltage through a
resistor. The resistor allows the signal to still be set to ground
@@ -809,6 +835,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
a set of 3 or 4 GPIOs to allow 8 to 16 different memory chips to be
used.
* RAPL - Running Average Power Limit
* RCB - PCIe: Read Completion Boundary - Sets the address alignment on which a read request may be serviced with multiple completions
* RCS - [**Revision control
system**](https://en.wikipedia.org/wiki/Revision_Control_System)
* Real mode - The original 20-bit addressing mode of the 8086 & 8088
@@ -816,7 +843,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
Segment:Offset index pair. In 2022, this is still the mode that
x86-64 processors are in at the reset vector!
* RDMA - [**Remote Direct Memory
Access**](http://en.wikipedia.org/wiki/Remote_Direct_Memory_Access) is
Access**](https://en.wikipedia.org/wiki/Remote_Direct_Memory_Access) is
a concept whereby two or more computers communicate via DMA directly
from main memory of one system to the main memory of another.
* RFC - Request for Comment
@@ -829,6 +856,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* ROM - Read Only Memory
* RoT - Root of Trust
* RPL - Intel: [**Raptor Lake**](https://en.wikipedia.org/wiki/Raptor_Lake)
* RPP - Intel: Raptor Point PCH
* RRG - AMD (ATI): Register Reference Guide
* RSDP - Root System Description Pointer
* RTC - Real Time Clock
@@ -920,6 +948,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* SMBus - [**System Management
Bus**](https://en.wikipedia.org/wiki/System_Management_Bus)
* [http://www.smbus.org/](http://www.smbus.org/)
* SME - AMD: Secure Memory Encryption
* SMI - System management interrupt
* SMM - [**System management
mode**](https://en.wikipedia.org/wiki/System_Management_Mode)
@@ -933,7 +962,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* SO-DIMM: Small Outline Dual In-Line Memory Module
* SoC - System on a Chip
* SOIC - [**Small-Outline Integrated
Circuit**](http://en.wikipedia.org/wiki/Small-outline_integrated_circuit)
Circuit**](https://en.wikipedia.org/wiki/Small-outline_integrated_circuit)
* SPD - [**Serial Presence
Detect**](https://en.wikipedia.org/wiki/Serial_presence_detect)
* SPI - [**Serial Peripheral
@@ -958,6 +987,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* SSI-TEB - Physical board format: [**SSI Thin Electronics
Bay**](https://en.wikipedia.org/wiki/SSI_CEB)
* SSP - [**Speech Signal Processor**](https://en.wikipedia.org/wiki/Speech_processing)
* SSPHY - USB: USB3 Super-Speed PHY
* STAPM - AMD: Skin Temperature Aware Power Management
* STB - AMD: Smart Trace Buffer
* SuperIO - The [**Super I/O**](https://en.wikipedia.org/wiki/Super_I/O)
@@ -965,13 +995,16 @@ Spec](https://uefi.org/specifications) for details, or run the tool
peripherals. Most common are: A PS/2 Keyboard and mouse port, LPT
Ports, UARTS, Watchdog Timers, Floppy drive Controllers, GPIOs, or any
of a number of various other devices.
* SVC - ARM: Supervisor Call
* SVI2/3 - Serial VID (Voltage Identification) Interface 2.0 / 3.0
* SWCM - Intel: Software Connection Manager
## T
* TBT - Thunderbolt
* TBT - Intel: Turbo Boost Technology
* tBUF - I2C: The bus free time between a STOP and START condition
* TCC - Intel: Thermal Control Circuit
* TCP - Transmission Control Protocol
* TCPC - Type C Port Controller
@@ -1013,6 +1046,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* uCode - [**Microcode**](https://en.wikipedia.org/wiki/Microcode)
* UDK - UEFI: UEFI Development Kit
* UDP - User Datagram Protocol
* UDMA - ATA: [**Ultra DMA**](https://en.wikipedia.org/wiki/UDMA) - The fastest transfer mode for ATA Hard Drives
* UEFI - Unified Extensible Firmware Interface
* UFC - User Facing Camera
* UFP - USB: Upstream Facing Port
@@ -1030,6 +1064,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* UPS - Uninterruptible Power Supply
* USART - Universal Synchronous/Asynchronous Receiver/Transmitter
* USB - Universal Serial Bus
* USF - Intel: Universal Scalable Firmware
## V
@@ -1038,6 +1073,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* VBNV - Vboot Non-Volatile storage
* VBT - [**Video BIOS
Table**](https://www.kernel.org/doc/html/latest/gpu/i915.html#video-bios-table-vbt)
* VDDQ Memory/Power: The supply voltage to the output buffers of a memory chip.
* VESA - Video Electronics Standards Association
* VGA: Video Graphics Array
* VID: Vendor Identifier
@@ -1045,12 +1081,17 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* VLB - VESA Local Bus
* VOIP - Voice over IP
* Voodoo mode - a silly name for Big Real mode.
* VMX - Intel: CPU flag for Hardware Virtualization
* VPD - Vital Product Data
* VPN - Virtual Private Network
* VPU - Intel: Versatile Processor Unit
* VR - Voltage Regulator
* VRAM - Video Random Access Memory
* VREF Memory/Power: Reference voltage for the input lines of a chip that determines the voltage level at which the threshold between a logical 1 and a logical 0 occurs. Usually 1/2 VDDQ.
* VRM - Voltage Regulator Module
* VT-d - Intel: Virtualization Technology for Directed I/O
* VTT Memory/Power: Tracking Termination Voltage
* vUART - Virtual UART
## W
@@ -1068,6 +1109,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* WLAN - Wireless LAN (Local Area Network)
* WWAN - Telecommunication: Wireless WAN (Wide Area Network)
* WP - Cache policy: [**Write-Protected**](https://en.wikipedia.org/wiki/Cache_%28computing%29)
* WPT - Intel: Wildcat Point - PCH for Broadwell
* WO - Write-only
* WOL - [**Wake-on-LAN**](https://en.wikipedia.org/wiki/Wake-on-LAN)
* WT - Cache Policy: [**Write Through**](https://en.wikipedia.org/wiki/Cache_%28computing%29)
@@ -1088,9 +1130,10 @@ Spec](https://uefi.org/specifications) for details, or run the tool
supporting 1.x, 2.0, and 3.x devices.
## Y
* YCC - Color Space: [**YCbCr**](https://en.wikipedia.org/wiki/YCbCr) - A family of color spaces used in video
## Z

17
Documentation/getting_started/build_system.md
View File

@@ -62,6 +62,23 @@ supported options are:
`position` and `align` are mutually exclusive.
### Adding Makefile fragments
You can use the `add_intermediate` helper to add new post-processing steps for
the final `coreboot.rom` image. For example you can add new files to CBFS by
adding something like this to `site-local/Makefile.inc`
```
$(call add_intermediate, add_mrc_data)
$(CBFSTOOL) $< write -r RW_MRC_CACHE -f site-local/my-mrc-recording.bin
```
Note that the second line must start with a tab, not spaces.
```eval_rst
See also :doc:`../tutorial/managing_local_additions`.
```
#### FMAP region support
With the addition of FMAP flash partitioning support to coreboot, there was a
need to extend the specification of files to provide more precise control

2
Documentation/mainboard/asus/p2b-ls.md
View File

@@ -92,7 +92,7 @@ for only CPU models that the board will actually be run with.
```eval_rst
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/i440bx/index` |
| Northbridge | Intel I440BX |
+------------------+--------------------------------------------------+
| Southbridge | i82371eb |
+------------------+--------------------------------------------------+

2
Documentation/mainboard/asus/p3b-f.md
View File

@@ -90,7 +90,7 @@ for only CPU models that the board will actually be run with.
```eval_rst
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/i440bx/index` |
| Northbridge | Intel I440BX |
+------------------+--------------------------------------------------+
| Southbridge | i82371eb |
+------------------+--------------------------------------------------+

11
Documentation/mainboard/hp/compaq_8300_usdt.md
View File

@@ -1,6 +1,6 @@
# HP Compaq 8300 Elite USDT
# HP Compaq Elite 8300 USDT
This page describes how to run coreboot on the [Compaq 8300 Elite USDT] desktop
This page describes how to run coreboot on the [Compaq Elite 8300 USDT] desktop
from [HP].
## Flashing coreboot
@@ -27,9 +27,8 @@ from [HP].
### Internal programming
TODO: investigate
The board has two jumpers that might be relevant: FDO (Flash Descriptor Override) and BB (?).
Internal programming is possible. Shorting the Flash Descriptor Override
(FDO) jumper bypasses all write protections.
### External programming
@@ -62,5 +61,5 @@ Wake on LAN is active works great.
This board has a Nuvoton NPCD379 SuperIO chip. Fan speed and PS/2 keyboard work
fine using coreboot's existing code for :doc:`../../superio/nuvoton/npcd378`.
[Compaq 8300 USDT]: https://support.hp.com/gb-en/product/hp-compaq-elite-8300-ultra-slim-pc/5232866
[Compaq Elite 8300 USDT]: https://support.hp.com/gb-en/product/hp-compaq-elite-8300-ultra-slim-pc/5232866
[HP]: https://www.hp.com/

4
Documentation/mainboard/index.md
View File

@@ -75,6 +75,7 @@ The boards in this section are not real mainboards, but emulators.
## HP
- [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
- [Compaq Elite 8300 USDT](hp/compaq_8300_usdt.md)
- [Z220 Workstation SFF](hp/z220_sff.md)
### EliteBook series
@@ -124,8 +125,7 @@ The boards in this section are not real mainboards, but emulators.
### Ivy Bridge series
- [T430](lenovo/t430.md)
- [T530](lenovo/w530.md)
- [W530](lenovo/w530.md)
- [T530 / W530](lenovo/w530.md)
- [T430 / T530 / X230 / W530 common](lenovo/Ivy_Bridge_series.md)
- [T431s](lenovo/t431s.md)
- [X230s](lenovo/x230s.md)

6
Documentation/releases/coreboot-4.22-relnotes.md
View File

@@ -13,7 +13,6 @@ Update this document with changes that should be in the release notes.
A final version of the notes are done after the release.
### Significant or interesting changes
----------------------------------
* Add changes that need a full description here
@@ -25,7 +24,6 @@ Update this document with changes that should be in the release notes.
* To be filled in immediately before the release by the release team
### Additional coreboot changes
---------------------------
The following are changes across a number of patches, or changes worth
noting, but not needing a full description.
@@ -33,22 +31,18 @@ noting, but not needing a full description.
* Changes that only need a line or two of description go here.
### Platform Updates
----------------
* To be filled in immediately before the release by the release team
### Plans to move platform support to a branch
------------------------------------------
* Section to be filled in or removed after discussion
### Statistics from the 4.21 to the 4.22 release
--------------------------------------------
* To be filled in immediately before the release by the release team
### Significant Known and Open Issues
---------------------------------
* To be filled in immediately before the release by the release team

30
Documentation/tutorial/part3.md
View File

@@ -1,20 +1,20 @@
# Writing unit tests for coreboot
## Introduction
General thoughts about unit testing coreboot can be found in [Unit
testing coreboot](../technotes/2020-03-unit-testing-coreboot.md).
General thoughts about unit testing coreboot can be found in
[Unit-testing coreboot](../technotes/2020-03-unit-testing-coreboot.md).
Additionally, [code coverage](../technotes/2021-05-code-coverage.md)
support is available for unit tests.
This document aims to guide developers through the process of adding and
writing unit tests for coreboot modules.
As an example of unit under test, `src/device/i2c.c` (referred hereafter
As an example of unit-under-test, `src/device/i2c.c` (referred hereafter
as UUT "Unit Under Test") will be used. This is simple module, thus it
should be easy for the reader to focus solely on the testing logic,
without the need to spend too much time on digging deeply into the
source code details and flow of operations. That being said, a good
understanding of what the unit under test is doing is crucial for
understanding of what the unit-under-test is doing is crucial for
writing unit tests.
This tutorial should also be helpful for developers who want to follow
@@ -23,7 +23,7 @@ though TDD has a different work flow of building tests first, followed
by the code that satisfies them, the process of writing tests and adding
them to the tree is the same.
## Analysis of unit under test
## Analysis of unit-under-test
First of all, it is necessary to precisely establish what we want to
test in a particular module. Usually this will be an externally exposed
API, which can be used by other modules.
@@ -69,7 +69,7 @@ UUT and not on the other modules. While some software dependencies may
be hard to be mock (for example due to complicated dependencies) and
thus should be simply linked into the test binaries, all hardware
dependencies need to be mocked out, since in the user-space host
environment, targets hardware is not available.
environment, target hardware is not available.
```eval_rst
.. admonition:: i2c-test example
@@ -142,12 +142,12 @@ for coreboot `make unit-tests`.
make unit-tests
```
When trying to build test binary, one can often see linker complains
about `undefined reference` to couple of symbols. This is one of
When trying to build test binary, one can often see the linker complaining
about `undefined reference` for a couple of symbols. This is one of the
solutions to determine all external dependencies of UUT - iteratively
build test and resolve errors one by one. At this step, developer should
decide either it's better to add an extra module to provide necessary
definitions or rather mock such dependency. Quick guide through adding
definitions or rather mock such dependency. A quick guide about adding
mocks is provided later in this doc.
## Writing new tests
@@ -324,8 +324,8 @@ a described range.
.. admonition:: i2c-test example
In our example, we may want to check that `platform_i2c_transfer` is
fed with number of segments bigger than 0, each segment has flags
which are in supported range and each segment has buf which is
fed with a number of segments bigger than 0, each segment has flags
which are in the supported range and each segment has a buf which is
non-NULL. We are expecting such values for _every_ call, thus the
last parameter in `expect*` macros is -1.
@@ -375,16 +375,16 @@ API documentation.
### Test runner
Finally, the developer needs to implement the test `main()` function.
All tests should be registered there and cmocka test runner invoked. All
methods for invoking Cmocka test are described
All tests should be registered there and the cmocka test runner invoked.
All methods for invoking Cmocka test are described
[here](https://api.cmocka.org/group__cmocka__exec.html).
```eval_rst
.. admonition:: i2c-test example
We don't need any extra setup and teardown functions for i2c-test, so
let's simply register test for `i2c_read_field` and return from main
value which is output of Cmocka's runner (it returns number of tests
let's simply register the test for `i2c_read_field` and return from
main the output of Cmocka's runner (it returns number of tests
that failed).
.. code-block:: c

12
Documentation/util.md
View File

@@ -49,8 +49,8 @@ file `Python`
* __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C`
* __chromeos__ - These scripts can be used to access ChromeOS
resources, for example to extract System Agent reference code and other
blobs (e.g. mrc.bin, refcode, VGA option roms) from a ChromeOS
recovery image. `C`
blobs (e.g. mrc.bin, refcode, VGA option roms) from a ChromeOS recovery
image. `C`
* __crossgcc__ - A cross toolchain builder for -elf toolchains (ie. no
libc support) `Bash`
* __docker__ - Dockerfiles for _coreboot-sdk_, _coreboot-jenkins-node_,
@@ -88,7 +88,7 @@ firmware of many HP laptops with 8051-based SMSC KBC1098/KBC1126
embedded controller and insert them to the firmware image. `C`
* __kconfig__ - Build system `Make`
* __lint__ - Source linter and linting rules `Shell`
* __liveiso__ - A script and NixOS configuration files to create an ISO
* __nixos__ - A script and NixOS configuration files to create an ISO
image for testing purposes and for working on firmware. `Bash`
* __mainboard__ - mainboard specific scripts
* _google_ - Directory for google mainboard specific scripts
@@ -138,6 +138,10 @@ for the files modified in a patch or for a file `Perl`
license headers `Shell`
* _parse-maintainers.pl_ - Script to alphabetize MAINTAINERS
file `Perl`
* _rm_unused_code_ - Remove all code not used for a platform
from the local git repository for auditing or release `Bash`
* _show_platforms.sh_ - Makes a list of platforms in the tree.
Does not show variants. `Shell`
* _ucode_h_to_bin.sh_ - Microcode conversion tool `Bash`
* _update_submodules_ - Check all submodules for updates `Bash`
* __showdevicetree__ - Compile and dump the device tree `C`
@@ -162,9 +166,9 @@ the documentation `Bash`
* __x86__ - Generates 32-bit PAE page tables based on a CSV input file.
`Go`
* __xcompile__ - Cross compile setup `Bash`
## In depth documentation
* [abuild](util/abuild/index.md)
* [cbfstool](util/cbfstool/index.md)
* [ifdtool](util/ifdtool/index.md)
* [intelp2m](util/intelp2m/index.md)

20
MAINTAINERS
View File

@@ -340,7 +340,7 @@ F: src/mainboard/gizmosphere/
GOOGLE REX MAINBOARDS
M: Subrata Banik <subratabanik@google.com>
M: Tarun Tuli <taruntuli@google.com>
M: Tarun Tuli <tstuli@gmail.com>
M: Kapil Porwal <kapilporwal@google.com>
M: Jakub Czapiga <jacz@semihalf.com>
M: Eran Mitrani <mitrani@google.com>
@@ -348,12 +348,14 @@ S: Maintained
F: src/mainboard/google/rex/
GOOGLE BRYA MAINBOARDS
M: Tarun Tuli <taruntuli@google.com>
M: Subrata Banik <subratabanik@google.com>
M: Nick Vaccaro <nvaccaro@chromium.org>
S: Maintained
F: src/mainboard/google/brya/
GOOGLE HATCH MAINBOARDS
M: Tarun Tuli <taruntuli@google.com>
M: Subrata Banik <subratabanik@google.com>
M: Nick Vaccaro <nvaccaro@chromium.org>
S: Maintained
F: src/mainboard/google/hatch/
@@ -866,7 +868,7 @@ F: src/soc/amd/stoneyridge/
INTEL METEORLAKE SOC
M: Subrata Banik <subratabanik@google.com>
M: Tarun Tuli <taruntuli@google.com>
M: Tarun Tuli <tstuli@gmail.com>
M: Kapil Porwal <kapilporwal@google.com>
M: Jakub Czapiga <jacz@semihalf.com>
M: Eran Mitrani <mitrani@google.com>
@@ -875,7 +877,7 @@ F: src/soc/intel/meteorlake/
INTEL ALDERLAKE SOC
M: Subrata Banik <subratabanik@google.com>
M: Tarun Tuli <taruntuli@google.com>
M: Nick Vaccaro <nvaccaro@chromium.org>
S: Maintained
F: src/soc/intel/alderlake/
@@ -910,7 +912,7 @@ F: src/soc/intel/elkhartlake/
INTEL TIGERLAKE SOC
M: Subrata Banik <subratabanik@google.com>
M: Tarun Tuli <taruntuli@google.com>
M: Nick Vaccaro <nvaccaro@chromium.org>
S: Maintained
F: src/soc/intel/tigerlake/
@@ -966,6 +968,12 @@ M: Stefan Reinauer <stefan.reinauer@coreboot.org>
M: Martin Roth <gaumless@gmail.com>
F: payloads/external/
COREDOOM PAYLOAD INTEGRATION
M: Nicholas Chin <nic.c3.14@gmail.com>
W: https://github.com/nic3-14159/coreDOOM
S: Maintained
F: payloads/external/coreDOOM/
LINUXBOOT PAYLOAD INTEGRATION
M: Christian Walter <christian.walter@9elements.com>
M: Marcello Sylvester Bauer <info@marcellobauer.com>

13
Makefile
View File

@@ -85,7 +85,7 @@ help_coreboot help::
@echo ' clean - Remove coreboot build artifacts'
@echo ' distclean - Remove build artifacts and config files'
@echo ' sphinx - Build sphinx documentation for coreboot'
@echo ' sphinx-lint - Build sphinx documenttion for coreboot with warnings as errors'
@echo ' sphinx-lint - Build sphinx documentation for coreboot with warnings as errors'
@echo ' filelist - Show files used in current build'
@echo ' printall - print makefile info for debugging'
@echo ' gitconfig - set up git to submit patches to coreboot'
@@ -316,6 +316,11 @@ $(eval $(postinclude-hooks))
# Eliminate duplicate mentions of source files in a class
$(foreach class,$(classes),$(eval $(class)-srcs:=$(sort $($(class)-srcs))))
ifeq ($(CONFIG_IWYU),y)
MAKEFLAGS += -k
SAVE_IWYU_OUTPUT := 2>&1 | grep "should\|\#include\|---\|include-list\|^[[:blank:]]\?\'" | tee -a $$(obj)/iwyu.txt
endif
# Build Kconfig .ads if necessary
ifeq ($(CONFIG_ROMSTAGE_ADA),y)
romstage-srcs += $(obj)/romstage/$(notdir $(KCONFIG_AUTOADS))
@@ -382,7 +387,7 @@ $$(call src-to-obj,$1,$$(1).$2): $$(1).$2 $(KCONFIG_AUTOHEADER) $(4)
@printf " CC $$$$(subst $$$$(obj)/,,$$$$(@))\n"
$(CC_$(1)) \
-MMD $$$$(CPPFLAGS_$(1)) $$$$(CFLAGS_$(1)) -MT $$$$(@) \
$(3) -c -o $$$$@ $$$$<
$(3) -c -o $$$$@ $$$$< $(SAVE_IWYU_OUTPUT)
end$(EMPTY)if
en$(EMPTY)def
end$(EMPTY)if
@@ -463,10 +468,10 @@ cscope:
cscope -bR
sphinx:
$(MAKE) -C Documentation -f Makefile.sphinx html
$(MAKE) -C Documentation sphinx
sphinx-lint:
$(MAKE) SPHINXOPTS=-W -C Documentation -f Makefile.sphinx html
$(MAKE) SPHINXOPTS=-W -C Documentation sphinx
symlink:
@echo "Creating Symbolic Links.."; \

10
configs/config.intel_galileo_gen1
View File

@@ -1,10 +0,0 @@
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_VENDOR_INTEL=y
CONFIG_BOARD_INTEL_GALILEO=y
# CONFIG_GALILEO_GEN2 is not set
# CONFIG_FSP_DEBUG_ALL is not set
# CONFIG_ENABLE_SD_TESTING is not set
CONFIG_BOOTBLOCK_NORMAL=y
CONFIG_ON_DEVICE_ROM_LOAD=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_SERIAL_460800=y

9
configs/config.intel_galileo_gen2
View File

@@ -1,9 +0,0 @@
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_VENDOR_INTEL=y
CONFIG_BOARD_INTEL_GALILEO=y
# CONFIG_FSP_DEBUG_ALL is not set
# CONFIG_ENABLE_SD_TESTING is not set
CONFIG_BOOTBLOCK_NORMAL=y
CONFIG_ON_DEVICE_ROM_LOAD=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_SERIAL_921600=y

13
configs/config.intel_galileo_gen2.debug
View File

@@ -1,13 +0,0 @@
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_VENDOR_INTEL=y
CONFIG_BOARD_INTEL_GALILEO=y
# CONFIG_FSP_DEBUG_ALL is not set
CONFIG_DISPLAY_MTRRS=y
CONFIG_DISPLAY_ESRAM_LAYOUT=y
CONFIG_BOOTBLOCK_NORMAL=y
CONFIG_ON_DEVICE_ROM_LOAD=y
CONFIG_VERIFY_HOBS=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_CONSOLE_SERIAL_921600=y

8
configs/config.intel_galileo_gen2.fsp2.0
View File

@@ -1,8 +0,0 @@
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_VENDOR_INTEL=y
CONFIG_BOARD_INTEL_GALILEO=y
# CONFIG_ENABLE_SD_TESTING is not set
CONFIG_BOOTBLOCK_NORMAL=y
CONFIG_ON_DEVICE_ROM_LOAD=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_SERIAL_921600=y

18
configs/config.intel_galileo_gen2.sd
View File

@@ -1,18 +0,0 @@
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_VENDOR_INTEL=y
CONFIG_BOARD_INTEL_GALILEO=y
# CONFIG_FSP_DEBUG_ALL is not set
CONFIG_BOOTBLOCK_NORMAL=y
CONFIG_ON_DEVICE_ROM_LOAD=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_COMMONLIB_STORAGE_MMC=y
CONFIG_STORAGE_ERASE=y
CONFIG_STORAGE_EARLY_ERASE=y
CONFIG_STORAGE_WRITE=y
CONFIG_STORAGE_EARLY_WRITE=y
CONFIG_SD_MMC_DEBUG=y
CONFIG_SD_MMC_TRACE=y
CONFIG_SDHC_TRACE=y
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_CONSOLE_SERIAL_921600=y

9
configs/config.intel_galileo_gen2.vboot
View File

@@ -1,9 +0,0 @@
CONFIG_VENDOR_INTEL=y
CONFIG_BOARD_INTEL_GALILEO=y
# CONFIG_FSP_DEBUG_ALL is not set
CONFIG_VBOOT_WITH_CRYPTO_SHIELD=y
# CONFIG_ENABLE_SD_TESTING is not set
CONFIG_BOOTBLOCK_NORMAL=y
CONFIG_ON_DEVICE_ROM_LOAD=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_SERIAL_921600=y

15
configs/config.scaleway_tagada
View File

@@ -1,15 +0,0 @@
CONFIG_VENDOR_SCALEWAY=y
CONFIG_BOARD_SCALEWAY_TAGADA=y
CONFIG_CBFS_SIZE=0x400000
CONFIG_CONSOLE_POST=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
# CONFIG_IQAT_ENABLE is not set
CONFIG_LEGACY_UART_MODE=y
CONFIG_USE_DENVERTON_NS_FSP_CAR=y
CONFIG_SPI_FLASH_NO_FAST_READ=y
CONFIG_PAYLOAD_ELF=y
CONFIG_PAYLOAD_FILE="UEFIPAYLOAD.fd"
CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
CONFIG_DISPLAY_FSP_HEADER=y
CONFIG_DEBUG_CBFS=y
CONFIG_DEBUG_BOOT_STATE=y

4
payloads/external/Makefile.inc vendored
View File

@@ -24,9 +24,9 @@ ifeq ($(CONFIG_PAYLOAD_LINUX)$(CONFIG_PAYLOAD_LINUXBOOT),y)
ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_COMMAND_LINE))),)
ADDITIONAL_PAYLOAD_CONFIG+=-C $(CONFIG_LINUX_COMMAND_LINE)
endif
ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD))),)
ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD)$(CONFIG_LINUXBOOT_INITRAMFS_PATH))),)
ifneq ($(CONFIG_LINUXBOOT_ARM64),y)
ADDITIONAL_PAYLOAD_CONFIG+=-I $(CONFIG_LINUX_INITRD)$(CONFIG_LINUXBOOT_INITRAMFS)$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX)
ADDITIONAL_PAYLOAD_CONFIG+=-I $(CONFIG_LINUX_INITRD)$(CONFIG_LINUXBOOT_INITRAMFS_PATH)$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX)
prebuilt-files += $(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD)$(CONFIG_LINUXBOOT_INITRAMFS)))
endif
endif

2
payloads/external/U-Boot/Kconfig.name vendored
View File

@@ -1,5 +1,5 @@
config PAYLOAD_UBOOT
bool "U-Boot (Experimental)"
bool "U-Boot"
depends on ARCH_X86
help
Select this option if you want to build a coreboot image

2
payloads/external/U-Boot/Makefile vendored
View File

@@ -5,7 +5,7 @@ TAG-$(CONFIG_UBOOT_STABLE)=$(STABLE_COMMIT_ID)
project_name=U-Boot
project_dir=u-boot
project_git_repo=http://git.denx.de/u-boot.git
project_git_repo=http://github.com/u-boot/u-boot/
project_build_dir=build
project_config_file=$(project_build_dir)/.config

2
payloads/libpayload/arch/x86/Makefile.inc
View File

@@ -26,7 +26,9 @@
## SUCH DAMAGE.
##
ifneq ($(CONFIG_LP_COMPILER_LLVM_CLANG),y)
CFLAGS += -mpreferred-stack-boundary=2
endif
head.o-y += head.S
libc-y += main.c sysinfo.c

2
payloads/libpayload/curses/form/frm_driver.c
View File

@@ -1326,7 +1326,7 @@ _nc_Synchronize_Options(FIELD *field, Field_Options newopts)
field->opts = oldopts;
returnCode(E_CURRENT);
}
if ((form->curpage == field->page))
if (form->curpage == field->page)
{
if (changed_opts & O_VISIBLE)
{

59
payloads/libpayload/include/delay.h Normal file
View File

@@ -0,0 +1,59 @@
/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef LIBPAYLOAD_DELAY_H
#define LIBPAYLOAD_DELAY_H
#include <stdint.h>
#define NSECS_PER_SEC 1000000000
#define USECS_PER_SEC 1000000
#define MSECS_PER_SEC 1000
#define NSECS_PER_MSEC (NSECS_PER_SEC / MSECS_PER_SEC)
#define NSECS_PER_USEC (NSECS_PER_SEC / USECS_PER_SEC)
#define USECS_PER_MSEC (USECS_PER_SEC / MSECS_PER_SEC)
unsigned int get_cpu_speed(void);
void arch_ndelay(uint64_t n);
/**
* Delay for a specified number of nanoseconds.
*
* @param ns Number of nanoseconds to delay for.
*/
static inline void ndelay(unsigned int ns)
{
arch_ndelay((uint64_t)ns);
}
/**
* Delay for a specified number of microseconds.
*
* @param us Number of microseconds to delay for.
*/
static inline void udelay(unsigned int us)
{
arch_ndelay((uint64_t)us * NSECS_PER_USEC);
}
/**
* Delay for a specified number of milliseconds.
*
* @param ms Number of milliseconds to delay for.
*/
static inline void mdelay(unsigned int ms)
{
arch_ndelay((uint64_t)ms * NSECS_PER_MSEC);
}
/**
* Delay for a specified number of seconds.
*
* @param s Number of seconds to delay for.
*/
static inline void delay(unsigned int s)
{
arch_ndelay((uint64_t)s * NSECS_PER_SEC);
}
#endif /* LIBPAYLOAD_DELAY_H */

43
payloads/libpayload/include/libpayload.h
View File

@@ -68,6 +68,7 @@
#include <sysinfo.h>
#include <pci.h>
#include <archive.h>
#include <delay.h>
#define BIT(x) (1ul << (x))
@@ -510,53 +511,11 @@ void lib_sysinfo_get_memranges(struct memrange **ranges,
/* Timer functions. */
/* Defined by each architecture. */
unsigned int get_cpu_speed(void);
uint64_t timer_hz(void);
uint64_t timer_raw_value(void);
uint64_t timer_us(uint64_t base);
void arch_ndelay(uint64_t n);
/* Generic. */
/**
* Delay for a specified number of nanoseconds.
*
* @param ns Number of nanoseconds to delay for.
*/
static inline void ndelay(unsigned int ns)
{
arch_ndelay((uint64_t)ns);
}
/**
* Delay for a specified number of microseconds.
*
* @param us Number of microseconds to delay for.
*/
static inline void udelay(unsigned int us)
{
arch_ndelay((uint64_t)us * NSECS_PER_USEC);
}
/**
* Delay for a specified number of milliseconds.
*
* @param ms Number of milliseconds to delay for.
*/
static inline void mdelay(unsigned int ms)
{
arch_ndelay((uint64_t)ms * NSECS_PER_MSEC);
}
/**
* Delay for a specified number of seconds.
*
* @param s Number of seconds to delay for.
*/
static inline void delay(unsigned int s)
{
arch_ndelay((uint64_t)s * NSECS_PER_SEC);
}
/**
* @defgroup readline Readline functions
* This interface provides a simple implementation of the standard readline()

7
payloads/libpayload/include/stddef.h
View File

@@ -26,11 +26,4 @@ typedef __SIZE_TYPE__ size_t;
typedef __SIZE_TYPE__ ssize_t;
#undef unsigned
#define NSECS_PER_SEC 1000000000
#define USECS_PER_SEC 1000000
#define MSECS_PER_SEC 1000
#define NSECS_PER_MSEC (NSECS_PER_SEC / MSECS_PER_SEC)
#define NSECS_PER_USEC (NSECS_PER_SEC / USECS_PER_SEC)
#define USECS_PER_MSEC (USECS_PER_SEC / MSECS_PER_SEC)
#endif

2
payloads/libpayload/libc/malloc.c
View File

@@ -112,7 +112,7 @@ void init_dma_memory(void *start, u32 size)
#endif
}
int dma_initialized()
int dma_initialized(void)
{
return dma != heap;
}

7
src/Kconfig
View File

@@ -47,8 +47,15 @@ config CBFS_PREFIX
Select the prefix to all files put into the image. It's "fallback"
by default, "normal" is a common alternative.
config DEFAULT_COMPILER_LLVM_CLANG
bool
help
Allows to override the default compiler. This can for instance be
set in site-local/Kconfig.
choice
prompt "Compiler to use"
default COMPILER_LLVM_CLANG if DEFAULT_COMPILER_LLVM_CLANG
default COMPILER_GCC
help
This option allows you to select the compiler used for building

71
src/acpi/acpi.c
View File

@@ -23,6 +23,7 @@
#include <cpu/cpu.h>
#include <device/mmio.h>
#include <device/pci.h>
#include <drivers/uart/pl011.h>
#include <string.h>
#include <types.h>
#include <version.h>
@@ -817,12 +818,48 @@ static void acpi_create_dbg2(acpi_dbg2_header_t *dbg2,
header->checksum = acpi_checksum((uint8_t *)dbg2, header->length);
}
static unsigned long acpi_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long current,
int space_id, uint64_t base, uint32_t size,
int access_size, const char *name)
{
acpi_dbg2_header_t *dbg2 = (acpi_dbg2_header_t *)current;
acpi_addr_t address;
memset(&address, 0, sizeof(address));
address.space_id = space_id;
address.addrl = (uint32_t)base;
address.addrh = (uint32_t)((base >> 32) & 0xffffffff);
address.access_size = access_size;
int subtype;
/* 16550-compatible with parameters defined in Generic Address Structure */
if (CONFIG(DRIVERS_UART_8250IO) || CONFIG(DRIVERS_UART_8250MEM))
subtype = ACPI_DBG2_PORT_SERIAL_16550;
else if (CONFIG(DRIVERS_UART_PL011))
subtype = ACPI_DBG2_PORT_SERIAL_ARM_PL011;
else
return current;
acpi_create_dbg2(dbg2,
ACPI_DBG2_PORT_SERIAL,
subtype,
&address, size,
name);
if (dbg2->header.length) {
current += dbg2->header.length;
current = acpi_align_current(current);
acpi_add_table(rsdp, dbg2);
}
return current;
}
unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current,
const struct device *dev, uint8_t access_size)
{
acpi_dbg2_header_t *dbg2 = (acpi_dbg2_header_t *)current;
struct resource *res;
acpi_addr_t address;
if (!dev) {
printk(BIOS_DEBUG, "%s: Device not found\n", __func__);
@@ -839,33 +876,25 @@ unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current,
return current;
}
memset(&address, 0, sizeof(address));
int space_id;
if (res->flags & IORESOURCE_IO)
address.space_id = ACPI_ADDRESS_SPACE_IO;
space_id = ACPI_ADDRESS_SPACE_IO;
else if (res->flags & IORESOURCE_MEM)
address.space_id = ACPI_ADDRESS_SPACE_MEMORY;
space_id = ACPI_ADDRESS_SPACE_MEMORY;
else {
printk(BIOS_ERR, "%s: Unknown address space type\n", __func__);
return current;
}
address.addrl = (uint32_t)res->base;
address.addrh = (uint32_t)((res->base >> 32) & 0xffffffff);
address.access_size = access_size;
return acpi_write_dbg2_uart(rsdp, current, space_id, res->base, res->size, access_size, acpi_device_path(dev));
}
acpi_create_dbg2(dbg2,
ACPI_DBG2_PORT_SERIAL,
ACPI_DBG2_PORT_SERIAL_16550,
&address, res->size,
acpi_device_path(dev));
if (dbg2->header.length) {
current += dbg2->header.length;
current = acpi_align_current(current);
acpi_add_table(rsdp, dbg2);
}
return current;
unsigned long acpi_pl011_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long current,
uint64_t base, const char *name)
{
return acpi_write_dbg2_uart(rsdp, current, ACPI_ADDRESS_SPACE_MEMORY, base,
sizeof(struct pl011_uart), ACPI_ACCESS_SIZE_DWORD_ACCESS,
name);
}
static void acpi_create_facs(void *header)

7
src/commonlib/bsd/include/commonlib/bsd/elog.h
View File

@@ -369,6 +369,13 @@ struct elog_event_extended_event {
#define ELOG_FW_EARLY_SOL_CSE_SYNC 0x0
#define ELOG_FW_EARLY_SOL_MRC 0x1
/* Platform Service Record(PSR) Events */
#define ELOG_TYPE_PSR_DATA_BACKUP 0xb9
#define ELOG_PSR_DATA_BACKUP_SUCCESS 0x0
#define ELOG_PSR_DATA_BACKUP_FAILED 0x1
#define ELOG_TYPE_PSR_DATA_LOST 0xba
/* Only the 7-LSB are used for size */
#define ELOG_MAX_EVENT_SIZE 0x7F

6
src/drivers/intel/fsp2_0/Makefile.inc
View File

@@ -68,8 +68,7 @@ $(FSP_M_CBFS)-options := --xip $(TXTIBB)
endif
ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_LZMA),y)
$(FSP_M_CBFS)-compression := LZMA
endif
ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_LZ4),y)
else ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_LZ4),y)
$(FSP_M_CBFS)-compression := LZ4
endif
ifneq ($(CONFIG_FSP_ALIGNMENT_FSP_M),)
@@ -81,8 +80,7 @@ $(FSP_S_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE))
$(FSP_S_CBFS)-type := fsp
ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_LZMA),y)
$(FSP_S_CBFS)-compression := LZMA
endif
ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_LZ4),y)
else ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_LZ4),y)
$(FSP_S_CBFS)-compression := LZ4
endif
ifneq ($(CONFIG_FSP_ALIGNMENT_FSP_S),)

2
src/drivers/intel/fsp2_0/include/fsp/util.h
View File

@@ -74,7 +74,7 @@ union extended_fsp_revision {
} rev;
};
#if CONFIG_UDK_VERSION < CONFIG_UDK_2017_VERSION
#if CONFIG_UDK_VERSION < 2017
enum resource_type {
EFI_RESOURCE_SYSTEM_MEMORY = 0,
EFI_RESOURCE_MEMORY_MAPPED_IO = 1,

2
src/drivers/mrc_cache/Kconfig
View File

@@ -54,7 +54,7 @@ config MRC_SAVE_HASH_IN_TPM
config MRC_CACHE_USING_MRC_VERSION
bool
default y if UDK_VERSION >= UDK_202302_VERSION
default y if UDK_VERSION >= 202302
default n
help
Use the MRC version info from FSP extended header to store the MRC cache data.

7
src/include/acpi/acpi.h
View File

@@ -854,7 +854,7 @@ typedef struct acpi_dbg2_header {
acpi_header_t header;
uint32_t devices_offset;
uint32_t devices_count;
} __attribute__((packed)) acpi_dbg2_header_t;
} __packed acpi_dbg2_header_t;
/* DBG2: Microsoft Debug Port Table 2 device entry */
typedef struct acpi_dbg2_device {
@@ -870,7 +870,7 @@ typedef struct acpi_dbg2_device {
uint8_t reserved[2];
uint16_t base_address_offset;
uint16_t address_size_offset;
} __attribute__((packed)) acpi_dbg2_device_t;
} __packed acpi_dbg2_device_t;
/* FADT (Fixed ACPI Description Table) */
typedef struct acpi_fadt {
@@ -1623,6 +1623,9 @@ void generate_cpu_entries(const struct device *device);
unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current,
const struct device *dev, uint8_t access_size);
unsigned long acpi_pl011_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long current,
uint64_t base, const char *name);
void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags,
unsigned long (*acpi_fill_dmar)(unsigned long));
unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags,

2
src/include/efi/efi_datatype.h
View File

@@ -6,7 +6,7 @@
#include <Base.h>
#include <Uefi/UefiBaseType.h>
#if CONFIG_UDK_VERSION >= CONFIG_UDK_2017_VERSION
#if CONFIG_UDK_VERSION >= 2017
#include <Guid/StatusCodeDataTypeId.h>
#include <IndustryStandard/Bmp.h>
#include <Pi/PiPeiCis.h>

5
src/lib/memrange.c
View File

@@ -427,11 +427,12 @@ bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size
return false;
if (from_top) {
limit = MIN(limit, r->end);
/* Ensure we're within the range, even aligned down.
Proof is simple: If ALIGN_UP(r->begin) would be
higher, the stolen range wouldn't fit.*/
assert(r->begin <= ALIGN_DOWN(range_entry_end(r) - size, POWER_OF_2(align)));
*stolen_base = ALIGN_DOWN(range_entry_end(r) - size, POWER_OF_2(align));
assert(r->begin <= ALIGN_DOWN(limit - size + 1, POWER_OF_2(align)));
*stolen_base = ALIGN_DOWN(limit - size + 1, POWER_OF_2(align));
} else {
*stolen_base = ALIGN_UP(r->begin, POWER_OF_2(align));
}

24
src/mainboard/amd/birman/devicetree_phoenix.cb
View File

@@ -255,6 +255,30 @@ chip soc/amd/phoenix
device ref acp on end # Audio Processor (ACP)
end
device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
device ref usb4_xhci_0 on
chip drivers/usb/acpi
device ref usb4_xhci_0_root_hub on
chip drivers/usb/acpi
device ref usb3_port0 on end
end
chip drivers/usb/acpi
device ref usb2_port0 on end
end
end
end
end
device ref usb4_xhci_1 on
chip drivers/usb/acpi
device ref usb4_xhci_1_root_hub on
chip drivers/usb/acpi
device ref usb3_port1 on end
end
chip drivers/usb/acpi
device ref usb2_port1 on end
end
end
end
end
end
end

18
src/mainboard/amd/mayan/Kconfig
View File

@@ -80,6 +80,24 @@ config CHROMEOS
# We don't have recovery buttons, so we can't manually enable devmode.
select GBB_FLAG_FORCE_DEV_SWITCH_ON
choice
prompt "DT SLOT/M.2 SSD1 ENABLE"
default ENABLE_DT_SLOT_MAYAN
help
Either DT slot or M.2 SSD1 can be used to boot on Mayan,
as they are sharing IO lanes.
config ENABLE_DT_SLOT_MAYAN
bool "Enable DT slot"
config ENABLE_M2_SSD1_MAYAN
bool "Enable M.2 SSD1"
config DISABLE_DT_M2_MAYAN
bool "Disable both DT and M.2 slot"
endchoice
if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig
config EFS_SPI_READ_MODE
default 3 # Quad IO (1-1-4)

39
src/mainboard/amd/mayan/ec.c
View File

@@ -17,6 +17,7 @@
#define EC_GPIO_3_ADDR 0xA3
#define EC_GPIO_EVAL_RST_AUX BIT(0)
#define EC_GPIO_LOM_RESET_AUX BIT(1)
#define EC_GPIO_DT_RESET_AUX BIT(2)
#define EC_GPIO_7_ADDR 0xA7
#define EC_GPIO_DT_PWREN BIT(2)
@@ -25,6 +26,9 @@
#define EC_GPIO_8_ADDR 0xA8
#define EC_GPIO_SMBUS0_EN BIT(0)
#define EC_GPIO_9_ADDR 0xA9
#define EC_GPIO_M2SSD1_PWREN BIT(5)
#define EC_GPIO_A_ADDR 0xAA
#define EC_GPIO_WWAN_PWREN BIT(3)
#define EC_GPIO_M2_SSD0_PWREN BIT(6)
@@ -34,6 +38,7 @@
#define EC_GPIO_DT_N_WLAN_SW BIT(1)
#define EC_GPIO_MP2_SEL BIT(2)
#define EC_GPIO_WWAN_N_LOM_SW BIT(3)
#define EC_GPIO_M2SSD1_HDD_SW BIT(6)
#define EC_SW02_ADDR 0xB7
#define EC_SW02_MS BIT(7)
@@ -42,8 +47,7 @@ static void configure_ec_gpio(void)
{
uint8_t tmp;
/* Enable MXM slot: set EC_GPIO_EVAL_PWREN, EC_GPIO_EVAL_SLOT_PWR
and EC_GPIO_EVAL_RST_AUX */
/* Enable MXM slot */
tmp = ec_read(EC_GPIO_1_ADDR);
tmp |= EC_GPIO_EVAL_PWREN;
ec_write(EC_GPIO_1_ADDR, tmp);
@@ -54,22 +58,51 @@ static void configure_ec_gpio(void)
tmp = ec_read(EC_GPIO_3_ADDR);
tmp |= EC_GPIO_LOM_RESET_AUX | EC_GPIO_EVAL_RST_AUX;
tmp |= EC_GPIO_LOM_RESET_AUX;
/* Enable DT slot */
if (CONFIG(ENABLE_DT_SLOT_MAYAN))
tmp |= EC_GPIO_DT_RESET_AUX;
else
tmp &= (~EC_GPIO_DT_RESET_AUX);
ec_write(EC_GPIO_3_ADDR, tmp);
tmp = ec_read(EC_GPIO_7_ADDR);
tmp |= EC_GPIO_WWAN_MODULE_RST | EC_GPIO_DT_PWREN;
tmp |= EC_GPIO_WWAN_MODULE_RST;
if (CONFIG(ENABLE_DT_SLOT_MAYAN))
tmp |= EC_GPIO_DT_PWREN;
else
tmp &= (~EC_GPIO_DT_PWREN);
ec_write(EC_GPIO_7_ADDR, tmp);
tmp = ec_read(EC_GPIO_8_ADDR);
tmp |= EC_GPIO_SMBUS0_EN;
ec_write(EC_GPIO_8_ADDR, tmp);
tmp = ec_read(EC_GPIO_9_ADDR);
/* Enable M2 SSD1 slot */
if (CONFIG(ENABLE_M2_SSD1_MAYAN))
tmp |= EC_GPIO_M2SSD1_PWREN;
else
tmp &= (~EC_GPIO_M2SSD1_PWREN);
ec_write(EC_GPIO_9_ADDR, tmp);
tmp = ec_read(EC_GPIO_A_ADDR);
tmp |= EC_GPIO_M2_SSD0_PWREN | EC_GPIO_LOM_PWREN | EC_GPIO_WWAN_PWREN;
ec_write(EC_GPIO_A_ADDR, tmp);
tmp = ec_read(EC_GPIO_C_ADDR);
tmp |= EC_GPIO_WWAN_N_LOM_SW | EC_GPIO_MP2_SEL | EC_GPIO_DT_N_WLAN_SW;
if (CONFIG(ENABLE_DT_SLOT_MAYAN)) {
tmp |= EC_GPIO_M2SSD1_HDD_SW;
tmp &= (~EC_GPIO_DT_N_WLAN_SW);
}
if (CONFIG(ENABLE_M2_SSD1_MAYAN)) {
tmp |= EC_GPIO_DT_N_WLAN_SW;
tmp &= (~EC_GPIO_M2SSD1_HDD_SW);
}
ec_write(EC_GPIO_C_ADDR, tmp);
tmp = ec_read(EC_SW02_ADDR);

3
src/mainboard/amd/mayan/port_descriptors.c
View File

@@ -71,7 +71,7 @@ static const fsp_dxio_descriptor mayan_dxio_descriptors[] = {
{
// DT
.engine_type = PCIE_ENGINE,
.port_present = true,
.port_present = !CONFIG(DISABLE_DT_M2_MAYAN),
.start_lane = 8,
.end_lane = 9,
.device_number = 1,
@@ -157,7 +157,6 @@ void mainboard_get_dxio_ddi_descriptors(
const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
{
mayan_ddi_descriptors[1].connector_type = get_ddi1_type();
*dxio_descs = mayan_dxio_descriptors;
*dxio_num = ARRAY_SIZE(mayan_dxio_descriptors);
*ddi_descs = mayan_ddi_descriptors;

4
src/mainboard/google/brya/Kconfig
View File

@@ -249,6 +249,8 @@ config MAINBOARD_PART_NUMBER
default "Gothrax" if BOARD_GOOGLE_GOTHRAX
default "Craaskov" if BOARD_GOOGLE_CRAASKOV
default "Pirrha" if BOARD_GOOGLE_PIRRHA
default "Quandiso" if BOARD_GOOGLE_QUANDISO
default "Nokris" if BOARD_GOOGLE_NOKRIS
config VARIANT_DIR
default "brya0" if BOARD_GOOGLE_BRYA0
@@ -299,6 +301,8 @@ config VARIANT_DIR
default "gothrax" if BOARD_GOOGLE_GOTHRAX
default "craaskov" if BOARD_GOOGLE_CRAASKOV
default "pirrha" if BOARD_GOOGLE_PIRRHA
default "quandiso" if BOARD_GOOGLE_QUANDISO
default "nokris" if BOARD_GOOGLE_NOKRIS
config VBOOT
select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA

8
src/mainboard/google/brya/Kconfig.name
View File

@@ -425,3 +425,11 @@ config BOARD_GOOGLE_ZYDRON
select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_RAPTORLAKE
config BOARD_GOOGLE_QUANDISO
bool "-> Quandiso"
select BOARD_GOOGLE_BASEBOARD_NISSA
config BOARD_GOOGLE_NOKRIS
bool "-> Nokris"
select BOARD_GOOGLE_BASEBOARD_NISSA

26
src/mainboard/google/brya/variants/banshee/overridetree.cb
View File

@@ -94,6 +94,32 @@ chip soc/intel/alderlake
}"
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "6"
# DDIA for eDP
register "device[0].name" = ""LCD""
# DDIB for HDMI
register "device[1].name" = ""DD01""
# TCP0 (DP-1) for port C0
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))"
# TCP1 (DP-2) for port C1
register "device[3].name" = ""DD03""
register "device[3].use_pld" = "true"
register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
# TCP2 (DP-3) for port C2
register "device[4].name" = ""DD04""
register "device[4].use_pld" = "true"
register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
# TCP3 (DP-4) for port C3
register "device[5].name" = ""DD05""
register "device[5].use_pld" = "true"
register "device[5].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))"
device generic 0 on end
end
end # Integrated Graphics Device
device ref dtt on
chip drivers/intel/dptf
## sensor information

28
src/mainboard/google/brya/variants/baseboard/brask/gpio.c
View File

@@ -2,6 +2,7 @@
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <intelblocks/early_graphics.h>
#include <types.h>
#include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -403,6 +404,33 @@ static const struct pad_config romstage_gpio_table[] = {
PAD_CFG_GPO(GPP_B4, 1, DEEP),
};
const struct pad_config early_graphics_gpio_table[] = {
/* A18 : DDSP_HPDB ==> HDMI_HPD */
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
/* D1 : ISH_GP1 ==> HDMI_IN_PLUGIN */
PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG),
/* D11 : ISH_SPI_MISO ==> HDMIA_CTRLCLK */
PAD_CFG_NF_LOCK(GPP_D11, NONE, NF2, LOCK_CONFIG),
/* D12 : ISH_SPI_MOSI ==> HDMIA_CTRLDATA */
PAD_CFG_NF_LOCK(GPP_D12, NONE, NF2, LOCK_CONFIG),
/* E14 : DDSP_HPDA ==> HDMIA_HPD */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* E20 : DDP2_CTRLCLK ==> HDMIA_CTRLCLK */
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
/* E21 : DDP2_CTRLDATA ==> HDMIA_CTRLDATA_STRAP */
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
/* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
/* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
};
const struct pad_config *variant_early_graphics_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_graphics_gpio_table);
return early_graphics_gpio_table;
}
const struct pad_config *__weak variant_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(gpio_table);

7
src/mainboard/google/brya/variants/constitution/overridetree.cb
View File

@@ -1,3 +1,10 @@
fw_config
field WIFI_SAR_ID 30 31
option ID_0 0
option UNUSED 3
end
end
chip soc/intel/alderlake
register "domain_vr_config[VR_DOMAIN_IA]" = "{
.enable_fast_vmode = 1,

5
src/mainboard/google/brya/variants/constitution/variant.c
View File

@@ -1,8 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h>
#include <fw_config.h>
#include <sar.h>
const char *get_wifi_sar_cbfs_filename(void)
{
if (fw_config_probe(FW_CONFIG(WIFI_SAR_ID, ID_0))) {
return "wifi_sar_0.hex";
}
return NULL;
}

22
src/mainboard/google/brya/variants/crota/overridetree.cb
View File

@@ -107,6 +107,28 @@ chip soc/intel/alderlake
register "tcc_offset" = "1" # TCC of 99C
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "6"
# DDIA for eDP
register "device[0].name" = ""LCD""
# DDIB for HDMI
register "device[1].name" = ""DD01""
# TCP0 (DP-1) for port C0
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
register "device[3].name" = ""DD03""
# TCP2 (DP-3) for port C2
register "device[4].name" = ""DD04""
register "device[4].use_pld" = "true"
register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
register "device[5].name" = ""DD05""
device generic 0 on end
end
end # Integrated Graphics Device
device ref dtt on
chip drivers/intel/dptf
## sensor information

22
src/mainboard/google/brya/variants/felwinter/overridetree.cb
View File

@@ -93,6 +93,28 @@ chip soc/intel/alderlake
}"
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "6"
# DDIA for eDP
register "device[0].name" = ""LCD""
# DDIB for HDMI
register "device[1].name" = ""DD01""
# TCP0 (DP-1) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP0
register "device[2].name" = ""DD02""
# TCP1 (DP-2) for port C1
register "device[3].name" = ""DD03""
register "device[3].use_pld" = "true"
register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))"
# TCP2 (DP-3) for port C2
register "device[4].name" = ""DD04""
register "device[4].use_pld" = "true"
register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
register "device[5].name" = ""DD05""
device generic 0 on end
end
end # Integrated Graphics Device
device ref dtt on
chip drivers/intel/dptf
## sensor information

22
src/mainboard/google/brya/variants/gimble/overridetree.cb
View File

@@ -74,6 +74,28 @@ chip soc/intel/alderlake
},
}"
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "6"
# DDIA for eDP
register "device[0].name" = ""LCD""
# DDIB for HDMI
register "device[1].name" = ""DD01""
# TCP0 (DP-1) for port C0
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
register "device[3].name" = ""DD03""
# TCP2 (DP-3) for port C1
register "device[4].name" = ""DD04""
register "device[4].use_pld" = "true"
register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
register "device[5].name" = ""DD05""
device generic 0 on end
end
end # Integrated Graphics Device
device ref dtt on
chip drivers/intel/dptf
## sensor information

22
src/mainboard/google/brya/variants/gimble4es/overridetree.cb
View File

@@ -39,6 +39,28 @@ chip soc/intel/alderlake
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A DB Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "6"
# DDIA for eDP
register "device[0].name" = ""LCD""
# DDIB for HDMI
register "device[1].name" = ""DD01""
# TCP0 (DP-1) for port C0
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
register "device[3].name" = ""DD03""
# TCP2 (DP-3) for port C1
register "device[4].name" = ""DD04""
register "device[4].use_pld" = "true"
register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
register "device[5].name" = ""DD05""
device generic 0 on end
end
end # Integrated Graphics Device
device ref dtt on
chip drivers/intel/dptf
## sensor information

12
src/mainboard/google/brya/variants/joxer/overridetree.cb
View File

@@ -1,4 +1,8 @@
fw_config
field DB_USB 0 1
option DB_ABSENT 0
option DB_1C 1
end
field THERMAL 2 2
option THERMAL_FANLESS 0
option THERMAL_FAN 1
@@ -340,7 +344,9 @@ chip soc/intel/alderlake
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
device ref tcss_usb3_port2 on end
device ref tcss_usb3_port2 on
probe DB_USB DB_1C
end
end
end
end
@@ -360,7 +366,9 @@ chip soc/intel/alderlake
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
device ref usb2_port2 on end
device ref usb2_port2 on
probe DB_USB DB_1C
end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A0 (MLB)""

22
src/mainboard/google/brya/variants/kano/overridetree.cb
View File

@@ -96,6 +96,28 @@ chip soc/intel/alderlake
}"
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "6"
# DDIA for eDP
register "device[0].name" = ""LCD""
# DDIB for HDMI
register "device[1].name" = ""DD01""
# TCP0 (DP-1) for port C0
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
register "device[3].name" = ""DD03""
# TCP2 (DP-3) for port C1
register "device[4].name" = ""DD04""
register "device[4].use_pld" = "true"
register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
register "device[5].name" = ""DD05""
device generic 0 on end
end
end # Integrated Graphics Device
device ref dtt on
chip drivers/intel/dptf
## sensor information

3
src/mainboard/google/brya/variants/kuldax/overridetree.cb
View File

@@ -198,13 +198,14 @@ chip soc/intel/alderlake
chip drivers/net
register "wake" = "GPE0_DW0_07"
register "led_feature" = "0xe0"
register "customized_leds" = "0x05af"
register "customized_led0" = "0x23f"
register "customized_led2" = "0x028"
register "enable_aspm_l1_2" = "1"
register "add_acpi_dma_property" = "true"
device pci 00.0 on end
end
end # RTL8125 Ethernet NIC
end # RTL8125 and RTL8111K Ethernet NIC
device ref pcie_rp8 on
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"

22
src/mainboard/google/brya/variants/marasov/overridetree.cb
View File

@@ -131,6 +131,28 @@ chip soc/intel/alderlake
register "tcc_offset" = "5" # TCC of 100
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "6"
# DDIA for eDP
register "device[0].name" = ""LCD""
# DDIB for HDMI
register "device[1].name" = ""DD01""
# TCP0 (DP-1) for port C0
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))"
# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
register "device[3].name" = ""DD03""
# TCP2 (DP-3) for port C1
register "device[4].name" = ""DD04""
register "device[4].use_pld" = "true"
register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
register "device[5].name" = ""DD05""
device generic 0 on end
end
end # Integrated Graphics Device
device ref dtt on
chip drivers/intel/dptf
## sensor information

22
src/mainboard/google/brya/variants/mithrax/overridetree.cb
View File

@@ -91,6 +91,28 @@ chip soc/intel/alderlake
}"
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "6"
# DDIA for eDP
register "device[0].name" = ""LCD""
# DDIB for HDMI
register "device[1].name" = ""DD01""
# TCP0 (DP-1) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP0
register "device[2].name" = ""DD02""
# TCP1 (DP-2) for port C1
register "device[3].name" = ""DD03""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
# TCP2 (DP-3) for port C2
register "device[4].name" = ""DD04""
register "device[4].use_pld" = "true"
register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
register "device[5].name" = ""DD05""
device generic 0 on end
end
end # Integrated Graphics Device
device ref dtt on
chip drivers/intel/dptf
## sensor information

8
src/mainboard/google/brya/variants/nokris/include/variant/ec.h Normal file
View File

@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __VARIANT_EC_H__
#define __VARIANT_EC_H__
#include <baseboard/ec.h>
#endif

8
src/mainboard/google/brya/variants/nokris/include/variant/gpio.h Normal file
View File

@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <baseboard/gpio.h>
#endif

5
src/mainboard/google/brya/variants/nokris/memory/Makefile.inc Normal file
View File

@@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
SPD_SOURCES = placeholder

1
src/mainboard/google/brya/variants/nokris/memory/dram_id.generated.txt Normal file
View File

@@ -0,0 +1 @@
DRAM Part Name ID to assign

11
src/mainboard/google/brya/variants/nokris/memory/mem_parts_used.txt Normal file
View File

@@ -0,0 +1,11 @@
# This is a CSV file containing a list of memory parts used by this variant.
# One part per line with an optional fixed ID in column 2.
# Only include a fixed ID if it is required for legacy reasons!
# Generated IDs are dependent on the order of parts in this file,
# so new parts must always be added at the end of the file!
#
# Generate an updated Makefile.inc and dram_id.generated.txt by running the
# part_id_gen tool from util/spd_tools.
# See util/spd_tools/README.md for more details and instructions.
# Part Name

6
src/mainboard/google/brya/variants/nokris/overridetree.cb Normal file
View File

@@ -0,0 +1,6 @@
chip soc/intel/alderlake
device domain 0 on
end
end

22
src/mainboard/google/brya/variants/omnigul/overridetree.cb
View File

@@ -122,6 +122,28 @@ chip soc/intel/alderlake
register "tcc_offset" = "8"
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "6"
# DDIA for eDP
register "device[0].name" = ""LCD""
# DDIB for HDMI
register "device[1].name" = ""DD01""
# TCP0 (DP-1) for port C0
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))"
# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
register "device[3].name" = ""DD03""
# TCP2 (DP-3) for port C1
register "device[4].name" = ""DD04""
register "device[4].use_pld" = "true"
register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
register "device[5].name" = ""DD05""
device generic 0 on end
end
end # Integrated Graphics Device
device ref dtt on
chip drivers/intel/dptf
## sensor information

22
src/mainboard/google/brya/variants/osiris/overridetree.cb
View File

@@ -64,6 +64,28 @@ chip soc/intel/alderlake
}"
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "6"
# DDIA for eDP
register "device[0].name" = ""LCD""
# DDIB for HDMI
register "device[1].name" = ""DD01""
# TCP0 (DP-1) for port C0
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
register "device[3].name" = ""DD03""
# TCP2 (DP-3) for port C1
register "device[4].name" = ""DD04""
register "device[4].use_pld" = "true"
register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
register "device[5].name" = ""DD05""
device generic 0 on end
end
end # Integrated Graphics Device
device ref dtt on
chip drivers/intel/dptf
## sensor information

22
src/mainboard/google/brya/variants/primus/overridetree.cb
View File

@@ -82,6 +82,28 @@ chip soc/intel/alderlake
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "6"
# DDIA for eDP
register "device[0].name" = ""LCD""
# DDIB for HDMI
register "device[1].name" = ""DD01""
# TCP0 (DP-1) for port C0
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(1, 1))"
# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
register "device[3].name" = ""DD03""
# TCP2 (DP-3) for port C2
register "device[4].name" = ""DD04""
register "device[4].use_pld" = "true"
register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
register "device[5].name" = ""DD05""
device generic 0 on end
end
end # Integrated Graphics Device
device ref dtt on
chip drivers/intel/dptf
## sensor information

22
src/mainboard/google/brya/variants/primus4es/overridetree.cb
View File

@@ -72,6 +72,28 @@ chip soc/intel/alderlake
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "6"
# DDIA for eDP
register "device[0].name" = ""LCD""
# DDIB for HDMI
register "device[1].name" = ""DD01""
# TCP0 (DP-1) for port C0
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(1, 1))"
# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
register "device[3].name" = ""DD03""
# TCP2 (DP-3) for port C2
register "device[4].name" = ""DD04""
register "device[4].use_pld" = "true"
register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
register "device[5].name" = ""DD05""
device generic 0 on end
end
end # Integrated Graphics Device
device ref dtt on
chip drivers/intel/dptf
## sensor information

8
src/mainboard/google/brya/variants/quandiso/include/variant/ec.h Normal file
View File

@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __VARIANT_EC_H__
#define __VARIANT_EC_H__
#include <baseboard/ec.h>
#endif

8
src/mainboard/google/brya/variants/quandiso/include/variant/gpio.h Normal file
View File

@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <baseboard/gpio.h>
#endif

5
src/mainboard/google/brya/variants/quandiso/memory/Makefile.inc Normal file
View File

@@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
SPD_SOURCES = placeholder

1
src/mainboard/google/brya/variants/quandiso/memory/dram_id.generated.txt Normal file
View File

@@ -0,0 +1 @@
DRAM Part Name ID to assign

11
src/mainboard/google/brya/variants/quandiso/memory/mem_parts_used.txt Normal file
View File

@@ -0,0 +1,11 @@
# This is a CSV file containing a list of memory parts used by this variant.
# One part per line with an optional fixed ID in column 2.
# Only include a fixed ID if it is required for legacy reasons!
# Generated IDs are dependent on the order of parts in this file,
# so new parts must always be added at the end of the file!
#
# Generate an updated Makefile.inc and dram_id.generated.txt by running the
# part_id_gen tool from util/spd_tools.
# See util/spd_tools/README.md for more details and instructions.
# Part Name

6
src/mainboard/google/brya/variants/quandiso/overridetree.cb Normal file
View File

@@ -0,0 +1,6 @@
chip soc/intel/alderlake
device domain 0 on
end
end

19
src/mainboard/google/brya/variants/taeko/overridetree.cb
View File

@@ -137,6 +137,25 @@ chip soc/intel/alderlake
[PchSerialIoIndexI2C5] = PchSerialIoPci,
}"
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "3"
# DDIA for eDP
register "device[0].name" = ""LCD""
# DDIB is unused and HDMI is not enumerated in the kernel, so no GFX device is added for DDIB
# TCP0 (DP-1) for port C0
register "device[1].name" = ""DD01""
register "device[1].use_pld" = "true"
register "device[1].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
# TCP1 is unused and not enumerated in the kernel, so no GFX device is added for TCP1
# TCP2 (DP-2) for port C1
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
# TCP3 is unused and not enumerated in the kernel, so no GFX device is added for TCP3
device generic 0 on end
end
end # Integrated Graphics Device
device ref dtt on
chip drivers/intel/dptf
## sensor information

19
src/mainboard/google/brya/variants/taeko4es/overridetree.cb
View File

@@ -118,6 +118,25 @@ chip soc/intel/alderlake
[PchSerialIoIndexI2C5] = PchSerialIoPci,
}"
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "3"
# DDIA for eDP
register "device[0].name" = ""LCD""
# DDIB is unused and HDMI is not enumerated in the kernel, so no GFX device is added for DDIB
# TCP0 (DP-1) for port C0
register "device[1].name" = ""DD01""
register "device[1].use_pld" = "true"
register "device[1].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
# TCP1 is unused and not enumerated in the kernel, so no GFX device is added for TCP1
# TCP2 (DP-2) for port C1
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
# TCP3 is unused and not enumerated in the kernel, so no GFX device is added for TCP3
device generic 0 on end
end
end # Integrated Graphics Device
device ref dtt on
chip drivers/intel/dptf
## sensor information

19
src/mainboard/google/brya/variants/taniks/overridetree.cb
View File

@@ -114,6 +114,25 @@ chip soc/intel/alderlake
[PchSerialIoIndexI2C5] = PchSerialIoPci,
}"
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "3"
# DDIA for eDP
register "device[0].name" = ""LCD""
# DDIB is unused and HDMI is not enumerated in the kernel, so no GFX device is added for DDIB
# TCP0 (DP-1) for port C0
register "device[1].name" = ""DD01""
register "device[1].use_pld" = "true"
register "device[1].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
# TCP1 is unused and not enumerated in the kernel, so no GFX device is added for TCP1
# TCP2 (DP-2) for port C1
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
# TCP3 is unused and not enumerated in the kernel, so no GFX device is added for TCP3
device generic 0 on end
end
end # Integrated Graphics Device
device ref dtt on
chip drivers/intel/dptf
## sensor information

19
src/mainboard/google/brya/variants/vell/overridetree.cb
View File

@@ -95,9 +95,26 @@ chip soc/intel/alderlake
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "1"
register "device_count" = "5"
# DDIA for eDP
register "device[0].name" = ""LCD""
# DDIB is unused and HDMI is not enumerated in the kernel, so no GFX device is added for DDIB
# TCP0 (DP-1) for port C0
register "device[1].name" = ""DD01""
register "device[1].use_pld" = "true"
register "device[1].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
# TCP1 (DP-2) for port C1
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
# TCP2 (DP-3) for port C2
register "device[3].name" = ""DD03""
register "device[3].use_pld" = "true"
register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))"
# TCP3 (DP-4) for port C3
register "device[4].name" = ""DD04""
register "device[4].use_pld" = "true"
register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))"
device generic 0 on end
end
end # Integrated Graphics Device

22
src/mainboard/google/brya/variants/volmar/overridetree.cb
View File

@@ -88,6 +88,28 @@ chip soc/intel/alderlake
device ref tbt_pcie_rp2 off end
device ref tcss_dma0 off end
device ref tcss_dma1 off end
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "6"
# DDIA for eDP
register "device[0].name" = ""LCD""
# DDIB for HDMI
register "device[1].name" = ""DD01""
# TCP0 (DP-1) for port C0
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
register "device[3].name" = ""DD03""
# TCP2 (DP-3) for port C1
register "device[4].name" = ""DD04""
register "device[4].use_pld" = "true"
register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
register "device[5].name" = ""DD05""
device generic 0 on end
end
end # Integrated Graphics Device
device ref dtt on
chip drivers/intel/dptf
## sensor information

11
src/mainboard/google/brya/variants/yaviks/fw_config.c
View File

@@ -61,6 +61,11 @@ static const struct pad_config sd_disable_pads[] = {
PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
};
static const struct pad_config disable_wifi_pch_susclk[] = {
/* GPD8 ==> NC */
PAD_NC(GPD8, NONE),
};
void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
{
if (fw_config_is_provisioned() && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) {
@@ -83,4 +88,10 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
gpio_padbased_override(padbased_table, sd_disable_pads,
ARRAY_SIZE(sd_disable_pads));
}
/* SAR_ID_3 for MT7922 */
if (fw_config_probe(FW_CONFIG(WIFI_SAR_ID, SAR_ID_3))) {
printk(BIOS_INFO, "Disable PCH SUSCLK.\n");
gpio_padbased_override(padbased_table, disable_wifi_pch_susclk,
ARRAY_SIZE(disable_wifi_pch_susclk));
}
}

5
src/mainboard/google/brya/variants/yaviks/overridetree.cb
View File

@@ -1,12 +1,15 @@
fw_config
field DB_USB 0 1
option DB_NONE 0
option DB_1A 0
option DB_1C_1A 1
option DB_1C 2
option DB_1C_LTE 3
end
field WIFI_SAR_ID 2 3
option SAR_ID_0 0
option SAR_ID_1 1
option SAR_ID_2 2
option SAR_ID_3 3
end
field STYLUS 9
option STYLUS_ABSENT 0

1
src/mainboard/google/dedede/Kconfig.name
View File

@@ -208,6 +208,7 @@ config BOARD_GOOGLE_TARANZA
select RT8168_GEN_ACPI_POWER_RESOURCE
select RT8168_GET_MAC_FROM_VPD
select RT8168_SET_LED_MODE
select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
config BOARD_GOOGLE_BOXY
bool "-> Boxy"

2
src/mainboard/google/dedede/variants/boxy/overridetree.cb
View File

@@ -222,7 +222,7 @@ chip soc/intel/jasperlake
end # I2C 4
device pci 1c.2 on
chip drivers/net
register "customized_leds" = "0x05af"
register "customized_leds" = "0x07af"
register "wake" = "GPE0_DW0_03" # GPP_B3
register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
register "device_index" = "0"

12
src/mainboard/google/dedede/variants/pirika/overridetree.cb
View File

@@ -51,12 +51,22 @@ chip soc/intel/jasperlake
}"
# USB Port Configuration
register "usb2_ports[0]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-C Port C0
register "usb2_ports[2]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A
}" # Type-A Port A0
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[7]" = "{
.enable = 1,

2
src/mainboard/google/dedede/variants/taranza/Makefile.inc
View File

@@ -1,3 +1,5 @@
## SPDX-License-Identifier: GPL-2.0-or-later
ramstage-y += gpio.c
ramstage-y += variant.c

8
src/mainboard/google/dedede/variants/taranza/variant.c Normal file
View File

@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <sar.h>
const char *get_wifi_sar_cbfs_filename(void)
{
return "wifi_sar-taranza.hex";
}

1
src/mainboard/google/rex/Kconfig
View File

@@ -48,6 +48,7 @@ config BOARD_GOOGLE_BASEBOARD_REX
config BOARD_GOOGLE_MODEL_REX
def_bool n
select BOARD_GOOGLE_BASEBOARD_REX
select CHROMEOS_WIFI_SAR if CHROMEOS
select DRIVERS_GENERIC_MAX98357A
select DRIVERS_GENESYSLOGIC_GL9755
select DRIVERS_INTEL_ISH

64
src/mainboard/google/rex/variants/karis/gpio.c
View File

@@ -28,10 +28,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_A12, 0, DEEP),
/* GPP_A13 : Not connected */
PAD_NC(GPP_A13, NONE),
/* GPP_A14 : [] ==> WWAN_RF_DISABLE_ODL */
PAD_NC_LOCK(GPP_A14, NONE, LOCK_CONFIG),
/* GPP_A15 : [] ==> WWAN_RST_L */
PAD_CFG_GPO(GPP_A15, 1, DEEP),
/* GPP_A14 : NC pad. */
PAD_NC(GPP_A14, NONE),
/* GPP_A15 : NC pad. */
PAD_NC(GPP_A15, NONE),
/* GPP_A16 : GPP_A16 ==> ESPI_SOC_ALERT_L */
PAD_CFG_NF_IOSSTATE(GPP_A16, UP_20K, DEEP, NF1, IGNORE),
/* GPP_A17 : [] ==> EC_SOC_INT_ODL */
@@ -43,8 +43,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_A19, 1, DEEP),
/* GPP_A20 : [] ==> SSD_PERST_L */
PAD_CFG_GPO_LOCK(GPP_A20, 1, LOCK_CONFIG),
/* GPP_A21 : [] ==> WWAN_CONFIG2 */
PAD_CFG_GPI(GPP_A21, NONE, DEEP),
/* GPP_A21 : [] ==> PMCALERT */
PAD_NC(GPP_A21, NONE),
/* GPP_B00 : [] ==> TCHPAD_INT_ODL_LS */
PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_B00, NONE, LEVEL, INVERT, LOCK_CONFIG),
@@ -80,8 +80,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF_LOCK(GPP_B15, NONE, NF1, LOCK_CONFIG),
/* GPP_B16 : [] ==> SOC_HDMI_HPD_L */
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
/* GPP_B17 : [] ==> EN_WWAN_PWR */
PAD_CFG_GPO(GPP_B17, 1, DEEP),
/* GPP_B17 : NC pad. */
PAD_NC(GPP_B17, NONE),
/* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */
PAD_CFG_NF_LOCK(GPP_B18, NONE, NF2, LOCK_CONFIG),
/* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */
@@ -92,8 +92,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF_LOCK(GPP_B21, NONE, NF2, LOCK_CONFIG),
/* GPP_B22 : [] ==> USB4_RT_FORCE_PWR */
PAD_CFG_GPO(GPP_B22, 0, DEEP),
/* GPP_B23 : [] ==> WWAN_CONFIG0 */
PAD_CFG_GPI_LOCK(GPP_B23, NONE, LOCK_CONFIG),
/* GPP_B23 : NC pad. */
PAD_NC(GPP_B23, NONE),
/* GPP_C00 : [] ==> EN_TCHSCR_PWR */
PAD_CFG_GPO(GPP_C00, 0, DEEP),
@@ -106,9 +106,11 @@ static const struct pad_config gpio_table[] = {
/* GPP_C04 : net NC. */
PAD_NC(GPP_C04, NONE),
/* GPP_C05 : [] ==> WWAN_PERST_L_STRAP */
PAD_CFG_GPO(GPP_C05, 1, PLTRST),
PAD_NC(GPP_C05, NONE),
/* GPP_C06 : [] ==> SOC_TCHSCR_RPT_EN */
PAD_CFG_GPO(GPP_C06, 0, DEEP),
/* GPP_C07 : [] ==> SOC_TCHSCR_INT */
PAD_CFG_GPI_APIC(GPP_C07, NONE, PLTRST, LEVEL, NONE),
/* GPP_C08 : [] ==> SOCHOT_ODL */
PAD_CFG_NF(GPP_C08, NONE, DEEP, NF2),
/* GPP_C09 : net NC is not present in the given design */
@@ -117,12 +119,12 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_C10, NONE),
/* GPP_C11 : Not Connected */
PAD_NC(GPP_C11, NONE),
/* GPP_C12 : [] ==> WWAN_CLKREQ_ODL */
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
/* GPP_C12 : NC pad. */
PAD_NC(GPP_C12, NONE),
/* GPP_C13 : Not connected */
PAD_NC(GPP_C13, NONE),
/* GPP_C15 : [] ==> WWAN_DPR_SAR_ODL */
PAD_CFG_GPO(GPP_C15, 1, DEEP),
PAD_NC(GPP_C15, NONE),
/* GPP_C16 : [] ==> USB_C0_LSX_TX */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
/* GPP_C17 : [] ==> USB_C0_LSX_RX */
@@ -199,8 +201,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_E05, 1, DEEP),
/* GPP_E06 : GPP_E06_STRAP ==> Component NC */
PAD_NC(GPP_E06, NONE),
/* GPP_E07 : [] ==> WWAN_FCPO_L */
PAD_CFG_GPO(GPP_E07, 1, DEEP),
/* GPP_E07 : NC pad. */
PAD_NC(GPP_E07, NONE),
/* GPP_E08 : [] ==> SAR2_INT_L */
PAD_CFG_GPI_APIC_LOCK(GPP_E08, NONE, LEVEL, NONE, LOCK_CONFIG),
/* GPP_E09 : Not Connected */
@@ -244,24 +246,24 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_F08, 1, DEEP),
/* GPP_F09 : [] ==> WLAN_PE_WAKE_ODL */
PAD_CFG_GPI_IRQ_WAKE(GPP_F09, NONE, PLTRST, LEVEL, INVERT),
/* GPP_F10 : [] ==> WWAN_PCIE_WAKE_ODL */
PAD_CFG_GPI_IRQ_WAKE(GPP_F10, NONE, PLTRST, LEVEL, INVERT),
/* GPP_F10 : NC pad. */
PAD_NC(GPP_F10, NONE),
/* GPP_F11 : GSP1_SOC_CLK_R */
PAD_CFG_NF(GPP_F11, NONE, DEEP, NF5),
/* GPP_F12 : GSPI1_SOC_DO_FPMCU_DI_R */
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF5),
/* GPP_F13 : GSPI1_SOC_DI_FPMCU_DO_LS_R */
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF5),
/* GPP_F14 : GSPI0_SOC_DO_TCHSCR_DI */
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
/* GPP_F15 : [] ==> GSPI0_SOC_DI_TCHSCR_DO */
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
/* GPP_F16 : [] ==> GSPI0_SOC_TCHSCR_CLK */
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
/* GPP_F14 : net NC. */
PAD_NC(GPP_F14, NONE),
/* GPP_F15 : net NC. */
PAD_NC(GPP_F15, NONE),
/* GPP_F16 : net NC. */
PAD_NC(GPP_F16, NONE),
/* GPP_F17 : [] ==> GSPI1_SOC_CS_L */
PAD_CFG_NF(GPP_F17, NONE, DEEP, NF5),
/* GPP_F18 : [] ==> GSPI0_SOC_TCHSCR_CS_L */
PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8),
/* GPP_F18 : net NC. */
PAD_NC(GPP_F18, NONE),
/* GPP_F19 : [] ==> GPP_F19_STRAP */
PAD_NC(GPP_F19, NONE),
/* GPP_F20 : [] ==> GPP_F20_STRAP */
@@ -365,21 +367,13 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* GPP_B17 : [] ==> EN_WWAN_PWR */
PAD_CFG_GPO(GPP_B17, 1, DEEP),
/* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2),
/* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */
PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2),
/* GPP_C05 : [] ==> WWAN_PERST_L_STRAP (updated in ramstage) */
PAD_CFG_GPO(GPP_C05, 0, DEEP),
/* GPP_A15 : [] ==> WWAN_RST_L (updated in ramstage) */
PAD_CFG_GPO(GPP_A15, 0, DEEP),
/* GPP_E03 : [] ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT),
/* GPP_E07 : [] ==> WWAN_FCPO_L (updated in romstage) */
PAD_CFG_GPO(GPP_E07, 0, DEEP),
/* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
/* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */
@@ -405,8 +399,6 @@ static const struct pad_config romstage_gpio_table[] = {
PAD_CFG_GPO(GPP_A20, 0, DEEP),
/* GPP_C23 : [] ==> FP_RST_ODL */
PAD_CFG_GPO(GPP_C23, 0, DEEP),
/* GPP_E07 : [] ==> WWAN_FCPO_L */
PAD_CFG_GPO(GPP_E07, 1, DEEP),
/* GPP_D02 : Not Connected */
PAD_NC(GPP_D02, NONE),
};

4
src/mainboard/google/rex/variants/karis/memory/Makefile.inc
View File

@@ -1,9 +1,9 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
# util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/google/rex/variants/karis/memory/ src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt
# util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/google/rex/variants/karis/memory src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt
SPD_SOURCES =
SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 0(0b0000) Parts = MT62F1G32D2DS-023 WT:B, H58G56BK8BX068
SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E
SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E, MT62F512M32D2DR-031 WT:B
SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 2(0b0010) Parts = K3KL8L80CM-MGCT

3
src/mainboard/google/rex/variants/karis/memory/dram_id.generated.txt
View File

@@ -1,10 +1,11 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
# util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/google/rex/variants/karis/memory/ src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt
# util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/google/rex/variants/karis/memory src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt
DRAM Part Name ID to assign
MT62F1G32D2DS-023 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 1 (0001)
H58G56BK8BX068 0 (0000)
K3KL8L80CM-MGCT 2 (0010)
MT62F512M32D2DR-031 WT:B 1 (0001)

1
src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt
View File

@@ -13,3 +13,4 @@ MT62F1G32D2DS-023 WT:B
H9JCNNNBK3MLYR-N6E
H58G56BK8BX068
K3KL8L80CM-MGCT
MT62F512M32D2DR-031 WT:B

63
src/mainboard/google/rex/variants/karis/overridetree.cb
View File

@@ -4,11 +4,6 @@ fw_config
option MAX98360_ALC5682I_I2S 1
option MAX98363_CS42L42_SNDW 2
end
field CELLULAR 4 5
option CELLULAR_ABSENT 0
option CELLULAR_USB 1
option CELLULAR_PCIE 2
end
field UFC 6 7
option UFC_USB 0
option UFC_MIPI 1
@@ -34,10 +29,6 @@ fw_config
option WIFI_CNVI 0
option WIFI_PCIE 1
end
field TOUCHSCREEN 19
option TOUCHSCREEN_I2C 0
option TOUCHSCREEN_I2C_SPI 1
end
field VPU 20
option VPU_DIS 0
option VPU_EN 1
@@ -73,7 +64,7 @@ chip soc/intel/meteorlake
}"
register "serial_io_gspi_mode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoPci,
[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI1] = PchSerialIoPci,
[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
}"
@@ -162,7 +153,6 @@ chip soc/intel/meteorlake
register "options.tsr[0].desc" = ""DDR_SOC""
register "options.tsr[1].desc" = ""Ambient""
register "options.tsr[2].desc" = ""Charger""
register "options.tsr[3].desc" = ""wwan""
## Active Policy
# FIXME: below values are initial reference values only
@@ -199,18 +189,6 @@ chip soc/intel/meteorlake
TEMP_PCT(65, 70),
TEMP_PCT(60, 50),
}
},
[3] = {
.target = DPTF_TEMP_SENSOR_3,
.thresholds = {
TEMP_PCT(75, 90),
TEMP_PCT(70, 80),
TEMP_PCT(65, 70),
TEMP_PCT(60, 60),
TEMP_PCT(55, 50),
TEMP_PCT(50, 40),
TEMP_PCT(45, 30),
}
}
}"
@@ -221,7 +199,6 @@ chip soc/intel/meteorlake
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000),
[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 80, 5000),
}"
## Critical Policy
@@ -231,7 +208,6 @@ chip soc/intel/meteorlake
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
}"
## Power Limits Control
@@ -436,9 +412,7 @@ chip soc/intel/meteorlake
register "generic.stop_off_delay_ms" = "2"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 10 on
probe TOUCHSCREEN TOUCHSCREEN_I2C
end
device i2c 10 on end
end
chip drivers/generic/gpio_keys
register "name" = ""PENH""
@@ -567,39 +541,6 @@ chip soc/intel/meteorlake
end
end
end #PCIE5 WLAN card
device ref pcie_rp6 on
probe CELLULAR CELLULAR_PCIE
# Enable WWAN Card PCIE 6 using clk 3
register "pcie_rp[PCH_RP(6)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C05)"
register "reset_off_delay_ms" = "20"
register "srcclk_pin" = "3"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "skip_on_off_support" = "true"
device generic 0 alias rp6_rtd3 on
probe CELLULAR CELLULAR_PCIE
end
end
chip drivers/wwan/fm
register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E07)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A15)"
register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C05)"
register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)"
register "add_acpi_dma_property" = "true"
use rp6_rtd3 as rtd3dev
device generic 0 alias rp6_wwan on
probe CELLULAR CELLULAR_PCIE
end
end
end #PCIE6 WWAN card
device ref gspi0 on
probe TOUCHSCREEN TOUCHSCREEN_I2C_SPI
end
device ref gspi1 on
chip drivers/spi/acpi
register "name" = ""CRFP""

2
src/mainboard/google/rex/variants/ovis/gpio.c
View File

@@ -69,7 +69,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_B07 : [] ==> RST_HP_L */
PAD_CFG_GPO(GPP_B07, 1, DEEP),
/* GPP_B08 : [] ==> PWM_BUZZER */
PAD_CFG_NF(GPP_B08, NONE, DEEP, NF2),
PAD_CFG_GPO(GPP_B08, 0, DEEP),
/* GPP_B09 : [] ==> GPP_B09 */
PAD_NC(GPP_B09, NONE),
/* GPP_B10 : [] ==> WIFI_DISABLE_L */

2
src/mainboard/google/rex/variants/rex0/variant.c
View File

@@ -12,7 +12,7 @@
const char *get_wifi_sar_cbfs_filename(void)
{
return "wifi_sar_0.hex";
return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
}
void variant_generate_s0ix_hook(enum s0ix_entry entry)

4
src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb
View File

@@ -9,9 +9,9 @@ chip northbridge/intel/sandybridge
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x3" # 0x1: 2.5" slot
register "sata_port_map" = "0x7" # 0x1: 2.5" slot
# 0x2: DVD
# 0x?: mSATA
# 0x4: mSATA
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
register "superspeed_capable_ports" = "0x0000000f"

29
src/mainboard/siemens/fa_ehl/Kconfig Normal file
View File

@@ -0,0 +1,29 @@
config BOARD_SIEMENS_BASEBOARD_FA_EHL
def_bool n
select SOC_INTEL_ELKHARTLAKE
select BOARD_ROMSIZE_KB_16384
select DRIVERS_I2C_GENERIC
select HAVE_ACPI_TABLES
select USE_SIEMENS_HWILIB
select SOC_INTEL_DISABLE_POWER_LIMITS
source "src/mainboard/siemens/fa_ehl/variants/*/Kconfig"
if BOARD_SIEMENS_BASEBOARD_FA_EHL
config MAINBOARD_DIR
default "siemens/fa_ehl"
config VARIANT_DIR
default "fa_ehl" if BOARD_SIEMENS_FA_EHL
config MAINBOARD_PART_NUMBER
default "FA EHL" if BOARD_SIEMENS_FA_EHL
config DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
config SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN
default y
endif # BOARD_SIEMENS_BASEBOARD_FA_EHL

5
src/mainboard/siemens/fa_ehl/Kconfig.name Normal file
View File

@@ -0,0 +1,5 @@
comment "FA EHL"
config BOARD_SIEMENS_FA_EHL
bool "-> FA EHL"
select BOARD_SIEMENS_BASEBOARD_FA_EHL

14
src/mainboard/siemens/fa_ehl/Makefile.inc Normal file
View File

@@ -0,0 +1,14 @@
## SPDX-License-Identifier: GPL-2.0-only
subdirs-y += spd
bootblock-y += bootblock.c
romstage-y += romstage_fsp_params.c
ramstage-y += mainboard.c
subdirs-y += variants/baseboard
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
subdirs-y += variants/$(VARIANT_DIR)

5
src/mainboard/siemens/fa_ehl/board_info.txt Normal file
View File

@@ -0,0 +1,5 @@
Vendor name: Siemens
Board name: FA EHL
Category: misc
ROM protocol: SPI
ROM socketed: n

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