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1 Commits
4.21 ... 4.20.1

Author SHA1 Message Date
Srinidhi N Kaushik
506ff8fb9e src/vc/intel/fsp/fsp2_0/sapphirerapids_sp: Update Spr header files 
This change updates Intel Copyright License for all header files
under Sapphirerapids dir

Cherry-picked from commit 7e2106627d.

Original-Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/75393
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Original-Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>

Change-Id: Ib04988194e5fe9515bea8620318eadff36f92181
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75469
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-06-01 13:06:21 +00:00
2861 changed files with 75361 additions and 105228 deletions
Expand all files Collapse all files

2
3rdparty/amd_blobs vendored

Submodule 3rdparty/amd_blobs updated: 6a1e1457af...acf7395452

2
3rdparty/arm-trusted-firmware vendored

Submodule 3rdparty/arm-trusted-firmware updated: 37366af8d4...4c985e8674

2
3rdparty/blobs vendored

Submodule 3rdparty/blobs updated: a8db7dfe82...01ba15667f

2
3rdparty/fsp vendored

Submodule 3rdparty/fsp updated: 3beceb01f9...6f2f17f3d3

2
3rdparty/intel-microcode vendored

Submodule 3rdparty/intel-microcode updated: 6f36ebde45...2be47edc99

2
3rdparty/libgfxinit vendored

Submodule 3rdparty/libgfxinit updated: a4be8a21b0...066e52eeaa

2
3rdparty/libhwbase vendored

Submodule 3rdparty/libhwbase updated: 584629b9f4...8be5a82b85

2
3rdparty/qc_blobs vendored

Submodule 3rdparty/qc_blobs updated: a252198ec6...33cc4f2fd8

2
3rdparty/vboot vendored

Submodule 3rdparty/vboot updated: 0c11187c75...35f50c3154

38
Documentation/Makefile
View File

@@ -4,12 +4,11 @@
# hacked together by Stefan Reinauer <stepan@openbios.org>
#
PDFLATEX = pdflatex -t a4
BUILDDIR ?= _build
PDFLATEX=pdflatex -t a4
FIGS=codeflow.pdf hypertransport.pdf
all: sphinx corebootPortingGuide.pdf
all: corebootPortingGuide.pdf
SVG2PDF=$(shell command -v svg2pdf)
INKSCAPE=$(shell command -v inkscape)
@@ -33,9 +32,6 @@ else ifneq ($(strip $(CONVERT)),)
convert $< $@
endif
$(BUILDDIR):
mkdir -p $(BUILDDIR)
corebootPortingGuide.toc: $(FIGS) corebootBuildingGuide.tex
# 2 times to make sure we have a current toc.
$(PDFLATEX) corebootBuildingGuide.tex
@@ -44,11 +40,11 @@ corebootPortingGuide.toc: $(FIGS) corebootBuildingGuide.tex
corebootPortingGuide.pdf: $(FIGS) corebootBuildingGuide.tex corebootPortingGuide.toc
$(PDFLATEX) corebootBuildingGuide.tex
sphinx: $(BUILDDIR)
$(MAKE) -f Makefile.sphinx html BUILDDIR="$(BUILDDIR)"
sphinx:
$(MAKE) -f Makefile.sphinx html
clean-sphinx:
$(MAKE) -f Makefile.sphinx clean BUILDDIR="$(BUILDDIR)"
$(MAKE) -f Makefile.sphinx clean
clean: clean-sphinx
rm -f *.aux *.idx *.log *.toc *.out $(FIGS)
@@ -56,25 +52,5 @@ clean: clean-sphinx
distclean: clean
rm -f corebootPortingGuide.pdf
livesphinx: $(BUILDDIR)
$(MAKE) -f Makefile.sphinx livehtml SPHINXOPTS="$(SPHINXOPTS)" BUILDDIR="$(BUILDDIR)"
test:
@echo "Test for logging purposes - Failing tests will not fail the build"
-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx html
-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx doctest
help:
@echo "all - Builds coreboot porting guide PDF (outdated)"
@echo "sphinx - Builds html documentation in _build directory"
@echo "clean - Cleans intermediate files"
@echo "clean-sphinx - Removes sphinx output files"
@echo "distclean - Removes PDF files as well"
@echo "test - Runs documentation tests"
@echo
@echo " Makefile.sphinx builds - run with $(MAKE) -f Makefile-sphinx [target]"
@echo
@$(MAKE) -s -f Makefile.sphinx help 2>/dev/null
.phony: help livesphinx sphinx test
.phony: distclean clean clean-sphinx
livesphinx:
$(MAKE) -f Makefile.sphinx livehtml SPHINXOPTS="$(SPHINXOPTS)"

11
Documentation/community/code_of_conduct.md
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@@ -95,17 +95,6 @@ If you feel you have been falsely or unfairly accused of violating this
Code of Conduct, you should notify the arbitration team with a concise
description of your grievance.
## Legal action
Threatening or starting legal action against the project, sibling
projects hosted on coreboot.org infrastructure, project or infrastructure
maintainers leads to an immediate ban from coreboot.org and related
systems.
The ban can be reconsidered, but it's the default action because the
people who pour lots of time and money into the projects aren't interested
in seeing their resources used against them.
## Scope
We expect all community participants (contributors, paid or otherwise;

2
Documentation/community/forums.md
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@@ -14,7 +14,7 @@ read its
## Real time chat
We also have a real time chat room on [IRC](ircs://irc.libera.chat/#coreboot),
also bridged to [Matrix](https://matrix.to/#/#coreboot:matrix.org) and a
also bridged to [Matrix](https://matrix.to/#/#coreboot:libera.chat) and a
[Discord](https://discord.gg/JqT8NM5Zbg) presence. You can also find us on
[OSF Slack](https://osfw.slack.com/), which has channels on many open source
firmware related topics. Slack requires that people come from specific domains

10
Documentation/conf.py
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@@ -55,7 +55,7 @@ else:
#
# This is also used if you do content translation via gettext catalogs.
# Usually you set "language" from the command line for these cases.
language = 'en'
language = None
# List of patterns, relative to source directory, that match files and
# directories to ignore when looking for source files.
@@ -87,9 +87,11 @@ html_theme = 'sphinx_rtd_theme'
# so a file named "default.css" will overwrite the builtin "default.css".
html_static_path = ['_static']
html_css_files = [
'theme_overrides.css', # override wide tables in RTD theme
]
html_context = {
'css_files': [
'_static/theme_overrides.css', # override wide tables in RTD theme
],
}
# Output file base name for HTML help builder.
htmlhelp_basename = 'corebootdoc'

2
Documentation/getting_started/devicetree.md
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@@ -79,7 +79,7 @@ with no properties as a direct child of the SoC.
## Device drivers
Platform independent device drivers are hooked up via entries in a devicetree.
See [Driver Devicetree Entries](../drivers/dt_entries.md) for more info.
See [Driver Devicetree Entries](drivers/dt_entries.md) for more info.
## Notes

66
Documentation/mainboard/hp/compaq_8300_usdt.md
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@@ -1,66 +0,0 @@
# HP Compaq 8300 Elite USDT
This page describes how to run coreboot on the [Compaq 8300 Elite USDT] desktop
from [HP].
## Flashing coreboot
```eval_rst
+---------------------+-------------+
| Type | Value |
+=====================+=============+
| Socketed flash | no |
+---------------------+-------------+
| Model | W25Q128BVFG |
+---------------------+-------------+
| Size | 16 MiB |
+---------------------+-------------+
| In circuit flashing | yes |
+---------------------+-------------+
| Package | SOIC-16 |
+---------------------+-------------+
| Write protection | No |
+---------------------+-------------+
| Dual BIOS feature | No |
+---------------------+-------------+
```
### Internal programming
TODO: investigate
The board has two jumpers that might be relevant: FDO (Flash Descriptor Override) and BB (?).
### External programming
Remove the lid. The flash chip can be found on the edge opposite to the CPU.
There is a spot for a "ROM RCVRY" header next to the flash chip but it is
unpopulated. If you don't feel like using a clip, you can easily solder
a standard pin header there yourself and use it for programming.
Programming powers some parts of the board. Programming when
Wake on LAN is active works great.
## Technology
```eval_rst
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+
| Southbridge | bd82x6x |
+------------------+--------------------------------------------------+
| CPU | model_206ax |
+------------------+--------------------------------------------------+
| SuperIO | NPCD379HAKFX |
+------------------+--------------------------------------------------+
| Coprocessor | Intel ME |
+------------------+--------------------------------------------------+
```
### SuperIO
This board has a Nuvoton NPCD379 SuperIO chip. Fan speed and PS/2 keyboard work
fine using coreboot's existing code for :doc:`../../superio/nuvoton/npcd378`.
[Compaq 8300 USDT]: https://support.hp.com/gb-en/product/hp-compaq-elite-8300-ultra-slim-pc/5232866
[HP]: https://www.hp.com/

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141
Documentation/mainboard/hp/elitebook_820_g2.md
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@@ -1,141 +0,0 @@
# HP EliteBook 820 G2
This page is about the notebook [HP EliteBook 820 G2].
## Release status
HP EliteBook 820 G2 was released in 2015 and is now end of life.
It can be bought from a secondhand market like Taobao or eBay.
## Required proprietary blobs
The following blobs are required to operate the hardware:
1. EC firmware
2. Intel ME firmware
3. Broadwell mrc.bin and refcode.elf
HP EliteBook 820 G2 uses SMSC MEC1324 as its embedded controller.
The EC firmware is stored in the flash chip, but we don't need to touch it
or use it in the coreboot build process.
Intel ME firmware is in the flash chip. It is not needed when building coreboot.
The Broadwell memory reference code binary and reference code blob is needed
when building coreboot. Read the document [Blobs used in Intel Broadwell boards]
on how to get these blobs.
## Programming
Before flashing, remove the battery and the hard drive cover according to the
[Maintenance and Service Guide] of this laptop.
HP EliteBook 820 G2 has two flash chips, a 16MiB system flash, and a 2MiB
private flash. To install coreboot, we need to program both flash chips.
Read [HP Sure Start] for detailed information.
![HP EliteBook 820 G2 flash chip](elitebook_820_g2_flash.jpg)
To access the system flash, we need to connect the AC adapter to the machine,
then clip on the flash chip with an SOIC-8 clip. An [STM32-based flash programmer]
made with an STM32 development board is tested to work.
To access the private flash chip, we can use a ch341a based flash programmer and
flash the chip with the AC adapter disconnected.
To flash coreboot on a board running OME firmware, create a backup for both flash
chips, then do the following:
1. Erase the private flash to disable the IFD protection
2. Modify the IFD to shrink the BIOS region, so that we can put the firmware outside
the protected flash region
To erase the private flash chip, attach it with the flash programmer via the SOIC-8 clip,
then run:
flashrom -p <programmer> --erase
To modify the IFD, write the following flash layout to a file:
00000000:00000fff fd
00001000:00002fff gbe
00003000:005fffff me
00600000:00bfffff bios
00eb5000:00ffffff pd
Suppose the above layout file is ``layout.txt`` and the origin content of the system flash
is in ``factory-sys.rom``, run:
ifdtool -n layout.txt factory-sys.rom
Then a flash image with a new IFD will be in ``factory-sys.rom.new``.
Flash the IFD of the system flash:
flashrom -p <programmer> --ifd -i fd -w factory-sys.rom.new
Then flash the coreboot image:
# first extend the 12M coreboot.rom to 16M
fallocate -l 16M build/coreboot.rom
flashrom -p <programmer> --ifd -i bios -w build/coreboot.rom
After coreboot is installed, the coreboot firmware can be updated with internal flashing:
flashrom -p internal --ifd -i bios --noverify-all -w build/coreboot.rom
## Debugging
The board can be debugged with EHCI debug. The EHCI debug port is the USB port on the left.
## Test status
### Untested
- NFC module
- Fingerprint reader
- Smart Card reader
### Working
- mainboards with i3-5010U, i5-5300U CPU, 16G+8G DDR3L memory
- SATA and M.2 SATA disk
- PCIe SSD
- Webcam
- Touch screen
- Audio output from speaker and headphone jack
- Intel GbE (needs a modified refcode documented in [Blobs used in Intel Broadwell boards])
- WLAN
- WWAN
- SD card reader
- Internal LCD, DisplayPort and VGA video outputs
- Dock
- USB
- Keyboard and touchpad
- EC ACPI
- S3 resume
- TPM
- Arch Linux with Linux 5.11.16
- Broadwell MRC version 2.6.0 Build 0 and refcode from Purism Librem 13 v1
- Graphics initialization with libgfxinit
- Payload: SeaBIOS 1.16.2
- EC firmware: KBC Revision 96.54 from OEM firmware version 01.05
- Internal flashing under coreboot
## Technology
```eval_rst
+------------------+-----------------------------+
| SoC | Intel Broadwell |
+------------------+-----------------------------+
| EC | SMSC MEC1324 |
+------------------+-----------------------------+
| Coprocessor | Intel Management Engine |
+------------------+-----------------------------+
```
[HP EliteBook 820 G2]: https://support.hp.com/us-en/product/HP-EliteBook-820-G2-Notebook-PC/7343192/
[Blobs used in Intel Broadwell boards]: ../../soc/intel/broadwell/blobs.md
[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c04775894.pdf
[STM32-based flash programmer]: https://github.com/dword1511/stm32-vserprog
[HP Sure Start]: hp_sure_start.md

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10
Documentation/mainboard/index.md
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@@ -85,7 +85,6 @@ The boards in this section are not real mainboards, but emulators.
- [EliteBook 2560p](hp/2560p.md)
- [EliteBook 8760w](hp/8760w.md)
- [EliteBook Folio 9480m](hp/folio_9480m.md)
- [EliteBook 820 G2](hp/elitebook_820_g2.md)
## Intel
@@ -206,33 +205,24 @@ The boards in this section are not real mainboards, but emulators.
- [Adder Workstation 1](system76/addw1.md)
- [Adder Workstation 2](system76/addw2.md)
- [Adder Workstation 3](system76/addw3.md)
- [Bonobo Workstation 14](system76/bonw14.md)
- [Bonobo Workstation 15](system76/bonw15.md)
- [Darter Pro 6](system76/darp6.md)
- [Darter Pro 7](system76/darp7.md)
- [Darter Pro 8](system76/darp8.md)
- [Darter Pro 9](system76/darp9.md)
- [Galago Pro 4](system76/galp4.md)
- [Galago Pro 5](system76/galp5.md)
- [Galago Pro 6](system76/galp6.md)
- [Galago Pro 7](system76/galp7.md)
- [Gazelle 15](system76/gaze15.md)
- [Gazelle 16](system76/gaze16.md)
- [Gazelle 17](system76/gaze17.md)
- [Gazelle 18](system76/gaze18.md)
- [Lemur Pro 9](system76/lemp9.md)
- [Lemur Pro 10](system76/lemp10.md)
- [Lemur Pro 11](system76/lemp11.md)
- [Lemur Pro 12](system76/lemp12.md)
- [Oryx Pro 5](system76/oryp5.md)
- [Oryx Pro 6](system76/oryp6.md)
- [Oryx Pro 7](system76/oryp7.md)
- [Oryx Pro 8](system76/oryp8.md)
- [Oryx Pro 9](system76/oryp9.md)
- [Oryx Pro 10](system76/oryp10.md)
- [Oryx Pro 11](system76/oryp11.md)
- [Serval Workstation 13](system76/serw13.md)
## Texas Instruments

5
Documentation/mainboard/starlabs/labtop_cml.md
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@@ -41,7 +41,7 @@
## Building coreboot
Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_labtop_cml` as config file.
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_cml` as config file.
## Flashing coreboot
@@ -63,6 +63,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
+---------------------+------------+
| External flashing | yes |
+---------------------+------------+
```
Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

5
Documentation/mainboard/starlabs/labtop_kbl.md
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@@ -38,7 +38,7 @@
## Building coreboot
Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_labtop_kbl` as config file.
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_kbl` as config file.
## Flashing coreboot
@@ -60,6 +60,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
+---------------------+------------+
| External flashing | yes |
+---------------------+------------+
```
Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

5
Documentation/mainboard/starlabs/lite_glk.md
View File

@@ -37,7 +37,7 @@
## Building coreboot
Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_lite_glk` as config file.
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glk` as config file.
## Flashing coreboot
@@ -59,6 +59,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
+---------------------+------------+
| External flashing | yes |
+---------------------+------------+
```
Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

5
Documentation/mainboard/starlabs/lite_glkr.md
View File

@@ -37,7 +37,7 @@
## Building coreboot
Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_lite_glkr` as config file.
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glkr` as config file.
## Flashing coreboot
@@ -59,6 +59,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
+---------------------+------------+
| External flashing | yes |
+---------------------+------------+
```
Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

19
Documentation/mainboard/starlabs/starbook_adl.md
View File

@@ -5,8 +5,6 @@
- CPU (full processor specs available at https://ark.intel.com)
- Intel i7-1260P (Alder Lake)
- Intel i3-1220P (Alder Lake)
- Intel i3-1315U (Raptor Lake)
- Intel i7-1360P (Raptor Lake)
- EC
- ITE IT5570E
- Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys
@@ -35,15 +33,14 @@
- RTS5129 MicroSD card reader
- USB
- 1920x1080 CCD camera
- USB 3.1 Gen 2 (left) (Alder Lake)
- Thunderbolt 4.0 (left) (Raptor Lake)
- USB 3.1 Gen 2 (left)
- USB 3.1 Gen 2 Type-A (left)
- USB 3.1 Gen 1 Type-A (right)
- USB 2.0 Type-A (right)
## Building coreboot
Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
### Preliminaries
@@ -61,21 +58,12 @@ These files exist in the correct location in the StarLabsLtd/blobs repo on GitHu
The following commands will build a working image:
Alder Lake:
```bash
make distclean
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl
make
```
Raptor Lake:
```bash
make distclean
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_rpl
make
```
## Flashing coreboot
```eval_rst
@@ -96,6 +84,5 @@ make
+---------------------+------------+
| External flashing | yes |
+---------------------+------------+
```
Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

5
Documentation/mainboard/starlabs/starbook_tgl.md
View File

@@ -40,7 +40,7 @@
## Building coreboot
Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_tgl` as config file.
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_tgl` as config file.
## Flashing coreboot
@@ -62,6 +62,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
+---------------------+------------+
| External flashing | yes |
+---------------------+------------+
```
Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

71
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@@ -1,71 +0,0 @@
# System76 Adder Workstation 3 (addw3)
## Specs
- CPU
- Intel Core i9-13900HX
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- dGPU options
- NVIDIA GeForce RTX 4050
- NVIDIA GeForce RTX 4060
- NVIDIA GeForce RTX 4070
- eDP displays
- 15.6" 1920x1080@144Hz LCD
- 17.3" 1920x1080@144Hz LCD
- External outputs
- 1x HDMI 2.1
- 1x Mini DisplayPort 1.4
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 4800 MHz
- Networking
- Intel I219-V gigabit Ethernet
- M.2 PCIe/CNVi WiFi/Bluetooth
- Intel Wi-Fi 6E AX210/AX211
- Power
- 280W (20V, 14A) DC-in port
- Included: Chicony A18-280P1A
- 73Wh 4-cell Lithium-Ion battery
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- Dedicated 3.5mm microphone jack
- HDMI, mDP, USB-C DP audio
- Storage
- 2x M.2 (PCIe NVMe Gen 4) SSDs
- MicroSD card reader
- USB
- 1x USB Type-C with Thunderbolt 4
- 1x USB 3.2 Gen 2 Type-C
- 1x USB 3.2 Gen 1 Type-A
- 1x USB 2.0 Type-A
- Dimensions
- 15": 2.71cm x 35.95cm x 23.8cm, 2.05kg
- 17": 2.82cm x 39.69cm x 26.2cm, 2.85kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U65) is above the battery connector.

65
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@@ -1,65 +0,0 @@
# System76 Bonobo Workstation 15 (bonw15)
## Specs
- CPU
- Intel Core i9-13900HX
- Chipset
- Intel HM770
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- dGPU options:
- NVIDIA GeForce RTX 4080
- NVIDIA GeForce RTX 4090
- eDP 17.3" 3840x2160@144Hz LCD (BOE NE173QUM-NY1)
- 1x HDMI 2.1
- 1x Mini DisplayPort 1.4
- 2x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5200 Mhz
- Networking
- Onboard Intel Killer Ethernet E3100X 2.5 GbE
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
- Power
- 330W (19.5V, 16.42A) AC adapter (Chicony A20-330P1A)
- Rectangular connector; not a barrel connector
- 99Wh 8-cell Lithium-ion battery
- Sound
- Realtek ALC1220 codec
- Realtek ALC1318 smart amp
- Internal speakers and microphone
- Combined 3.5mm headphone & microphone jack
- Combined 3.5mm microphone & S/PDIF jack
- HDMI, mDP, USB-C DP audio
- Storage
- 3x M.2 PCIe NVMe Gen 4 SSDs
- USB
- 2x USB Type-C with Thunderbolt 4
- 2x USB 3.2 Gen 2 Type-A
- Dimensions
- 2.49cm x 39.6cm x 27.8cm, 3.29kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U58) is next to the left M.2 port.

62
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@@ -1,62 +0,0 @@
# Syste76 Darter Pro 9 (darp9)
## Specs
- CPU
- Intel Core i5-1340P
- Intel Core i7-1360P
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- Intel Iris Xe Graphics
- eDP 15.6" 1920x1080@60Hz LCD
- 1x HDMI
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5600 MHz
- Networking
- Gigabit Ethernet (Realtek RTL8111H)
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6E AX210/211)
- Power
- 90W (19V, 4.74A) AC barrel adapter
- USB-C charging, compatible with 65W+ chargers
- 73Wh 4-cell Lithium-ion battery (L140BAT-4)
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- HDMI, USB-C DisplayPort audio
- Storage
- 2x M.2 PCIe NVMe Gen 4 SSDs
- MicroSD card reader (OZ711LV2)
- USB
- 1x USB Type-C with Thunderbolt 4
- 1x USB 3.2 Gen 2 Type-C
- 1x USB 3.2 Gen 2 Type-A
- 1x USB 2.0 Type-A
- Dimensions
- 35.7cm x 22.05cm x 1.99cm, 1.74kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U22) is above the left DIMM slot.

58
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@@ -1,58 +0,0 @@
# System76 Galago Pro 7 (galp7)
## Specs
- CPU
- Intel Core i5-13500H
- Intel Core i7-13700H
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- Intel Iris Xe Graphics
- eDP 14.1" 1920x1080@144Hz LCD (Sharp LQ140M1JW49)
- 1x HDMI 2.1
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
- Networking
- Gigabit Ethernet
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
- Power
- 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A)
- USB-C charging, compatible with 90W+ chargers
- 53Wh 4-cell Lithium-ion battery
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- HDMI, USB-C DisplayPort audio
- USB
- 1x USB-C Type-C with Thunderbolt 4
- 1x USB 3.2 (Gen 2) Type-C
- 2x USB 3.2 (Gen 1) Type-A
- Dimensions
- 32.49cm x 22.5cm x 1.82cm, 1.45kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | Macronix |
+---------------------+---------------------+
| Model | MX25L25673G |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U43) is left of the wireless card.

65
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@@ -1,65 +0,0 @@
# System76 Gazelle 17 (gaze17)
The gaze17 comes in 2 variants: gaze17-3050 and gaze17-3060-b.
## Specs
- CPU
- Intel Core i5-12500H
- Intel Core i7-12700H
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- dGPU options
- NVIDIA GeForce RTX 3050
- NVIDIA GeForce RTX 3050 Ti
- NVIDIA GeForce RTX 3060
- Memory
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MT/s
- Networking
- Gigabit Ethernet
- 3050: Realtek RTL8111H controller
- 3060: Onboard Intel I219-V
- M.2 PCIe/CNVi WiFi/Bluetooth
- Intel Wi-Fi 6 AX201
- Power
- 3050: 150W (20V, 7.5A) AC barrel adapter
- 3060: 180W (20V, 9A) AC barrel adapter
- Lite-On PA-1181-76, using a C5 power cord
- 54Wh 4-cell Li-ion battery (NP50BAT-4-54)
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- Dedicated 3.5mm microphone jack
- Storage
- 1x M.2 PCIe NVMe Gen 4 SSD
- 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
- MicroSD card reader (Realtek RTS5227S/OZ711LV2)
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The position of the flash chip depends on the variant:
- 3050: U24, below the bottom DIMM slot.
- 3060: U55, left of the PCIe 4.0 M.2 slot.

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@@ -1,72 +0,0 @@
# System76 Gazelle 18 (gaze18)
## Specs
- CPU
- Intel i9-13900H
- Chipset
- Intel HM770
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- NVIDIA GeForce RTX 3050 (70W TDP)
- Intel Irix Xe Graphics
- eDP displays
- 17.3" 1920x1080@144Hz LCD
- 15.6" 1920x1080@144Hz LCD
- External outputs
- 1x HDMI 2.1
- 1x Mini DisplayPort 1.4
- Memory
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
- Networking
- Realtek RTL8111H gigabit Ethernet
- M.2 PCIe/CNVi WiFi/Bluetooth
- Intel Wi-Fi 6E AX210/AX211
- Power
- 150W AC barrel adapter
- Included: LiteOn PA-1151-76, using a C5 power cord
- 54Wh 4-cell battery (NP50BAT-4-54)
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- Dedicated 3.5mm microphone jack
- HDMI, mDP audio
- Storage
- 1x M.2 (PCIe NVMe Gen 4)
- 1x M.2 (PCIe NVMe Gen 3)
- MicroSD card reader
- Realtek RTS5227S
- USB
- 2x USB 3.2 Gen 2 Type-C
- Does not support USB-C charging (USB-PD) or Thunderbolt
- 1x USB 3.2 Gen 2 Type-A
- 1x USB 2.0 Type-A
- Dimensions
- 15": 35.95cm x 23.8cm x 2.27cm, 1.99kg
- 17": 39.69cm x 26.2cm x 2.5cm, 2.41kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U24) is right of the M.2 SSD connectors.

62
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@@ -1,62 +0,0 @@
# System76 Lemur Pro 12 (lemp12)
## Specs
- CPU
- Intel Core i5-1335U
- Intel Core i7-1355U
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- Intel Iris Xe Graphics
- eDP 14.0" 1920x1080@60Hz LCD (Innolux N140HCE-EN2)
- 1x HDMI 2.1
- 1x DisplayPort 1.4 over USB-C
- Memory
- Channel 0: 8-GB onboard DDR5 (Samsung M425R1GB4BB0-CQKOD)
- Channel 1: 8/16/32-GB DDR5 SO-DIMM @ 4800 MHz
- Networking
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
- Power
- 65W (19V, 3.42A) AC adapter (AcBel ADA012)
- USB-C charging, compatible with 65W+ charger
- 73Wh 4-cell Lithium-ion battery
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5 mm headphone/microphone jack
- HDMI, USB-C DisplayPort audio
- Storage
- 1x M.2 PCIe NVMe Gen 4 SSD
- 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
- MicroSD card reader (RTS5227S)
- USB
- 1x USB Type-C with Thudnerbolt 4
- 1x USB 3.2 Gen 2 Type-A
- 1x USB 3.2 Gen 1 Type-A
- Dimensions
- 1.65cm x 32.2cm x 21.68cm, 1.15kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | Macronix |
+---------------------+---------------------+
| Model | MX25L25673G |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U41) is left of the DIMM slot.

66
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@@ -1,66 +0,0 @@
# System76 Oryx Pro 11 (oryp11)
## Specs
- CPU
- Intel Core i9-13900H
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- dGPU options:
- NVIDIA GeForce RTX 4050
- NVIDIA GeForce RTX 4060
- NVIDIA GeForce RTX 4070
- 16" 1920x1200@165Hz LCD
- External outputs:
- 1x HDMI 2.1
- 1x Mini DisplayPort 1.4
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5600 MHz
- Networking
- Realtek RTL8125BG-CG 2.5G Ethernet
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
- Power
- 180W (20V, 9A) AC barrel adapter (Lite-On PA-1181-86)
- 73Wh 4-cell Lithium-ion battery (NV40BAT-4-73)
- Sound
- Realtek ALC1220 codec
- Realtek ALC1318 smart amp
- Internal speakers and microphone
- Combined 3.5mm headphone & microphone jack
- Combined 3.5mm microphone & S/PDIF jack
- HDMI, mDP, USB-C DP audio
- Storage
- 2x M.2 PCIe NVMe Gen 4 SSD
- MicroSD card reader (Realtek RTS5227S)
- USB
- 1x USB Type-C with Thunderbolt 4
- 1x USB 3.2 Gen 2 Type-C
- 2x USB 2.1 Gen 1 Type-A
- Dimensions
- 35.95cm x 27.3cm x 1.99cm, 2.7kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U61) is left of the memory slots.

69
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@@ -1,69 +0,0 @@
# System76 Serval Workstation 13 (serw13)
## Specs
- CPU
- Intel Core i9-13900HX
- Chipset
- Intel HM770
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- dGPU options:
- NVIDIA GeForce RTX 4060
- NVIDIA GeForce RTX 4070
- eDP options:
- 15.6" 1920x1080@165Hz LCD (BOE NV156FHM-NY8)
- 17.6" 3840x2160@144Hz LCD (AUO B173ZAN03.0)
- 1x HDMI 2.1
- 1x Mini DisplayPort 1.4
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5200 Mhz
- Networking
- Realtek RTL8125BG-CG 2.5G Ethernet
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
- Power
- 280W (20V, 14A) AC adapter (Chicony A18-280P1A)
- 80Wh 6-cell Lithium-ion battery ()
- Sound
- Realtek ALC1220 codec
- Realtek ALC1318 smart amp
- Internal speakers and microphone
- Combined 3.5mm headphone & microphone jack
- Combined 3.5mm microphone & S/PDIF jack
- HDMI, mDP, USB-C DP audio
- Storage
- 2x M.2 PCIe NVMe Gen 4 SSDs
- MicroSD card reader (Realtek RTS5227S)
- USB
- 1x USB Type-C with Thunderbolt 4
- 1x USB 3.2 Gen 2 Type-C
- 2x USB 3.2 Gen 1 Type-A
- Dimensions
- 15": 2.49cm x 35.8cm x 24.0cm, 2.4kg
- 17": 2.49cm x 39.6cm x 26.2cm, 2.8kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U46) is left of the memory slots.

21
Documentation/releases/coreboot-4.19-relnotes.md
View File

@@ -15,10 +15,6 @@ It takes constant effort to just stay afloat, let alone improve the
codebase. Thank you very much to everyone who has contributed, both in
this release and in previous times.
Note that the first set of tarballs posted for the 4.19 release had
bad timestamps. This has been fixed. Hashes for all tarballs are at
the bottom of this document.
The 4.20 release is planned for the 20th of April, 2023.
@@ -248,20 +244,3 @@ Issues from the coreboot bugtracker: https://ticket.coreboot.org/
| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD |
+-----+-----------------------------------------------------------------+
```
Hashes for tarballs & signatures
--------------------------------
Old tarballs:
- a1f9ec1252a3cc19f0b4ba1a2b9d66ea9327499cbeecebd85377db7d5c68555d coreboot-4.19.tar.xz
- 6ceaa39429a2094d75e4c8a94615ae60664ddad7b4115570b65b9bb516cbd96d coreboot-4.19.tar.xz.sig
- 881a3477221d1b77e161759344df14eccda115086af3ef54e66485ae0eb2e5d9 coreboot-blobs-4.19.tar.xz
- 16f4f1f7acc6203ce915ffea64edce8512bd9eb9e94e65db22a0cb5282a6e157 coreboot-blobs-4.19.tar.xz.sig
New tarballs:
- 65ccb2f46535b996e0066a1b76f81c8cf1ff3e27df84b3f97d8ad7b3e7cf0a43 coreboot-4.19.tar.xz
- d3c52a209b8ccb49049960318f04f158dd47db52ebe6019d6a3dffe3196d9cbe coreboot-4.19.tar.xz.sig
- 30214caed07b25f11e47bec022ff6234841376e36689eb674de2330a3e980cbc coreboot-blobs-4.19.tar.xz
- 023d511d074703beab98c237c3e964dc7c598af86d5a0e2091195c68980b6c5d coreboot-blobs-4.19.tar.xz.sig

79
Documentation/releases/coreboot-4.20.1-relnotes.md → Documentation/releases/coreboot-4.20-relnotes.md
View File

@@ -1,16 +1,10 @@
coreboot 4.20 release
Upcoming release - coreboot 4.20
========================================================================
The 4.20 release was done on May 15, 2023. Unfortunately, a licensing
issues was found immediately after the release was completed, and it
was decided to hold the release until that was fixed.
Please do not use the 4.20 tag, and use the 4.20.1 git tag instead. The
4.20_branch will contain all code for 4.20, 4.20.1, and any further
changes required for this release.
The 4.20 release is being done on May 15, 2023.
The coreboot community has done a tremendous amount of work on the
codebase over the last three and a half months. We've had over 1600
codebase over the last three and a half month. We've had over 1600
commits in that time period, doing ongoing cleanup and improvement.
It can be hard to remember at times how much the codebase really has
@@ -25,23 +19,20 @@ or push even a single patch to fix a bug that they've noticed.
Many thanks to everyone involved!
We plan to get the 4.21 release done in mid August, 2023.
We plan to get the 4.21 release done in mid August, 2023,
Significant or interesting changes
----------------------------------
### cpu/mp_init.c: Only enable CPUs once they execute code
On some systems the BSP cannot know how many CPUs are present in the
system. A typical use case is a multi socket system. Setting the enable
flag only on CPUs that actually exist makes it more flexible.
### cpu/x86/smm: Add PCI resource store functionality
In certain cases data within protected memory areas like SMRAM could
In certain cases data within protected memmory areas like SMRAM could
be leaked or modified if an attacker remaps PCI BARs to point within
that area. Add support to the existing SMM runtime to allow storing
PCI resources in SMRAM and then later retrieving them.
@@ -49,12 +40,10 @@ PCI resources in SMRAM and then later retrieving them.
This helps prevent moving BARs around to get SMM to access memory in
areas that shouldn't be accessed.
### acpi: Add SRAT x2APIC table support
For platforms using X2APIC mode add SRAT x2APIC table
generation. This allows the setup of proper SRAT tables.
generation. This allows to setup proper SRAT tables.
### drivers/usb/acpi: Add USB _DSM method to enable/disable USB LPM per port
@@ -68,11 +57,10 @@ The ACPI and USB driver of linux kernel need corresponding functions
to support this feature. Please see
https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm
### drivers/efi: Add EFI variable store option support
Add a driver to read and write EFI variables stored in a region device.
This is particularly useful for EDK2 as payload and allows it to reuse
This is particularly useful for EDK2 as payload and allows to reuse
existing EFI tools to set/get options used by the firmware.
The write implementation is fault tolerant and doesn't corrupt the
@@ -101,11 +89,11 @@ variable, first a new is written to the end of the store and then the
previous is marked invalid. This only works on PNOR flash that allow to
clear set bits, but keep cleared bits state.
This mechanisms allows a fault tolerant write, but it also requires to
"clean" the variable store from time to time. This cleaning would remove
"clean" the variable store for time to time. This cleaning would remove
variables that have been marked "deleted".
Such cleaning mechanism in turn must be fault tolerant and thus must use
a second partition in the SPI flash as backup/working region.
For now, cleaning is done in coreboot.
For now to cleaning is done in coreboot.
Fault checking:
The driver should check if a previous write was successful and if not
@@ -117,7 +105,6 @@ mark variables as deleted on the next operation.
Add EWL (Enhanced Warning Log) driver which handles Intel EWL HOB
and prints EWL type 3 primarily associated with MRC training failures.
### Toolchain updates
* Upgrade MPC from version 1.2.1 to 1.3.1
@@ -127,7 +114,6 @@ and prints EWL type 3 primarily associated with MRC training failures.
* Upgrade GCC from version 11.2.0 to 11.3.0
* Upgrade binutils from version 2.37 to 2.40
Additional coreboot changes
---------------------------
@@ -149,10 +135,8 @@ Additional coreboot changes
* Do initial work on Xeon SPR
* CMOS defaults greater than 128 bytes long now extend to bank 1.
New Mainboards
--------------
* Asrock: B75M-ITX
* Dell: Latitude E6400
* Google: Aurash
@@ -178,21 +162,16 @@ New Mainboards
* System76: oryp10
* System76: oryp9
Removed Mainboards
------------------
* Intel Icelake U DDR4/LPDDR4 RVP
* Intel Icelake Y LPDDR4 RVP
* Scaleway TAGADA
Updated SoCs
------------
* Removed soc/intel/icelake
Plans to move platform support to a branch
------------------------------------------
@@ -209,57 +188,39 @@ be maintained on the release 4.20 branch.
* Intel Quark SoC
* Intel Galileo mainboard
Statistics from the 4.19 to the 4.20 release
--------------------------------------------
Total Commits: 1630
Average Commits per day: 13.72
Total lines added: 102592
Average lines added per commit: 62.94
Number of patches adding more than 100 lines: 128
Average lines added per small commit: 37.99
Total lines removed: 34824
Average lines removed per commit: 21.36
Total difference between added and removed: 67768
Total Commits: ~1625
Average Commits per day: ~13.71
Total lines added: ~101911
Average lines added per commit: ~62.71
Number of patches adding more than 100 lines: ~126
Average lines added per small commit: ~37.98
Total lines removed: ~34756
Average lines removed per commit: ~21.39
Total difference between added and removed: ~67155
Total authors: ~170
New authors: ~35
Significant Known and Open Issues
---------------------------------
Issues from the coreboot bugtracker: https://ticket.coreboot.org/
```eval_rst
+-----+-----------------------------------------------------------------+
| # | Subject |
+=====+=================================================================+
|-----|-----------------------------------------------------------------|
| 478 | X200 booting Linux takes a long time with TSC |
+-----+-----------------------------------------------------------------+
| 474 | X200s crashes after graphic init with 8GB RAM |
+-----+-----------------------------------------------------------------+
| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb |
+-----+-----------------------------------------------------------------+
| 453 | Intel HDMI / DP Audio device not showing up after libgfxinit |
+-----+-----------------------------------------------------------------+
| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
+-----+-----------------------------------------------------------------+
| 448 | Thinkpad T440P ACPI Battery Value Issues |
+-----+-----------------------------------------------------------------+
| 446 | Optiplex 9010 No Post |
+-----+-----------------------------------------------------------------+
| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz) |
+-----+-----------------------------------------------------------------+
| 427 | x200: Two battery charging issues |
+-----+-----------------------------------------------------------------+
| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
+-----+-----------------------------------------------------------------+
| 412 | x230 reboots on suspend |
+-----+-----------------------------------------------------------------+
| 393 | T500 restarts rather than waking up from suspend |
+-----+-----------------------------------------------------------------+
| 350 | I225 PCIe device not detected on Harcuvar |
+-----+-----------------------------------------------------------------+
| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD |
+-----+-----------------------------------------------------------------+
```

400
Documentation/releases/coreboot-4.21-relnotes.md
View File

@@ -1,407 +1,51 @@
Upcoming release - coreboot 4.21
========================================================================
The 4.21 release is scheduled for August 21st, 2023
The 4.21 release is planned for mid-August, 2023
In the past quarter year, the coreboot project has gotten over 1200 new
patches from around 140 authors, 20 of whom contributed for the first
time.
Update this document with changes that should be in the release notes.
Thank you to all of our donors, the code contributors, the people who
take time to review all of those patches and all of the people who care
about the coreboot project. There have been a number of new companies
starting to use coreboot recently, and we appreciate all of the
contributions and support.
### Upcoming switch from master branch to main branch
Historically, the initial branch that was created in a new git
repository was named ‘master’. In line with many other projects,
coreboot has decided to switch away from this name and use the name
‘main’ instead. You can read about the initial reasoning on the SFC’s
website: https://sfconservancy.org/news/2020/jun/23/gitbranchname/
At some point before the 4.22 release, coreboot will be switching from
the master branch to the main branch. This shouldn’t be a difficult
change for most people, as everyone will just have to rebase on top of
a different branch name.
We’ve already created the main branch, and it is currently synced with
the master branch. Please update any scripts to point to main instead
of master.
At the point of the changeover, we will move all patches in gerrit to
the main branch and disable pushes to the master branch.
After the switch, we will sync the main branch to the master branch for
a while to give people a little more time to update any scripts that
are currently pointed at the master branch. Note that this update will
probably be done just once per day, and the frequency of updates will
be decreased over time. We plan to stop updating the master branch
following the 4.22 release.
* Please use Markdown.
* See the past few release notes for the general format.
* The chip and board additions and removals will be updated right
before the release, so those do not need to be added.
* Note that all changes before the release are done are marked upcoming.
A final version of the notes are done after the release.
Significant or interesting changes
----------------------------------
### lib: Support localized text of memory_training_desc in ux_locales.c
Most of the text in coreboot is for logging, and does not use
localization. There are however, some bits of text that can be
presented to the user, and this patch supplies a method to localize
them.
To support the localized text, we need to get the locale id by vboot
APIs and read raw string content file: preram_locales located at either
RO or RW.
The preram_locales file follows the format:
[PRERAM_LOCALES_VERSION_BYTE (\x01)]
[string_name_1] [\x00]
[locale_id_1] [\x00] [localized_string_1] [\x00]
[locale_id_2] [\x00] [localized_string_2] …
[\x01]
[string_name_2] [\x00] ...
This code will search for the correct localized string that its string
name is `memory_training_desc` and its locale ID matches the ID vb2api
returns. If no valid string found, we will try to display in English
(locale ID 0).
### Improved the bootsplash support
The JPEG decoder, that was added many years ago to display a bootsplash
in coreboot, has a few quirks. People used to do some voodoo with GIMP
to convert images to the right format, but we can also achieve the same
with ImageMagick's `convert`. The currently known constraints are:
* The framebuffer's color format is ignored,
* only YCC 4:2:0 color sampling is supported, and
* width and height have to be a multiple of 16 pixels.
Beside that, we can only display the bootsplash if it completely fits
into the framebuffer. As the latter's size is often decided at runtime,
we can't do much more than offering an option to set a specific size.
The build system has been extended so that the necessary adjustments to
the picture can be done by it and several options have been added to
Kconfig.
### libpayload/uhci: Re-write UHCI RH driver w/ generic_hub API
This is a complete rewrite of the UHCI root-hub driver, based on the
xHCI one. We are doing things by the book as far as possible. One
special case is uhci_rh_reset_port() which does the reset sequencing
that usually the hardware would do.
This abandons some quirks of the old driver:
* Ports are not disabled/re-enabled for every attachment anymore.
* We solely rely on the Connect Status Change bit to track changes.
* Further status changes are now deferred to the next polling round.
### linux_trampoline: Handle coreboot framebuffer & 64-bit addresses
Translate the coreboot framebuffer info from coreboot tables to the
Linux zero page.
To support full 64-bit addresses, there is a new field `ext_lfb_base`
since Linux 4.1. It is unclear, however, how a loader is supposed to
know if the kernel is compatible with this. Filling these previously
reserved bits doesn't hurt, but an old kernel would probably ignore
them and not know that it's handling a clipped, invalid address. So we
play safe, and only allow 64-bit addresses for kernels after the 2.15
version bump of the boot protocol.
### arch/x86: Don't allow hw floating point operations
Even though coreboot does not allow floating point operations, some
compilers like clang generate code using hw floating point registers,
e.g. SSE %XMMx registers on 64bit code by default. Floating point
operations need to be enabled in hardware for this to work (CR4). Also
in SMM we explicitly need to save and restore floating point registers
for this reason. If we instruct the compiler to not generate code with
FPU ops, this simplifies our code as we can skip that step.
With clang this reduces the binary size a bit. For instance ramstage
for emulation/qemu-q35 drops by 4 kB from from 216600 bytes
decompressed to 212768 bytes.
Since we now explicitly compile both ramstage and smihandler code
without floating point operations and associated registers we don't
need to save/restore floating point registers in SMM.
The EFER MSR is in the SMM save state and RSM properly restores it.
Returning to 32bit mode was only done so that fxsave was done in the
same mode as fxrstor, but this is no longer done.
### Caching of PCIe 5.0 HSPHY firmware in SPI flash
This adds the ability to cache the PCIe 5.0 HSPHY firmware in the SPI
flash. A new flashmap region is created for that purpose. The goal of
caching is to reduce the dependency on the CSME (Converged Security and
Management Engine) and the HECI (Host Embedded Controller Interface) IP
LOAD command which may fail when the CSME is disabled, e.g. soft
disabled by HECI command or HAP (High Assurance Platform mode). By
caching that firmware, this allows the PCIe 5.0 root ports to keep
functioning even if CSME/HECI is not functional.
### Extracting of TPM logs using cbmem tool
CBMEM can contain logs in different forms (at most one is present):
* coreboot-specific format (CBMEM_ID_TPM_CB_LOG exported as
LB_TAG_TPM_CB_LOG)
* TPM1.2 format (CBMEM_ID_TCPA_TCG_LOG)
* TPM2 format (CBMEM_ID_TPM2_TCG_LOG)
The last two follow specifications by Trusted Computing Group, but
until now cbmem couldn't print them.
These changes make the cbmem utility check for existence of TPM1.2/TPM2
logs in CBMEM and add code necessary for parsing and printing of their
entries.
`cbmem -L` for CONFIG_TPM1=y case
```
TCPA log:
Specification: 1.21
Platform class: PC Client
TCPA log entry 1:
PCR: 2
Event type: Action
Digest: 5622416ea417186aa1ac32b32c527ac09009fb5e
Event data: FMAP: FMAP
```
`cbmem -L` for CONFIG_TPM2=y case
```
TPM2 log:
Specification: 2.00
Platform class: PC Client
TPM2 log entry 1:
PCR: 2
Event type: Action
Digests:
SHA256: 68d27f08cb261463a6d004524333ac5db1a3c2166721785a6061327b6538657c
Event data: FMAP: FMAP
```
### soc/amd: read domain resource window configuration from hardware
Read the MMIO and IO decode windows for the PCI root complex and the
PCI bus number range decoded to the PCI root complex from the data
fabric registers and pass the information to the resource allocator so
it has the correct constraints to do its job. Also generate the
corresponding ACPI resource producers in the SSDT so that the OS knows
about this too. This is required for the upcoming USB 4 support.
### Add changes that need a full description here
* This section should have full descriptions and can or should have
a link to the referenced commits.
Additional coreboot changes
---------------------------
* Added SPDX headers to more files to help automated license checking.
The linter has been enabled to check the Makefiles as well.
* Cleaned up Kconfig files and source code.
* Enabled acpigen to generate tables for SPCR (Serial Port Console
Redirection) and GTDT (Generic Timer Description Table).
* The resource allocation above the 4GiB boundary has been improved.
* Most of the code has been adjusted to make use of C99 flexible arrays
instead of one-element or zero-length arrays.
* Additional Dockerfiles based on Arch and Alpine Linux have been added
to build-test with alternate build environments, including musl-libc.
They are very basic at the moment and not equal to the coreboot-sdk.
They will be extended in the future.
* Added support for ITE IT8784E to superiotool.
* Added support for Intel 700 chipset series to inteltool and a build
issue with musl–libc has been fixed.
* Added support for Intel 800 chipset series to ifdtool.
* The coreboot-sdk container has been extended so that it allows
extracting the MRC binary from Haswell-based ChromeOS firmware images.
* From now on POST code preprocessor macros should have a POSTCODE
prefix following the name of the POST code.
* The NASM compiler provided by the coreboot toolchain wasn’t properly
integrated into xcompile and thus it wasn’t used by the build system.
Instead, it was required to install NASM on the host in order to use
it. This has been fixed.
* The time measurement done in abuild got improved and also an issue
has been fixed when the variant name contains hyphens.
* The RISC-V code was enabled to build with Clang.
* Initial work has been done to transform Camelcase options to
Snakecase.
* The buildgcc script is now able to just fetch the tarballs if desired,
which is needed for reproducible build environments for example.
The following are changes across a number of patches, or changes worth
noting, but not needing a full description.
* Changes that only need a line or two of description go here.
Platform Updates
----------------
Changes to external resources
-----------------------------
* To be filled in immediately before the release by the release team
### Toolchain
* binutils
* Added binutils-2.40_stop_losing_entry_point_when_LTO_enabled.patch
* Upgrade IASL from 20221020 to 20230628
* Upgrade LLVM from 15.0.7 to 16.0.6
* Upgrade NASM from 2.15.05 to 2.16.01
* Added nasm-2.16.01_handle_warning_files_while_building_in_a_directory.patch
* Upgrade CMake from 3.26.3 to 3.26.4
* Upgrade GCC from 11.3.0 to 11.4.0
* Added gcc-11.4.0_rv32iafc.patch
### Git submodule pointers
#### /3rdparty
* amd_blobs: Update from commit id 1cd6ea5cc5 to 6a1e1457af (5 commits)
* arm-trusted-firmware: Update from commit id 4c985e8674 to 37366af8d4
(851 commits)
* blobs: Update from commit id 01ba15667f to a8db7dfe82 (14 commits)
* fsp: Update from commit id 6f2f17f3d3 to 3beceb01f9 (24 commits)
* intel-microcode: Update from commit id 2be47edc99 to 6f36ebde45 (5
commits)
* libgfxinit: Update from commit id 066e52eeaa to a4be8a21b0 (18
commits)
* libhwbase: Update from commit id 8be5a82b85 to 584629b9f4 (2 commits)
* qc_blobs: Update from commit id 33cc4f2fd8 to a252198ec6 (4 commits)
* vboot: Update from commit id 35f50c3154 to 0c11187c75 (83 commits)
#### /util
* goswid: Update from commit id bdd55e4202 to 567a1c99b0 (5 commits)
* nvidia/cbootimage: Update from commit id 65a6d94dd5 to 80c499ebbe (1
commit)
### External payloads
* Update the depthcharge payload from commit ID 902681db13 to c48613a71c
* Upgrade EDK2-MrChromebox from version 202304 to version 202306
* Upgrade SeaBIOS from version 1.16.1 to version 1.16.2
* Update tint from version 0.05 to version 0.07
* Update U-Boot from version 2021.07 to version v2023.07
Added mainboards:
-----------------
* ByteDance ByteDance bd_egs
* Google: Craaskov
* Google: Expresso
* Google: Karis
* Google: Karis4ES
* Google: Pirrha
* Google: Ponyta
* Google: Screebo4ES
* Google: Ovis
* Google: Ovis4ES
* Google: Rex EC ISH
* Google: Rex4ES
* HP Compaq Elite 8300 USDT
* HP EliteBook 820 G2
* IBM SBP1
* Intel Raptorlake silicon with Alderlake-P RVP
* Inventec Transformers
* MSI PRO Z790-P (WIFI)
* MSI PRO Z790-P (WIFI) DDR4
* Star Labs Star Labs StarBook Mk VI (i3-1315U and i7-1360P)
* System76 addw3
* System76 bonw15
* System76 darp9
* System76 galp7
* System76 gaze17 3050
* System76 gaze17 3060-b
* System76 gaze18
* System76 lemp12
* System76 oryp11
* System76 serw13
Removed Mainboards
------------------
* Intel Galileo
Updated SoCs
------------
* Removed src/soc/intel/quark
Plans to move platform support to a branch
------------------------------------------
* Seciton to be filled in or removed after discussion
Statistics from the 4.20 to the 4.21 release
--------------------------------------------
* Total Commits: 1252
* Average Commits per day: 12.59
* Total lines added: 317734
* Average lines added per commit: 253.78
* Number of patches adding more than 100 lines: 86
* Average lines added per small commit: 36.22
* Total lines removed: 261063
* Average lines removed per commit: 208.52
* Total difference between added and removed: 56671
* Total authors: 143
* New authors: 21
* To be filled in immediately before the release by the release team
Significant Known and Open Issues
---------------------------------
* To be filled in immediately before the release by the release team
Issues from the coreboot bugtracker: https://ticket.coreboot.org/
```eval_rst
+-----+-----------------------------------------------------------------+
| # | Subject |
+=====+=================================================================+
| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled |
+-----+-----------------------------------------------------------------+
| 495 | Stoney chromebooks not booting PSPSecureOS |
+-----+-----------------------------------------------------------------+
| 478 | X200 booting Linux takes a long time with TSC |
+-----+-----------------------------------------------------------------+
| 474 | X200s crashes after graphic init with 8GB RAM |
+-----+-----------------------------------------------------------------+
| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb |
+-----+-----------------------------------------------------------------+
| 453 | Intel HDMI / DP Audio device not showing up after libgfxinit |
+-----+-----------------------------------------------------------------+
| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
+-----+-----------------------------------------------------------------+
| 448 | Thinkpad T440P ACPI Battery Value Issues |
+-----+-----------------------------------------------------------------+
| 446 | Optiplex 9010 No Post |
+-----+-----------------------------------------------------------------+
| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz) |
+-----+-----------------------------------------------------------------+
| 427 | x200: Two battery charging issues |
+-----+-----------------------------------------------------------------+
| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
+-----+-----------------------------------------------------------------+
| 412 | x230 reboots on suspend |
+-----+-----------------------------------------------------------------+
| 393 | T500 restarts rather than waking up from suspend |
+-----+-----------------------------------------------------------------+
| 350 | I225 PCIe device not detected on Harcuvar |
+-----+-----------------------------------------------------------------+
| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD |
+-----+-----------------------------------------------------------------+
```
coreboot Links and Contact Information
--------------------------------------
* Main Web site: https://www.coreboot.org
* IRC: https://web.libera.chat/#coreboot
* Downloads: https://coreboot.org/downloads.html
* Source control: https://review.coreboot.org
* Documentation: https://doc.coreboot.org
* Issue tracker: https://ticket.coreboot.org/projects/coreboot
* Donations: https://coreboot.org/donate.html

54
Documentation/releases/coreboot-4.22-relnotes.md
View File

@@ -1,54 +0,0 @@
Upcoming release - coreboot 4.22
========================================================================
The 4.22 release is planned for mid-November, 2023
Update this document with changes that should be in the release notes.
* Please use Markdown.
* See the past few release notes for the general format.
* The chip and board additions and removals will be updated right
before the release, so those do not need to be added.
* Note that all changes before the release are done are marked upcoming.
A final version of the notes are done after the release.
### Significant or interesting changes
----------------------------------
* Add changes that need a full description here
* This section should have full descriptions and can or should have
a link to the referenced commits.
### Toolchain updates
* To be filled in immediately before the release by the release team
### Additional coreboot changes
---------------------------
The following are changes across a number of patches, or changes worth
noting, but not needing a full description.
* Changes that only need a line or two of description go here.
### Platform Updates
----------------
* To be filled in immediately before the release by the release team
### Plans to move platform support to a branch
------------------------------------------
* Section to be filled in or removed after discussion
### Statistics from the 4.21 to the 4.22 release
--------------------------------------------
* To be filled in immediately before the release by the release team
### Significant Known and Open Issues
---------------------------------
* To be filled in immediately before the release by the release team

43
Documentation/releases/index.md
View File

@@ -3,7 +3,7 @@
## Upcoming release
Please add to the release notes as changes are added:
* [4.22 - November 2023](coreboot-4.22-relnotes.md)
* [4.21 - August 2023](coreboot-4.21-relnotes.md)
The [checklist] contains instructions to ensure that a release covers all
important things and provides a reliable format for tarballs, branch
@@ -15,27 +15,26 @@ important is taken care of.
## Previous releases
* [4.21 - August 2023](coreboot-4.21-relnotes.md)
* [4.20.1 - May 2023](coreboot-4.20.1-relnotes.md)
* [4.19 - January 2023](coreboot-4.19-relnotes.md)
* [4.18 - October 2022](coreboot-4.18-relnotes.md)
* [4.17 - May 2022](coreboot-4.17-relnotes.md)
* [4.16 - February 2022](coreboot-4.16-relnotes.md)
* [4.15 - November 2021](coreboot-4.15-relnotes.md)
* [4.14 - May 2021](coreboot-4.14-relnotes.md)
* [4.13 - November 2020](coreboot-4.13-relnotes.md)
* [4.12 - May 2020](coreboot-4.12-relnotes.md)
* [4.11 - November 2019](coreboot-4.11-relnotes.md)
* [4.10 - July 2019](coreboot-4.10-relnotes.md)
* [4.9 - December 2018](coreboot-4.9-relnotes.md)
* [4.8.1 - May 2018](coreboot-4.8.1-relnotes.md)
* [4.7 - January 2018](coreboot-4.7-relnotes.md)
* [4.6 - April 2017](coreboot-4.6-relnotes.md)
* [4.5 - October 2016](coreboot-4.5-relnotes.md)
* [4.4 - May 2016](coreboot-4.4-relnotes.md)
* [4.3 - January 2016](coreboot-4.3-relnotes.md)
* [4.2 - October 2015](coreboot-4.2-relnotes.md)
* [4.1 - July 2015](coreboot-4.1-relnotes.md)
* [4.20 - May 2023](coreboot-4.20-relnotes.md)
* [4.19 - January 2023](coreboot-4.19-relnotes.md)
* [4.18 - October 2022](coreboot-4.18-relnotes.md)
* [4.17 - May 2022](coreboot-4.17-relnotes.md)
* [4.16 - February 2022](coreboot-4.16-relnotes.md)
* [4.15 - November 2021](coreboot-4.15-relnotes.md)
* [4.14 - May 2021](coreboot-4.14-relnotes.md)
* [4.13 - November 2020](coreboot-4.13-relnotes.md)
* [4.12 - May 2020](coreboot-4.12-relnotes.md)
* [4.11 - November 2019](coreboot-4.11-relnotes.md)
* [4.10 - July 2019](coreboot-4.10-relnotes.md)
* [4.9 - December 2018](coreboot-4.9-relnotes.md)
* [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
* [4.7 - January 2018](coreboot-4.7-relnotes.md)
* [4.6 - April 2017](coreboot-4.6-relnotes.md)
* [4.5 - October 2016](coreboot-4.5-relnotes.md)
* [4.4 - May 2016](coreboot-4.4-relnotes.md)
* [4.3 - January 2016](coreboot-4.3-relnotes.md)
* [4.2 - October 2015](coreboot-4.2-relnotes.md)
* [4.1 - July 2015](coreboot-4.1-relnotes.md)
[checklist]: checklist.md

72
Documentation/security/vboot/list_vboot.md
View File

@@ -36,37 +36,16 @@
- Agah
- Anahera
- Anahera4ES
- Aurash
- Banshee
- Brask
- Brya 0
- Craask
- Craaskov
- Constitution
- Crota
- Felwinter
- Gaelin
- Gimble
- Gimble4ES
- Gladios
- Gothrax
- Hades
- Kano
- Kinox
- Kuldax
- Joxer
- Lisbon
- Marasov
- Mithrax
- Moli
- Nivviks
- Nereid
- Omnigul
- Osiris
- Pirrha
- Primus
- Primus4ES
- Pujjo
- Redrix
- Redrix4ES
- Skolas
@@ -74,13 +53,31 @@
- Taeko
- Taeko4ES
- Taniks
- Uldren
- Vell
- Volmar
- Banshee
- Crota
- Moli
- Kinox
- Craask
- Osiris
- Mithrax
- Kuldax
- Joxer
- Pujjo
- Xivu
- Gaelin
- Yaviks
- Yavilla
- Lisbon
- Zydron
- Gladios
- Marasov
- Omnigul
- Constitution
- Aurash
- Hades
- Uldren
- Yavilla
- Butterfly (HP Pavilion Chromebook 14)
- Cherry
- Dojo
@@ -88,7 +85,6 @@
- Kingler
- Steelix
- Voltorb
- Ponyta
- Krabby
- Tentacruel
- Magikarp
@@ -215,13 +211,6 @@
- Coral
- Rex 0
- Screebo
- Screebo4ES
- Karis
- Karis4ES
- Rex EC ISH
- Ovis
- Ovis4ES
- Rex4ES
- Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
- Sarien (Dell Latitude 5400 Chromebook Enterprise)
- Skyrim
@@ -256,21 +245,21 @@
- Veyron_Speedy (ASUS C201 Chromebook)
- Veyron_Mickey (Asus Chromebit CS10)
- Veyron_Rialto
- Chronicler (FMV Chromebook 14F)
- Collis (Asus Chromebook Flip CX3)
- Chronicler
- Collis
- Copano (ASUS Chromebook Flip CX5400)
- Delbin (ASUS Chromebook Flip CX5)
- Drobit (ASUS Chromebook CX9400)
- Eldrid (HP Chromebook x360 14c)
- Eldrid
- Elemi (HP Pro c640 G2 Chromebook)
- Halvor
- Lindar (Lenovo 5i-14/Slim 5 Chromebook)
- Lindar
- Malefor
- Terrador
- Todor
- Trondo
- Voema (Acer Chromebook Spin 514)
- Volet (Acer Chromebook 515)
- Voema
- Volet
- Volteer
- Volteer2
- Volteer2_Ti50
@@ -298,7 +287,6 @@
- Alderlake-M RVP with Chrome EC
- Alderlake-N RVP
- Alderlake-N RVP with Chrome EC
- Raptorlake silicon with Alderlake-P RVP
- Raptorlake silicon with Alderlake-P RVP and Chrome EC
- Basking Ridge CRB
- Coffeelake U SO-DIMM DDR4 RVP
@@ -307,6 +295,7 @@
- Coffeelake S U-DIMM DDR4 RVP8
- Cometlake U DDR4 RVP
- Elkhartlake LPDDR4x CRB
- Galileo
- Glkrvp
- Jasperlake DDR4/LPDDR4 RVP
- Jasperlake DDR4/LPDDR4 RVP with Chrome EC
@@ -358,8 +347,6 @@
## MSI
- PRO Z690-A (WIFI) DDR4
- PRO Z690-A (WIFI)
- PRO Z790-P (WIFI) DDR4
- PRO Z790-P (WIFI)
## OpenCellular
- Elgon (GBCv2)
@@ -385,11 +372,6 @@
## Star Labs
- Star Labs Lite Mk III (N5000)
- Star Labs Lite Mk IV (N5030)
- Star Labs LabTop Mk III (i7-8550u)
- Star Labs LabTop Mk IV (i3-10110U and i7-10710U)
- Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)
- Star Labs StarBook Mk VI (i3-1220P and i7-1260P)
- Star Labs StarBook Mk VI (i3-1315U and i7-1360P)
## Supermicro
- X11SSH-TF

6
Documentation/soc/amd/psp_integration.md
View File

@@ -127,11 +127,11 @@ implementations currently use combo tables.
+--------------+---------------+------------------+----------------------------+
| Address Mode | 0x0F[7:6] | 2 | 00: x86 Physical address |
| | | | 01: offset from start of |
| | | | BIOS (flash offset) |
| | | | BIOS (flash offset) |
| | | | 02: offset from start of |
| | | | directory header |
| | | | directory header |
| | | | 03: offset from start of |
| | | | partition |
| | | | partition |
+--------------+---------------+------------------+----------------------------+
```

19
Documentation/soc/intel/broadwell/blobs.md
View File

@@ -29,25 +29,6 @@ field. For boards with an Intel GbE device, a modification of `refcode` is neede
otherwise `refcode` will disable the Intel GbE device and the OS cannot find it
in the list of PCI devices.
For the refcode binary extracted from Purism Librem 13 v1 (SHA256:
8a919ffece61ba21664b1028b0ebbfabcd727d90c1ae2f72b48152b8774323a4,
.program section starts at file offset 0x2040), we can see the
following code sequence:
1e06b: c6 43 0c 00 movb $0x0,0xc(%ebx)
1e06f: c6 83 7e 03 00 00 00 movb $0x0,0x37e(%ebx)
1e076: c6 83 70 03 00 00 01 movb $0x1,0x370(%ebx)
1e07d: 66 89 43 0a mov %ax,0xa(%ebx)
1e081: c6 83 da 01 00 00 01 movb $0x1,0x1da(%ebx)
1e088: c6 83 86 03 00 00 01 movb $0x1,0x386(%ebx)
The code at 0x1e06f sets the field that is to enable the GbE to the
hardcoded 0 value. Change the byte at 0x1e075 (file offset 0x200b5)
to 0x01 to make the refcode support Intel GbE:
cp refcode.elf refcode_gbe.elf
printf '\x01' | dd of=refcode_gbe.elf bs=1 seek=131253 count=1 conv=notrunc
## Use Broadwell SoC code for Haswell ULT boards
Haswell ULT boards can use Broadwell SoC code. To use Broadwell code for Haswell ULT

260
Documentation/util/abuild/index.md
View File

@@ -1,260 +0,0 @@
abuild
======
This utility is a great tool to check whether your coreboot tree
compiles for one or all targets. It compiles the 'default' build for a
mainboard. This is roughly equivalent to removing the .config file,
running `make menuconfig`, selecting the manufacturer and mainboard,
then saving the config without making any other changes.
It is run on all patches submitted via gerrit as part of the process.
Before submitting a patch, it is a very good idea to run abuild first
to make sure your patch compiles cleanly for all.
Note that abuild is a tool to do a simple build test, and binaries it
produces may well not boot if flashed to a system.
### Basic usage
abuild needs to be run from the coreboot directory. If you cd into the
coreboot/util/abuild directory and try to run it from there, it will
not run correctly.
If you invoke abuild with no parameters, it will build all boards
automatically.
You can also specify a single board to build with the -t option. For
example, to build the Lenovo X230 target, run:
```bash
$ util/abuild/abuild -t lenovo/x230
```
### Where builds and logs are stored
The resulting images and logs are stored in directory coreboot-builds/
under your current directory. This can be overridden with --outdir:
```bash
$ util/abuild/abuild --outdir /mnt/portable/coreboot-builds
```
This is useful if you want to divert the build to an external hard
drive, e.g. to keep the solid-state drive holding the coreboot tree
young.
(We will still refer to this directory as "coreboot-builds" below.)
After running the X230 build above, the build log will be in
coreboot-builds/LENOVO_X230/make.log.
For an overview of what passed and what failed, look at
coreboot-builds/passing_boards and coreboot-builds/failing_boards.
**These logs are overwritten with each abuild run.** Save them elsewhere
if you feel a need to reference the results later.
### Payloads
You can also specify a payload directory with -p:
```bash
mkdir payloads
cp /somewhere/filo.elf payloads
```
Then add a file payloads/payload.sh which prints the name of the
payload to use (and takes the mainboard as a parameter) such as:
```bash
echo "`dirname $0`/build/filo.elf"
```
Then you can build an image with payload by specifying:
```bash
util/abuild/abuild -t lenovo/x230 -p ./payloads
```
You can also tell abuild not to use a payload:
```bash
util/abuild/abuild -t lenovo/x230 -p none
```
### Build non-default configurations
Sometimes you do need to build test a custom, non-default configuration.
This can be accomplished by placing a config file in configs/.
First, clean your slate with `make distclean` or `rm .config`.
Then run `make menuconfig`, select the manufacturer and mainboard, and
configure the options you need to test building for.
Then save a minimal config file omitting options that did not change
from default:
```bash
make savedefconfig
```
This file is saved as `defconfig` and can be edited further.
Now this file can be saved in configs/ which will form the basis of a
custom configuration included in an abuild. However, it needs to be
named in a specific way for abuild to pick it up:
```
config.<board>_<suffix>
```
<board> is effectively the BOARD\_xxx Kconfig option without "BOARD\_".
<suffix> is a free form description of the configuration being built.
For example, a config for ASUS P8Z77-M PRO that tests building with MRC
raminit code (as opposed to the default native raminit) would be named
`config.asus_p8z77_m_pro_mrc_bin` and contains:
```
CONFIG_VENDOR_ASUS=y
CONFIG_BOARD_ASUS_P8Z77_M_PRO=y
# CONFIG_USE_NATIVE_RAMINIT is not set
CONFIG_CPU_MICROCODE_CBFS_NONE=y
# CONFIG_BOOTBLOCK_CONSOLE is not set
# CONFIG_POSTCAR_CONSOLE is not set
```
For what we are trying to do, not setting USE_NATIVE_RAMINIT is the
important part. The other three optional changes are meant to speed
things up. All these options can be selected during `make menuconfig`.
Path to MRC binary blob remains default and thus not included here.
Custom configurations can also be put in a file and applied to an entire
abuild run using -K. Assume for example you are not interested in
the postcar stage at all and just want it to shut up, you can create
a file named `myconfig` with this line:
```
# CONFIG_POSTCAR_CONSOLE is not set
```
and run `abuild -K myconfig` to build everything with a silent postcar
stage.
### Selectively build certain targets only (also config file naming caveats)
The P8Z77-M PRO example above would fail for P8Z77-M, because the
config file name is ambiguous. `abuild` would pick up this config when
building for P8Z77-M, but fails when it sees that this config isn't
meant for P8Z77-M (but for P8Z77-M PRO). To avoid this error, you have
to skip this config using --skip_set:
```bash
util/abuild/abuild --skip_set BOARD_ASUS_P8Z77_M_PRO
```
To complete the test, run abuild again specifically for this board
variant (see next section).
You can skip building other targets based on other Kconfigs. To skip
building targets without a Kconfig set, use --skip_unset:
```bash
util/abuild/abuild --skip_unset USE_NATIVE_RAMINIT
```
This example skips building configs not using (Sandy/Ivy Bridge) native
RAM init.
### Additional Examples
Many boards have multiple variants. You can build for a specific
variant of a board:
```bash
util/abuild/abuild -t asus/p8x7x-series -b p8z77-m_pro -p none
```
Many of the boards need files from the 'blobs' repository, which will
be initialized by the -B option. If the blobs repo has already been
initialized in your local tree, it won't hurt to add the -B.
```bash
util/abuild/abuild -B -t lenovo/x230 -p none
```
Adding ccache to your system and telling abuild to use it with the -y
option will speed things up a bit:
```bash
util/abuild/abuild -B -y -t lenovo/x230 -p none
```
Telling abuild to use multiple cores with the -c option helps speed
things up as well:
```bash
util/abuild/abuild -B -y -c 8 -t lenovo/x230 -p none
```
Of course, the real power of abuild is in testing multiple boards.
```bash
util/abuild/abuild -B -y -c 8 -p none
```
### Full options list
```text
coreboot autobuild v0.11.01 (Feb 3, 2023)
[...]
Usage: util/abuild/abuild [options]
util/abuild/abuild [-V|--version]
util/abuild/abuild [-h|--help]
Options:
[-a|--all] Build previously succeeded ports as well
[-A|--any-toolchain] Use any toolchain
[-b|--board-variant <name>] Build specific board variant under the
given target.
[-B|--blobs] Allow using binary files
[--checksum <path/basefile>] Store checksums at path/basefile
[-c|--cpus <numcpus>] Build on <numcpus> at the same time
[-C|--config] Configure-only mode
[-d|--dir <dir>] Directory containing config files
[-e|--exitcode] Exit with a non-zero errorlevel on failure
[-J|--junit] Write JUnit formatted xml log file
[-K|--kconfig <name>] Prepend file to generated Kconfig
[-l|--loglevel <num>] Set loglevel
[-L|--clang] Use clang on supported arch
[-n|--name] Set build name - also sets xmlfile if not
already set
[-o|--outdir <path>] Store build results in path
(defaults to coreboot-builds)
[-p|--payloads <dir>] Use payloads in <dir> to build images
[-P|--prefix <name>] File name prefix in CBFS
[-q|--quiet] Print fewer messages
[-r|--remove] Remove output dir after build
[-R|--root <path>] Absolute path to coreboot sources
(defaults to /usr/src/coreboot)
[--scan-build] Use clang's static analyzer
[--skip_set <value>] Skip building boards with this Kconfig set
[--skip_unset <value>] Skip building boards with this Kconfig not set
[--timeless] Generate timeless builds
[-t|--target <vendor/board>] Attempt to build target vendor/board only
[-T|--test] Submit image(s) to automated test system
[-u|--update] Update existing image
[-v|--verbose] Print more messages
[-x|--chromeos] Build with CHROMEOS enabled
Skip boards without ChromeOS support
[-X|--xmlfile <name>] Set JUnit XML log file filename
(defaults to /usr/src/coreboot/abuild.xml)
[-y|--ccache] Use ccache
[-z|--clean] Remove build results when finished
[-Z|--clean-somewhat] Remove build but keep coreboot.rom + config
[-V|--version] Print version number and exit
[-h|--help] Print this help and exit
[-s|--silent] obsolete
```

16
MAINTAINERS
View File

@@ -342,8 +342,6 @@ GOOGLE REX MAINBOARDS
M: Subrata Banik <subratabanik@google.com>
M: Tarun Tuli <taruntuli@google.com>
M: Kapil Porwal <kapilporwal@google.com>
M: Jakub Czapiga <jacz@semihalf.com>
M: Eran Mitrani <mitrani@google.com>
S: Maintained
F: src/mainboard/google/rex/
@@ -419,10 +417,7 @@ M: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
S: Maintained
F: src/mainboard/intel/harcuvar/
INVENTEC MAINBOARDS
M: Annie Chen <Chen.AnnieET@inventec.com>
S: Maintained
F: src/mainboard/inventec/
JETWAY MAINBOARDS
S: Orphan
@@ -868,8 +863,6 @@ INTEL METEORLAKE SOC
M: Subrata Banik <subratabanik@google.com>
M: Tarun Tuli <taruntuli@google.com>
M: Kapil Porwal <kapilporwal@google.com>
M: Jakub Czapiga <jacz@semihalf.com>
M: Eran Mitrani <mitrani@google.com>
S: Maintained
F: src/soc/intel/meteorlake/
@@ -892,10 +885,6 @@ S: Maintained
F: /src/soc/intel/braswell/
F: /src/vendorcode/intel/fsp/fsp1_1/braswell/
INTEL CANNONLAKE SOC
S: Orphan
F: src/soc/intel/cannonlake/
INTEL DENVERTON-NS SOC
M: Jeff Daly <jeffd@silicom-usa.com>
M: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
@@ -1125,7 +1114,8 @@ F: src/drivers/*/tpm/
F: src/security/tpm/
SUPERIOS & SUPERIOTOOL
S: Orphan
M: Felix Held <felix-coreboot@felixheld.de>
S: Odd Fixes
F: src/superio/
F: util/superiotool/

31
Makefile
View File

@@ -190,6 +190,10 @@ endif
# are reproducible
export LANG LC_ALL TZ SOURCE_DATE_EPOCH
ifneq ($(CONFIG_MMX),y)
CFLAGS_x86_32 += -mno-mmx
endif
ifneq ($(UNIT_TEST),1)
include toolchain.inc
endif
@@ -197,10 +201,6 @@ endif
strip_quotes = $(strip $(subst ",,$(subst \",,$(1))))
# fix makefile syntax highlighting after strip macro \" "))
ifneq ($(NOCOMPILE),1)
$(shell rm -f $(CCACHE_STATSLOG))
endif
# The primary target needs to be here before we include the
# other files
@@ -273,18 +273,17 @@ src-to-ali=\
# Add paths to files in X-y to X-srcs
# Add subdirs-y to subdirs
includemakefiles= \
$(if $(wildcard $(1)), \
$(foreach class,classes subdirs $(classes) $(special-classes), $(eval $(class)-y:=)) \
$(eval -include $(1)) \
$(foreach class,$(classes-y), $(call add-class,$(class))) \
$(foreach special,$(special-classes), \
$(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \
$(foreach class,$(classes), \
$(eval $(class)-srcs+= \
$$(subst $(absobj)/,$(obj)/, \
$$(subst $(top)/,, \
$$(abspath $$(subst $(dir $(1))/,/,$$(addprefix $(dir $(1)),$$($(class)-y)))))))) \
$(eval subdirs+=$$(subst $(CURDIR)/,,$$(wildcard $$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y)))))))
$(foreach class,classes subdirs $(classes) $(special-classes), $(eval $(class)-y:=)) \
$(eval -include $(1)) \
$(foreach class,$(classes-y), $(call add-class,$(class))) \
$(foreach special,$(special-classes), \
$(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \
$(foreach class,$(classes), \
$(eval $(class)-srcs+= \
$$(subst $(absobj)/,$(obj)/, \
$$(subst $(top)/,, \
$$(abspath $$(subst $(dir $(1))/,/,$$(addprefix $(dir $(1)),$$($(class)-y)))))))) \
$(eval subdirs+=$$(subst $(CURDIR)/,,$$(wildcard $$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y))))))
# For each path in $(subdirs) call includemakefiles
# Repeat until subdirs is empty

84
Makefile.inc
View File

@@ -23,7 +23,7 @@ ifeq ($(BUILD_TIMELESS),1)
KERNELVERSION := -TIMELESS--LESSTIME-
else
KERNELVERSION := $(strip $(if $(GIT),\
$(shell git describe --abbrev=12 --dirty --always || git describe),\
$(shell git describe --dirty --always || git describe),\
$(if $(wildcard $(top)/.coreboot-version),\
$(shell cat $(top)/.coreboot-version),\
coreboot-unknown$(KERNELREVISION))))
@@ -66,11 +66,8 @@ coreboot: $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool $(obj)/ifwitool $(
# targets after the build completes by creating a Makefile.inc in the
# site-local directory with a target named 'build_complete::'
build_complete:: coreboot
printf "\nBuilt %s (%s)\n" $(MAINBOARDDIR) $(CONFIG_MAINBOARD_PART_NUMBER)
if [ -f "$(CCACHE_STATSLOG)" ]; then \
printf "\nccache statistics\n"; \
$(CCACHE) --show-log-stats -v; \
fi
printf "\nBuilt %s (%s)\n" $(MAINBOARDDIR) \
$(CONFIG_MAINBOARD_PART_NUMBER)
# This target can be used to run rules after all files were added to CBFS,
# for example to process FMAP regions or the entire image.
@@ -146,7 +143,6 @@ $(foreach supported_arch,$(ARCH_SUPPORTED), \
# tolower: returns the value in all lowercase
# toupper: returns the value in all uppercase
# ws_to_under: returns the value with any whitespace changed to underscores
# get_fmap_value returns the value of a given FMAP field from fmap_config.h
_toint=$(shell printf "%d" $1)
_tohex=$(shell printf 0x"%x" $1)
_int-add2=$(shell expr $(call _toint,$1) + $(call _toint,$2))
@@ -166,7 +162,6 @@ file-size=$(strip $(shell wc -c "$1" | cut -f 1 -d ' '))
tolower=$(shell echo '$1' | tr '[:upper:]' '[:lower:]')
toupper=$(shell echo '$1' | tr '[:lower:]' '[:upper:]')
ws_to_under=$(shell echo '$1' | tr ' \t' '_')
get_fmap_value=$(shell awk '$$2 == "$1" {print $$3}' $(obj)/fmap_config.h)
#######################################################################
# Helper functions for ramstage postprocess
@@ -331,19 +326,6 @@ define cbfs-files-processor-config
mv -f $(2).tmp $(2))
endef
#######################################################################
# Add a file to CBFS with just type and compression values
# arg1: name in CBFS
# arg2: filename and path
# arg3: type in CBFS
# arg4: compression type
define add-cbfs-file-simple
$(eval cbfs-files-y += $(1))
$(eval $(1)-file := $(2))
$(eval $(1)-type := $(3))
$(eval $(1)-compression := $(4))
endef
#######################################################################
# Compile a C file with a bare struct definition into binary
# arg1: C source file
@@ -356,41 +338,6 @@ cbfs-files-processor-struct= \
rm -f $(2).tmp) \
$(eval DEPENDENCIES += $(2).d)
#######################################################################
# Convert image to YCC 4:2:0 JPEG
#
# In two steps:
# 1. Convert to RGB colors, optionally resize and store as BMP.
# 2. Round final size to multiples of 16, optionally swap colors,
# convert (back) to sRGB and store as JPEG.
# The split is necessary because we don't know the exact, scaled
# size due to aspect-ratio. Note: IM v7 would allow us to do the
# calculations in one command using %[fx:...] syntax.
#
# arg1: image input file
# arg2: output jpg
cbfs-files-processor-jpg420= \
$(eval $(2): $(1) $(KCONFIG_AUTOCONFIG); \
printf " CONVERT $$<\n"; \
res=$(CONFIG_BOOTSPLASH_CONVERT_RESOLUTION); \
res=$$$$(convert $$< \
-colorspace RGB \
$$(BOOTSPLASH_RESIZE-y) \
-format '%wx%h' -write info: \
bmp:$$@); \
convert $$@ \
$$(BOOTSPLASH_ROUND16) \
$$(BOOTSPLASH_COLORSWAP-y) \
-colorspace sRGB \
-quality $$(CONFIG_BOOTSPLASH_CONVERT_QUALITY)% \
-interlace none -colorspace YCC -sampling-factor 4:2:0 \
jpg:$$@)
BOOTSPLASH_FLOOR = $$(($${res%%x*} & ~15))x$$(($${res\#\#*x} & ~15))
BOOTSPLASH_RESIZE-$(CONFIG_BOOTSPLASH_CONVERT_RESIZE) = -resize $(BOOTSPLASH_FLOOR)
BOOTSPLASH_CEIL = $$((($${res%%x*} + 15) & ~15))x$$((($${res\#\#*x} + 15) & ~15))
BOOTSPLASH_ROUND16 = -background black -gravity center -extent $(BOOTSPLASH_CEIL)
BOOTSPLASH_COLORSWAP-$(CONFIG_BOOTSPLASH_CONVERT_COLORSWAP) := -channel-fx 'red<=>blue'
#######################################################################
# Add handler for arbitrary files in CBFS
$(call add-special-class,cbfs-files)
@@ -488,7 +435,7 @@ ifeq ($(CONFIG_COMPILER_GCC),y)
ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
CFLAGS_common += -Wno-packed-not-aligned
CFLAGS_common += -fconserve-stack
CFLAGS_common += -Wnull-dereference
CFLAGS_common += -Wnull-dereference -Wreturn-type
CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wno-array-compare
endif
endif
@@ -650,8 +597,6 @@ APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py
APCB_V3_EDIT_TOOL:=$(top)/util/apcb/apcb_v3_edit.py
APCB_V3A_EDIT_TOOL:=$(top)/util/apcb/apcb_v3a_edit.py
CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage
FUTILITY?=$(objutil)/futility/futility
@@ -866,7 +811,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(objcbfs)/%.map
# mma, efi, deleted, null
# 4 - Compression type [$(FILENAME)-compression]
# none, LZMA
# 5 - Base address [$(FILENAME)-position]
# 5 - Base address [$(FILANAME)-position]
# 6 - Alignment [$(FILENAME)-align]
# 7 - cbfstool flags [$(FILENAME)-options]
#
@@ -1068,15 +1013,6 @@ else
FMAP_VPD_ENTRY :=
endif
ifeq ($(CONFIG_INCLUDE_HSPHY_IN_FMAP),y)
FMAP_HSPHY_FW_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x1000)
FMAP_HSPHY_FW_SIZE := $(CONFIG_HSPHY_FW_MAX_SIZE)
FMAP_HSPHY_FW_ENTRY := HSPHY_FW@$(FMAP_HSPHY_FW_BASE) $(FMAP_HSPHY_FW_SIZE)
FMAP_CURRENT_BASE := $(call int-add, $(FMAP_HSPHY_FW_BASE) $(FMAP_HSPHY_FW_SIZE))
else
FMAP_HSPHY_FW_ENTRY :=
endif
#
# X86 FMAP region
#
@@ -1155,7 +1091,6 @@ $(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h
-e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \
-e "s,##SPD_CACHE_ENTRY##,$(FMAP_SPD_CACHE_ENTRY)," \
-e "s,##VPD_ENTRY##,$(FMAP_VPD_ENTRY)," \
-e "s,##HSPHY_FW_ENTRY##,$(FMAP_HSPHY_FW_ENTRY)," \
-e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \
-e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \
$(DEFAULT_FLASHMAP) > $@.tmp
@@ -1316,19 +1251,10 @@ cbfs-files-y += build_info
build_info-file := $(obj)/build_info
build_info-type := raw
ifeq ($(CONFIG_BOOTSPLASH_CONVERT),y)
ifeq ($(shell command -v convert),)
$(error CONFIG_BOOTSPLASH_CONVERT requires the convert program (part of ImageMagick))
endif
cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash.jpg
bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)):jpg420
bootsplash.jpg-type := bootsplash
else
BOOTSPLASH_SUFFIX=$(suffix $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)))
cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash$(BOOTSPLASH_SUFFIX)
bootsplash$(BOOTSPLASH_SUFFIX)-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))
bootsplash$(BOOTSPLASH_SUFFIX)-type := bootsplash
endif
# Ensure that no payload segment overlaps with memory regions used by ramstage
# (not for x86 since it can relocate itself in that case)

16
configs/builder/config.transformers
View File

@@ -1,16 +0,0 @@
# Inventec Transformers coreboot is modified from Intel ArcherCity CRB
# Inventec Transformers is a dual socket CRB based on Intel.
# Sapphire Rapids Scalable Processor (SPR-SP) chipset.
#
# Type this in coreboot root directory to get a working .config:
# make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.ac
CONFIG_VENDOR_INVENTEC=y
CONFIG_BOARD_INVENTEC_TRANSFORMERS=y
CONFIG_HAVE_IFD_BIN=y
CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
CONFIG_PAYLOAD_LINUX=y
CONFIG_PAYLOAD_FILE="site-local/transformers/linuxboot_bzImage"
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-55-04"

11
configs/config.msi_ms7e06_ddr4
View File

@@ -1,11 +0,0 @@
CONFIG_VENDOR_MSI=y
CONFIG_VBOOT=y
CONFIG_BOARD_MSI_Z790_P_PRO_WIFI_DDR4=y
CONFIG_TPM_MEASURED_BOOT=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
CONFIG_TPM2=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_PAYLOAD_EDK2=y
CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
CONFIG_EDK2_CBMEM_LOGGING=y
CONFIG_EDK2_FOLLOW_BGRT_SPEC=y

11
configs/config.msi_ms7e06_ddr5
View File

@@ -1,11 +0,0 @@
CONFIG_VENDOR_MSI=y
CONFIG_VBOOT=y
CONFIG_BOARD_MSI_Z790_P_PRO_WIFI=y
CONFIG_TPM_MEASURED_BOOT=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
CONFIG_TPM2=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_PAYLOAD_EDK2=y
CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
CONFIG_EDK2_CBMEM_LOGGING=y
CONFIG_EDK2_FOLLOW_BGRT_SPEC=y

8
configs/config.starlabs_starbook_adl_option_table
View File

@@ -1,8 +0,0 @@
CONFIG_VENDOR_STARLABS=y
CONFIG_BOARD_STARLABS_STARBOOK_ADL=y
CONFIG_MAINBOARD_SERIAL_NUMBER="B6I0000"
CONFIG_USE_OPTION_TABLE=y
CONFIG_LOCALVERSION="8.42"
CONFIG_MAINBOARD_USE_LIBGFXINIT=n
CONFIG_SMMSTORE=y
CONFIG_SMMSTORE_V2=y

2
payloads/coreinfo/bootlog_module.c
View File

@@ -17,7 +17,7 @@ static s32 g_max_cursor_line = 0;
struct cbmem_console {
u32 size;
u32 cursor;
u8 body[];
u8 body[0];
} __packed;
#define CURSOR_MASK ((1 << 28) - 1)

4
payloads/coreinfo/cbfs_module.c
View File

@@ -31,7 +31,7 @@ struct cbheader {
u32 align;
u32 offset;
u32 architecture;
u32 pad[];
u32 pad[1];
} __packed;
struct cbfile {
@@ -40,7 +40,7 @@ struct cbfile {
u32 type;
u32 checksum;
u32 offset;
char filename[];
char filename[0];
} __packed;
static int filecount = 0, selected = 0, start_row = 0;

2
payloads/external/FILO/Kconfig vendored
View File

@@ -9,7 +9,7 @@ config FILO_STABLE
help
Tested FILO version
config FILO_HEAD
config FILO_MASTER
bool "HEAD"
help
Newest FILO version

6
payloads/external/FILO/Makefile vendored
View File

@@ -1,5 +1,5 @@
TAG-$(CONFIG_FILO_HEAD)=origin/main
NAME-$(CONFIG_FILO_HEAD)=MAIN
TAG-$(CONFIG_FILO_MASTER)=origin/master
NAME-$(CONFIG_FILO_MASTER)=MASTER
TAG-$(CONFIG_FILO_STABLE)=c2fa1ea6125c63e84cdf7779c37d76da8c5bc412
NAME-$(CONFIG_FILO_STABLE)=STABLE
@@ -20,7 +20,7 @@ checkout:
test -d filo || \
git clone $(project_git_repo) $(project_dir)
cd filo && \
git checkout main && \
git checkout master && \
git remote update && \
test -n $(TAG-y) && \
git branch -f $(NAME-y) $(TAG-y) && \

116
payloads/external/LinuxBoot/Kconfig vendored
View File

@@ -19,13 +19,6 @@ config LINUXBOOT_X86
help
X86 kernel and initramfs
config LINUXBOOT_ARM
bool "arm64"
depends on ARCH_ARM
select PAYLOAD_FIT_SUPPORT
help
arm kernel and initramfs
config LINUXBOOT_ARM64
bool "arm64"
depends on ARCH_ARM64
@@ -33,16 +26,9 @@ config LINUXBOOT_ARM64
help
AARCH64 kernel and initramfs
config LINUXBOOT_RISCV_RV32
config LINUXBOOT_RISCV
bool "RISC-V"
depends on ARCH_RISCV_RV32
select PAYLOAD_FIT_SUPPORT
help
RISC-V kernel and initramfs
config LINUXBOOT_RISCV_RV64
bool "RISC-V"
depends on ARCH_RISCV_RV64
depends on ARCH_RISCV
select PAYLOAD_FIT_SUPPORT
help
RISC-V kernel and initramfs
@@ -55,38 +41,76 @@ config LINUXBOOT_COMPILE_KERNEL
bool "Compile kernel"
default n
if LINUXBOOT_COMPILE_KERNEL
comment "parse linux crosscompiler with: LINUXBOOT_CROSS_COMPILE"
endif
config LINUXBOOT_KERNEL_PATH
string "Path to kernel"
default "build/uImage" if LINUXBOOT_KERNEL_UIMAGE
default "build/bzImage" if LINUXBOOT_KERNEL_BZIMAGE
help
The kernel path is either and absolute path or relative to the
LinuxBoot directory
default "Image"
depends on !LINUXBOOT_COMPILE_KERNEL
if LINUXBOOT_COMPILE_KERNEL
config LINUXBOOT_CROSS_COMPILE
string "cross compiler"
default "" # e.g. "aarch64-linux-gnu-"
choice
prompt "Kernel release"
default LINUXBOOT_KERNEL_STABLE
help
Choose a custom cross compiler toolchain to use.
It can be useful if you don't want to use the coreboot toolchain
or experience problems using it.
Choose the kernel release.
config LINUXBOOT_KERNEL_VERSION
Select 'custom' if your want to define the kernel version.
For more information about the current 'mainline', 'stable' or 'longterm'
version, visit: https://www.kernel.org/
config LINUXBOOT_KERNEL_MAINLINE
bool "mainline"
help
Mainline kernel version
config LINUXBOOT_KERNEL_STABLE
bool "stable"
help
Stable kernel version
config LINUXBOOT_KERNEL_LONGTERM
bool "longterm"
help
Longterm (LTS) kernel version
config LINUXBOOT_KERNEL_CUSTOM
bool "custom"
help
Custom kernel version
endchoice
config LINUXBOOT_KERNEL_CUSTOM_VERSION
string "kernel version"
default "6.3"
default ""
depends on LINUXBOOT_KERNEL_CUSTOM
help
Choose the Linux kernel version number. (x.x.x)
Release candidate kernels (rc) are currently are not supported.
choice
prompt "Kernel configuration"
default LINUXBOOT_KERNEL_ARCH_DEFAULT_CONFIG
config LINUXBOOT_KERNEL_ARCH_DEFAULT_CONFIG
bool "Default architecture configuration"
help
This option will use the default configuration for the
selected architecture.
config LINUXBOOT_KERNEL_CUSTOM_CONFIG
bool "Custom (def)config file"
endchoice
config LINUXBOOT_KERNEL_CONFIGFILE
string "Config file path"
default "i386/defconfig" if LINUXBOOT_X86
default "x86_64/defconfig" if LINUXBOOT_X86_64
default "arm64/defconfig" if LINUXBOOT_ARM64
default "riscv/defconfig-32" if LINUXBOOT_RISCV_RV32
default "riscv/defconfig-64" if LINUXBOOT_RISCV_RV64
default "defconfig"
depends on LINUXBOOT_KERNEL_CUSTOM_CONFIG
help
Path to the kernel configuration file.
@@ -95,7 +119,7 @@ config LINUXBOOT_KERNEL_CONFIGFILE
choice
prompt "Kernel binary format"
default LINUXBOOT_KERNEL_BZIMAGE if LINUXBOOT_X86 || LINUXBOOT_X86_64
default LINUXBOOT_KERNEL_UIMAGE if LINUXBOOT_ARM64 || LINUXBOOT_RISCV_RV32 || LINUXBOOT_RISCV_RV64
default LINUXBOOT_KERNEL_UIMAGE if LINUXBOOT_ARM64 || LINUXBOOT_RISCV
config LINUXBOOT_KERNEL_BZIMAGE
bool "bzImage"
@@ -103,14 +127,14 @@ config LINUXBOOT_KERNEL_BZIMAGE
config LINUXBOOT_KERNEL_UIMAGE
bool "uImage"
depends on LINUXBOOT_ARM64 || LINUXBOOT_RISCV_RV32 || LINUXBOOT_RISCV_RV64
depends on LINUXBOOT_ARM64 || LINUXBOOT_RISCV
endchoice
config LINUXBOOT_DTS_FILE
config LINUXBOOT_DTB_FILE
string "Compiled devicetree file"
depends on LINUXBOOT_ARM64 || LINUXBOOT_RISCV_RV32 || LINUXBOOT_RISCV_RV64
default "empty.dts"
depends on LINUXBOOT_ARM64 || LINUXBOOT_RISCV
default ""
endif #LINUXBOOT_COMPILE_KERNEL
@@ -121,7 +145,9 @@ config LINUX_COMMAND_LINE
Add your own kernel command-line arguments.
config PAYLOAD_FILE
default "payloads/external/LinuxBoot/build/Image"
default "payloads/external/LinuxBoot/linuxboot/bzImage" if LINUXBOOT_COMPILE_KERNEL && ( LINUXBOOT_X86 || LINUXBOOT_X86_64 )
default "payloads/external/LinuxBoot/linuxboot/uImage" if LINUXBOOT_COMPILE_KERNEL && (LINUXBOOT_ARM64 || LINUXBOOT_RISCV)
default LINUXBOOT_KERNEL_PATH if !LINUXBOOT_COMPILE_KERNEL
comment "Linux initramfs"
@@ -131,17 +157,16 @@ config LINUXBOOT_BUILD_INITRAMFS
config LINUXBOOT_INITRAMFS_PATH
string "Path to initramfs"
default "build/initramfs_u-root.cpio" if LINUXBOOT_UROOT
depends on !LINUXBOOT_BUILD_INITRAMFS
if LINUXBOOT_BUILD_INITRAMFS
choice
prompt "Initramfs"
prompt "Payload Mode"
default LINUXBOOT_UROOT
config LINUXBOOT_UROOT
bool "u-root"
depends on !LINUXBOOT_RISCV_RV32 # not supported by u-root
help
Enable u-root linuxboot mode.
See http://u-root.tk/ for more information.
@@ -320,6 +345,11 @@ config LINUXBOOT_INITRAMFS_COMPRESSION_XZ
endchoice
config LINUX_INITRD
string
default "payloads/external/LinuxBoot/linuxboot/initramfs_u-root.cpio" if LINUXBOOT_UROOT
default LINUXBOOT_INITRAMFS_PATH if !LINUXBOOT_BUILD_INITRAMFS
config LINUXBOOT_INITRAMFS_SUFFIX
string
default "" if LINUXBOOT_INITRAMFS_COMPRESSION_NONE

85
payloads/external/LinuxBoot/Makefile vendored
View File

@@ -1,57 +1,62 @@
## SPDX-License-Identifier: GPL-2.0-only
project_dir=linuxboot
unexport $(COREBOOT_EXPORTS)
DTC ?= dtc
all: linuxboot
LINUX_ARCH-$(CONFIG_LINUXBOOT_X86_64) = x86_64
LINUX_ARCH-$(CONFIG_LINUXBOOT_X86) = i386
LINUX_ARCH-$(CONFIG_LINUXBOOT_ARM64) = arm64
LINUX_ARCH-$(CONFIG_LINUXBOOT_RISCV_RV32) = riscv
LINUX_ARCH-$(CONFIG_LINUXBOOT_RISCV_RV64) = riscv
u-root:
$(MAKE) -f targets/u-root.mk
build/Image: $(CONFIG_LINUXBOOT_KERNEL_PATH) | build
ln -s -r $< $@
ifeq ($(CONFIG_LINUXBOOT_BUILD_INITRAMFS),y)
ifeq ($(CONFIG_LINUXBOOT_UROOT),y)
initramfs: u-root
endif
else
ifneq ($(CONFIG_LINUXBOOT_INITRAMFS),)
initramfs:
if [[ ! -f "$(top)/$(CONFIG_LINUXBOOT_INITRAMFS)" ]]; then \
echo "<< Linux initramfs '$(CONFIG_LINUXBOOT_INITRAMFS)' is missing. >>"; \
exit 1; \
fi
endif
endif
initramfs_compressed: initramfs
ifeq ($(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ),y)
xz --keep --force --check=crc32 --lzma2=dict=1MiB $(top)/$(CONFIG_LINUXBOOT_INITRAMFS)
endif
ifeq ($(CONFIG_LINUXBOOT_COMPILE_KERNEL),y)
include targets/linux.mk
ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
kernel: initramfs
if [[ ! -f "$(top)/$(CONFIG_LINUXBOOT_DTB_FILE)" ]]; then \
echo "<< Linux kernel devicetree is missing. >>"; \
exit 1; \
fi
$(MAKE) -f targets/linux.mk
else
kernel:
$(MAKE) -f targets/linux.mk
endif
ifeq ($(CONFIG_LINUXBOOT_UROOT),y)
include targets/u-root.mk
else
kernel:
if [[ ! -f "$(top)/$(CONFIG_LINUXBOOT_KERNEL)" ]]; then \
echo "<< Linux kernel '$(CONFIG_LINUXBOOT_KERNEL)' is missing. >>"; \
exit 1; \
fi
endif
build/initramfs: $(CONFIG_LINUXBOOT_INITRAMFS_PATH) | build
ifeq ($(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ),y)
xz --keep --force --check=crc32 --lzma2=dict=1MiB $(CONFIG_LINUXBOOT_INITRAMFS_PATH)
endif
cp $(CONFIG_LINUXBOOT_INITRAMFS_PATH)$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX) $@
ifeq ($(CONFIG_LINUXBOOT_KERNEL_BZIMAGE),y)
build/bzImage: $(kernel_dir)/arch/x86/boot/bzImage | build
cp $< $@
else ifeq ($(CONFIG_LINUXBOOT_KERNEL_UIMAGE),y)
build/target.dtb: $(CONFIG_LINUXBOOT_DTS_FILE)
$(DTC) -o $@ $<
build/uImage: build/vmlinux.bin.lzma build/initramfs build/target.dtb $(LINUX_ARCH-y)/kernel_fdt_lzma.its | build
mkimage -f $(LINUX_ARCH-y)/kernel_fdt_lzma.its $@
endif # CONFIG_LINUXBOOT_KERNEL_BZIMAGE
build:
mkdir build
linuxboot: kernel initramfs_compressed
clean:
rm -rf build/kernel*
rm -f build/u-root
rm -f build/initramfs*
rm -f build/bzImage
rm -rf $(project_dir)/kernel*
rm -f $(project_dir)/u-root
rm -f $(project_dir)/initramfs*
rm -f $(project_dir)/bzImage
distclean:
rm -rf build
rm -rf $(project_dir)
.PHONY: linuxboot clean distclean
.PHONY: linuxboot kernel initramfs_compressed initramfs u-root clean distclean

7
payloads/external/LinuxBoot/arm64/kernel_fdt_lzma.its vendored
View File

@@ -11,7 +11,7 @@
images {
kernel {
description = "Vanilla Linux kernel";
data = /incbin/("../build/vmlinux.bin.lzma");
data = /incbin/("vmlinux.bin.lzma");
type = "kernel";
arch = "arm64";
os = "linux";
@@ -30,7 +30,7 @@
};
fdt-1 {
description = "Flattened Device Tree blob";
data = /incbin/("../build/target.dtb");
data = /incbin/("target.dtb");
type = "flat_dt";
arch = "arm64";
compression = "none";
@@ -46,7 +46,7 @@
};
ramdisk-1 {
description = "Compressed Initramfs";
data = /incbin/("../build/initramfs");
data = /incbin/("initramfs");
type = "ramdisk";
arch = "arm64";
os = "linux";
@@ -65,7 +65,6 @@
configurations {
default = "conf-1";
conf-1 {
compatible = "linuxboot";
description = "Boot Linux kernel with FDT blob";
kernel = "kernel";
fdt = "fdt-1";

4
payloads/external/LinuxBoot/empty.dts vendored
View File

@@ -1,4 +0,0 @@
/dts-v1/;
/ {
};

4
payloads/external/LinuxBoot/riscv/defconfig-32 vendored
View File

@@ -1,4 +0,0 @@
CONFIG_ARCH_RV32I=y
CONFIG_32BIT=y
# CONFIG_PORTABLE is not set
CONFIG_NONPORTABLE=y

2
payloads/external/LinuxBoot/riscv/defconfig-64 vendored
View File

@@ -1,2 +0,0 @@
CONFIG_ARCH_RV64I=y
CONFIG_64BIT=y

74
payloads/external/LinuxBoot/riscv/kernel_fdt_lzma.its vendored
View File

@@ -1,74 +0,0 @@
/*
* Simple U-Boot uImage source file containing a single kernel and FDT blob
*/
/dts-v1/;
/ {
description = "Simple image with single Linux kernel and FDT blob";
#address-cells = <1>;
images {
kernel {
description = "Vanilla Linux kernel";
data = /incbin/("../build/vmlinux.bin.lzma");
type = "kernel";
arch = "riscv64";
os = "linux";
compression = "lzma";
load = <0x80000>;
entry = <0x80000>;
hash-1 {
algo = "crc32";
};
hash-2 {
algo = "sha1";
};
hash-3 {
algo = "sha256";
};
};
fdt-1 {
description = "Flattened Device Tree blob";
data = /incbin/("../build/target.dtb");
type = "flat_dt";
arch = "riscv64";
compression = "none";
hash-1 {
algo = "crc32";
};
hash-2 {
algo = "sha1";
};
hash-3 {
algo = "sha256";
};
};
ramdisk-1 {
description = "Compressed Initramfs";
data = /incbin/("../build/initramfs");
type = "ramdisk";
arch = "riscv64";
os = "linux";
compression = "none";
load = <00000000>;
entry = <00000000>;
hash-1 {
algo = "sha1";
};
hash-2 {
algo = "sha256";
};
};
};
configurations {
default = "conf-1";
conf-1 {
description = "Boot Linux kernel with FDT blob";
kernel = "kernel";
fdt = "fdt-1";
ramdisk = "ramdisk-1";
};
};
};

123
payloads/external/LinuxBoot/targets/linux.mk vendored
View File

@@ -1,20 +1,41 @@
## SPDX-License-Identifier: GPL-2.0-only
SHELL := /bin/sh
SHELL := /bin/bash
OBJCOPY:=$(CONFIG_LINUXBOOT_CROSS_COMPILE)objcopy
ARCH-$(CONFIG_LINUXBOOT_X86_64)=x86_64
ARCH-$(CONFIG_LINUXBOOT_X86)=x86
ARCH-$(CONFIG_LINUXBOOT_ARM64)=arm64
TAG-$(CONFIG_LINUXBOOT_KERNEL_MAINLINE)=mainline
TAG-$(CONFIG_LINUXBOOT_KERNEL_STABLE)=stable
TAG-$(CONFIG_LINUXBOOT_KERNEL_LONGTERM)=longterm
pwd:=$(shell pwd)
top:=../../..
project_dir=linuxboot
tarball_dir:=$(project_dir)/tarball
decompress_flag=.done
OBJCOPY:=$(LINUXBOOT_CROSS_COMPILE)objcopy
KERNEL_MAKE_FLAGS = \
CROSS_COMPILE=$(CONFIG_LINUXBOOT_CROSS_COMPILE) \
ARCH=$(LINUX_ARCH-y) \
ARCH=$(ARCH-y) \
KBUILD_BUILD_USER="coreboot" \
KBUILD_BUILD_HOST="reproducible" \
KBUILD_BUILD_TIMESTAMP="$(shell perl -e 'print scalar gmtime($(SOURCE_DATE_EPOCH))')" \
KBUILD_BUILD_VERSION="0"
kernel_version = $(CONFIG_LINUXBOOT_KERNEL_VERSION)
kernel_dir = build/kernel-$(subst .,_,$(kernel_version))
kernel_tarball = linux-$(kernel_version).tar
kernel_mirror = https://mirrors.edge.kernel.org/pub/linux/kernel
ifeq ($(CONFIG_LINUXBOOT_KERNEL_CUSTOM),y)
kernel_version:=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM_VERSION)
else
kernel_version:=$(shell curl -sS -k https://www.kernel.org/feeds/kdist.xml | \
sed -n -e 's@.*<guid isPermaLink="false">\(.*\)</guid>.*@\1@p' | \
awk -F ',' '/$(TAG-y)/{ print $$3 }' | \
head -n 1)
endif
kernel_dir=$(project_dir)/kernel-$(subst .,_,$(kernel_version))
kernel_tarball=linux-$(kernel_version).tar
kernel_mirror=https://mirrors.edge.kernel.org/pub/linux/kernel
ifeq ($(findstring x2.6.,x$(kernel_version)),x2.6.)
kernel_mirror_path := $(kernel_mirror)/v2.6
@@ -28,35 +49,81 @@ else ifeq ($(findstring x6.,x$(kernel_version)),x6.)
kernel_mirror_path := $(kernel_mirror)/v6.x
endif
build/$(kernel_tarball).xz: | build
echo " Test $(kernel_version)"
echo " WWW $(kernel_mirror_path)/$(kernel_tarball).xz";
curl -OLSs --output-dir build "$(kernel_mirror_path)/$(kernel_tarball).xz";
all: kernel
$(kernel_dir): build/$(kernel_tarball).xz
echo " XZ $(kernel_tarball).xz";
mkdir $(kernel_dir);
tar xJf build/$(kernel_tarball).xz --strip 1 -C $(kernel_dir);
lookup:
ifeq ($(kernel_version),)
$(error kernel version lookup failed for $(TAG-y) release)
endif
@echo " WWW Kernel [$(TAG-y)] $(kernel_version)"
$(kernel_dir)/.config: $(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) | $(kernel_dir)
fetch:
ifneq ($(shell [[ -d "$(kernel_dir)" && -f "$(kernel_dir)/$(decompress_flag)" ]];echo $$?),0)
mkdir -p $(tarball_dir)
if [[ ! -f $(tarball_dir)/$(kernel_tarball).xz && ! -f $(tarball_dir)/$(kernel_tarball).xz ]]; then \
echo " WWW $(kernel_tarball).xz"; \
cd $(tarball_dir); \
curl -OLSs "$(kernel_mirror_path)/$(kernel_tarball).xz"; \
cd $(pwd); \
fi
endif
unpack: fetch
if [[ -d "$(kernel_dir)" && ! -f "$(kernel_dir)/$(decompress_flag)" ]]; then \
rm -rf $(kernel_dir); \
fi
if [[ ! -d "$(kernel_dir)" ]]; then \
mkdir $(kernel_dir); \
echo " XZ $(kernel_tarball).xz"; \
tar xJf $(tarball_dir)/$(kernel_tarball).xz --strip 1 -C $(kernel_dir); \
fi
touch $(kernel_dir)/$(decompress_flag)
$(kernel_dir)/.config: unpack
@echo " CONFIG Linux $(kernel_version)"
ifeq ($(CONFIG_LINUXBOOT_KERNEL_CUSTOM_CONFIG),y)
cp $(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) $(kernel_dir)/.config
else
cp $(ARCH-y)/defconfig $(kernel_dir)/.config
endif
$(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) olddefconfig
$(kernel_dir)/vmlinux : $(kernel_dir)/.config | $(kernel_dir)
build: $(kernel_dir)/.config
@echo " MAKE Linux $(kernel_version)"
echo "$(MAKE) -j 4 -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) vmlinux"
$(MAKE) -j 4 -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) vmlinux
ifeq ($(CONFIG_LINUXBOOT_KERNEL_BZIMAGE),y)
$(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) bzImage
else
ifeq ($(CONFIG_LINUXBOOT_KERNEL_UIMAGE),y)
$(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) vmlinux
endif
endif
build/vmlinux.bin: $(kernel_dir)/vmlinux | build
ifeq ($(CONFIG_LINUXBOOT_KERNEL_BZIMAGE),y)
$(top)/$(CONFIG_LINUXBOOT_KERNEL): build
@echo " CP bzImage"
cp $(kernel_dir)/arch/x86/boot/bzImage $@
else
ifeq ($(CONFIG_LINUXBOOT_KERNEL_UIMAGE),y)
$(project_dir)/target.dtb: $(top)/$(CONFIG_LINUXBOOT_DTB_FILE)
cp $< $@
$(project_dir)/vmlinux.bin: $(kernel_dir)/vmlinux
$(OBJCOPY) -O binary $< $@
build/vmlinux.bin.lzma: build/vmlinux.bin
$(project_dir)/vmlinux.bin.lzma: $(project_dir)/vmlinux.bin
xz -c -k -f --format=lzma --lzma1=dict=1MiB,lc=3,lp=0,pb=3 $< > $@
$(top)/$(CONFIG_LINUXBOOT_KERNEL): build $(project_dir)/vmlinux.bin.lzma $(project_dir)/target.dtb
cp $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir)
cp $(top)/$(CONFIG_LINUXBOOT_INITRAMFS)$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX) $(project_dir)/initramfs
mkimage -f $(project_dir)/kernel_fdt_lzma.its $@
else
$(error Kernel image format not found)
exit 1
endif
endif
$(kernel_dir)/arch/x86/boot/bzImage: $(kernel_dir)/.config
@echo " MAKE Linux $(kernel_version)"
echo "$(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) bzImage"
$(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) bzImage
ifneq ($(TAG-y),)
kernel: lookup $(top)/$(CONFIG_LINUXBOOT_KERNEL)
else
kernel: $(top)/$(CONFIG_LINUXBOOT_KERNEL)
endif
.PHONY: kernel
.PHONY: all kernel build unpack fetch check

66
payloads/external/LinuxBoot/targets/u-root.mk vendored
View File

@@ -1,26 +1,29 @@
## SPDX-License-Identifier: GPL-2.0-only
uroot_package = github.com/u-root/u-root
uroot_build = build/go/src/$(uroot_package)
project_dir=$(shell pwd)/linuxboot
go_path_dir=$(project_dir)/go
uroot_bin=$(project_dir)/u-root
uroot_package=github.com/u-root/u-root
UROOT_ARCH-$(CONFIG_LIBUXBOOT_X86_64) = amd64
UROOT_ARCH-$(CONFIG_LINUXBOOT_X86) = 386
UROOT_ARCH-$(CONFIG_LINUXBOOT_ARM64) = arm64
UROOT_ARCH-$(CONFIG_LINUXBOOT_RISCV_RV64) = riscv64
ARCH-$(CONFIG_LIBUXBOOT_X86_64)=amd64
ARCH-$(CONFIG_LINUXBOOT_X86)=i386
ARCH-$(CONFIG_LINUXBOOT_ARM64)=arm64
go_version = $(shell go version | sed -nr 's/.*go([0-9]+\.[0-9]+.?[0-9]?).*/\1/p' )
go_version_major = $(shell echo $(go_version) | sed -nr 's/^([0-9]+)\.([0-9]+)\.?([0-9]*)$$/\1/p')
go_version_minor = $(shell echo $(go_version) | sed -nr 's/^([0-9]+)\.([0-9]+)\.?([0-9]*)$$/\2/p')
go_version=$(shell go version | sed -nr 's/.*go([0-9]+\.[0-9]+.?[0-9]?).*/\1/p' )
go_version_major=$(shell echo $(go_version) | sed -nr 's/^([0-9]+)\.([0-9]+)\.?([0-9]*)$$/\1/p')
go_version_minor=$(shell echo $(go_version) | sed -nr 's/^([0-9]+)\.([0-9]+)\.?([0-9]*)$$/\2/p')
uroot_args += -build=$(CONFIG_LINUXBOOT_UROOT_FORMAT)
uroot_args += -initcmd $(CONFIG_LINUXBOOT_UROOT_INITCMD)
uroot_args += -uinitcmd=$(CONFIG_LINUXBOOT_UROOT_UINITCMD)
uroot_args += -defaultsh $(CONFIG_LINUXBOOT_UROOT_SHELL)
uroot_args+=-build=$(CONFIG_LINUXBOOT_UROOT_FORMAT)
uroot_args+=-initcmd $(CONFIG_LINUXBOOT_UROOT_INITCMD)
uroot_args+=-uinitcmd=$(CONFIG_LINUXBOOT_UROOT_UINITCMD)
uroot_args+=-defaultsh $(CONFIG_LINUXBOOT_UROOT_SHELL)
ifneq (CONFIG_LINUXBOOT_UROOT_FILES,)
uroot_args += $(foreach file,$(CONFIG_LINUXBOOT_UROOT_FILES),-files $(PWD)/$(file))
uroot_args+=$(foreach file,$(CONFIG_LINUXBOOT_UROOT_FILES),-files $(PWD)/$(file))
endif
uroot_cmds = $(CONFIG_LINUXBOOT_UROOT_COMMANDS)
uroot_cmds=$(CONFIG_LINUXBOOT_UROOT_COMMANDS)
all: u-root
version:
ifeq ("$(go_version)","")
@@ -35,16 +38,27 @@ ifeq ($(shell if [ $(go_version_minor) -lt 9 ]; then echo y; fi),y)
endif
endif
$(uroot_build):
git clone https://$(uroot_package) $(uroot_build)
git -C $(uroot_build) checkout --quiet $(CONFIG_LINUXBOOT_UROOT_VERSION)
get: version
if [ -d "$(go_path_dir)/src/$(uroot_package)" ]; then \
git -C $(go_path_dir)/src/$(uroot_package) checkout --quiet main; \
git -C $(go_path_dir)/src/$(uroot_package) pull || \
echo -e "\n<<Pulling u-root package from GitHub failed>>\n"; \
else \
git clone https://${uroot_package} ${go_path_dir}/src/${uroot_package} || \
(echo -e "\n<<Failed to clone u-root package. Please check your internet access>>\n" && \
exit 1); \
fi
$(uroot_build)/u-root: $(uroot_build)
cd $(uroot_build); \
go build -o u-root .
checkout: get
git -C $(go_path_dir)/src/$(uroot_package) checkout --quiet $(CONFIG_LINUXBOOT_UROOT_VERSION)
#$(CONFIG_LINUXBOOT_INITRAMFS_PATH)
build/initramfs_u-root.cpio: $(uroot_build)/u-root
GOARCH=$(UROOT_ARCH-y) $(uroot_build)/u-root \
-uroot-source $(uroot_build) \
$(uroot_args) -o build/initramfs_u-root.cpio $(uroot_cmds)
build: checkout
cd ${go_path_dir}/src/${uroot_package}; \
go build -o ${uroot_bin} .
u-root: build
GOARCH=$(ARCH-y) $(uroot_bin) \
-uroot-source ${go_path_dir}/src/${uroot_package} \
$(uroot_args) -o $(project_dir)/initramfs_u-root.cpio $(uroot_cmds)
.PHONY: all u-root build checkout get version

0
payloads/external/LinuxBoot/i386/defconfig → payloads/external/LinuxBoot/x86/defconfig vendored
View File

67
payloads/external/Makefile.inc vendored
View File

@@ -26,8 +26,8 @@ ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_COMMAND_LINE))),)
endif
ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD))),)
ifneq ($(CONFIG_LINUXBOOT_ARM64),y)
ADDITIONAL_PAYLOAD_CONFIG+=-I $(CONFIG_LINUX_INITRD)$(CONFIG_LINUXBOOT_INITRAMFS)$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX)
prebuilt-files += $(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD)$(CONFIG_LINUXBOOT_INITRAMFS)))
ADDITIONAL_PAYLOAD_CONFIG+=-I $(CONFIG_LINUX_INITRD)$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX)
prebuilt-files += $(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD)))
endif
endif
endif
@@ -161,7 +161,6 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
CONFIG_EDK2_REPOSITORY=$(CONFIG_EDK2_REPOSITORY) \
CONFIG_EDK2_TAG_OR_REV=$(CONFIG_EDK2_TAG_OR_REV) \
CONFIG_EDK2_UEFIPAYLOAD=$(CONFIG_EDK2_UEFIPAYLOAD) \
CONFIG_EDK2_UNIVERSAL_PAYLOAD=$(CONFIG_EDK2_UNIVERSAL_PAYLOAD) \
CONFIG_EDK2_REPO_OFFICIAL=$(CONFIG_EDK2_REPO_OFFICIAL) \
CONFIG_EDK2_REPO_MRCHROMEBOX=$(CONFIG_EDK2_REPO_MRCHROMEBOX) \
CONFIG_EDK2_REPO_CUSTOM=$(CONFIG_EDK2_REPO_CUSTOM) \
@@ -185,14 +184,9 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
CONFIG_EDK2_SD_MMC_TIMEOUT=$(CONFIG_EDK2_SD_MMC_TIMEOUT) \
CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \
CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=$(CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS) \
CONFIG_CPU_XTAL_HZ=$(CONFIG_CPU_XTAL_HZ) \
CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_V2) \
CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_v2) \
CONFIG_EDK2_SECURE_BOOT_SUPPORT=$(CONFIG_EDK2_SECURE_BOOT_SUPPORT) \
CONFIG_EDK2_GOP_DRIVER=$(CONFIG_EDK2_GOP_DRIVER) \
CONFIG_EDK2_GOP_FILE=$(CONFIG_EDK2_GOP_FILE) \
CONFIG_INTEL_GMA_VBT_FILE=$(CONFIG_INTEL_GMA_VBT_FILE) \
CONFIG_TPM_GOOGLE_CR50=$(CONFIG_TPM_GOOGLE_CR50) \
GCC_CC_x86_32=$(GCC_CC_x86_32) \
GCC_CC_x86_64=$(GCC_CC_x86_64) \
GCC_CC_arm=$(GCC_CC_arm) \
@@ -210,7 +204,6 @@ $(obj)/ShimmedUniversalPayload.elf: $(DOTCONFIG)
CONFIG_EDK2_REPOSITORY=$(CONFIG_EDK2_REPOSITORY) \
CONFIG_EDK2_TAG_OR_REV=$(CONFIG_EDK2_TAG_OR_REV) \
CONFIG_EDK2_UEFIPAYLOAD=$(CONFIG_EDK2_UEFIPAYLOAD) \
CONFIG_EDK2_UNIVERSAL_PAYLOAD=$(CONFIG_EDK2_UNIVERSAL_PAYLOAD) \
CONFIG_EDK2_REPO_OFFICIAL=$(CONFIG_EDK2_REPO_OFFICIAL) \
CONFIG_EDK2_REPO_MRCHROMEBOX=$(CONFIG_EDK2_REPO_MRCHROMEBOX) \
CONFIG_EDK2_REPO_CUSTOM=$(CONFIG_EDK2_REPO_CUSTOM) \
@@ -233,7 +226,7 @@ $(obj)/ShimmedUniversalPayload.elf: $(DOTCONFIG)
CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \
CONFIG_CPU_XTAL_HZ=$(CONFIG_CPU_XTAL_HZ) \
CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_V2) \
CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_v2) \
GCC_CC_x86_32=$(GCC_CC_x86_32) \
GCC_CC_x86_64=$(GCC_CC_x86_64) \
GCC_CC_arm=$(GCC_CC_arm) \
@@ -304,14 +297,8 @@ img/tint-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG)
# Memtest86+
ifeq ($(CONFIG_MEMTEST86PLUS_V6),y)
memtest_dir:=memtest86plus_v6
else
memtest_dir:=memtest86plus_v5
endif
cbfs-files-$(CONFIG_MEMTEST_SECONDARY_PAYLOAD) += img/memtest
img/memtest-file := payloads/external/Memtest86Plus/$(memtest_dir)/memtest
img/memtest-file := payloads/external/Memtest86Plus/memtest86plus/memtest
img/memtest-type := payload
img/memtest-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG)
@@ -321,7 +308,7 @@ ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy)
SERIAL_BAUD_RATE=$(CONFIG_TTYS0_BAUD)
endif
payloads/external/Memtest86Plus/$(memtest_dir)/memtest: $(DOTCONFIG)
payloads/external/Memtest86Plus/memtest86plus/memtest: $(DOTCONFIG)
$(MAKE) -C payloads/external/Memtest86Plus all \
CC="$(CC_x86_32)" \
LD="$(LD_x86_32)" \
@@ -329,10 +316,8 @@ payloads/external/Memtest86Plus/$(memtest_dir)/memtest: $(DOTCONFIG)
AS="$(AS_x86_32)" \
CONFIG_MEMTEST_REVISION=$(CONFIG_MEMTEST_REVISION) \
CONFIG_MEMTEST_REVISION_ID=$(CONFIG_MEMTEST_REVISION_ID) \
CONFIG_MEMTEST_MAIN=$(CONFIG_MEMTEST_MAIN) \
CONFIG_MEMTEST_MASTER=$(CONFIG_MEMTEST_MASTER) \
CONFIG_MEMTEST_STABLE=$(CONFIG_MEMTEST_STABLE) \
CONFIG_MEMTEST86PLUS_V5=$(CONFIG_MEMTEST86PLUS_V5) \
CONFIG_MEMTEST86PLUS_V6=$(CONFIG_MEMTEST86PLUS_V6) \
$(MEMTEST_SERIAL_OPTIONS) \
MFLAGS= MAKEFLAGS=
@@ -379,45 +364,41 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(PXE_CONFIG_SCRIPT)
MFLAGS= MAKEFLAGS=
# LinuxBoot
LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_X86) = x86_32
LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_X86_64) = x86_64
LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_ARM) = arm
LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_ARM64) = arm64
LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_RISCV_RV32) = riscv
LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_RISCV_RV64) = riscv
ifeq ($(CONFIG_LINUXBOOT_CROSS_COMPILE),"")
CONFIG_LINUXBOOT_CROSS_COMPILE=$(CROSS_COMPILE_$(LINUXBOOT_CROSS_COMPILE_ARCH-y))
endif
.PHONY: linuxboot
payloads/external/LinuxBoot/build/Image linuxboot:
linuxboot:
$(MAKE) -C payloads/external/LinuxBoot \
CPUS=$(CPUS) \
CONFIG_LINUXBOOT_X86_64=$(CONFIG_LINUXBOOT_X86_64) \
CONFIG_LINUXBOOT_X86=$(CONFIG_LINUXBOOT_X86) \
CONFIG_LINUXBOOT_ARM=$(CONFIG_LINUXBOOT_ARM) \
CONFIG_LINUXBOOT_ARM64=$(CONFIG_LINUXBOOT_ARM64) \
CONFIG_LINUXBOOT_RISCV_RV32=$(CONFIG_LINUXBOOT_RISCV_RV32) \
CONFIG_LINUXBOOT_RISCV_RV64=$(CONFIG_LINUXBOOT_RISCV_RV64) \
CONFIG_LINUXBOOT_CROSS_COMPILE=$(CONFIG_LINUXBOOT_CROSS_COMPILE) \
CONFIG_LINUXBOOT_BUILD_INITRAMFS=$(CONFIG_LINUXBOOT_BUILD_INITRAMFS) \
CONFIG_LINUXBOOT_INITRAMFS_PATH=$(CONFIG_LINUXBOOT_INITRAMFS_PATH) \
CONFIG_LINUXBOOT_KERNEL=$(CONFIG_PAYLOAD_FILE) \
CONFIG_LINUXBOOT_INITRAMFS=$(CONFIG_LINUX_INITRD) \
CONFIG_LINUXBOOT_INITRAMFS_SUFFIX=$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX) \
CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ=$(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ) \
CONFIG_LINUXBOOT_COMPILE_KERNEL=$(CONFIG_LINUXBOOT_COMPILE_KERNEL) \
CONFIG_LINUXBOOT_KERNEL_PATH=$(CONFIG_LINUXBOOT_KERNEL_PATH) \
CONFIG_LINUXBOOT_KERNEL_VERSION=$(CONFIG_LINUXBOOT_KERNEL_VERSION) \
CONFIG_LINUXBOOT_BUILD_INITRAMFS=$(CONFIG_LINUXBOOT_BUILD_INITRAMFS) \
CONFIG_LINUXBOOT_KERNEL_MAINLINE=$(CONFIG_LINUXBOOT_KERNEL_MAINLINE) \
CONFIG_LINUXBOOT_KERNEL_STABLE=$(CONFIG_LINUXBOOT_KERNEL_STABLE) \
CONFIG_LINUXBOOT_KERNEL_LONGTERM=$(CONFIG_LINUXBOOT_KERNEL_LONGTERM) \
CONFIG_LINUXBOOT_KERNEL_CUSTOM=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM) \
CONFIG_LINUXBOOT_KERNEL_CUSTOM_VERSION=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM_VERSION) \
CONFIG_LINUXBOOT_KERNEL_CUSTOM_CONFIG=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM_CONFIG) \
CONFIG_LINUXBOOT_KERNEL_BZIMAGE=$(CONFIG_LINUXBOOT_KERNEL_BZIMAGE) \
CONFIG_LINUXBOOT_KERNEL_UIMAGE=$(CONFIG_LINUXBOOT_KERNEL_UIMAGE) \
CONFIG_LINUXBOOT_KERNEL_CONFIGFILE=$(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) \
CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ=$(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ) \
CONFIG_LINUXBOOT_UROOT=$(CONFIG_LINUXBOOT_UROOT) \
CONFIG_LINUXBOOT_UROOT_VERSION=$(CONFIG_LINUXBOOT_UROOT_VERSION) \
CONFIG_LINUXBOOT_UROOT_FORMAT=$(CONFIG_LINUXBOOT_UROOT_FORMAT) \
CONFIG_LINUXBOOT_UROOT_INITCMD=$(CONFIG_LINUXBOOT_UROOT_INITCMD) \
CONFIG_LINUXBOOT_UROOT_UINITCMD=$(CONFIG_LINUXBOOT_UROOT_UINITCMD) \
CONFIG_LINUXBOOT_UROOT_UINITCMD=$(CONFIG_LINUXBOOT_UROOT_UINITCMD)\
CONFIG_LINUXBOOT_UROOT_SHELL=$(CONFIG_LINUXBOOT_UROOT_SHELL) \
CONFIG_LINUXBOOT_UROOT_COMMANDS=$(CONFIG_LINUXBOOT_UROOT_COMMANDS) \
CONFIG_LINUXBOOT_UROOT_FILES=$(CONFIG_LINUXBOOT_UROOT_FILES) \
CONFIG_LINUXBOOT_DTS_FILE=$(CONFIG_LINUXBOOT_DTS_FILE)
CONFIG_LINUXBOOT_DTB_FILE=$(CONFIG_LINUXBOOT_DTB_FILE)
payloads/external/LinuxBoot/linuxboot/bzImage: linuxboot
payloads/external/LinuxBoot/linuxboot/uImage: linuxboot
payloads/external/LinuxBoot/linuxboot/initramfs_u-root.cpio: linuxboot
# BOOTBOOT

37
payloads/external/Memtest86Plus/Kconfig.secondary vendored
View File

@@ -1,32 +1,8 @@
if MEMTEST_SECONDARY_PAYLOAD
comment "Memtest86+"
choice
prompt "Memtest86+ 5/6"
config MEMTEST86PLUS_V6
bool "Memtest86+ V6"
config MEMTEST86PLUS_V5
bool "Memtest86+ V5"
endchoice
choice
prompt "Target architecture"
depends on MEMTEST86PLUS_V6
config MEMTEST86PLUS_ARCH_64
bool "64 bit"
config MEMTEST86PLUS_ARCH_32
bool "32 bit"
endchoice
choice
prompt "Memtest86+ revision"
prompt "Memtest86+ version"
default MEMTEST_STABLE
depends on MEMTEST_SECONDARY_PAYLOAD
config MEMTEST_STABLE
@@ -35,21 +11,20 @@ config MEMTEST_STABLE
Stable Memtest86+ version.
For reproducible builds, this option must be selected.
config MEMTEST_MAIN
bool "Main"
config MEMTEST_MASTER
bool "Master"
help
Newest Memtest86+ version.
This option will fetch the newest version of the Memtest86+ code,
updating as new changes are committed. This makes the build
non-reproducible, as it can fetch different code each time.
config MEMTEST_REVISION
bool "git revision"
help
Select this option if you have a specific commit or branch
that you want to use as the revision from which to
build Memtest86+. Using a branch version makes the build
build Memtest86+. This makes the build
non-reproducible, as it can fetch different code each time.
You will be able to specify the name of a branch or a commit id
@@ -60,7 +35,7 @@ endchoice
config MEMTEST_REVISION_ID
string "Insert a commit's SHA-1 or a branch name"
depends on MEMTEST_REVISION
default "origin/main"
default "origin/master"
help
The commit's SHA-1 or branch name of the revision to use.

45
payloads/external/Memtest86Plus/Makefile vendored
View File

@@ -1,32 +1,14 @@
## SPDX-License-Identifier: GPL-2.0-only
project_name=Memtest86+
ifeq ($(CONFIG_MEMTEST86PLUS_V6),y)
project_dir=$(CURDIR)/memtest86plus_v6
ifeq ($(MEMTEST86PLUS_ARCH_64),y)
build_dir=$(project_dir)/build64
else
build_dir=$(project_dir)/build32
endif
project_git_repo=https://github.com/memtest86plus/memtest86plus.git
TAG-$(CONFIG_MEMTEST_MAIN)=origin/main
NAME-$(CONFIG_MEMTEST_MAIN)=Main
TAG-$(CONFIG_MEMTEST_STABLE)=v6.20
NAME-$(CONFIG_MEMTEST_STABLE)=Stable
TAG-$(CONFIG_MEMTEST_REVISION)=$(CONFIG_MEMTEST_REVISION_ID)
else
project_dir=$(CURDIR)/memtest86plus_v5
build_dir=$(project_dir)
project_git_repo=https://review.coreboot.org/memtest86plus.git
TAG-$(CONFIG_MEMTEST_MAIN)=origin/main
NAME-$(CONFIG_MEMTEST_MAIN)=Main
TAG-$(CONFIG_MEMTEST_MASTER)=origin/master
NAME-$(CONFIG_MEMTEST_MASTER)=Master
TAG-$(CONFIG_MEMTEST_STABLE)=0bd34c22604660e4283316331f3e7bf8a3863753
NAME-$(CONFIG_MEMTEST_STABLE)=Stable
TAG-$(CONFIG_MEMTEST_REVISION)=$(CONFIG_MEMTEST_REVISION_ID)
endif
project_name=Memtest86+
project_dir=$(CURDIR)/memtest86plus
project_git_repo=https://review.coreboot.org/memtest86plus.git
all: build
@@ -43,27 +25,24 @@ ifeq ($(CONFIG_MEMTEST_REVISION),y)
endif
false
endif
-cd $(project_dir) 2>/dev/null; git show $(TAG-y) >/dev/null 2>&1 ; \
if [ $$? -ne 0 ] || [ "$(TAG-y)" = "origin/main" ]; then \
-cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ; \
if [ $$? -ne 0 ] || [ "$(TAG-y)" = "origin/master" ]; then \
echo " Fetching new commits from the $(project_name) git repo"; \
git fetch; fi
checkout: fetch
echo " Checking out $(project_name) revision $(NAME-y) ($(TAG-y))"
cd $(project_dir); \
git checkout main; \
git checkout master; \
git branch -D coreboot 2>/dev/null; \
git checkout -b coreboot $(TAG-y)
build: checkout
echo " MAKE $(project_name) $(NAME-y)"
$(MAKE) -C $(build_dir) all
ifeq ($(CONFIG_MEMTEST86PLUS_V6),y)
cp $(build_dir)/memtest.bin $(project_dir)/memtest
endif
$(MAKE) -C $(project_dir) all
clean:
test -d $(build_dir) && $(MAKE) -C $(build_dir) clean || exit 0
test -d $(project_dir) && $(MAKE) -C $(project_dir) clean || exit 0
distclean:
rm -rf $(project_dir)
@@ -71,4 +50,4 @@ distclean:
print-repo-info:
echo "$(project_git_repo) $(project_dir)"
.PHONY: all build checkout check_version clean distclean fetch print-repo-info
.PHONY: all build checkout clean distclean fetch print-repo-info

2
payloads/external/SeaBIOS/Kconfig vendored
View File

@@ -15,7 +15,7 @@ choice
default SEABIOS_STABLE
config SEABIOS_STABLE
bool "1.16.2"
bool "1.16.1"
help
Stable SeaBIOS version
config SEABIOS_MASTER

2
payloads/external/SeaBIOS/Makefile vendored
View File

@@ -1,5 +1,5 @@
TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
TAG-$(CONFIG_SEABIOS_STABLE)=ea1b7a0733906b8425d948ae94fba63c32b1d425
TAG-$(CONFIG_SEABIOS_STABLE)=3208b098f51a9ef96d0dfa71d5ec3a3eaec88f0a
TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)
project_git_repo=https://review.coreboot.org/seabios.git

4
payloads/external/U-Boot/Kconfig vendored
View File

@@ -7,14 +7,14 @@ config PAYLOAD_SPECIFIC_OPTIONS
config UBOOT_STABLE_COMMIT_ID
string
default "v2023.07"
default "v2021.07"
choice
prompt "U-Boot version"
default UBOOT_STABLE
config UBOOT_STABLE
bool "v2023.07"
bool "v2021.07"
help
Stable U-Boot version

4
payloads/external/depthcharge/Makefile vendored
View File

@@ -1,5 +1,5 @@
# 2023-05-10
STABLE_COMMIT_ID=c48613a71c1ee29295b184c51fe5dadf71b543c4
# Wed Apr 25, 2018
STABLE_COMMIT_ID=902681db13c170fc2d028f7391a9e9a5f69082a3
project_name=depthcharge
project_dir=$(CURDIR)/depthcharge

47
payloads/external/edk2/Kconfig vendored
View File

@@ -3,42 +3,15 @@ if PAYLOAD_EDK2
config PAYLOAD_FILE
string "edk2 binary"
default "$(obj)/UEFIPAYLOAD.fd" if EDK2_UEFIPAYLOAD
default "$(obj)/ShimmedUniversalPayload.elf" if EDK2_UNIVERSAL_PAYLOAD
help
The result of a UefiPayloadPkg build
choice
prompt "EDK II build type"
default EDK2_UEFIPAYLOAD
help
Select the build type for edk2. UniversalPayload is recommended, as it is
replacing UefiPayloadPkg. Whilst in the transition phase between the two,
both options exist.
config EDK2_UEFIPAYLOAD
bool "Build UefiPayloadPkg"
default y
help
Build the standard UefiPayloadPkg
config EDK2_UNIVERSAL_PAYLOAD
bool "Build Universal Payload"
help
Select this option if you want to build a coreboot image
with EDK2s Universal Payload. If you don't know what this is
about, just leave it enabled.
Universal Payload should ideally only be built from upstream EDK2,
https://github.com/tianocore/edk2, as this is regularly build tested
and it encourages patches to be merged upstream.
Whilst the required patches are being merged, this is pointed to
Star Labs GitHub repository which contains these patches and is based
on a known working commit.
See https://universalscalablefirmware.github.io/documentation/ for more information.
endchoice
choice
prompt "Tianocore's EDK II payload"
default EDK2_REPO_MRCHROMEBOX
@@ -71,7 +44,6 @@ endchoice
config EDK2_REPOSITORY
string "URL to git repository for edk2"
default "https://github.com/starlabsltd/edk2" if EDK2_UNIVERSAL_PAYLOAD
default "https://github.com/mrchromebox/edk2" if EDK2_REPO_MRCHROMEBOX
default "https://github.com/tianocore/edk2" if EDK2_REPO_OFFICIAL
default "" if EDK2_REPO_CUSTOM
@@ -81,8 +53,7 @@ config EDK2_REPOSITORY
config EDK2_TAG_OR_REV
string "Insert a commit's SHA-1 or a branch name"
default "origin/uefipayload_202306" if EDK2_REPO_MRCHROMEBOX
default "origin/universalpayload" if EDK2_UNIVERSAL_PAYLOAD
default "origin/uefipayload_202304" if EDK2_REPO_MRCHROMEBOX
default "origin/master" if EDK2_REPO_OFFICIAL
default "" if EDK2_REPO_CUSTOM
help
@@ -262,20 +233,6 @@ config EDK2_SECURE_BOOT_SUPPORT
Select this option to enable UEFI SecureBoot support in edk2.
UEFI SecureBoot will be disabled by default and can be enabled from the menu option.
config EDK2_GOP_DRIVER
bool "Add a GOP driver to the Tianocore build"
depends on INTEL_GMA_ADD_VBT && NO_GFX_INIT && (EDK2_REPO_MRCHROMEBOX || EDK2_REPO_CUSTOM)
default y if INTEL_GMA_ADD_VBT && NO_GFX_INIT && EDK2_REPO_MRCHROMEBOX
help
Select this option to have edk2 use an external GOP driver for display init.
config EDK2_GOP_FILE
string "GOP driver file"
depends on EDK2_GOP_DRIVER
default "IntelGopDriver.efi"
help
The name of the GOP driver file passed to edk2.
config EDK2_CUSTOM_BUILD_PARAMS
string "edk2 additional custom build parameters"
default "-D VARIABLE_SUPPORT=SMMSTORE" if EDK2_REPO_MRCHROMEBOX && SMMSTORE_V2

27
payloads/external/edk2/Makefile vendored
View File

@@ -71,10 +71,6 @@ endif
ifeq ($(CONFIG_EDK2_FOLLOW_BGRT_SPEC),y)
BUILD_STR += -D FOLLOW_BGRT_SPEC=TRUE
endif
# MAX_VARIABLE_SIZE = 0x10000
ifeq ($(CONFIG_SMMSTORE_V2),y)
BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize=0x8000
endif
# PCIE_BASE_ADDRESS = 0
ifneq ($(CONFIG_ECAM_MMCONF_LENGTH),)
BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS)
@@ -115,14 +111,6 @@ endif
ifeq ($(CONFIG_EDK2_SECURE_BOOT_SUPPORT), y)
BUILD_STR += -D SECURE_BOOT_ENABLE=TRUE
endif
# PCIEXP_SUPPORT_RESIZABLE_BARS = FALSE
ifeq ($(CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS), y)
BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport=TRUE
endif
# GOP_DRIVER = FALSE
ifeq ($(CONFIG_EDK2_GOP_DRIVER), y)
BUILD_STR += -D USE_PLATFORM_GOP=TRUE
endif
#
# EDKII has the below PCDs that are relevant to coreboot:
@@ -135,10 +123,6 @@ BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow=0
BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn=0
endif
ifeq ($(CONFIG_TPM_GOOGLE_CR50)$(CONFIG_EDK2_REPO_MRCHROMEBOX),yy)
BUILD_STR += -D TPM_ENABLE=FALSE
endif
bootloader = $(word 8,$(subst /, ,$(BUILD_STR)))
ifneq ($(CONFIG_EDK2_CUSTOM_BUILD_PARAMS),)
@@ -199,13 +183,6 @@ logo: $(EDK2_PATH)
BMP3:$(EDK2_PATH)/MdeModulePkg/Logo/Logo.bmp;; \
esac \
gop_driver:
if [ -n "$(CONFIG_EDK2_GOP_DRIVER)" ]; then \
echo "Using GOP driver $(CONFIG_EDK2_GOP_FILE)"; \
cp $(top)/$(CONFIG_EDK2_GOP_FILE) $(EDK2_PATH)/UefiPayloadPkg/IntelGopDriver.efi; \
cp $(top)/$(CONFIG_INTEL_GMA_VBT_FILE) $(EDK2_PATH)/UefiPayloadPkg/vbt.bin; \
fi; \
checktools:
echo -n "EDK2: Checking uuid-dev:"
echo "#include <uuid/uuid.h>" > libtest.c
@@ -243,7 +220,7 @@ print:
-e 's/s /Build: Silent/' \
-e 's/t /Toolchain: /'
prep: $(EDK2_PATH) $(EDK2_PLATFORMS_PATH) clean checktools logo gop_driver
prep: $(EDK2_PATH) $(EDK2_PLATFORMS_PATH) clean checktools logo
cd $(WORKSPACE); \
source $(EDK2_PATH)/edksetup.sh; \
unset CC; $(MAKE) -C $(EDK2_PATH)/BaseTools 2>&1; \
@@ -270,7 +247,7 @@ $(WORKSPACE)/Build/UefiPayloadPkgX64/UniversalPayload.elf: \
cd $(WORKSPACE); \
source $(EDK2_PATH)/edksetup.sh; \
echo -n "EDK2: Building... "; \
$(EDK2_PATH)/UefiPayloadPkg/UniversalPayloadBuild.sh -a IA32 -b $(RELEASE_STR) $(BUILD_STR)
$(EDK2_PATH)/UefiPayloadPkg/UniversalPayloadBuild.sh -a IA32 -a X64 -b $(RELEASE_STR) $(BUILD_STR)
if [ ! -f $@ ]; then \
echo "Failed!"; \
exit 1; \

9
payloads/external/tint/Makefile vendored
View File

@@ -6,11 +6,12 @@
# Properties of the current TINT version
#
TINT_VERSION=0.07
TINT_BASE_URL="https://mirror.fsf.org/trisquel/pool/main/t/tint"
TINT_VERSION=0.05
TINT_EXT_VERSION=0.05
TINT_ARCHIVE_LINK="https://mirror.fsf.org/trisquel/pool/main/t/tint/tint_${TINT_EXT_VERSION}.tar.xz"
TINT_ARCHIVE="tint_${TINT_VERSION}.tar.xz"
TINT_DIR="tint-${TINT_VERSION}"
TINT_SHA1SUM="a7ec9355b9ea9d47576757219e9b1f4e51ac93a7"
TINT_SHA1SUM="859008216930a4584e622d0df41fd75c44d2b47f"
#
# Locations of the input/output scripts
@@ -49,7 +50,7 @@ tint:
"./generate_core.sh" ${buildgcc} ${corescript} "prepare_before_patch" ; \
chmod +x "./tintify_core.sh" ; \
"./tintify_core.sh" ${corescript} ${tintified} \
${TINT_BASE_URL} ${TINT_ARCHIVE} ${TINT_DIR} ${TINT_SHA1SUM} ; \
${TINT_ARCHIVE_LINK} ${TINT_ARCHIVE} ${TINT_DIR} ${TINT_SHA1SUM} ; \
fi ; \
chmod +x ${tintified}
${tintified}

1
payloads/external/tint/generate_core.sh vendored
View File

@@ -97,7 +97,6 @@ sed -i -e "s/util\/crossgcc\///g" "$corescript"
if [ ! -z "${prepare_before_patch}" ] ; then
sed -i -e "/\$TAR \$FLAGS \"\$(basename \"\$archive\")\"/a prepare_\${package} || exit \"\$?\"" "$corescript"
sed -i -e "/\$TAR \$FLAGS \"\$archive\"/a prepare_\${package} || exit \"\$?\"" "$corescript"
fi
#

0
payloads/external/tint/tint-0.07_libpayload.patch → payloads/external/tint/tint-0.05_libpayload.patch vendored
View File

6
payloads/external/tint/tintify_core.sh vendored
View File

@@ -9,7 +9,7 @@
#
# USAGE:
# ./tintify_core.sh <corescript> <tintified> \
# <TINT_BASE_URL> <TINT_ARCHIVE> <TINT_DIR> <TINT_SHA1SUM>
# <TINT_ARCHIVE_LINK> <TINT_ARCHIVE> <TINT_DIR> <TINT_SHA1SUM>
# where
# corescript - path to input core script
# tintified - path to output tint script
@@ -28,12 +28,10 @@ tintified="$2"
#
echo "#!/bin/sh" > "$tintified"
echo "TINT_BASE_URL=${3}" >> "$tintified"
echo "TINT_ARCHIVE_LINK=${3}" >> "$tintified"
echo "TINT_ARCHIVE=${4}" >> "$tintified"
echo "TINT_ARCHIVE_LINK=${3}/${4}" >> "$tintified"
echo "TINT_DIR=${5}" >> "$tintified"
echo "TINT_SHA1SUM=${6}" >> "$tintified"
echo "USE_COREBOOT_MIRROR=0" >> "$tintified"
#
# Add the replace_plus_with_minus() function - needed to fix the version number

8
payloads/libpayload/Kconfig
View File

@@ -167,6 +167,14 @@ config BASE_ADDRESS
endmenu
config USE_MARCH_586
bool "Use march=586 qualifier to build"
default n
depends on ARCH_X86
help
Allow a platform or processor to select to be compiled using
the '-march=i586' option instead of the typical '-march=i686'
menu "Standard Libraries"
config LIBC

7
payloads/libpayload/arch/arm/Kconfig
View File

@@ -26,5 +26,10 @@
## SUCH DAMAGE.
##
config ARCH_ARM
if ARCH_ARM
config ARCH_SPECIFIC_OPTIONS
def_bool y
select LITTLE_ENDIAN
endif

7
payloads/libpayload/arch/arm/main.c
View File

@@ -29,6 +29,11 @@
#include <exception.h>
#include <libpayload.h>
int main_argc; /**< The argc value to pass to main() */
/** The argv value to pass to main() */
char *main_argv[MAX_ARGC_COUNT];
/**
* This is our C entry function - set up the system
* and jump into the payload entry point.
@@ -58,7 +63,7 @@ void start_main(void)
* In the future we may care about the return value.
*/
(void) main(0, NULL);
(void) main(main_argc, (main_argc != 0) ? main_argv : NULL);
/*
* Returning here will go to the _leave function to return

7
payloads/libpayload/arch/arm64/Kconfig
View File

@@ -26,11 +26,12 @@
## SUCH DAMAGE.
##
config ARCH_ARM64
select LITTLE_ENDIAN
if ARCH_ARM64
config ARCH_SPECIFIC_OPTIONS
def_bool y
select LITTLE_ENDIAN
config ARM64_A53_ERRATUM_843419
bool "Enable Cortex-A53 erratum 843419 linker workaround"
default n

7
payloads/libpayload/arch/arm64/main.c
View File

@@ -30,6 +30,11 @@
#include <libpayload.h>
#include <arch/mmu.h>
int main_argc; /**< The argc value to pass to main() */
/** The argv value to pass to main() */
char *main_argv[MAX_ARGC_COUNT];
/*
* Func: pre_sysinfo_scan_mmu_setup
* Desc: We need to setup and enable MMU before we can go to scan coreboot
@@ -120,7 +125,7 @@ void start_main(void)
* In the future we may care about the return value.
*/
(void) main(0, NULL);
(void) main(main_argc, (main_argc != 0) ? main_argv : NULL);
/*
* Returning here will go to the _leave function to return

9
payloads/libpayload/arch/mock/Kconfig
View File

@@ -1,9 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
config ARCH_MOCK
select LITTLE_ENDIAN if !ARCH_MOCK_BIG_ENDIAN
select BIG_ENDIAN if ARCH_MOCK_BIG_ENDIAN
if ARCH_MOCK
config ARCH_MOCK_BIG_ENDIAN
@@ -12,4 +8,9 @@ config ARCH_MOCK_BIG_ENDIAN
help
This option enables big-endinan support in the code.
config ARCH_SPECIFIC_OPTIONS
def_bool y
select LITTLE_ENDIAN if !ARCH_MOCK_BIG_ENDIAN
select BIG_ENDIAN if ARCH_MOCK_BIG_ENDIAN
endif

7
payloads/libpayload/arch/x86/Kconfig
View File

@@ -26,12 +26,13 @@
## SUCH DAMAGE.
##
config ARCH_X86
if ARCH_X86
config ARCH_SPECIFIC_OPTIONS
def_bool y
select LITTLE_ENDIAN
select IO_ADDRESS_SPACE
if ARCH_X86
config ENABLE_APIC
bool "Enables the Local APIC"

8
payloads/libpayload/arch/x86/coreboot.c
View File

@@ -59,9 +59,6 @@ int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info)
return 1;
}
/* This pointer gets set in head.S and is passed in from coreboot. */
void *cb_header_ptr;
int get_coreboot_info(struct sysinfo_t *info)
{
int ret;
@@ -70,10 +67,7 @@ int get_coreboot_info(struct sysinfo_t *info)
* an invalid value. */
info->x86_rom_var_mtrr_index = -1;
ret = cb_parse_header(cb_header_ptr, 1, info);
if (ret)
ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info);
ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info);
if (ret)
ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info);

19
payloads/libpayload/arch/x86/head.S
View File

@@ -55,6 +55,11 @@ mb_header:
.long _end
.long _init
#define CB_MAGIC_VALUE 0x12345678
#define CB_MAGIC 0x04
#define CB_ARGV 0x08
#define CB_ARGC 0x10
/*
* This function saves off the previous stack and switches us to our
* own execution environment.
@@ -67,10 +72,18 @@ _init:
movl %eax, loader_eax
movl %ebx, loader_ebx
/* save pointer to coreboot tables */
movl 4(%esp), %eax
movl %eax, cb_header_ptr
/* Copy argv[] and argc as demanded by the Payload API,
* see https://www.coreboot.org/Payload_API and exec.S.
*/
cmpl $CB_MAGIC_VALUE, CB_MAGIC(%esp)
jne 1f
movl CB_ARGV(%esp), %eax
movl %eax, main_argv
movl CB_ARGC(%esp), %eax
movl %eax, main_argc
1:
/* Store current stack pointer and set up new stack. */
movl %esp, %eax
movl $_stack, %esp

6
payloads/libpayload/configs/config.galileo Normal file
View File

@@ -0,0 +1,6 @@
CONFIG_LP_CHROMEOS=y
CONFIG_LP_ARCH_X86=y
CONFIG_LP_USE_MARCH_586=y
CONFIG_LP_8250_SERIAL_CONSOLE=y
CONFIG_LP_USB_OHCI=y
CONFIG_LP_USB_EHCI=y

2
payloads/libpayload/drivers/cbmem_console.c
View File

@@ -32,7 +32,7 @@
struct cbmem_console {
uint32_t size;
uint32_t cursor;
uint8_t body[];
uint8_t body[0];
} __packed;
#define CURSOR_MASK ((1 << 28) - 1)

24
payloads/libpayload/drivers/usb/uhci.c
View File

@@ -310,7 +310,7 @@ min(int a, int b)
}
static int
uhci_control(usbdev_t *dev, direction_t dir, int drlen, void *devreq, const int dalen,
uhci_control(usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen,
unsigned char *data)
{
int endp = 0; /* this is control: always 0 */
@@ -339,7 +339,6 @@ uhci_control(usbdev_t *dev, direction_t dir, int drlen, void *devreq, const int
TD_STATUS_ACTIVE;
int toggle = 1;
int len_left = dalen;
for (i = 1; i < count; i++) {
switch (dir) {
case SETUP: tds[i].token = UHCI_SETUP; break;
@@ -348,14 +347,14 @@ uhci_control(usbdev_t *dev, direction_t dir, int drlen, void *devreq, const int
}
tds[i].token |= dev->address << TD_DEVADDR_SHIFT |
endp << TD_EP_SHIFT |
maxlen(min(mlen, len_left)) << TD_MAXLEN_SHIFT |
maxlen(min(mlen, dalen)) << TD_MAXLEN_SHIFT |
toggle << TD_TOGGLE_SHIFT;
tds[i].bufptr = virt_to_phys(data);
tds[i].ctrlsts = (3 << TD_COUNTER_SHIFT) |
(dev->speed?TD_LOWSPEED:0) |
TD_STATUS_ACTIVE;
toggle ^= 1;
len_left -= mlen;
dalen -= mlen;
data += mlen;
}
@@ -375,7 +374,7 @@ uhci_control(usbdev_t *dev, direction_t dir, int drlen, void *devreq, const int
qh_data);
int result;
if (td == 0) {
result = dalen; /* TODO: We should return the actually transferred length. */
result = 0;
} else {
usb_debug("control packet, req %x\n", req);
td_dump(td);
@@ -439,26 +438,25 @@ run_schedule(usbdev_t *dev, td_t *td)
/* finalize == 1: if data is of packet aligned size, add a zero length packet */
static int
uhci_bulk(endpoint_t *ep, const int dalen, u8 *data, int finalize)
uhci_bulk(endpoint_t *ep, int size, u8 *data, int finalize)
{
int maxpsize = ep->maxpacketsize;
if (maxpsize == 0)
fatal("MaxPacketSize == 0!!!");
int numpackets = (dalen + maxpsize - 1) / maxpsize;
if (finalize && ((dalen % maxpsize) == 0)) {
int numpackets = (size + maxpsize - 1) / maxpsize;
if (finalize && ((size % maxpsize) == 0)) {
numpackets++;
}
if (numpackets == 0)
return 0;
td_t *tds = create_schedule(numpackets);
int i = 0, toggle = ep->toggle;
int len_left = dalen;
while ((len_left > 0) || ((len_left == 0) && (finalize != 0))) {
fill_schedule(&tds[i], ep, min(len_left, maxpsize), data,
while ((size > 0) || ((size == 0) && (finalize != 0))) {
fill_schedule(&tds[i], ep, min(size, maxpsize), data,
&toggle);
i++;
data += maxpsize;
len_left -= maxpsize;
size -= maxpsize;
}
if (run_schedule(ep->dev, tds) == 1) {
free(tds);
@@ -466,7 +464,7 @@ uhci_bulk(endpoint_t *ep, const int dalen, u8 *data, int finalize)
}
ep->toggle = toggle;
free(tds);
return dalen; /* TODO: We should return the actually transferred length. */
return 0;
}
typedef struct {

253
payloads/libpayload/drivers/usb/uhci_rh.c
View File

@@ -1,6 +1,6 @@
/*
*
* Copyright (C) 2013 secunet Security Networks AG
* Copyright (C) 2008-2010 coresystems GmbH
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -28,123 +28,184 @@
//#define USB_DEBUG
#include <stdint.h>
#include <stdbool.h>
#include <usb/usb.h>
#include "generic_hub.h"
#include "uhci_private.h"
#include <libpayload.h>
#include "uhci.h"
#include "uhci_private.h"
#define PORTSC(p) (PORTSC1 + ((p) - 1) * sizeof(uint16_t))
#define PORTSC_CCS (1 << 0)
#define PORTSC_CSC (1 << 1)
#define PORTSC_PED (1 << 2)
#define PORTSC_PEDC (1 << 3)
#define PORTSC_LSDA (1 << 8)
#define PORTSC_PR (1 << 9)
#define PORTSC_SUSP (1 << 12)
#define PORTSC_SC_BITS (PORTSC_CSC | PORTSC_PEDC)
typedef struct {
int port[2];
} rh_inst_t;
static int
uhci_rh_port_status_changed(usbdev_t *const dev, const int port)
#define RH_INST(dev) ((rh_inst_t*)(dev)->data)
static void
uhci_rh_enable_port(usbdev_t *dev, int port)
{
const u16 portsc = uhci_reg_read16(dev->controller, PORTSC(port));
const bool changed = portsc & (PORTSC_CSC | PORTSC_PEDC);
u16 value;
hci_t *controller = dev->controller;
if (port == 1)
port = PORTSC1;
else if (port == 2)
port = PORTSC2;
else {
usb_debug("Invalid port %d\n", port);
return;
}
/* always clear all the status change bits */
uhci_reg_write16(dev->controller, PORTSC(port), portsc);
uhci_reg_write16(controller, port,
uhci_reg_read16(controller, port) & ~(1 << 12)); /* wakeup */
return changed;
uhci_reg_write16(controller, port,
uhci_reg_read16(controller, port) | 1 << 9); /* reset */
mdelay(30); // >10ms
uhci_reg_write16(controller, port,
uhci_reg_read16(controller, port) & ~(1 << 9));
mdelay(1); // >5.3us per spec, <3ms because some devices make trouble
uhci_reg_write16(controller, port,
uhci_reg_read16(controller, port) | 1 << 2); /* enable */
/* wait for controller to enable port */
/* TOTEST: how long to wait? 100ms for now */
int timeout = 200; /* time out after 200 * 500us == 100ms */
do {
value = uhci_reg_read16(controller, port);
udelay(500); timeout--;
} while (((value & (1 << 2)) == 0) && (value & 0x01) && timeout);
if (!timeout)
usb_debug("Warning: uhci_rh: port enabling timed out.\n");
}
/* disable root hub */
static void
uhci_rh_disable_port(usbdev_t *dev, int port)
{
hci_t *controller = dev->controller;
if (port == 1)
port = PORTSC1;
else if (port == 2)
port = PORTSC2;
else {
usb_debug("Invalid port %d\n", port);
return;
}
uhci_reg_write16(controller, port,
uhci_reg_read16(controller, port) & ~4);
u16 value;
/* wait for controller to disable port */
/* TOTEST: how long to wait? 100ms for now */
int timeout = 200; /* time out after 200 * 500us == 100ms */
do {
value = uhci_reg_read16(controller, port);
udelay(500); timeout--;
} while (((value & (1 << 2)) != 0) && timeout);
if (!timeout)
usb_debug("Warning: uhci_rh: port disabling timed out.\n");
}
static void
uhci_rh_scanport(usbdev_t *dev, int port)
{
int portsc, offset;
if (port == 1) {
portsc = PORTSC1;
offset = 0;
} else if (port == 2) {
portsc = PORTSC2;
offset = 1;
} else {
usb_debug("Invalid port %d\n", port);
return;
}
int devno = RH_INST(dev)->port[offset];
if ((devno != -1) && (dev->controller->devices[devno] != 0)) {
usb_detach_device(dev->controller, devno);
RH_INST(dev)->port[offset] = -1;
}
uhci_reg_write16(dev->controller, portsc,
uhci_reg_read16(dev->controller, portsc) | (1 << 3) | (1 << 2)); // clear port state change, enable port
mdelay(100); // wait for signal to stabilize
if ((uhci_reg_read16(dev->controller, portsc) & 1) != 0) {
// device attached
uhci_rh_disable_port(dev, port);
uhci_rh_enable_port(dev, port);
usb_speed speed = ((uhci_reg_read16(dev->controller, portsc) >> 8) & 1);
RH_INST(dev)->port[offset] = usb_attach_device(dev->controller, dev->address, portsc, speed);
}
}
static int
uhci_rh_port_connected(usbdev_t *const dev, const int port)
uhci_rh_report_port_changes(usbdev_t *dev)
{
const u16 portsc = uhci_reg_read16(dev->controller, PORTSC(port));
return !!(portsc & PORTSC_CCS);
u16 stored, real;
stored = (RH_INST(dev)->port[0] == -1);
real = ((uhci_reg_read16(dev->controller, PORTSC1) & 1) == 0);
if (stored != real) {
usb_debug("change on port 1\n");
return 1;
}
stored = (RH_INST(dev)->port[1] == -1);
real = ((uhci_reg_read16(dev->controller, PORTSC2) & 1) == 0);
if (stored != real) {
usb_debug("change on port 2\n");
return 2;
}
// maybe detach+attach happened between two scans?
if ((uhci_reg_read16(dev->controller, PORTSC1) & 2) > 0) {
usb_debug("possibly re-attached on port 1\n");
return 1;
}
if ((uhci_reg_read16(dev->controller, PORTSC2) & 2) > 0) {
usb_debug("possibly re-attached on port 2\n");
return 2;
}
// no change
return -1;
}
static int
uhci_rh_port_enabled(usbdev_t *const dev, const int port)
static void
uhci_rh_destroy(usbdev_t *dev)
{
const u16 portsc = uhci_reg_read16(dev->controller, PORTSC(port));
return !(portsc & PORTSC_SUSP) && (portsc & PORTSC_PED);
usb_detach_device(dev->controller, 1);
usb_detach_device(dev->controller, 2);
uhci_rh_disable_port(dev, 1);
uhci_rh_disable_port(dev, 2);
free(RH_INST(dev));
}
static usb_speed
uhci_rh_port_speed(usbdev_t *const dev, const int port)
static void
uhci_rh_poll(usbdev_t *dev)
{
const u16 portsc = uhci_reg_read16(dev->controller, PORTSC(port));
const bool low_speed = portsc & PORTSC_LSDA;
return low_speed ? LOW_SPEED : FULL_SPEED;
int port;
while ((port = uhci_rh_report_port_changes(dev)) != -1)
uhci_rh_scanport(dev, port);
}
static int
uhci_rh_enable_port(usbdev_t *const dev, const int port)
{
const u16 portsc = uhci_reg_read16(dev->controller, PORTSC(port)) & ~PORTSC_SUSP;
uhci_reg_write16(dev->controller, PORTSC(port), portsc & ~(PORTSC_SC_BITS | PORTSC_SUSP));
uhci_reg_write16(dev->controller, PORTSC(port), (portsc & ~PORTSC_SC_BITS) | PORTSC_PED);
return 0;
}
static int
uhci_rh_disable_port(usbdev_t *const dev, const int port)
{
const u16 portsc = uhci_reg_read16(dev->controller, PORTSC(port));
uhci_reg_write16(dev->controller, PORTSC(port), portsc & ~(PORTSC_SC_BITS | PORTSC_PED));
return 0;
}
static int
uhci_rh_reset_port(usbdev_t *const dev, const int port)
{
const u16 portsc = uhci_reg_read16(dev->controller, PORTSC(port)) & ~PORTSC_PR;
/* Trigger port reset. */
uhci_reg_write16(dev->controller, PORTSC(port), portsc | PORTSC_PR);
/* Wait for 15ms (usb20 spec 11.5.1.5: reset should take 10 to 20ms). */
mdelay(15);
/* Clear port reset. */
uhci_reg_write16(dev->controller, PORTSC(port), portsc & ~PORTSC_PR);
udelay(10); /* Linux waits this long. */
/* Enable port. */
uhci_reg_write16(dev->controller, PORTSC(port), portsc | PORTSC_PED);
/* Clear status-change bits one last time. */
uhci_reg_write16(dev->controller, PORTSC(port), portsc | PORTSC_PED | PORTSC_SC_BITS);
return 0;
}
static const generic_hub_ops_t uhci_rh_ops = {
.hub_status_changed = NULL,
.port_status_changed = uhci_rh_port_status_changed,
.port_connected = uhci_rh_port_connected,
.port_in_reset = NULL,
.port_enabled = uhci_rh_port_enabled,
.port_speed = uhci_rh_port_speed,
.enable_port = uhci_rh_enable_port,
.disable_port = uhci_rh_disable_port,
.start_port_reset = NULL,
.reset_port = uhci_rh_reset_port,
};
void
uhci_rh_init(usbdev_t *dev)
{
/* we can set them here because a root hub _really_ shouldn't appear elsewhere */
dev->destroy = uhci_rh_destroy;
dev->poll = uhci_rh_poll;
uhci_rh_enable_port(dev, 1);
uhci_rh_enable_port(dev, 2);
dev->data = xmalloc(sizeof(rh_inst_t));
RH_INST(dev)->port[0] = -1;
RH_INST(dev)->port[1] = -1;
/* we can set them here because a root hub _really_ shouldn't
appear elsewhere */
dev->address = 0;
dev->hub = -1;
dev->port = -1;
generic_hub_init(dev, 2, &uhci_rh_ops);
usb_debug("UHCI: root hub init done\n");
}

4
payloads/libpayload/drivers/usb/xhci.c
View File

@@ -155,9 +155,6 @@ xhci_init(unsigned long physical_bar)
{
int i;
if (!physical_bar)
goto _exit_xhci;
/* First, allocate and initialize static controller structures */
hci_t *const controller = new_controller();
@@ -304,7 +301,6 @@ _free_xhci:
/* _free_controller: */
detach_controller(controller);
free(controller);
_exit_xhci:
return NULL;
}

14
payloads/libpayload/include/coreboot_tables.h
View File

@@ -125,7 +125,7 @@ struct cb_memory_range {
struct cb_memory {
u32 tag;
u32 size;
struct cb_memory_range map[];
struct cb_memory_range map[0];
};
struct cb_hwrpb {
@@ -139,7 +139,7 @@ struct cb_mainboard {
u32 size;
u8 vendor_idx;
u8 part_number_idx;
u8 strings[];
u8 strings[0];
};
enum type_c_orientation {
@@ -166,13 +166,13 @@ struct type_c_port_info {
struct type_c_info {
u32 port_count;
struct type_c_port_info port_info[];
struct type_c_port_info port_info[0];
};
struct cb_string {
u32 tag;
u32 size;
u8 string[];
u8 string[0];
};
struct cb_serial {
@@ -255,7 +255,7 @@ struct cb_gpios {
u32 size;
u32 count;
struct cb_gpio gpios[];
struct cb_gpio gpios[0];
};
struct cb_pcie {
@@ -305,7 +305,7 @@ struct cb_spi_flash {
* space and host address space. This determines the number of entries in mmap_table.
*/
uint32_t mmap_count;
struct flash_mmap_window mmap_table[];
struct flash_mmap_window mmap_table[0];
};
struct cb_boot_media_params {
@@ -344,7 +344,7 @@ struct cb_macs {
uint32_t tag;
uint32_t size;
uint32_t count;
struct mac_address mac_addrs[];
struct mac_address mac_addrs[0];
};
struct cb_mmc_info {

1
payloads/libpayload/include/stdarg.h
View File

@@ -40,7 +40,6 @@
#define va_start(v,l) __builtin_va_start(v,l)
#define va_end(v) __builtin_va_end(v)
#define va_arg(v,l) __builtin_va_arg(v,l)
#define va_copy(d,s) __builtin_va_copy(d,s)
typedef __builtin_va_list va_list;
#else
#include_next <stdarg.h>

1
payloads/libpayload/include/sysinfo.h
View File

@@ -113,7 +113,6 @@ struct sysinfo_t {
uintptr_t acpi_gnvs;
uintptr_t acpi_cnvs;
uintptr_t acpi_rsdp;
uintptr_t smbios;
#define UNDEFINED_STRAPPING_ID (~0)
#define UNDEFINED_FW_CONFIG ~((uint64_t)0)

3
payloads/libpayload/libc/coreboot.c
View File

@@ -224,9 +224,6 @@ static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info)
case CBMEM_ID_ACPI_GNVS:
info->acpi_gnvs = cbmem_entry->address;
break;
case CBMEM_ID_SMBIOS:
info->smbios = cbmem_entry->address;
break;
case CBMEM_ID_CBFS_RO_MCACHE:
info->cbfs_ro_mcache_offset = cbmem_entry->address;
info->cbfs_ro_mcache_size = cbmem_entry->entry_size;

10
payloads/libpayload/libcbfs/cbfs.c
View File

@@ -151,7 +151,6 @@ static void *do_load(union cbfs_mdata *mdata, ssize_t offset, void *buf, size_t
bool skip_verification)
{
bool malloced = false;
size_t buf_size = 0;
size_t out_size;
uint32_t compression = CBFS_COMPRESS_NONE;
const struct cbfs_file_attr_compression *cattr =
@@ -163,13 +162,8 @@ static void *do_load(union cbfs_mdata *mdata, ssize_t offset, void *buf, size_t
out_size = be32toh(mdata->h.len);
}
if (size_inout) {
buf_size = *size_inout;
*size_inout = out_size;
}
if (buf) {
if (!size_inout || buf_size < out_size) {
if (!size_inout || *size_inout < out_size) {
ERROR("'%s' buffer too small\n", mdata->h.filename);
return NULL;
}
@@ -189,6 +183,8 @@ static void *do_load(union cbfs_mdata *mdata, ssize_t offset, void *buf, size_t
free(buf);
return NULL;
}
if (size_inout)
*size_inout = out_size;
return buf;
}

26
spd/lp4x/memory_parts.json
View File

@@ -363,30 +363,6 @@
"ranksPerChannel": 2,
"speedMbps": 4267
}
},
{
"name": "K4UCE3Q4AB-MGCL",
"attribs": {
"densityPerChannelGb": 8,
"banks": 8,
"channelsPerDie": 4,
"diesPerPackage": 2,
"bitWidthPerChannel": 8,
"ranksPerChannel": 2,
"speedMbps": 4267
}
},
{
"name": "CXDB4ABAM-ML",
"attribs": {
"densityPerChannelGb": 8,
"banks": 8,
"channelsPerDie": 1,
"diesPerPackage": 2,
"bitWidthPerChannel": 16,
"ranksPerChannel": 1,
"speedMbps": 4267
}
}
}
]
}

2
spd/lp4x/set-0/parts_spd_manifest.generated.txt
View File

@@ -31,5 +31,3 @@ K4U6E3S4AB-MGCL,spd-1.hex
K4UBE3D4AB-MGCL,spd-3.hex
MT53E2G32D4NQ-046 WT:C,spd-7.hex
H54G68CYRBX248,spd-2.hex
K4UCE3Q4AB-MGCL,spd-2.hex
CXDB4ABAM-ML,spd-8.hex

32
spd/lp4x/set-0/spd-8.hex
View File

@@ -1,32 +0,0 @@
23 11 11 0E 15 21 00 08 00 00 00 00 02 01 00 00
00 00 04 FF 92 54 05 00 87 00 90 A8 90 C0 08 60
04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

2
spd/lp4x/set-1/parts_spd_manifest.generated.txt
View File

@@ -31,5 +31,3 @@ K4U6E3S4AB-MGCL,spd-1.hex
K4UBE3D4AB-MGCL,spd-3.hex
MT53E2G32D4NQ-046 WT:C,spd-10.hex
H54G68CYRBX248,spd-2.hex
K4UCE3Q4AB-MGCL,spd-2.hex
CXDB4ABAM-ML,spd-11.hex

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