Add support for meer9

Change-Id: I37a0b808cf383379b8e284831644c824c0d4817e
Signed-off-by: Jeremy Soller <jackpot51@gmail.com>

src/mainboard/system76/meer9/Kconfig

@@ -0,0 +1,84 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_SYSTEM76_MEER9_COMMON
+	def_bool n
+	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_UART_8250IO
+	select DRIVERS_GENERIC_CBFS_SERIAL
+	select DRIVERS_GENERIC_CBFS_UUID
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_SUPPORT_RESIZABLE_BARS
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_CRASHLOG
+	select SOC_INTEL_METEORLAKE
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+
+config BOARD_SYSTEM76_MEER9
+	select BOARD_SYSTEM76_MEER9_COMMON
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SOC_INTEL_METEORLAKE_U_H
+
+if BOARD_SYSTEM76_MEER9_COMMON
+
+config MAINBOARD_DIR
+	default "system76/meer9"
+
+config VARIANT_DIR
+	default "meer9" if BOARD_SYSTEM76_MEER9
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config MAINBOARD_PART_NUMBER
+	default "meer9" if BOARD_SYSTEM76_MEER9
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Meerkat" if BOARD_SYSTEM76_MEER9
+
+config MAINBOARD_VERSION
+	default "meer9" if BOARD_SYSTEM76_MEER9
+
+config CMOS_DEFAULT_FILE
+	default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
+
+config CONSOLE_POST
+	default y
+
+config D3COLD_SUPPORT
+	default n
+
+config DIMM_SPD_SIZE
+	default 1024
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
+
+config ONBOARD_VGA_IS_PRIMARY
+	default y
+
+config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS
+	default 36
+
+config POST_DEVICE
+	default n
+
+config TPM_MEASURED_BOOT
+	default y
+
+config UART_FOR_CONSOLE
+	default 0
+
+# PM Timer Disabled, saves power
+config USE_PM_ACPI_TIMER
+	default n
+
+endif

src/mainboard/system76/meer9/Kconfig.name

@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_SYSTEM76_MEER9
+	bool "meer9"
+

src/mainboard/system76/meer9/Makefile.mk

@@ -0,0 +1,13 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
+bootblock-y += bootblock.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
+
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
+
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-y += variants/$(VARIANT_DIR)/ramstage.c

src/mainboard/system76/meer9/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: System76
+Category: desktop
+ROM package: WSON-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/meer9/bootblock.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <mainboard/gpio.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	mainboard_configure_early_gpios();
+}

src/mainboard/system76/meer9/cmos.default

@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+boot_option=Fallback
+debug_level=Debug
+me_state=Disable

src/mainboard/system76/meer9/cmos.layout

@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+entries
+
+0	384	r	0	reserved_memory
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# RTC_CLK_ALTCENTURY
+400	8	r	0	century
+
+412	4	e	6	debug_level
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+
+# CMOS_VSTART_ramtop
+800	80	r	0	ramtop
+
+984	16	h	0	check_sum
+
+enumerations
+
+2	0	Enable
+2	1	Disable
+
+4	0	Fallback
+4	1	Normal
+
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+
+checksums
+
+checksum 408 799 984

src/mainboard/system76/meer9/devicetree.cb

@@ -0,0 +1,49 @@
+chip soc/intel/meteorlake
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+	# Thermal
+	register "tcc_offset" = "8"
+
+	device cpu_cluster 0 on end
+
+	device domain 0 on
+		device ref system_agent on end
+		device ref igpu on
+			# DDIA is HDMI1, DDIB is HDMI2
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			}"
+		end
+		device ref ioe_shared_sram on end
+		device ref pmc_shared_sram on end
+		device ref cnvi_wifi on
+			register "cnvi_bt_core" = "true"
+			register "cnvi_bt_audio_offload" = "true"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+
+		device ref heci1 on end
+		device ref soc_espi on
+			register "gen1_dec" = "0x007c0281" # Port 0x280 to 0x2FF (unknown)
+			register "gen2_dec" = "0x000c0081" # Port 0x80 to 0x8F (debug)
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device ref p2sb on end
+		device ref hda on
+			register "pch_hda_sdi_enable[0]" = "1"
+			register "pch_hda_audio_link_hda_enable" = "1"
+			register "pch_hda_idisp_codec_enable" = "1"
+			register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+			register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+		end
+		device ref smbus on end
+		device ref fast_spi on end
+	end
+end

src/mainboard/system76/meer9/dsdt.asl

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+//TODO: HACK FOR MISSING MISCCFG_GPIO_PM_CONFIG_BITS
+#include <soc/gpio.h>
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/meteorlake/acpi/southbridge.asl>
+		#include <soc/intel/meteorlake/acpi/tcss.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+}

src/mainboard/system76/meer9/include/mainboard/gpio.h

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_configure_early_gpios(void);
+void mainboard_configure_gpios(void);
+
+#endif

src/mainboard/system76/meer9/ramstage.c

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/ramstage.h>
+
+static void mainboard_init(void *chip_info)
+{
+	mainboard_configure_gpios();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};

src/mainboard/system76/meer9/variants/meer9/board.fmd

@@ -0,0 +1,12 @@
+FLASH 32M {
+	SI_DESC 16K
+	SI_ME 10160K
+	SI_BIOS@16M 16M {
+		RW_MRC_CACHE 64K
+		SMMSTORE(PRESERVE) 256K
+		WP_RO {
+			FMAP 4K
+			COREBOOT(CBFS)
+		}
+	}
+}

src/mainboard/system76/meer9/variants/meer9/board_info.txt

@@ -0,0 +1,2 @@
+Board name: meer9
+Release year: 2024

src/mainboard/system76/meer9/variants/meer9/gpio.c

@@ -0,0 +1,208 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	PAD_CFG_NF(GPP_A00, UP_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A01, UP_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A02, UP_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A03, UP_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A04, UP_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A05, UP_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_A06, NONE, PLTRST, NF1),
+	PAD_NC(GPP_A07, NONE),
+	PAD_NC(GPP_A08, NONE),
+	PAD_NC(GPP_A09, NONE),
+	PAD_NC(GPP_A10, NONE),
+	PAD_CFG_GPI(GPP_A11, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_A12, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_A13, UP_20K, PLTRST),
+	PAD_CFG_GPI(GPP_A14, UP_20K, PLTRST),
+	PAD_CFG_GPI(GPP_A15, NONE, PLTRST),
+	PAD_CFG_NF(GPP_A16, UP_20K, PLTRST, NF1),
+	PAD_CFG_GPI(GPP_A17, UP_20K, PLTRST),
+	PAD_CFG_GPI(GPP_A18, UP_20K, PLTRST),
+	PAD_CFG_GPI(GPP_A19, UP_20K, DEEP),
+	PAD_CFG_GPI(GPP_A20, NATIVE, DEEP),
+	PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_B00, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_B01, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_B02, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_B03, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_B04, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_B05, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_B06, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_B07, NONE, PLTRST),
+	PAD_CFG_GPO(GPP_B08, 1, PLTRST),
+	PAD_CFG_GPI(GPP_B09, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_B10, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_B11, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_B12, NONE, PLTRST),
+	PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1),
+	PAD_CFG_GPI(GPP_B14, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_B15, NONE, PLTRST),
+	PAD_CFG_NF(GPP_B16, NONE, PLTRST, NF2),
+	PAD_CFG_GPI(GPP_B17, NONE, PLTRST),
+	PAD_CFG_GPO(GPP_B18, 1, PLTRST),
+	PAD_CFG_GPO(GPP_B19, 1, PLTRST),
+	PAD_CFG_GPI(GPP_B20, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_B21, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_B22, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_B23, NONE, PLTRST),
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_C03, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_C04, NONE, PLTRST),
+	PAD_CFG_NF(GPP_C05, UP_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_C06, UP_20K, PLTRST, NF1),
+	PAD_CFG_GPI(GPP_C07, NONE, PLTRST),
+	PAD_CFG_NF(GPP_C08, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_C09, NONE, PLTRST, NF1),
+	PAD_CFG_GPI(GPP_C10, NONE, PLTRST),
+	PAD_CFG_NF(GPP_C11, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1),
+	PAD_CFG_GPI(GPP_C13, NONE, PLTRST),
+	PAD_NC(GPP_C14, NONE),
+	PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_CFG_GPI(GPP_C20, NONE, PLTRST),
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_C23, NONE, PLTRST),
+	PAD_CFG_GPO(GPP_D00, 0, PWROK),
+	PAD_CFG_GPI(GPP_D01, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_D02, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_D03, NONE, PLTRST),
+	PAD_CFG_GPO(GPP_D04, 1, PWROK),
+	PAD_CFG_GPO(GPP_D05, 1, PLTRST),
+	PAD_CFG_GPO(GPP_D06, 1, PLTRST),
+	PAD_CFG_GPO(GPP_D07, 1, PLTRST),
+	PAD_CFG_GPO(GPP_D08, 1, PLTRST),
+	PAD_CFG_GPO(GPP_D09, 0, PWROK),
+	PAD_CFG_NF(GPP_D10, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D11, NATIVE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D12, NATIVE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D13, NATIVE, PLTRST, NF1),
+	PAD_CFG_GPI(GPP_D14, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_D15, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_D16, NONE, PLTRST),
+	PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+	PAD_NC(GPP_D19, NONE),
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_D22, NATIVE, PLTRST),
+	PAD_CFG_GPI(GPP_D23, NATIVE, PLTRST),
+	PAD_CFG_GPI(GPP_E00, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_E01, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_E02, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_E03, NONE, PLTRST),
+	PAD_CFG_GPO(GPP_E04, 0, PLTRST),
+	PAD_CFG_GPO(GPP_E05, 1, PLTRST),
+	PAD_CFG_GPI(GPP_E06, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_E07, NONE, PLTRST),
+	PAD_CFG_NF(GPP_E08, NONE, PLTRST, NF1),
+	PAD_CFG_GPI(GPP_E09, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_E10, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_E11, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_E12, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_E13, NONE, PLTRST),
+	PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1),
+	PAD_CFG_GPI(GPP_E15, NONE, PLTRST),
+	PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF2),
+	PAD_CFG_GPI(GPP_E17, NONE, PLTRST),
+	PAD_NC(GPP_E18, NONE),
+	PAD_NC(GPP_E19, NONE),
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE),
+	PAD_CFG_NF(GPP_E22, DN_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_F00, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_F01, UP_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_F02, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_F03, UP_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_F04, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_F05, NONE, PLTRST, NF3),
+	PAD_CFG_NF(GPP_F06, NONE, PLTRST, NF1),
+	PAD_CFG_TERM_GPO(GPP_F07, 1, DN_20K, PWROK),
+	PAD_CFG_GPI(GPP_F08, DN_20K, PLTRST),
+	PAD_CFG_GPI(GPP_F09, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F11, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F12, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F13, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F14, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F15, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F16, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F17, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F18, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F19, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F21, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F22, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F23, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_H00, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_H01, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_H02, NONE, PLTRST),
+	PAD_NC(GPP_H03, NONE),
+	PAD_CFG_NF(GPP_H04, NONE, PLTRST, NF2),
+	PAD_CFG_NF(GPP_H05, NONE, PLTRST, NF2),
+	PAD_CFG_GPI(GPP_H06, UP_20K, PLTRST),
+	PAD_CFG_GPI(GPP_H07, UP_20K, PLTRST),
+	PAD_CFG_GPI(GPP_H08, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_H09, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_H10, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_H11, NONE, PLTRST),
+	PAD_NC(GPP_H12, NONE),
+	PAD_CFG_GPI(GPP_H13, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_H14, NONE, PLTRST),
+	PAD_CFG_GPO(GPP_H15, 1, PLTRST),
+	PAD_CFG_NF(GPP_H16, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_H17, NONE, PLTRST, NF1),
+	PAD_NC(GPP_H18, NONE),
+	PAD_CFG_NF(GPP_H19, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1),
+	PAD_CFG_GPO(GPP_H21, 1, PLTRST),
+	PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_S00, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_S01, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_S02, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_S03, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_S04, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_S05, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_S06, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_S07, NONE, PLTRST),
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_V05, UP_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_V06, NATIVE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_V07, NATIVE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_V08, UP_20K, PLTRST, NF1),
+	PAD_CFG_NF(GPP_V09, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_V10, NONE, PLTRST, NF1),
+	PAD_CFG_GPI(GPP_V11, NONE, PLTRST),
+	PAD_NC(GPP_V12, NONE),
+	PAD_CFG_NF(GPP_V13, NONE, PLTRST, NF1),
+	PAD_CFG_GPI(GPP_V14, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_V15, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_V16, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_V17, NONE, PLTRST),
+	PAD_NC(GPP_V18, NONE),
+	PAD_CFG_NF(GPP_V19, NONE, PLTRST, NF1),
+	PAD_NC(GPP_V20, NONE),
+	PAD_NC(GPP_V21, NONE),
+	PAD_NC(GPP_V22, NONE),
+	PAD_NC(GPP_V23, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/meer9/variants/meer9/gpio_early.c

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/system76/meer9/variants/meer9/hda_verb.c

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC256 */
+	0x10ec0256, /* Vendor ID */
+	0x18490256, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x18490256),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x13, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x14, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a11020),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40400001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x02211010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/meer9/variants/meer9/overridetree.cb

@@ -0,0 +1,83 @@
+chip soc/intel/meteorlake
+	device domain 0 on
+		#TODO: all the devices have different subsystem product IDs
+		#subsystemid 0x1849 TODO inherit
+
+		device ref tbt_pcie_rp0 on end
+		device ref tcss_xhci on
+			#TODO
+		end
+		device ref tcss_dma0 on end
+		device ref xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC_SKIP),	/* TODO */
+				[1] = USB2_PORT_MID(OC_SKIP),	/* TODO */
+				[2] = USB2_PORT_MID(OC_SKIP),	/* TODO */
+				[3] = USB2_PORT_MID(OC_SKIP),	/* TODO */
+				[4] = USB2_PORT_MID(OC_SKIP),	/* TODO */
+				[5] = USB2_PORT_MID(OC_SKIP),	/* TODO */
+				[6] = USB2_PORT_MID(OC_SKIP),	/* TODO */
+				[7] = USB2_PORT_MID(OC_SKIP),	/* TODO */
+				[8] = USB2_PORT_MID(OC_SKIP),	/* TODO */
+				[9] = USB2_PORT_MID(OC_SKIP),	/* TODO */
+			}"
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC_SKIP),	/* TODO */
+				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* TODO */
+			}"
+		end
+		device ref pcie_rp5 on
+			# GLAN1
+			register "pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,
+			}"
+			register "pcie_clk_config_flag[2]" = "PCIE_CLK_FREE_RUNNING"
+			device pci 00.0 on end
+		end
+		device ref pcie_rp6 on
+			# GLAN2
+			register "pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp7 on
+			# M.2 Key-E1
+			register "pcie_rp[PCH_RP(7)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp10 on
+			# M.2 Key-M1
+			# XXX: Schematics show RP[13:16] used
+			register "pcie_rp[PCH_RP(10)]" = "{
+				.clk_src = 8,
+				.clk_req = 8,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp11 on
+			# M.2 Key-M2
+			# XXX: Schematics show RP[17:20] used
+			register "pcie_rp[PCH_RP(11)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref sata on
+			register "sata_salp_support" = "1"
+			register "sata_ports_enable[0]" = "1" # SATA 0
+			register "sata_ports_dev_slp[0]" = "1"
+		end
+		device ref hda on
+			subsystemid 0x1849 0x0256
+		end
+		device ref gbe on end
+	end
+end

src/mainboard/system76/meer9/variants/meer9/ramstage.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// XXX: Enabling C10 reporting causes system to constantly enter and
+	// exit opportunistic suspend when idle.
+	params->PchEspiHostC10ReportEnable = 0;
+}

src/mainboard/system76/meer9/variants/meer9/romstage.c

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR5,
+		.ect = true,
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = { .addr_dimm[0] = 0x50, },
+			[1] = { .addr_dimm[0] = 0x52, },
+		},
+	};
+	const bool half_populated = false;
+
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}

src/mainboard/system76/mtl/Makefile.mk

@@ -17,4 +17,4 @@ ramstage-y += variants/$(VARIANT_DIR)/gpio.c
 ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
 ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
 
-SPD_SOURCES = samsung-M425R1GB4BB0-CQKOD samsung-M425R1GB4PB0-CWMOD
+SPD_SOURCES = samsung-M425R1GB4BB0-CQKOD

src/mainboard/system76/mtl/spd/samsung-M425R1GB4BB0-CQKOD.spd.hex

@@ -62,4 +62,4 @@
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

src/mainboard/system76/mtl/spd/samsung-M425R1GB4PB0-CWMOD.spd.hex

@@ -1,65 +0,0 @@
-# Samsung M425R1GB4PB0-CWMOD
-30 10 12 03 04 00 40 42 00 00 00 00 B0 02 09 00
-00 00 00 00 65 01 F2 03 7A AD 00 00 00 00 80 3E
-80 3E 80 3E 00 7D 80 BB 30 75 27 01 A0 00 82 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 88 13 08 88 13 08 20 4E 20 10
-27 10 CD 37 28 10 27 10 C4 09 04 4C 1D 0C 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-10 00 80 B3 80 21 80 B3 82 20 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 0F 01 02 81 00 22 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 5E 9B
-80 CE 00 00 00 00 00 00 00 4D 34 32 35 52 31 47
-42 34 50 42 30 2D 43 57 4D 4F 44 20 20 20 20 20
-20 20 20 20 20 20 20 00 80 CE 50 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

src/mainboard/system76/mtl/variants/lemp13/gpio.c

@@ -109,7 +109,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_E08, 0, PLTRST),
 	PAD_CFG_GPI(GPP_E09, NONE, DEEP),
 	PAD_CFG_GPO(GPP_E10, 0, PLTRST),
-	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP),
 	_PAD_CFG_STRUCT(GPP_E12, 0x84002200, 0x0000),
 	_PAD_CFG_STRUCT(GPP_E13, 0x44002100, 0x0000),
 	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),

src/mainboard/system76/mtl/variants/lemp13/gpio_early.c

@@ -6,7 +6,6 @@
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK
 	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA
-	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX
 };

src/mainboard/system76/mtl/variants/lemp13/romstage.c

@@ -1,19 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <soc/gpio.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
 
-static size_t get_spd_index(void)
-{
-	// BOARD_ID1 is high if 5600 MT/s and low if 4800 MT/s
-	if (gpio_get(GPP_E11)) {
-		return 1;
-	} else {
-		return 0;
-	}
-}
-
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
 	const struct mb_cfg board_cfg = {
@@ -23,7 +12,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const struct mem_spd spd_info = {
 		.topo = MEM_TOPO_MIXED,
-		.cbfs_index = get_spd_index(),
+		.cbfs_index = 0,
 		.smbus[1] = { .addr_dimm[0] = 0x52, },
 	};
 	const bool half_populated = false;