mb/system76/rpl: lemp12: Add timeouts for PCIE RPs

The FSP may fail to detect PCIe 4.0 devices in PCIe 3.0 slots on S3
resume.

Change-Id: Ib2efec2febc9f6c25b1dd8766fa08c560365325d
Signed-off-by: Tim Crawford <tcrawford@system76.com>

src/drivers/smmstore/ramstage.c

@@ -57,6 +57,7 @@ static void init_store(void *unused)
 
 	printk(BIOS_INFO, "SMMSTORE: Setting up SMI handler\n");
 
+	for (int retries = 0; retries < 3; retries++) {
 		/* Issue SMI using APM to update the com buffer and to lock the SMMSTORE */
 		__asm__ __volatile__ (
 			"outb %%al, %%dx"
@@ -66,9 +67,12 @@ static void init_store(void *unused)
 			  "d" (APM_CNT)
 			: "memory");
 
-	if (eax != SMMSTORE_RET_SUCCESS) {
-		printk(BIOS_ERR, "SMMSTORE: Failed to install com buffer\n");
-		return;
+		if (eax == SMMSTORE_RET_SUCCESS) {
+			printk(BIOS_INFO, "SMMSTORE: Installed com buffer\n");
+			break;
+		}
+
+		printk(BIOS_ERR, "SMMSTORE: Failed to install com buffer: 0x%x\n", eax);
 	}
 }
 

src/mainboard/system76/adl/Kconfig

@@ -1,6 +1,7 @@
 config BOARD_SYSTEM76_ADL_COMMON
 	def_bool n
 	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
 	select DRIVERS_I2C_HID

src/mainboard/system76/rpl/Kconfig

@@ -1,6 +1,7 @@
 config BOARD_SYSTEM76_RPL_COMMON
 	def_bool n
 	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
 	select DRIVERS_I2C_HID

src/mainboard/system76/rpl/variants/lemp12/overridetree.cb

@@ -77,6 +77,7 @@ chip soc/intel/alderlake
 				.clk_src = 1,
 				.clk_req = 1,
 				.flags = PCIE_RP_LTR,
+				.pcie_rp_detect_timeout_ms = 50,
 			}"
 		end
 	end

src/mainboard/system76/tgl-h/Kconfig

@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_GAZE16_3050 || BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GA
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
 	select DRIVERS_GFX_NVIDIA

src/soc/intel/alderlake/include/soc/gpio.h

@@ -5,8 +5,13 @@
 
 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
 #include <soc/gpio_defs_pch_s.h>
+#if CONFIG(SOC_INTEL_RAPTORLAKE)
+#define CROS_GPIO_NAME		"INTC1085"
+#define CROS_GPIO_DEVICE_NAME	"INTC1085:00"
+#else
 #define CROS_GPIO_NAME		"INTC1056"
 #define CROS_GPIO_DEVICE_NAME	"INTC1056:00"
+#endif
 #elif CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
 #include <soc/gpio_defs.h>
 #define CROS_GPIO_NAME		"INTC1057"

src/soc/intel/alderlake/include/soc/iomap.h

@@ -20,8 +20,14 @@
 #define PCH_TRACE_HUB_BASE_SIZE	0x00800000
 #endif
 
+/* Hack to include SBREG in PCH_RESERVED region on ADL-S/RPL-S */
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
+#define PCH_PRESERVED_BASE_ADDRESS	0xe0000000
+#define PCH_PRESERVED_BASE_SIZE		0x1e800000
+#else
 #define PCH_PRESERVED_BASE_ADDRESS	0xfc800000
 #define PCH_PRESERVED_BASE_SIZE		0x02000000
+#endif
 
 #define UART_BASE_SIZE		0x1000