mb/system76/rpl: lemp12: Add timeouts for PCIE RPs

The FSP may fail to detect PCIe 4.0 devices in PCIe 3.0 slots on S3
resume.

Change-Id: Ib2efec2febc9f6c25b1dd8766fa08c560365325d
Signed-off-by: Tim Crawford <tcrawford@system76.com>

.gitmodules

@@ -1,67 +1,67 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe
 [submodule "util/goswid"]
 	path = util/goswid
-	url = ../goswid
+	url = https://review.coreboot.org/goswid.git
 	branch = trunk

Documentation/mainboard/index.md

@@ -85,7 +85,6 @@ The boards in this section are not real mainboards, but emulators.
 ## Intel
 
 - [DG43GT](intel/dg43gt.md)
-- [IceLake RVP](intel/icelake_rvp.md)
 - [KBLRVP11](intel/kblrvp11.md)
 
 ## Kontron
@@ -208,12 +207,16 @@ The boards in this section are not real mainboards, but emulators.
 - [Galago Pro 6](system76/galp6.md)
 - [Gazelle 15](system76/gaze15.md)
 - [Gazelle 16](system76/gaze16.md)
+- [Gazelle 17](system76/gaze17.md)
 - [Lemur Pro 9](system76/lemp9.md)
 - [Lemur Pro 10](system76/lemp10.md)
+- [Lemur Pro 11](system76/lemp11.md)
 - [Oryx Pro 5](system76/oryp5.md)
 - [Oryx Pro 6](system76/oryp6.md)
 - [Oryx Pro 7](system76/oryp7.md)
 - [Oryx Pro 8](system76/oryp8.md)
+- [Oryx Pro 9](system76/oryp9.md)
+- [Oryx Pro 10](system76/oryp10.md)
 
 ## Texas Instruments
 

Documentation/mainboard/intel/icelake_rvp.md

@@ -1,40 +0,0 @@
-# Intel Ice Lake RVP (Reference Validation Platform)
-
-This page describes how to run coreboot on the Intel icelake_rvp board.
-
-Ice Lake RVP is based on Intel Ice Lake platform, please refer to below link to get more details
-```eval_rst
-:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
-```
-
-## Building coreboot
-
-* Follow build instructions mentioned in Ice Lake document
-```eval_rst
-:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
-```
-
-* The default options for this board should result in a fully working image:
-```bash
-	# echo "CONFIG_VENDOR_INTEL=y" > .config
-	# echo "CONFIG_BOARD_INTEL_ICELAKE_RVPU=y" >> .config
-	# make olddefconfig && make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Winbond    |
-+---------------------+------------+
-| Size                | 32 MiB     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-```

Documentation/mainboard/system76/gaze17.md

@@ -0,0 +1,65 @@
+# System76 Gazelle 17 (gaze17)
+
+The gaze17 comes in 2 variants: gaze17-3050 and gaze17-3060-b.
+
+## Specs
+
+- CPU
+  - Intel Core i5-12500H
+  - Intel Core i7-12700H
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - dGPU options
+    - NVIDIA GeForce RTX 3050
+    - NVIDIA GeForce RTX 3050 Ti
+    - NVIDIA GeForce RTX 3060
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MT/s
+- Networking
+  - Gigabit Ethernet
+    - 3050: Realtek RTL8111H controller
+    - 3060: Onboard Intel I219-V
+  - M.2 PCIe/CNVi WiFi/Bluetooth
+    - Intel Wi-Fi 6 AX201
+- Power
+  - 3050: 150W (20V, 7.5A) AC barrel adapter
+  - 3060: 180W (20V, 9A) AC barrel adapter
+      - Lite-On PA-1181-76, using a C5 power cord
+  - 54Wh 4-cell Li-ion battery (NP50BAT-4-54)
+- Sound
+  - Realtek ALC256 codec
+  - Internal speakers and microphone
+  - Combined 3.5mm headphone/microphone jack
+  - Dedicated 3.5mm microphone jack
+- Storage
+  - 1x M.2 PCIe NVMe Gen 4 SSD
+  - 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
+  - MicroSD card reader (Realtek RTS5227S/OZ711LV2)
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+---------------------+
+| Type                | Value               |
++=====================+=====================+
+| Socketed flash      | no                  |
++---------------------+---------------------+
+| Vendor              | GigaDevice          |
++---------------------+---------------------+
+| Model               | GD25B256E           |
++---------------------+---------------------+
+| Size                | 32 MiB              |
++---------------------+---------------------+
+| Package             | WSON-8              |
++---------------------+---------------------+
+| Internal flashing   | yes                 |
++---------------------+---------------------+
+| External flashing   | yes                 |
++---------------------+---------------------+
+```
+
+The position of the flash chip depends on the variant:
+
+- 3050: U24, below the bottom DIMM slot.
+- 3060: U55, left of the PCIe 4.0 M.2 slot.

Documentation/mainboard/system76/lemp11.md

@@ -0,0 +1,62 @@
+# System76 Lemur Pro 11 (lemp11)
+
+## Specs
+
+- CPU
+  - Intel Core i5-1235U
+  - Intel Core i7-1255U
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - Intel Iris Xe Graphics
+  - eDP 14.0" 1920x1080@60Hz LCD
+  - 1x HDMI 2.1
+  - 1x DisplayPort 1.4 over USB-C
+- Memory
+  - Channel 0: 8-GB on-board DDR4 (Samsung K4AAG165WA-BCWE)
+  - Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM @ 3200 MHz
+- Networking
+  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
+- Power
+  - 65W (19V, 3.42A) AC barrel adapter (AcBel ADA012)
+  - USB-C charging, compatible with 65W+ chargers
+  - 73Wh 4-cell Lithium-ion battery (L140BAT-4)
+- Sound
+  - Realtek ALC256 codec
+  - Internal speakers and microphone
+  - Combined 3.5 mm headphone/microphone jack
+  - HDMI, USB-C DisplayPort audio
+- Storage
+  - M.2 PCIe NVMe Gen 4 SSD
+  - M.2 PCIe NVMe Gen 3 or SATA 3 SSD
+  - MicroSD card reader (RTS5227S)
+- USB
+  - 1x USB Type-C with Thunderbolt 4
+  - 1x USB 3.2 (Gen 2) Type-A
+  - 1x USB 3.2 (Gen 1) Type-A
+- Dimensions
+    - 1.65cm x 32.2cm x 21.68cm, 1.15kg
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+---------------------+
+| Type                | Value               |
++=====================+=====================+
+| Socketed flash      | no                  |
++---------------------+---------------------+
+| Vendor              | Macronix            |
++---------------------+---------------------+
+| Model               | MX25L25673G         |
++---------------------+---------------------+
+| Size                | 32 MiB              |
++---------------------+---------------------+
+| Package             | WSON-8              |
++---------------------+---------------------+
+| Internal flashing   | yes                 |
++---------------------+---------------------+
+| External flashing   | yes                 |
++---------------------+---------------------+
+```
+
+The flash chip (U41) is left of the DIMM slot.

Documentation/mainboard/system76/oryp10.md

@@ -0,0 +1,69 @@
+# System76 Oryx Pro 10 (oryp10)
+
+## Specs
+
+- CPU
+  - Intel Core i7-12700H
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - dGPU options:
+    - NVIDIA GeForce RTX 3070 Ti (Max-Q)
+    - NVIDIA GeForce RTX 3080 Ti (Max-Q)
+  - eDP options:
+    - 15.6" 3840x2160@60Hz OLED (Samsung ATNA56WR14-0)
+    - 15.6" 1920x1080@144Hz LCD (BOE NV156FHM-NY5)
+    - 17.3" 1920x1080@144Hz LCD (BOE NV173FHM-NY1)
+  - 1x HDMI 2.1
+  - 1x Mini DisplayPort 1.4
+  - 1x DisplayPort 1.4 over USB-C
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 4800 MHz
+- Networking
+  - Gigabit Ethernet
+  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
+- Power
+  - 230W (20V, 11.5A)  AC barrel adapter (Lite-On PA-1231-26)
+  - 80Wh 6-cell Lithium-ion battery
+- Sound
+  - Realtek ALC1220 codec
+  - Realtek ALC1306 smart amp
+  - Internal speakers and microphone
+  - Combined 3.5mm headphone & microphone jack
+  - Combined 3.5mm microphone & S/PDIF jack
+  - HDMI, mDP, USB-C DP audio
+- Storage
+  - 2x M.2 PCIe NVMe Gen 4 SSD
+  - MicroSD card reader (RTS5227S)
+- USB
+  - 1x USB Type-C with Thunderbolt 4
+  - 1x USB 3.2 (Gen 2) Type-C
+  - 2x USB 3.2 (Gen 1) Type-A
+- Dimensions
+  - 15": 35.814cm x 24.003cm x 2.489cm, 2.4kg
+  - 17": 39.599cm x 26.213cm x 2.489cm, 2.8kg
+
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+---------------------+
+| Type                | Value               |
++=====================+=====================+
+| Socketed flash      | no                  |
++---------------------+---------------------+
+| Vendor              | Macronix            |
++---------------------+---------------------+
+| Model               | MX25L25673G         |
++---------------------+---------------------+
+| Size                | 32 MiB              |
++---------------------+---------------------+
+| Package             | WSON-8              |
++---------------------+---------------------+
+| Internal flashing   | yes                 |
++---------------------+---------------------+
+| External flashing   | yes                 |
++---------------------+---------------------+
+```
+
+The flash chip (U61) is left of the DIMM slots.

Documentation/mainboard/system76/oryp9.md

@@ -0,0 +1,67 @@
+# System76 Oryx Pro 9 (oryp9)
+
+## Specs
+
+- CPU
+  - Intel Core i7-12700H
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - dGPU options:
+    - NVIDIA GeForce RTX 3070 Ti (Max-Q)
+    - NVIDIA GeForce RTX 3080 Ti (Max-Q)
+  - eDP options:
+    - 15.6" 1920x1080@144Hz LCD (BOE NV156FHM-NY5)
+    - 17.3" 1920x1080@144Hz LCD (BOE NV173FHM-NY1)
+  - 1x HDMI 2.1
+  - 1x Mini DisplayPort 1.4
+  - 1x DisplayPort 1.4 over USB-C
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
+- Networking
+  - Gigabit Ethernet
+  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
+- Power
+  - 230W (20V, 11.5A)  AC barrel adapter (Lite-On PA-1231-26)
+  - 80Wh 6-cell Lithium-ion battery
+- Sound
+  - Realtek ALC1220 codec
+  - TI TAS5825M smart amp
+  - Internal speakers and microphone
+  - Combined 3.5mm headphone & microphone jack
+  - Combined 3.5mm microphone & S/PDIF jack
+  - HDMI, mDP, USB-C DP audio
+- Storage
+  - 2x M.2 PCIe NVMe Gen 4 SSD
+  - MicroSD card reader (RTS5227S)
+- USB
+  - 1x USB Type-C with Thunderbolt 4
+  - 1x USB 3.2 (Gen 2) Type-C
+  - 2x USB 3.2 (Gen 1) Type-A
+- Dimensions
+  - 15": 35.814cm x 24.003cm x 2.489cm, 1.99kg
+  - 17": 39.599cm x 26.213cm x 2.489cm, 2.3kg
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+---------------------+
+| Type                | Value               |
++=====================+=====================+
+| Socketed flash      | no                  |
++---------------------+---------------------+
+| Vendor              | Macronix            |
++---------------------+---------------------+
+| Model               | MX25L25673G         |
++---------------------+---------------------+
+| Size                | 32 MiB              |
++---------------------+---------------------+
+| Package             | WSON-8              |
++---------------------+---------------------+
+| Internal flashing   | yes                 |
++---------------------+---------------------+
+| External flashing   | yes                 |
++---------------------+---------------------+
+```
+
+The flash chip (U61) is left of the DIMM slots.

Documentation/security/vboot/list_vboot.md

@@ -1,9 +1,11 @@
 # vboot-enabled devices
 
 ## AMD
-- Birman
+- Birman for Phoenix SoC
+- Birman for Glinda SoC
 - Chausie
 - Majolica
+- Mayan for Phoenix SoC
 
 ## Clevo
 - N130WU / N131WU
@@ -64,16 +66,20 @@
 - Joxer
 - Pujjo
 - Xivu
-- Gaelin4ADL
+- Gaelin
 - Yaviks
 - Lisbon
 - Zydron
+- Gladios
+- Marasov
+- Omnigul
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
 - Dojo
 - Tomato
 - Kingler
 - Steelix
+- Voltorb
 - Krabby
 - Tentacruel
 - Magikarp
@@ -191,22 +197,6 @@
 - Puff
 - Scout
 - Wyvern (CTL Chromebox CBx2)
-- Banjo (Acer Chromebook 15 (CB3-531))
-- Candy (Dell Chromebook 11 3120)
-- Clapper (Lenovo N20 Chromebook)
-- Enguarde
-- Glimmer (Lenovo ThinkPad 11e Chromebook)
-- Gnawty (Acer Chromebook 11 (CB3-111/131,C730/C730E/C735))
-- Heli (Haier Chromebook G2)
-- Kip (HP Chromebook 11 G3 / G4 / G4 EE)
-- Ninja (AOpen Chromebox Commercial)
-- Orco (Lenovo 100S Chromebook)
-- Quawks (ASUS Chromebook C300)
-- Squawks (ASUS Chromebook C200)
-- Rambi
-- Sumo (AOpen Chromebase Commercial)
-- Swanky (Toshiba Chromebook 2)
-- Winky (Samsung Chromebook 2 (XE500C12))
 - Reef/Electro (Acer Chromebook Spin 11 R751T)
 - Pyro (Lenovo Thinkpad (Yoga) 11e Chromebook)
 - Sand (Acer Chromebook 15 CB515-1HT/1H)
@@ -217,8 +207,9 @@
 - Sarien (Dell Latitude 5400 Chromebook Enterprise)
 - Skyrim
 - Winterhold
-- Morthal
 - Frostflow
+- Crystaldrift
+- Markarth
 - Falco (HP Chromebook 14)
 - Leon (Toshiba Chromebook)
 - Peppy (Acer C720/C720P Chromebook)
@@ -299,8 +290,6 @@
 - Emerald Lake 2 CRB
 - Galileo
 - Glkrvp
-- Icelake U DDR4/LPDDR4 RVP
-- Icelake Y LPDDR4 RVP
 - Jasperlake DDR4/LPDDR4 RVP
 - Jasperlake DDR4/LPDDR4 RVP with Chrome EC
 - Kabylake LPDDR3 RVP3
@@ -308,6 +297,8 @@
 - Kabylake DDR4 RVP8
 - Kabylake DDR4 RVP11
 - Kunimitsu
+- Meteorlake-P RVP
+- Meteorlake-P RVP with Chrome EC
 - shadowmountain
 - Strago
 - Tigerlake UP3 RVP
@@ -346,7 +337,8 @@
 - ThinkPad X60 / X60s / X60t
 
 ## MSI
-- PRO Z690-A WIFI DDR4
+- PRO Z690-A (WIFI) DDR4
+- PRO Z690-A (WIFI)
 
 ## OpenCellular
 - Elgon (GBCv2)

Documentation/soc/intel/icelake/iceLake_coreboot_development.md

@@ -1,67 +0,0 @@
-# Intel Ice Lake coreboot development
-
-## Introduction
-
-This document captures the coreboot development strategy for Intel SoC named Ice lake.
-
-The Ice Lake processor family is the next generation Intel® Core processor family.
-These processors are built using Intel's 10 nm+ process.
-
-* [What is Ice Lake?](https://www.intel.in/content/www/in/en/design/products-and-solutions/processors-and-chipsets/ice-lake/overview.html)
-
-## Development Strategy
-
-Like any other Intel SoC, Ice Lake coreboot development is also based on "Intel common code development model".
-
-1. Intel develops initial Firmware code for Ice Lake SoC.
-
-2. Additionally provides Firmware code support for Intel Reference Platform (RVP), known as Ice lake RVP with same SoC.
-   ```eval_rst
-   :doc:`../../../mainboard/intel/icelake_rvp`
-   ```
-
-### Summary:
-* SoC is Ice Lake.
-* Reference platform is icelake_rvp.
-* OEM board is Dragonegg.
-
-## Create coreboot Image
-
-1. Clone latest coreboot code as below
-   ```bash
-   $ git clone https://review.coreboot.org/coreboot.git
-   ```
-
-2. Place blobs (ucode, me.bin and FSP packages) in appropriate locations
-
-   Note:
-   Consider the fact that ucode and ME kit for Ice Lake SoC will be available from Intel VIP site.
-   After product launch, FSP binary will be available externally as any other program.
-
-3. Create coreboot .config
-
-4. Build toolchain
-   ```bash
-   CPUS=$(nproc--ignore=1)  make  crossgcc-i386  iasl
-   ```
-
-5. Build image
-   ```bash
-   $ make # the image is generated as build/coreboot.rom
-   ```
-
-## Flashing coreboot
-
-Flashing mechanism might be different between Intel RVP (Reference Validation Platform) and Chromebooks:
-
-* Make use of dediprog while flashing coreboot image on Intel-RVP
-* For Chromebook related platform like dragonegg, one can flash via servo:
-
-```bash
-   $ dut-control spi2_vref:pp3300 spi2_buf_en:on spi2_buf_on_flex_en:on warm_reset:on
-   $ sudo flashrom -n -p ft2232_spi:type=servo-v2 -w <bios_image>
-   $ dut-control spi2_vref:off spi2_buf_en:off spi2_buf_on_flex_en:off warm_reset:off
-```
-### References
-* [flashrom](https://flashrom.org/Flashrom)
-* [Servo](https://www.chromium.org/chromium-os/servo)

Documentation/soc/intel/icelake/index.md

@@ -1,7 +0,0 @@
-# Intel Ice Lake SOC-specific documentation
-
-This section contains documentation about coreboot on specific Intel "Ice Lake" SOCs.
-
-## Ice Lake coreboot development
-
-- [Ice Lake coreboot development](iceLake_coreboot_development.md)

Documentation/soc/intel/index.md

@@ -7,7 +7,6 @@ This section contains documentation about coreboot on specific Intel SOCs.
 - [Common code development strategy](code_development_model/code_development_model.md)
 - [FSP](fsp/index.md)
 - [Broadwell](broadwell/index.md)
-- [Ice Lake/9th Gen Core-i series](icelake/index.md)
 - [MP Initialization](mp_init/mp_init.md)
 - [Microcode Updates](microcode.md)
 - [Firmware Interface Table](fit.md)

payloads/external/FILO/Kconfig.name

@@ -6,4 +6,4 @@ config PAYLOAD_FILO
 	  with a FILO payload. If you don't know what this is
 	  about, just leave it enabled.
 
-	  See https://coreboot.org/Payloads for more information.
+	  See https://doc.coreboot.org/payloads.html for more information.

payloads/external/GRUB2/Kconfig.name

@@ -7,7 +7,7 @@ config PAYLOAD_GRUB2
 	  with a GRUB2 payload. If you don't know what this is
 	  about, just leave it enabled.
 
-	  See https://coreboot.org/Payloads for more information.
+	  See https://doc.coreboot.org/payloads.html for more information.
 
 config PAYLOAD_SEAGRUB
 	bool "GRUB2 atop SeaBIOS"
@@ -19,4 +19,4 @@ config PAYLOAD_SEAGRUB
 	  with a GRUB2 payload running atop SeaBIOS to improve its
 	  hardware compatibility.
 
-	  See https://coreboot.org/Payloads for more information.
+	  See https://doc.coreboot.org/payloads.html for more information.

payloads/external/LinuxBoot/Kconfig.name

@@ -8,4 +8,4 @@ config PAYLOAD_LINUXBOOT
 	  with a LinuxBoot payload. If you don't know what this is
 	  about, just leave it enabled.
 
-	  See https://coreboot.org/Payloads for more information.
+	  See https://doc.coreboot.org/payloads.html for more information.

payloads/external/SeaBIOS/Kconfig.name

@@ -7,4 +7,4 @@ config PAYLOAD_SEABIOS
 	  with a SeaBIOS payload. If you don't know what this is
 	  about, just leave it enabled.
 
-	  See https://coreboot.org/Payloads for more information.
+	  See https://doc.coreboot.org/payloads.html for more information.

payloads/external/U-Boot/Kconfig.name

@@ -5,6 +5,6 @@ config PAYLOAD_UBOOT
 	  Select this option if you want to build a coreboot image
 	  with a U-Boot payload.
 
-	  See https://coreboot.org/Payloads and U-Boot's documentation
+	  See https://doc.coreboot.org/payloads.html and U-Boot's documentation
 	  at http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86
 	  for more information.

payloads/external/depthcharge/Kconfig.name

@@ -5,4 +5,4 @@ config PAYLOAD_DEPTHCHARGE
 	  Select this option if you want to build a coreboot image
 	  with a depthcharge payload.
 
-	  See https://coreboot.org/Payloads for more information.
+	  See https://doc.coreboot.org/payloads.html for more information.

payloads/external/edk2/Kconfig.name

@@ -6,4 +6,4 @@ config PAYLOAD_EDK2
 	  with a edk2 payload. If you don't know what this is
 	  about, just leave it enabled.
 
-	  See https://coreboot.org/Payloads for more information.
+	  See https://doc.coreboot.org/payloads.html for more information.

src/acpi/acpigen_dsm.c

@@ -47,3 +47,26 @@ void acpigen_write_dsm_i2c_hid(struct dsm_i2c_hid_config *config)
 }
 
 /* ------------------- End: I2C HID DSM ------------------------- */
+
+#define USB_DSM_UUID    "CE2EE385-00E6-48CB-9F05-2EDB927C4899"
+
+static void usb_dsm_func5_cb(void *arg)
+{
+	struct dsm_usb_config *config = arg;
+	acpigen_write_return_byte(config->usb_lpm_incapable);
+}
+
+static void (*usb_dsm_callbacks[6])(void *) = {
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	usb_dsm_func5_cb,
+};
+
+void acpigen_write_dsm_usb(struct dsm_usb_config *config)
+{
+	acpigen_write_dsm(USB_DSM_UUID, usb_dsm_callbacks,
+			  ARRAY_SIZE(usb_dsm_callbacks), config);
+}

src/arch/x86/Kconfig

@@ -135,15 +135,6 @@ config X86_TOP4G_BOOTMEDIA_MAP
 	depends on !X86_CUSTOM_BOOTMEDIA
 	default y
 
-# This is something you almost certainly don't want to mess with.
-# How many SIPIs do we send when starting up APs and cores?
-# The answer in 2000 or so was '2'. Nowadays, on many systems,
-# it is 1. Set a safe default here, and you can override it
-# on reasonable platforms.
-config NUM_IPI_STARTS
-	int
-	default 2
-
 config PRERAM_CBMEM_CONSOLE_SIZE
 	hex
 	default 0xc00

src/arch/x86/include/mode_switch.h

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <stddef.h>
 #include <stdint.h>
 
 #if ENV_X86_64

src/arch/x86/include/smm.h

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <stddef.h>
 #include <stdint.h>
 #include <cpu/x86/smm.h>
 

src/drivers/gfx/nvidia/Kconfig

@@ -0,0 +1,38 @@
+config DRIVERS_GFX_NVIDIA
+	bool
+	default n
+	help
+	  Support for NVIDIA Optimus graphics
+
+config DRIVERS_GFX_NVIDIA_BRIDGE
+	hex "PCI bridge for the GPU device"
+	default 0x01
+	depends on DRIVERS_GFX_NVIDIA
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	depends on DRIVERS_GFX_NVIDIA
+	bool
+	default n
+	help
+	  Support for NVIDIA Dynamic Boost
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
+	int "Total processor power offset from default TGP in watts"
+	default 45
+	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	help
+	  This identifies the available power for the CPU or GPU boost
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN
+	int "Minimum TGP offset from default TGP in watts"
+	default 0
+	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	help
+	  This is used to transfer power from the GPU to the CPU
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
+	int "Maximum TGP offset from default TGP in watts"
+	default 0
+	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	help
+	  This is used to transfer power from the CPU to the GPU

src/drivers/gfx/nvidia/Makefile.inc

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
+
+ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c

src/drivers/gfx/nvidia/acpi/coffeelake.asl

@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* NVIDIA GC6 on CFL and CML CPU PCIe ports */
+
+// Memory mapped PCI express config space
+OperationRegion (PCIC, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + (CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15), 0x1000)
+
+Field (PCIC, ByteAcc, NoLock, Preserve) {
+	PVID,   16,
+	PDID,   16,
+
+	Offset (0x248),
+		,   7,
+	L23E,   1,      /* L23_Rdy Entry Request */
+	L23R,   1,      /* L23_Rdy to Detect Transition */
+
+	Offset (0xC20),
+		,   4,
+	P0AP,   2,      /* Additional power savings */
+
+	Offset (0xC38),
+		,   3,
+	P0RM,   1,      /* Robust squelch mechanism */
+}
+
+// Enter L23
+Method (DL23, 0, Serialized) {
+	Printf("      GPU PORT DL23 START")
+
+	L23E = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23E) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+
+	P0RM = 1
+	P0AP = 3
+
+	Printf("      GPU PORT DL23 FINISH")
+}
+
+// Exit L23
+Method (L23D, 0, Serialized) {
+	Printf("      GPU PORT L23D START")
+
+	L23R = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23R) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+
+	P0RM = 0
+	P0AP = 0
+
+	Printf("      GPU PORT L23D FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PORT PWRR._ON")
+
+		^^DEV0._ON()
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PORT PWRR._OFF")
+
+		^^DEV0._OFF()
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
+
+#include "common/gpu.asl"

src/drivers/gfx/nvidia/acpi/common/dsm.asl

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define NV_ERROR_SUCCESS 0x0
+#define NV_ERROR_UNSPECIFIED 0x80000001
+#define NV_ERROR_UNSUPPORTED 0x80000002
+
+#include "gps.asl"
+#include "nvjt.asl"
+
+Method (_DSM, 4, Serialized) {
+	Printf("GPU _DSM")
+	If (Arg0 == ToUUID (JT_DSM_GUID)) {
+		If (ToInteger(Arg1) >= JT_REVISION_ID_MIN) {
+			Return (NVJT(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported JT revision: %o", SFST(Arg1))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	} ElseIf (Arg0 == ToUUID (GPS_DSM_GUID)) {
+		If (ToInteger(Arg1) == GPS_REVISION_ID) {
+			Return (GPS(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported GPS revision: %o", SFST(Arg1))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	} Else {
+		Printf("  Unsupported GUID: %o", IDST(Arg0))
+		Return (NV_ERROR_UNSPECIFIED)
+	}
+}

src/drivers/gfx/nvidia/acpi/common/gps.asl

@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define GPS_DSM_GUID "A3132D01-8CDA-49BA-A52E-BC9D46DF6B81"
+#define GPS_REVISION_ID 0x00000200
+#define GPS_FUNC_SUPPORT 0x00000000
+#define GPS_FUNC_PSHARESTATUS 0x00000020
+#define GPS_FUNC_PSHAREPARAMS 0x0000002A
+
+Method(GPS, 2, Serialized) {
+	Printf("  GPU GPS")
+	Switch(ToInteger(Arg0)) {
+		Case(GPS_FUNC_SUPPORT) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << GPS_FUNC_SUPPORT) |
+				(1 << GPS_FUNC_PSHARESTATUS) |
+				(1 << GPS_FUNC_PSHAREPARAMS)
+			))
+		}
+		Case(GPS_FUNC_PSHARESTATUS) {
+			Printf("    Power Share Status")
+			Return(ITOB(0))
+		}
+		Case(GPS_FUNC_PSHAREPARAMS) {
+			Printf("    Power Share Parameters")
+
+			CreateField(Arg1, 0, 4, QTYP) // Query type
+
+			Name(GPSP, Buffer(36) { 0x00 })
+			CreateDWordField(GPSP, 0, RSTS) // Response status
+			CreateDWordField(GPSP, 4, VERS) // Version
+
+			// Set query type of response
+			RSTS = QTYP
+			// Set version of response
+			VERS = 0x00010000
+
+			Switch(ToInteger(QTYP)) {
+				Case(0) {
+					Printf("      Request Current Information")
+					// No required information
+					Return(GPSP)
+				}
+				Case(1) {
+					Printf("      Request Supported Fields")
+					// Support GPU temperature field
+					RSTS |= (1 << 8)
+					Return(GPSP)
+				}
+				Case(2) {
+					Printf("      Request Current Limits")
+					// No required limits
+					Return(GPSP)
+				}
+				Default {
+					Printf("      Unknown Query: %o", SFST(QTYP))
+					Return(NV_ERROR_UNSUPPORTED)
+				}
+			}
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return(NV_ERROR_UNSUPPORTED)
+		}
+	}
+}

src/drivers/gfx/nvidia/acpi/common/gpu.asl

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (DEV0) {
+	Name(_ADR, 0x00000000)
+
+	#include "utility.asl"
+	#include "dsm.asl"
+	#include "power.asl"
+}
+
+#if CONFIG(DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST)
+Scope (\_SB) {
+	Device(NPCF) {
+		#include "utility.asl"
+		#include "nvpcf.asl"
+	}
+}
+#endif

src/drivers/gfx/nvidia/acpi/common/nvjt.asl

@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define JT_DSM_GUID "CBECA351-067B-4924-9CBD-B46B00B86F34"
+#define JT_REVISION_ID_MIN 0x00000100
+#define JT_REVISION_ID_MAX 0x00000200
+#define JT_FUNC_SUPPORT 0x00000000
+#define JT_FUNC_CAPS 0x00000001
+#define JT_FUNC_POWERCONTROL 0x00000003
+
+//TODO: SMI traps and EGIN/XCLM
+#define JT_GPC_GSS 0 // Get current GPU GCx sleep status
+#define JT_GPC_EGNS 1 // Enter GC6 without self-refresh
+#define JT_GPC_EGIS 2 // Enter GC6 with self-refresh
+#define JT_GPC_XGXS 3 // Exit GC6 and stop self-refresh
+#define JT_GPC_XGIS 4 // Exit GC6 for self-refresh update
+
+#define JT_DFGC_NONE 0 // Handle request immediately
+#define JT_DFGC_DEFER 1 // Defer GPC and GPCX
+//TODO #define JT_DFGC_CLEAR 2 // Clear pending requests
+
+// Deferred GC6 enter/exit until D3-cold (saved DFGC)
+Name(DFEN, 0)
+
+// Deferred GC6 enter control (saved GPC)
+Name(DFCI, 0)
+
+// Deferred GC6 exit control (saved GPCX)
+Name(DFCO, 0)
+
+Method (NVJT, 2, Serialized) {
+	Printf("  GPU NVJT")
+	Switch (ToInteger(Arg0)) {
+		Case (JT_FUNC_SUPPORT) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << JT_FUNC_SUPPORT) |
+				(1 << JT_FUNC_CAPS) |
+				(1 << JT_FUNC_POWERCONTROL)
+			))
+		}
+		Case (JT_FUNC_CAPS) {
+			Printf("    Capabilities")
+			Return(ITOB(
+				(1 << 0) | // G-SYNC NSVR power-saving features are enabled
+				(1 << 1) | // NVSR disabled
+				(2 << 3) | // Panel power and backlight are on the suspend rail
+				(0 << 5) | // self-refresh controller remains powered while panel is powered
+				(0 << 6) | // FB is not on the suspend rail but is powered on in GC6
+				(0 << 8) | // Combined power rail for all GPUs
+				(0 << 10) | // External SPI ROM
+				(1 << 11) | // No SMI handler for kernel panic exit while in GC6
+				(0 << 12) | // Supports notify on GC6 state done
+				(1 << 13) | // Support deferred GC6
+				(1 << 14) | // Support fine-grained root port control
+				(2 << 15) | // GC6 version is GC6-R
+				(0 << 17) | // GC6 exit ISR is not supported
+				(0 << 18) | // GC6 self wakeup not supported
+				(JT_REVISION_ID_MAX << 20) // Highest revision supported
+			))
+		}
+		Case (JT_FUNC_POWERCONTROL) {
+			Printf("    Power Control: %o", SFST(Arg1))
+
+			CreateField (Arg1, 0, 3, GPC) // GPU power control
+			CreateField (Arg1, 4, 1, PPC) // Panel power control
+			CreateField (Arg1, 14, 2, DFGC) // Defer GC6 enter/exit until D3 cold
+			CreateField (Arg1, 16, 3, GPCX) // Deferred GC6 exit control
+
+			// Save deferred GC6 request
+			If ((ToInteger(GPC) != 0) || (ToInteger(DFGC) != 0)) {
+				DFEN = DFGC
+				DFCI = GPC
+				DFCO = GPCX
+			}
+
+			// Buffer to cache current state
+			Name (JTBF, Buffer (4) { 0, 0, 0, 0 })
+			CreateField (JTBF, 0, 3, CGCS) // Current GC state
+			CreateField (JTBF, 3, 1, CGPS) // Current GPU power status
+			CreateField (JTBF, 7, 1, CPSS) // Current panel and SRC state (0 when on)
+
+			// If doing deferred GC6 request, return now
+			If (ToInteger(DFGC) != 0) {
+				CGCS = 1
+				CGPS = 1
+				Return (JTBF)
+			}
+
+			// Apply requested state
+			Switch (ToInteger(GPC)) {
+				Case (JT_GPC_GSS) {
+					Printf("    Get current GPU GCx sleep status")
+					//TODO: include transitions!
+					If (GTXS(DGPU_RST_N)) {
+						// GPU powered on
+						CGCS = 1
+						CGPS = 1
+					} ElseIf (GTXS(DGPU_PWR_EN)) {
+						// GPU powered off, GC6
+						CGCS = 3
+						CGPS = 0
+					} Else {
+						// GPU powered off, D3 cold
+						CGCS = 2
+						CGPS = 0
+					}
+				}
+				Case (JT_GPC_EGNS) {
+					Printf("    Enter GC6 without self-refresh")
+					GC6I()
+					CPSS = 1
+				}
+				Case (JT_GPC_EGIS) {
+					Printf("    Enter GC6 with self-refresh")
+					GC6I()
+					If (ToInteger(PPC) == 0) {
+						CPSS = 0
+					}
+				}
+				Case (JT_GPC_XGXS) {
+					Printf("    Exit GC6 and stop self-refresh")
+					GC6O()
+
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger(PPC) != 0) {
+						CPSS = 0
+					}
+				}
+				Case (JT_GPC_XGIS) {
+					Printf("    Exit GC6 for self-refresh update")
+					GC6O()
+
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger(PPC) != 0) {
+						CPSS = 0
+					}
+				}
+				Default {
+					Printf("    Unsupported GPU power control: %o", SFST(GPC))
+				}
+			}
+
+			Return (JTBF)
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	}
+}

src/drivers/gfx/nvidia/acpi/common/nvpcf.asl

@@ -0,0 +1,111 @@
+#define NVPCF_DSM_GUID "36b49710-2483-11e7-9598-0800200c9a66"
+#define NVPCF_REVISION_ID 0x00000200
+#define NVPCF_ERROR_SUCCESS 0x0
+#define NVPCF_ERROR_GENERIC 0x80000001
+#define NVPCF_ERROR_UNSUPPORTED 0x80000002
+#define NVPCF_FUNC_GET_SUPPORTED 0x00000000
+#define NVPCF_FUNC_GET_STATIC_CONFIG_TABLES 0x00000001
+#define NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS 0x00000002
+
+Name(_HID, "NVDA0820")
+
+Name(_UID, "NPCF")
+
+Method(_DSM, 4, Serialized) {
+	Printf("NVPCF _DSM")
+	If (Arg0 == ToUUID(NVPCF_DSM_GUID)) {
+		If (ToInteger(Arg1) == NVPCF_REVISION_ID) {
+			Return(NPCF(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported NVPCF revision: %o", SFST(Arg1))
+			Return(NVPCF_ERROR_GENERIC)
+		}
+	} Else {
+		Printf("  Unsupported GUID: %o", IDST(Arg0))
+		Return(NVPCF_ERROR_GENERIC)
+	}
+}
+
+Method(NPCF, 2, Serialized) {
+	Printf("  NVPCF NPCF")
+	Switch(ToInteger(Arg0)) {
+		Case(NVPCF_FUNC_GET_SUPPORTED) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << NVPCF_FUNC_GET_SUPPORTED) |
+				(1 << NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) |
+				(1 << NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS)
+			))
+		}
+		Case(NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) {
+			Printf("    Get Static Config")
+			Return(Buffer(14) {
+				// Device table header
+				0x20, 0x03, 0x01,
+				// Intel + NVIDIA
+				0x00,
+				// Controller table header
+				0x23, 0x04, 0x05, 0x01,
+				// Dynamic boost controller
+				0x01,
+				// Supports DC
+				0x01,
+				// Reserved
+				0x00, 0x00, 0x00,
+				// Checksum
+				0xAD
+			})
+		}
+		Case(NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS) {
+			Printf("    Update Dynamic Boost")
+
+			CreateField(Arg1, 0x28, 2, ICMD) // Input command
+
+			Name(PCFP, Buffer(49) {
+				// Table version
+				0x23,
+				// Table header size
+				0x05,
+				// Size of common status in bytes
+				0x10,
+				// Size of controller entry in bytes
+				0x1C,
+				// Other fields filled in later
+			})
+			CreateByteField(PCFP, 0x04, CCNT) // Controller count
+			CreateWordField(PCFP, 0x19, ATPP) // AC TPP offset
+			CreateWordField(PCFP, 0x1D, AMXP) // AC maximum TGP offset
+			CreateWordField(PCFP, 0x21, AMNP) // AC minimum TGP offset
+
+			Switch(ToInteger(ICMD)) {
+				Case(0) {
+					Printf("      Get Controller Params")
+					// Number of controllers
+					CCNT = 1
+					// AC total processor power offset from default TGP in 1/8 watt units
+					ATPP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP << 3)
+					// AC maximum TGP offset from default TGP in 1/8 watt units
+					AMXP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX << 3)
+					// AC minimum TGP offset from default TGP in 1/8 watt units
+					AMNP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN << 3)
+					Printf("PCFP: %o", SFST(PCFP))
+					Return(PCFP)
+				}
+				Case(1) {
+					Printf("      Set Controller Status")
+					//TODO
+					Printf("PCFP: %o", SFST(PCFP))
+					Return(PCFP)
+				}
+				Default {
+					Printf("      Unknown Input Command: %o", SFST(ICMD))
+					Return(NV_ERROR_UNSUPPORTED)
+				}
+			}
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return(NVPCF_ERROR_UNSUPPORTED)
+		}
+	}
+}

src/drivers/gfx/nvidia/acpi/common/power.asl

@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+//TODO: evaluate sleeps
+
+OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
+Field (PCIC, DwordAcc, NoLock, Preserve) {
+	Offset (0x40),
+	SSID, 32, // Subsystem vendor and product ID
+}
+
+// Enter GC6
+Method(GC6I, 0, Serialized) {
+	Printf("    GPU GC6I START")
+
+	// Enter L23
+	^^DL23()
+	Sleep(5)
+
+	// Put GPU into reset
+	Printf("      Put GPU into reset")
+	CTXS(DGPU_RST_N)
+	Sleep(5)
+
+	Printf("    GPU GC6I FINISH")
+}
+
+// Exit GC6
+Method(GC6O, 0, Serialized) {
+	Printf("    GPU GC6O START")
+
+	// Bring GPU out of reset
+	Printf("      Bring GPU out of reset")
+	STXS(DGPU_RST_N)
+	Sleep(5)
+
+	// Exit L23
+	^^L23D()
+	Sleep(5)
+
+	Printf("    GPU GC6O FINISH")
+}
+
+Method (_ON, 0, Serialized) {
+	Printf("  GPU _ON START")
+
+	If (DFEN == JT_DFGC_DEFER) {
+		Switch (ToInteger(DFCO)) {
+			Case (JT_GPC_XGXS) {
+				Printf("    Exit GC6 and stop self-refresh")
+				GC6O()
+			}
+			Default {
+				Printf("    Unsupported DFCO: %o", SFST(DFCO))
+			}
+		}
+		DFEN = JT_DFGC_NONE
+	} Else {
+		Printf("    Standard RTD3 power on")
+		STXS(DGPU_PWR_EN)
+		Sleep(5)
+		GC6O()
+	}
+
+	Printf("  GPU _ON FINISH")
+}
+
+Method (_OFF, 0, Serialized) {
+	Printf("  GPU _OFF START")
+
+	If (DFEN == JT_DFGC_DEFER) {
+		Switch (ToInteger(DFCI)) {
+			Case (JT_GPC_EGNS) {
+				Printf("    Enter GC6 without self-refresh")
+				GC6I()
+			}
+			Case (JT_GPC_EGIS) {
+				Printf("    Enter GC6 with self-refresh")
+				GC6I()
+			}
+			Default {
+				Printf("    Unsupported DFCI: %o", SFST(DFCI))
+			}
+		}
+		DFEN = JT_DFGC_NONE
+	} Else {
+		Printf("    Standard RTD3 power off")
+		GC6I()
+		CTXS(DGPU_PWR_EN)
+		Sleep(5)
+	}
+
+	Printf("  GPU _OFF FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PWRR._ON")
+
+		// Restore SSID
+		^^SSID = DGPU_SSID
+		Printf("  Restore SSID: %o", SFST(^^SSID))
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PWRR._OFF")
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })

src/drivers/gfx/nvidia/acpi/common/utility.asl

@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Convert a byte to a hex string, trimming extra parts
+Method (BHEX, 1) {
+	Local0 = ToHexString(Arg0)
+	Return (Mid(Local0, SizeOf(Local0) - 2, 2))
+}
+
+// UUID to string
+Method (IDST, 1) {
+	Local0 = ""
+	Fprintf(
+		Local0,
+		"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
+		BHEX(DerefOf(Arg0[3])),
+		BHEX(DerefOf(Arg0[2])),
+		BHEX(DerefOf(Arg0[1])),
+		BHEX(DerefOf(Arg0[0])),
+		BHEX(DerefOf(Arg0[5])),
+		BHEX(DerefOf(Arg0[4])),
+		BHEX(DerefOf(Arg0[7])),
+		BHEX(DerefOf(Arg0[6])),
+		BHEX(DerefOf(Arg0[8])),
+		BHEX(DerefOf(Arg0[9])),
+		BHEX(DerefOf(Arg0[10])),
+		BHEX(DerefOf(Arg0[11])),
+		BHEX(DerefOf(Arg0[12])),
+		BHEX(DerefOf(Arg0[13])),
+		BHEX(DerefOf(Arg0[14])),
+		BHEX(DerefOf(Arg0[15]))
+	)
+	Return (Local0)
+}
+
+// Safe hex conversion, checks type first
+Method (SFST, 1) {
+	Local0 = ObjectType(Arg0)
+	If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
+		Return (ToHexString(Arg0))
+	} Else {
+		Return (Concatenate("Type: ", Arg0))
+	}
+}
+
+// Convert from 4-byte buffer to 32-bit integer
+Method (BTOI, 1) {
+	Return(
+		DerefOf(Arg0[0]) |
+		(DerefOf(Arg0[1]) << 8) |
+		(DerefOf(Arg0[2]) << 16) |
+		(DerefOf(Arg0[3]) << 24)
+	)
+}
+
+// Convert from 32-bit integer to 4-byte buffer
+Method (ITOB, 1) {
+	Local0 = Buffer(4) { 0, 0, 0, 0 }
+	Local0[0] = Arg0 & 0xFF
+	Local0[1] = (Arg0 >> 8) & 0xFF
+	Local0[2] = (Arg0 >> 16) & 0xFF
+	Local0[3] = (Arg0 >> 24) & 0xFF
+	Return (Local0)
+}

src/drivers/gfx/nvidia/acpi/tigerlake.asl

@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* NVIDIA GC6 on (TGL and ADL) (CPU and PCH) PCIe ports */
+
+// Port mapped PCI express config space
+OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
+
+Field (PCIC, AnyAcc, NoLock, Preserve) {
+	Offset(0x52),  /* LSTS - Link Status Register */
+	, 13,
+	LASX, 1,       /* 0, Link Active Status */
+
+	Offset(0x60),  /* RSTS - Root Status Register */
+	, 16,
+	PSPX, 1,       /* 16,  PME Status */
+
+	Offset(0xD8),  /* 0xD8, MPC - Miscellaneous Port Configuration Register */
+	, 30,
+	HPEX, 1,       /* 30,  Hot Plug SCI Enable */
+	PMEX, 1,       /* 31,  Power Management SCI Enable */
+
+	Offset (0xE0), /* 0xE0, SPR - Scratch Pad Register */
+	SCB0, 1,       /* Scratch bit 0 */
+
+	Offset(0xE2),  /* 0xE2, RPPGEN - Root Port Power Gating Enable */
+	, 2,
+	L23E, 1,       /* 2,   L23_Rdy Entry Request (L23ER) */
+	L23R, 1,       /* 3,   L23_Rdy to Detect Transition (L23R2DT) */
+}
+
+Field (PCIC, AnyAcc, NoLock, WriteAsZeros) {
+	Offset(0xDC),  /* 0xDC, SMSCS - SMI/SCI Status Register */
+	, 30,
+	HPSX, 1,       /* 30,  Hot Plug SCI Status */
+	PMSX, 1        /* 31,  Power Management SCI Status */
+}
+
+// Enter L23
+Method (DL23, 0, Serialized) {
+	Printf("      GPU PORT DL23 START")
+
+	L23E = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23E) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+	SCB0 = 1
+
+	Printf("      GPU PORT DL23 FINISH")
+}
+
+// Exit L23
+Method (L23D, 0, Serialized) {
+	Printf("      GPU PORT L23D START")
+
+	If ((SCB0 == 1)) {
+		L23R = 1
+		Local0 = 0
+		While (L23R) {
+			If ((Local0 > 4)) {
+				Break
+			}
+			Sleep (16)
+			Local0++
+		}
+
+		SCB0 = 0
+		Local0 = 0
+		While ((LASX == 0)) {
+			If ((Local0 > 8)) {
+				Break
+			}
+			Sleep (16)
+			Local0++
+		}
+	}
+
+	Printf("      GPU PORT L23D FINISH")
+}
+
+Method (HPME, 0, Serialized) {
+	Printf("  GPU PORT HPME START")
+
+	If (PMSX == 1) {
+		Printf("    Notify GPU driver of PME SCI")
+		Notify(DEV0, 0x2)
+		Printf("    Clear PME SCI")
+		PMSX = 1
+		Printf("    Consume PME notification")
+		PSPX = 1
+	}
+
+	Printf("  GPU PORT HPME FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PORT PWRR._ON")
+
+		HPME();
+		If (PMEX == 1) {
+			Printf("  Disable power management SCI")
+			PMEX = 0
+		}
+
+		^^DEV0._ON()
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PORT PWRR._OFF")
+
+		^^DEV0._OFF()
+
+		If (PMEX == 0) {
+			Printf("  Enable power management SCI")
+			PMEX = 1
+			HPME()
+		}
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
+
+#include "common/gpu.asl"

src/drivers/gfx/nvidia/chip.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_
+#define _DRIVERS_GFX_NVIDIA_CHIP_H_
+
+struct drivers_gfx_nvidia_config {
+	/* TODO: Set GPIOs in devicetree? */
+};
+
+#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */

src/drivers/gfx/nvidia/gpu.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_
+#define _DRIVERS_GFX_NVIDIA_GPU_H_
+
+#include <stdbool.h>
+
+struct nvidia_gpu_config {
+	/* GPIO for GPU_PWR_EN */
+	unsigned int power_gpio;
+	/* GPIO for GPU_RST# */
+	unsigned int reset_gpio;
+	/* Enable or disable GPU power */
+	bool enable;
+};
+
+void nvidia_set_power(const struct nvidia_gpu_config *config);
+
+#endif /* _DRIVERS_NVIDIA_GPU_H_ */

src/drivers/gfx/nvidia/nvidia.c

@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40
+
+static void nvidia_read_resources(struct device *dev)
+{
+	printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev));
+
+	pci_dev_read_resources(dev);
+
+	// Find all BARs on GPU, mark them above 4g if prefetchable
+	for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
+		struct resource *res = probe_resource(dev, bar);
+
+		if (res) {
+			if (res->flags & IORESOURCE_PREFETCH) {
+				printk(BIOS_INFO, "  BAR at 0x%02x marked above 4g\n", bar);
+				res->flags |= IORESOURCE_ABOVE_4G;
+			} else {
+				printk(BIOS_DEBUG, "  BAR at 0x%02x not prefetch\n", bar);
+			}
+		} else {
+			printk(BIOS_DEBUG, "  BAR at 0x%02x not found\n", bar);
+		}
+	}
+}
+
+static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
+{
+	pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations nvidia_device_ops_pci = {
+	.set_subsystem = nvidia_set_subsystem,
+};
+
+static struct device_operations nvidia_device_ops = {
+	.read_resources   = nvidia_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.write_acpi_tables = pci_rom_write_acpi_tables,
+	.acpi_fill_ssdt    = pci_rom_ssdt,
+#endif
+	.init             = pci_dev_init,
+	.ops_pci          = &nvidia_device_ops_pci,
+
+};
+
+static void nvidia_enable(struct device *dev)
+{
+	if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
+		return;
+
+	if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_NVIDIA)
+		return;
+
+	dev->ops = &nvidia_device_ops;
+}
+
+struct chip_operations drivers_gfx_nvidia_ops = {
+	CHIP_NAME("NVIDIA Optimus Graphics Device")
+	.enable_dev = nvidia_enable
+};

src/drivers/gfx/nvidia/romstage.c

@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <gpio.h>
+#include "chip.h"
+#include "gpu.h"
+
+void nvidia_set_power(const struct nvidia_gpu_config *config)
+{
+	if (!config->power_gpio || !config->reset_gpio) {
+		printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__);
+		return;
+	}
+
+	printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio);
+	printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio);
+
+	gpio_set(config->reset_gpio, 0);
+	mdelay(10);
+
+	if (config->enable) {
+		gpio_set(config->power_gpio, 1);
+		mdelay(25);
+		gpio_set(config->reset_gpio, 1);
+	} else {
+		gpio_set(config->power_gpio, 0);
+	}
+
+	mdelay(10);
+}

src/drivers/intel/dtbt/Kconfig

@@ -0,0 +1,5 @@
+config DRIVERS_INTEL_DTBT
+	bool
+	default n
+	help
+	  Support for discrete Thunderbolt controllers

src/drivers/intel/dtbt/Makefile.inc

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_DRIVERS_INTEL_DTBT) += dtbt.c

src/drivers/intel/dtbt/chip.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_INTEL_DTBT_CHIP_H_
+#define _DRIVERS_INTEL_DTBT_CHIP_H_
+
+struct drivers_intel_dtbt_config {};
+
+#endif /* _DRIVERS_INTEL_DTBT_CHIP_H_ */

src/drivers/intel/dtbt/dtbt.c

@@ -0,0 +1,212 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include <acpi/acpigen.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include <device/pci_ids.h>
+
+#define PCIE2TBT 0x54C
+#define PCIE2TBT_GO2SX ((0x02 << 1) | 1)
+#define PCIE2TBT_GO2SX_NO_WAKE ((0x03 << 1) | 1)
+#define PCIE2TBT_SX_EXIT_TBT_CONNECTED ((0x04 << 1) | 1)
+#define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED ((0x05 << 1) | 1)
+#define PCIE2TBT_SET_SECURITY_LEVEL ((0x08 << 1) | 1)
+#define PCIE2TBT_GET_SECURITY_LEVEL ((0x09 << 1) | 1)
+#define PCIE2TBT_BOOT_ON ((0x18 << 1) | 1)
+#define TBT2PCIE 0x548
+
+static void dtbt_cmd(struct device *dev, u32 command) {
+	printk(BIOS_INFO, "DTBT send command %08x\n", command);
+
+	pci_write_config32(dev, PCIE2TBT, command);
+
+	u32 timeout;
+	u32 status;
+	for (timeout = 1000000; timeout > 0; timeout--) {
+		status = pci_read_config32(dev, TBT2PCIE);
+		if (status & 1) {
+			break;
+		}
+		udelay(1);
+	}
+	if (timeout == 0) {
+		printk(BIOS_ERR, "DTBT command %08x timeout on status %08x\n", command, status);
+	}
+
+	printk(BIOS_INFO, "DTBT command %08x status %08x\n", command, status);
+
+	pci_write_config32(dev, PCIE2TBT, 0);
+
+	u32 status_clear;
+	for (timeout = 1000000; timeout > 0; timeout--) {
+		status_clear = pci_read_config32(dev, TBT2PCIE);
+		if (!(status_clear & 1)) {
+			break;
+		}
+		udelay(1);
+	}
+	if (timeout == 0) {
+		printk(BIOS_ERR, "DTBT command %08x timeout on status clear %08x\n", command, status_clear);
+	}
+}
+
+static void dtbt_fill_ssdt(const struct device *dev) {
+	printk(BIOS_INFO, "DTBT fill SSDT\n");
+
+	if (!dev) {
+		printk(BIOS_ERR, "DTBT device invalid\n");
+	}
+	printk(BIOS_INFO, "  Dev %s\n", dev_path(dev));
+
+	struct bus *bus = dev->bus;
+	if (!bus) {
+		printk(BIOS_ERR, "DTBT bus invalid\n");
+	}
+	printk(BIOS_INFO, "  Bus %s\n", bus_path(bus));
+
+	struct device *parent = bus->dev;
+	if (!parent || parent->path.type != DEVICE_PATH_PCI) {
+		printk(BIOS_ERR, "DTBT parent invalid\n");
+		return;
+	}
+	printk(BIOS_INFO, "  Parent %s\n", dev_path(parent));
+
+	const char *parent_scope = acpi_device_path(parent);
+	if (!parent_scope) {
+		printk(BIOS_ERR, "DTBT parent scope not valid\n");
+		return;
+	}
+
+	{ /* Scope */
+		printk(BIOS_INFO, "  Scope %s\n", parent_scope);
+		acpigen_write_scope(parent_scope);
+
+		struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
+
+		/* Indicate that device supports hotplug in D3. */
+		acpi_device_add_hotplug_support_in_d3(dsd);
+
+		/* Indicate that port is external. */
+		acpi_device_add_external_facing_port(dsd);
+
+		acpi_dp_write(dsd);
+
+		{ /* Device */
+			const char *dev_name = acpi_device_name(dev);
+			printk(BIOS_INFO, "    Device %s\n", dev_name);
+			acpigen_write_device(dev_name);
+
+			acpigen_write_name_integer("_ADR", 0);
+
+			uintptr_t mmconf_base = (uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS
+			                      + (((uintptr_t)(bus->secondary)) << 20);
+			printk(BIOS_INFO, "      MMCONF base %08lx\n", mmconf_base);
+			const struct opregion opregion = OPREGION("PXCS", SYSTEMMEMORY, mmconf_base, 0x1000);
+			const struct fieldlist fieldlist[] = {
+				FIELDLIST_OFFSET(TBT2PCIE),
+				FIELDLIST_NAMESTR("TB2P", 32),
+				FIELDLIST_OFFSET(PCIE2TBT),
+				FIELDLIST_NAMESTR("P2TB", 32),
+			};
+			acpigen_write_opregion(&opregion);
+			acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist),
+					    FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE);
+
+			{ /* Method */
+				acpigen_write_method_serialized("PTS", 0);
+
+				acpigen_write_debug_string("DTBT prepare to sleep");
+
+				acpigen_write_store_int_to_namestr(PCIE2TBT_GO2SX_NO_WAKE, "P2TB");
+				acpigen_write_delay_until_namestr_int(600, "TB2P", PCIE2TBT_GO2SX_NO_WAKE);
+
+				acpigen_write_debug_namestr("TB2P");
+
+				acpigen_write_store_int_to_namestr(0, "P2TB");
+				acpigen_write_delay_until_namestr_int(600, "TB2P", 0);
+
+				acpigen_write_debug_namestr("TB2P");
+
+				acpigen_write_method_end();
+			}
+
+			acpigen_write_device_end();
+		}
+
+		acpigen_write_scope_end();
+	}
+
+	{ /* Scope */
+		acpigen_write_scope("\\");
+
+		{ /* Method */
+			acpigen_write_method("TBTS", 0);
+
+			acpigen_emit_namestring(acpi_device_path_join(dev, "PTS"));
+
+			acpigen_write_method_end();
+		}
+
+		acpigen_write_scope_end();
+	}
+}
+
+static const char *dtbt_acpi_name(const struct device *dev) {
+	return "DTBT";
+}
+
+static struct pci_operations dtbt_device_ops_pci = {
+	.set_subsystem = 0,
+};
+
+static struct device_operations dtbt_device_ops = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.acpi_fill_ssdt   = dtbt_fill_ssdt,
+	.acpi_name 		  = dtbt_acpi_name,
+	.scan_bus         = pciexp_scan_bridge,
+	.reset_bus        = pci_bus_reset,
+	.ops_pci          = &dtbt_device_ops_pci,
+};
+
+static void dtbt_enable(struct device *dev)
+{
+	if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
+		return;
+
+	if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_INTEL)
+		return;
+
+	//TODO: check device ID
+
+	dev->ops = &dtbt_device_ops;
+
+	printk(BIOS_INFO, "DTBT controller found at %s\n", dev_path(dev));
+
+	printk(BIOS_INFO, "DTBT get security level\n");
+	dtbt_cmd(dev, PCIE2TBT_GET_SECURITY_LEVEL);
+
+	printk(BIOS_INFO, "DTBT set security level SL0\n");
+	dtbt_cmd(dev, PCIE2TBT_SET_SECURITY_LEVEL);
+
+	printk(BIOS_INFO, "DTBT get security level\n");
+	dtbt_cmd(dev, PCIE2TBT_GET_SECURITY_LEVEL);
+
+	if (acpi_is_wakeup_s3()) {
+		printk(BIOS_INFO, "DTBT SX exit\n");
+		dtbt_cmd(dev, PCIE2TBT_SX_EXIT_TBT_CONNECTED);
+	} else {
+		printk(BIOS_INFO, "DTBT boot on\n");
+		dtbt_cmd(dev, PCIE2TBT_BOOT_ON);
+	}
+}
+
+struct chip_operations drivers_intel_dtbt_ops = {
+	CHIP_NAME("Intel Discrete Thunderbolt Device")
+	.enable_dev = dtbt_enable
+};

src/drivers/intel/gma/hires_fb/gma-gfx_init.adb

@@ -102,7 +102,7 @@ is
       success : boolean;
    begin
       HW.GFX.GMA.Initialize (Clean_State => True,
-      			     Success => success);
+			     Success => success);
       if success then
          stop_ok := 1;
       else

src/drivers/intel/gma/text_fb/gma-gfx_init.adb

@@ -61,7 +61,7 @@ is
       success : boolean;
    begin
       HW.GFX.GMA.Initialize (Clean_State => True,
-      			     Success => success);
+			     Success => success);
       if success then
          stop_ok := 1;
       else

src/drivers/mrc_cache/mrc_cache.c

@@ -25,7 +25,7 @@
 /* Signature "MRCD" was used for older header format before CB:67670. */
 #define MRC_DATA_SIGNATURE       (('M'<<0)|('R'<<8)|('C'<<16)|('d'<<24))
 
-const static uint32_t mrc_invalid_sig = ~MRC_DATA_SIGNATURE;
+static const uint32_t mrc_invalid_sig = ~MRC_DATA_SIGNATURE;
 
 struct mrc_metadata {
 	uint32_t signature;

src/drivers/pc80/tpm/tis.c

@@ -114,6 +114,7 @@ static const struct device_name infineon_devices[] = {
 #if CONFIG(TPM2)
 	{0x001a, "SLB9665 TT 2.0"},
 	{0x001b, "SLB9670 TT 2.0"},
+	{0x001d, "SLB9672 TT 2.0"},
 #else
 	{0x001a, "SLB9660 TT 1.2"},
 	{0x001b, "SLB9670 TT 1.2"},

src/drivers/smmstore/ramstage.c

@@ -57,18 +57,22 @@ static void init_store(void *unused)
 
 	printk(BIOS_INFO, "SMMSTORE: Setting up SMI handler\n");
 
-	/* Issue SMI using APM to update the com buffer and to lock the SMMSTORE */
-	__asm__ __volatile__ (
-		"outb %%al, %%dx"
-		: "=a" (eax)
-		: "a" ((SMMSTORE_CMD_INIT << 8) | APM_CNT_SMMSTORE),
-		  "b" (ebx),
-		  "d" (APM_CNT)
-		: "memory");
+	for (int retries = 0; retries < 3; retries++) {
+		/* Issue SMI using APM to update the com buffer and to lock the SMMSTORE */
+		__asm__ __volatile__ (
+			"outb %%al, %%dx"
+			: "=a" (eax)
+			: "a" ((SMMSTORE_CMD_INIT << 8) | APM_CNT_SMMSTORE),
+			  "b" (ebx),
+			  "d" (APM_CNT)
+			: "memory");
 
-	if (eax != SMMSTORE_RET_SUCCESS) {
-		printk(BIOS_ERR, "SMMSTORE: Failed to install com buffer\n");
-		return;
+		if (eax == SMMSTORE_RET_SUCCESS) {
+			printk(BIOS_INFO, "SMMSTORE: Installed com buffer\n");
+			break;
+		}
+
+		printk(BIOS_ERR, "SMMSTORE: Failed to install com buffer: 0x%x\n", eax);
 	}
 }
 

src/drivers/usb/acpi/chip.h

@@ -72,6 +72,12 @@ struct drivers_usb_acpi_config {
 	 * will always return ON.
 	 */
 	bool use_gpio_for_status;
+
+	/*
+	 * Generate _DSM method Function 5 to disable USB U1/U2 transition
+	 * for a port
+	 */
+	bool usb_lpm_incapable;
 };
 
 /* Method to get PLD structure from USB device */

src/drivers/usb/acpi/usb_acpi.c

@@ -3,6 +3,7 @@
 #include <acpi/acpi_device.h>
 #include <acpi/acpi_pld.h>
 #include <acpi/acpigen.h>
+#include <acpi/acpigen_dsm.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/path.h>
@@ -38,6 +39,7 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev)
 	struct drivers_usb_acpi_config *config = dev->chip_info;
 	const char *path = acpi_device_path(dev);
 	struct acpi_pld pld;
+	struct dsm_usb_config usb_cfg;
 
 	if (!path || !config)
 		return;
@@ -56,6 +58,11 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev)
 	else
 		printk(BIOS_ERR, "Error retrieving PLD for %s\n", path);
 
+	if (config->usb_lpm_incapable) {
+		usb_cfg.usb_lpm_incapable = 1;
+		acpigen_write_dsm_usb(&usb_cfg);
+	}
+
 	/* Resources */
 	if (usb_acpi_add_gpios_to_crs(config) == true) {
 		struct acpi_dp *dsd;

src/ec/system76/ec/Kconfig

@@ -8,12 +8,12 @@ config EC_SYSTEM76_EC_BAT_THRESHOLDS
 	bool
 	default y
 
-config EC_SYSTEM76_EC_COLOR_KEYBOARD
+config EC_SYSTEM76_EC_DGPU
 	depends on EC_SYSTEM76_EC
 	bool
 	default n
 
-config EC_SYSTEM76_EC_DGPU
+config EC_SYSTEM76_EC_LOCKDOWN
 	depends on EC_SYSTEM76_EC
 	bool
 	default n

src/ec/system76/ec/Makefile.inc

@@ -2,6 +2,7 @@
 ifeq ($(CONFIG_EC_SYSTEM76_EC),y)
 
 all-y += system76_ec.c
+ramstage-$(CONFIG_EC_SYSTEM76_EC_LOCKDOWN) += lockdown.c
 smm-$(CONFIG_DEBUG_SMI) += system76_ec.c
 
 endif

src/ec/system76/ec/acpi/ec.asl

@@ -90,9 +90,6 @@ Device (\_SB.PCI0.LPCB.EC0)
 			// Notify of changes
 			Notify(^^^^AC, 0)
 			Notify(^^^^BAT0, 0)
-
-			// Reset System76 Device
-			^^^^S76D.RSET()
 		}
 	}
 

src/ec/system76/ec/acpi/s76.asl

@@ -16,10 +16,8 @@ Device (S76D) {
 	Method (RSET, 0, Serialized) {
 		Printf ("S76D: RSET")
 		SAPL(0)
-		SKBL(0)
-#if CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD)
-			SKBC(0xFFFFFF)
-#endif // CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD)
+		SKBB(0)
+		SKBC(0xFFFFFF)
 	}
 
 	Method (INIT, 0, Serialized) {
@@ -67,53 +65,63 @@ Device (S76D) {
 		}
 	}
 
-#if CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD)
-	// Set KB LED Brightness
-	Method (SKBL, 1, Serialized) {
+	// Get Keyboard Backlight Kind
+	// 0 - No backlight
+	// 1 - White backlight
+	// 2 - RGB backlight
+	Method (GKBK, 0, Serialized) {
+		Local0 = 0
 		If (^^PCI0.LPCB.EC0.ECOK) {
-			^^PCI0.LPCB.EC0.FDAT = 6
-			^^PCI0.LPCB.EC0.FBUF = Arg0
-			^^PCI0.LPCB.EC0.FBF1 = 0
-			^^PCI0.LPCB.EC0.FBF2 = Arg0
+			^^PCI0.LPCB.EC0.FDAT = 2
 			^^PCI0.LPCB.EC0.FCMD = 0xCA
+			Local0 = ^^PCI0.LPCB.EC0.FBUF
 		}
+		Return (Local0)
 	}
 
-	// Set Keyboard Color
-	Method (SKBC, 1, Serialized) {
-		If (^^PCI0.LPCB.EC0.ECOK) {
-			^^PCI0.LPCB.EC0.FDAT = 0x3
-			^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF)
-			^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF)
-			^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF)
-			^^PCI0.LPCB.EC0.FCMD = 0xCA
-			Return (Arg0)
-		} Else {
-			Return (0)
-		}
-	}
-#else // CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD)
-	// Get KB LED
-	Method (GKBL, 0, Serialized) {
+	// Get Keyboard Brightness
+	Method (GKBB, 0, Serialized) {
 		Local0 = 0
 		If (^^PCI0.LPCB.EC0.ECOK) {
 			^^PCI0.LPCB.EC0.FDAT = 1
 			^^PCI0.LPCB.EC0.FCMD = 0xCA
 			Local0 = ^^PCI0.LPCB.EC0.FBUF
-			^^PCI0.LPCB.EC0.FCMD = 0
 		}
 		Return (Local0)
 	}
 
-	// Set KB Led
-	Method (SKBL, 1, Serialized) {
+	// Set Keyboard Brightness
+	Method (SKBB, 1, Serialized) {
 		If (^^PCI0.LPCB.EC0.ECOK) {
 			^^PCI0.LPCB.EC0.FDAT = 0
 			^^PCI0.LPCB.EC0.FBUF = Arg0
 			^^PCI0.LPCB.EC0.FCMD = 0xCA
 		}
 	}
-#endif // CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD)
+
+	// Get Keyboard Color
+	Method (GKBC, 0, Serialized) {
+		Local0 = 0
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = 4
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+			Local0 = ^^PCI0.LPCB.EC0.FBUF
+			Local0 |= (^^PCI0.LPCB.EC0.FBF1) << 16
+			Local0 |= (^^PCI0.LPCB.EC0.FBF2) << 8
+		}
+		Return (Local0)
+	}
+
+	// Set Keyboard Color
+	Method (SKBC, 1, Serialized) {
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = 3
+			^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF)
+			^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF)
+			^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF)
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+		}
+	}
 
 	// Fan names
 	Method (NFAN, 0, Serialized) {

src/ec/system76/ec/lockdown.c

@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <commonlib/region.h>
+#include <fmap.h>
+#include <spi_flash.h>
+
+#include "system76_ec.h"
+
+static int protect_region_by_name(const char *name)
+{
+	int res;
+	struct region region;
+
+	res = fmap_locate_area(name, &region);
+	if (res < 0) {
+		printk(BIOS_ERR, "fmap_locate_area '%s' failed: %d\n", name, res);
+		return res;
+	}
+
+	res = spi_flash_ctrlr_protect_region(
+		boot_device_spi_flash(),
+		&region,
+		WRITE_PROTECT
+	);
+	if (res < 0) {
+		printk(BIOS_ERR, "spi_flash_ctrlr_protect_region '%s' failed: %d\n", name, res);
+		return res;
+	}
+
+	printk(BIOS_INFO, "protected '%s'\n", name);
+	return 0;
+}
+
+static void lock(void *unused)
+{
+	uint8_t state = SYSTEM76_EC_SECURITY_STATE_UNLOCK;
+	if (system76_ec_security_get(&state) < 0) {
+		printk(BIOS_INFO, "failed to get security state, assuming unlocked\n");
+		state = SYSTEM76_EC_SECURITY_STATE_UNLOCK;
+	}
+
+	printk(BIOS_INFO, "security state: %d\n", state);
+	if (state != SYSTEM76_EC_SECURITY_STATE_UNLOCK) {
+		// Protect WP_RO region, which should contain FMAP and COREBOOT
+		protect_region_by_name("WP_RO");
+		// Protect RW_MRC_CACHE region, this must be done after it is written
+		protect_region_by_name("RW_MRC_CACHE");
+		//TODO: protect entire flash except when in SMM?
+	}
+}
+
+/*
+ * Keep in sync with mrc_cache.c
+ */
+
+#if CONFIG(MRC_WRITE_NV_LATE)
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, lock, NULL);
+#else
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, lock, NULL);
+#endif

src/ec/system76/ec/system76_ec.c

@@ -3,6 +3,7 @@
 #include <arch/io.h>
 #include <console/system76_ec.h>
 #include <timer.h>
+#include "system76_ec.h"
 
 // This is the command region for System76 EC firmware. It must be
 // enabled for LPC in the mainboard.
@@ -11,15 +12,22 @@
 
 #define REG_CMD 0
 #define REG_RESULT 1
+#define REG_DATA 2
 
 // When command register is 0, command is complete
 #define CMD_FINISHED 0
 
 // Print command. Registers are unique for each command
 #define CMD_PRINT 4
-#define CMD_PRINT_REG_FLAGS 2
-#define CMD_PRINT_REG_LEN 3
-#define CMD_PRINT_REG_DATA 4
+#define CMD_PRINT_REG_FLAGS REG_DATA
+#define CMD_PRINT_REG_LEN (REG_DATA + 1)
+#define CMD_PRINT_REG_DATA (REG_DATA + 2)
+
+// Get security state command
+#define CMD_SECURITY_GET 20
+
+// OK result, any other values are errors
+#define RESULT_OK 0
 
 static inline uint8_t system76_ec_read(uint8_t addr)
 {
@@ -59,3 +67,81 @@ void system76_ec_print(uint8_t byte)
 	if (byte == '\n' || len >= (SYSTEM76_EC_SIZE - CMD_PRINT_REG_DATA))
 		system76_ec_flush();
 }
+
+// Issue a command not checking if the console needs to be flushed
+// Do not print from this command to avoid EC protocol issues
+static int system76_ec_unsafe(uint8_t cmd, uint8_t * data, int length) {
+	// Error if length is too long
+	if (length > (SYSTEM76_EC_SIZE - REG_DATA)) {
+		return -1;
+	}
+
+	// Error if command is in progress
+	if (system76_ec_read(REG_CMD) != CMD_FINISHED) {
+		return -1;
+	}
+
+	// Write command data
+	for (int i = 0; i < length; i++) {
+		system76_ec_write(REG_DATA + i, data[i]);
+	}
+
+	// Start command
+	system76_ec_write(REG_CMD, cmd);
+
+	// Wait for command completion, for up to 10 milliseconds, with a
+	// test period of 1 microsecond
+	wait_us(10000, system76_ec_read(REG_CMD) == CMD_FINISHED);
+
+	// Error if command did not complete
+	if (system76_ec_read(REG_CMD) != CMD_FINISHED) {
+		return -1;
+	}
+
+	// Read command data
+	for (int i = 0; i < length; i++) {
+		data[i] = system76_ec_read(REG_DATA + i);
+	}
+
+	// Check result
+	if (system76_ec_read(REG_RESULT) != RESULT_OK) {
+		return -1;
+	}
+
+	return 0;
+}
+
+// Wrapper to allow issuing commands while console is being used
+// Do not print from this command to avoid EC protocol issues
+static int system76_ec_command(uint8_t cmd, uint8_t * data, int length) {
+	// Error if command is in progress
+	if (system76_ec_read(REG_CMD) != CMD_FINISHED) {
+		return -1;
+	}
+
+	// Flush print buffer if it has data
+	// Checked for completion by system76_ec_unsafe
+	if (system76_ec_read(CMD_PRINT_REG_LEN) > 0) {
+		system76_ec_flush();
+	}
+
+	// Run command now that print buffer is flushed
+	int res = system76_ec_unsafe(cmd, data, length);
+	if (res < 0) {
+		return res;
+	}
+
+	// Clear command data (for future prints)
+	// Length is checked by system76_ec_unsafe
+	for (int i = 0; i < length; i++) {
+		system76_ec_write(REG_DATA + i, 0);
+	}
+
+	return 0;
+}
+
+// Get security state
+int system76_ec_security_get(uint8_t * state) {
+	*state = 0;
+	return system76_ec_command(CMD_SECURITY_GET, state, sizeof(uint8_t));
+}

src/ec/system76/ec/system76_ec.h

@@ -0,0 +1,16 @@
+#ifndef EC_SYSTEM76_EC_H
+#define EC_SYSTEM76_EC_H
+
+// Default value, flashing is prevented, cannot be set with CMD_SECURITY_SET
+#define SYSTEM76_EC_SECURITY_STATE_LOCK 0
+// Flashing is allowed, cannot be set with CMD_SECURITY_SET
+#define SYSTEM76_EC_SECURITY_STATE_UNLOCK 1
+// Flashing will be prevented on the next reboot
+#define SYSTEM76_EC_SECURITY_STATE_PREPARE_LOCK 2
+// Flashing will be allowed on the next reboot
+#define SYSTEM76_EC_SECURITY_STATE_PREPARE_UNLOCK 3
+
+// Get security state
+int system76_ec_security_get(uint8_t * state);
+
+#endif /* EC_SYSTEM76_EC_H */

src/include/acpi/acpigen_dsm.h

@@ -11,4 +11,9 @@ struct dsm_i2c_hid_config {
 
 void acpigen_write_dsm_i2c_hid(struct dsm_i2c_hid_config *config);
 
+struct dsm_usb_config {
+	uint8_t usb_lpm_incapable;
+};
+void acpigen_write_dsm_usb(struct dsm_usb_config *config);
+
 #endif /* __ACPI_ACPIGEN_DSM_H__ */

src/include/cpu/intel/cpu_ids.h

@@ -36,8 +36,6 @@
 #define CPUID_COFFEELAKE_B0		0x906eb
 #define CPUID_COFFEELAKE_P0		0x906ec
 #define CPUID_COFFEELAKE_R0		0x906ed
-#define CPUID_ICELAKE_A0		0x706e0
-#define CPUID_ICELAKE_B0		0x706e1
 #define CPUID_JASPERLAKE_A0		0x906c0
 #define CPUID_COMETLAKE_U_A0		0xa0660
 #define CPUID_COMETLAKE_U_K0_S0		0xa0661
@@ -64,7 +62,11 @@
 #define CPUID_ALDERLAKE_N_A0		0xb06e0
 #define CPUID_METEORLAKE_A0_1		0xa06a0
 #define CPUID_METEORLAKE_A0_2		0xa06a1
-#define CPUID_RAPTORLAKE_P_J0		0xb06a2
-#define CPUID_RAPTORLAKE_P_Q0		0xb06a3
+#define CPUID_RAPTORLAKE_E_S_HX_B0	0xb0671
+#define CPUID_RAPTORLAKE_HX_S_8_8_C0	0xb06f2
+#define CPUID_RAPTORLAKE_H_P_J0		0xb06a2
+#define CPUID_RAPTORLAKE_S_6_0_C0	0xb06f5
+#define CPUID_RAPTORLAKE_S_A0		0xb0670
+#define CPUID_RAPTORLAKE_U_Q0		0xb06a3
 
 #endif /* CPU_INTEL_CPU_IDS_H */

src/include/device/pci_ids.h

@@ -2908,13 +2908,6 @@
 #define PCI_DID_INTEL_CNP_H_LPC_QM370		0xa30c
 #define PCI_DID_INTEL_CNP_H_LPC_HM370		0xa30d
 #define PCI_DID_INTEL_CNP_H_LPC_CM246		0xa30e
-#define PCI_DID_INTEL_ICL_U_SUPER_U_ESPI	0x3480
-#define PCI_DID_INTEL_ICL_U_SUPER_U_ESPI_REV0		0x3481
-#define PCI_DID_INTEL_ICL_U_PREMIUM_ESPI	0x3482
-#define PCI_DID_INTEL_ICL_BASE_Y_ESPI		0x3483
-#define PCI_DID_INTEL_ICL_BASE_U_ESPI		0x3484
-#define PCI_DID_INTEL_ICL_Y_PREMIUM_ESPI	0x3487
-#define PCI_DID_INTEL_ICL_SUPER_Y_ESPI		0x3486
 #define PCI_DID_INTEL_CMP_SUPER_U_LPC		0x0281
 #define PCI_DID_INTEL_CMP_PREMIUM_Y_LPC		0x0283
 #define PCI_DID_INTEL_CMP_PREMIUM_U_LPC		0x0284
@@ -3469,6 +3462,35 @@
 #define PCI_DID_INTEL_RPL_P_PCIE_RP2			0xa70d
 #define PCI_DID_INTEL_RPL_P_PCIE_RP3			0xa72d
 
+#define PCI_DID_INTEL_RPP_S_PCIE_RP1			0x7a38
+#define PCI_DID_INTEL_RPP_S_PCIE_RP2			0x7a39
+#define PCI_DID_INTEL_RPP_S_PCIE_RP3			0x7a3a
+#define PCI_DID_INTEL_RPP_S_PCIE_RP4			0x7a3b
+#define PCI_DID_INTEL_RPP_S_PCIE_RP5			0x7a3c
+#define PCI_DID_INTEL_RPP_S_PCIE_RP6			0x7a3d
+#define PCI_DID_INTEL_RPP_S_PCIE_RP7			0x7a3e
+#define PCI_DID_INTEL_RPP_S_PCIE_RP8			0x7a3f
+#define PCI_DID_INTEL_RPP_S_PCIE_RP9			0x7a30
+#define PCI_DID_INTEL_RPP_S_PCIE_RP10			0x7a31
+#define PCI_DID_INTEL_RPP_S_PCIE_RP11			0x7a32
+#define PCI_DID_INTEL_RPP_S_PCIE_RP12			0x7a33
+#define PCI_DID_INTEL_RPP_S_PCIE_RP13			0x7a34
+#define PCI_DID_INTEL_RPP_S_PCIE_RP14			0x7a35
+#define PCI_DID_INTEL_RPP_S_PCIE_RP15			0x7a36
+#define PCI_DID_INTEL_RPP_S_PCIE_RP16			0x7a37
+#define PCI_DID_INTEL_RPP_S_PCIE_RP17			0x7a40
+#define PCI_DID_INTEL_RPP_S_PCIE_RP18			0x7a41
+#define PCI_DID_INTEL_RPP_S_PCIE_RP19			0x7a42
+#define PCI_DID_INTEL_RPP_S_PCIE_RP20			0x7a43
+#define PCI_DID_INTEL_RPP_S_PCIE_RP21			0x7a44
+#define PCI_DID_INTEL_RPP_S_PCIE_RP22			0x7a45
+#define PCI_DID_INTEL_RPP_S_PCIE_RP23			0x7a46
+#define PCI_DID_INTEL_RPP_S_PCIE_RP24			0x7a47
+#define PCI_DID_INTEL_RPP_S_PCIE_RP25			0x7a48
+#define PCI_DID_INTEL_RPP_S_PCIE_RP26			0x7a49
+#define PCI_DID_INTEL_RPP_S_PCIE_RP27			0x7a4a
+#define PCI_DID_INTEL_RPP_S_PCIE_RP28			0x7a4b
+
 /* Intel SATA device Ids */
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE			0x8c00
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI			0x8c02
@@ -3543,6 +3565,7 @@
 #define PCI_DID_INTEL_MTL_SATA			0x7e63
 #define PCI_DID_INTEL_RPP_P_SATA_1		0x51d3
 #define PCI_DID_INTEL_RPP_P_SATA_2		0x51d7
+#define PCI_DID_INTEL_RPP_S_SATA		0x7a62
 
 /* Intel PMC device Ids */
 #define PCI_DID_INTEL_SPT_LP_PMC		0x9d21
@@ -3678,6 +3701,13 @@
 #define PCI_DID_INTEL_ADP_M_N_I2C4		0x54c5
 #define PCI_DID_INTEL_ADP_M_N_I2C5		0x54c6
 
+#define PCI_DID_INTEL_RPP_S_I2C0		0x7a4c
+#define PCI_DID_INTEL_RPP_S_I2C1		0x7a4d
+#define PCI_DID_INTEL_RPP_S_I2C2		0x7a4e
+#define PCI_DID_INTEL_RPP_S_I2C3		0x7a4f
+#define PCI_DID_INTEL_RPP_S_I2C4		0x7a7c
+#define PCI_DID_INTEL_RPP_S_I2C5		0x7a7d
+
 #define PCI_DID_INTEL_MTL_I2C0			0x7e78
 #define PCI_DID_INTEL_MTL_I2C1			0x7e79
 #define PCI_DID_INTEL_MTL_I2C2			0x7e7a
@@ -3755,6 +3785,11 @@
 #define PCI_DID_INTEL_ADP_M_N_UART2		0x54c7
 #define PCI_DID_INTEL_ADP_M_N_UART3		0x54da
 
+#define PCI_DID_INTEL_RPP_S_UART0		0x7a28
+#define PCI_DID_INTEL_RPP_S_UART1		0x7a29
+#define PCI_DID_INTEL_RPP_S_UART2		0x7a7e
+#define PCI_DID_INTEL_RPP_S_UART3		0x7a5c
+
 #define PCI_DID_INTEL_MTL_UART0			0x7e25
 #define PCI_DID_INTEL_MTL_UART1			0x7e26
 #define PCI_DID_INTEL_MTL_UART2			0x7e52
@@ -3840,6 +3875,12 @@
 #define PCI_DID_INTEL_ADP_M_N_SPI1		0x54ab
 #define PCI_DID_INTEL_ADP_M_SPI2		0x54fb
 
+#define PCI_DID_INTEL_RPP_S_HWSEQ_SPI		0x7a24
+#define PCI_DID_INTEL_RPP_S_SPI0		0x7a2a
+#define PCI_DID_INTEL_RPP_S_SPI1		0x7a2b
+#define PCI_DID_INTEL_RPP_S_SPI2		0x7a7b
+#define PCI_DID_INTEL_RPP_S_SPI3		0x7a79
+
 #define PCI_DID_INTEL_SPR_HWSEQ_SPI		0x1bca
 
 #define PCI_DID_INTEL_MTL_HWSEQ_SPI		0x7e23
@@ -3904,22 +3945,6 @@
 #define PCI_DID_INTEL_CFL_S_GT2_3			0x3e9a
 #define PCI_DID_INTEL_CFL_S_GT2_4			0x3e91
 #define PCI_DID_INTEL_CFL_S_GT2_5			0x3e96
-#define PCI_DID_INTEL_ICL_GT0_ULT			0x8A70
-#define PCI_DID_INTEL_ICL_GT0_5_ULT			0x8A71
-#define PCI_DID_INTEL_ICL_GT1_ULT			0x8A40
-#define PCI_DID_INTEL_ICL_GT2_ULX_0			0x8A50
-#define PCI_DID_INTEL_ICL_GT2_ULX_1			0x8A5D
-#define PCI_DID_INTEL_ICL_GT2_ULT_1			0x8A5B
-#define PCI_DID_INTEL_ICL_GT2_ULX_2			0x8A5C
-#define PCI_DID_INTEL_ICL_GT2_ULT_2			0x8A5A
-#define PCI_DID_INTEL_ICL_GT2_ULX_3			0x8A51
-#define PCI_DID_INTEL_ICL_GT2_ULT_3			0x8A52
-#define PCI_DID_INTEL_ICL_GT2_ULX_4			0x8A53
-#define PCI_DID_INTEL_ICL_GT2_ULT_4			0x8A54
-#define PCI_DID_INTEL_ICL_GT2_ULX_5			0x8A55
-#define PCI_DID_INTEL_ICL_GT2_ULT_5			0x8A56
-#define PCI_DID_INTEL_ICL_GT2_ULX_6			0x8A57
-#define PCI_DID_INTEL_ICL_GT3_ULT			0x8A62
 #define PCI_DID_INTEL_CML_GT1_ULT_1			0x9B21
 #define PCI_DID_INTEL_CML_GT1_ULT_2			0x9B2A
 #define PCI_DID_INTEL_CML_GT2_ULT_1			0x9B41
@@ -4006,6 +4031,10 @@
 #define PCI_DID_INTEL_MTL_P_GT2_2			0x7d50
 #define PCI_DID_INTEL_MTL_P_GT2_3			0x7d55
 #define PCI_DID_INTEL_MTL_P_GT2_4			0x7d60
+#define PCI_DID_INTEL_RPL_HX_GT1			0xa788
+#define PCI_DID_INTEL_RPL_HX_GT2			0xa78b
+#define PCI_DID_INTEL_RPL_HX_GT3			0x4688
+#define PCI_DID_INTEL_RPL_HX_GT4			0x468b
 #define PCI_DID_INTEL_RPL_P_GT1				0xa720
 #define PCI_DID_INTEL_RPL_P_GT2				0xa7a8
 #define PCI_DID_INTEL_RPL_P_GT3				0xa7a0
@@ -4050,10 +4079,6 @@
 #define PCI_DID_INTEL_CFL_ID_S_S_4		0x3e33
 #define PCI_DID_INTEL_CFL_ID_S_S_6		0x3eca
 #define PCI_DID_INTEL_CFL_ID_S_S_8		0x3e32
-#define PCI_DID_INTEL_ICL_ID_U			0x8A12
-#define PCI_DID_INTEL_ICL_ID_U_2_2		0x8A02
-#define PCI_DID_INTEL_ICL_ID_Y			0x8A10
-#define PCI_DID_INTEL_ICL_ID_Y_2		0x8A00
 #define PCI_DID_INTEL_CML_ULT			0x9B61
 #define PCI_DID_INTEL_CML_ULT_2_2		0x9B71
 #define PCI_DID_INTEL_CML_ULT_6_2		0x9B51
@@ -4133,6 +4158,14 @@
 #define PCI_DID_INTEL_MTL_P_ID_2		0x7D02
 #define PCI_DID_INTEL_MTL_P_ID_3		0x7d14
 #define PCI_DID_INTEL_MTL_P_ID_4		0x7d15
+#define PCI_DID_INTEL_RPL_HX_ID_1		0xa702
+#define PCI_DID_INTEL_RPL_HX_ID_2		0xa729
+#define PCI_DID_INTEL_RPL_HX_ID_3		0xa728
+#define PCI_DID_INTEL_RPL_HX_ID_4		0xa72a
+#define PCI_DID_INTEL_RPL_HX_ID_5		0xa719
+#define PCI_DID_INTEL_RPL_HX_ID_6		0x4637
+#define PCI_DID_INTEL_RPL_HX_ID_7		0x463b
+#define PCI_DID_INTEL_RPL_HX_ID_8		0x4647
 #define PCI_DID_INTEL_RPL_P_ID_1		0xa706
 #define PCI_DID_INTEL_RPL_P_ID_2		0xa707
 #define PCI_DID_INTEL_RPL_P_ID_3		0xa708
@@ -4163,6 +4196,7 @@
 #define PCI_DID_INTEL_ADP_M_N_SMBUS			0x54a3
 #define PCI_DID_INTEL_MTL_SMBUS				0x7e22
 #define PCI_DID_INTEL_RPP_P_SMBUS			0x51a3
+#define PCI_DID_INTEL_RPP_S_SMBUS			0x7a23
 
 /* Intel EHCI device IDs */
 #define PCI_DID_INTEL_LPT_H_EHCI_1		0x8c26
@@ -4199,6 +4233,7 @@
 #define PCI_DID_INTEL_MTL_M_TCSS_XHCI		0x7eb0
 #define PCI_DID_INTEL_MTL_P_TCSS_XHCI		0x7ec0
 #define PCI_DID_INTEL_RPP_P_TCSS_XHCI		0xa71e
+#define PCI_DID_INTEL_RPP_S_XHCI		0x7a60
 
 /* Intel P2SB device Ids */
 #define PCI_DID_INTEL_APL_P2SB			0x5a92
@@ -4210,7 +4245,6 @@
 #define PCI_DID_INTEL_KBL_P2SB			0xa2a0
 #define PCI_DID_INTEL_CNL_P2SB			0x9da0
 #define PCI_DID_INTEL_CNP_H_P2SB		0xa320
-#define PCI_DID_INTEL_ICL_P2SB			0x34a0
 #define PCI_DID_INTEL_CMP_P2SB			0x02a0
 #define PCI_DID_INTEL_CMP_H_P2SB		0x06a0
 #define PCI_DID_INTEL_TGL_P2SB			0xa0a0
@@ -4230,7 +4264,6 @@
 #define PCI_DID_INTEL_GLK_SRAM			0x31ec
 #define PCI_DID_INTEL_CNL_SRAM			0x9def
 #define PCI_DID_INTEL_CNP_H_SRAM		0xa36f
-#define PCI_DID_INTEL_ICL_SRAM			0x34ef
 #define PCI_DID_INTEL_CMP_SRAM			0x02ef
 #define PCI_DID_INTEL_CMP_H_SRAM		0x06ef
 #define PCI_DID_INTEL_TGL_H_SRAM		0x43ef
@@ -4252,7 +4285,6 @@
 #define PCI_DID_INTEL_LWB_AUDIO_SUPER		0xa270
 #define PCI_DID_INTEL_KBL_AUDIO			0x9d71
 #define PCI_DID_INTEL_CNP_H_AUDIO		0xa348
-#define PCI_DID_INTEL_ICL_AUDIO			0x34c8
 #define PCI_DID_INTEL_CMP_AUDIO			0x02c8
 #define PCI_DID_INTEL_CMP_H_AUDIO		0x06c8
 #define PCI_DID_INTEL_BSW_AUDIO			0x2284
@@ -4270,6 +4302,14 @@
 #define PCI_DID_INTEL_ADP_S_AUDIO_8		0x7ad7
 #define PCI_DID_INTEL_ADP_P_AUDIO		0x51c8
 #define PCI_DID_INTEL_RPP_P_AUDIO		0x51ca
+#define PCI_DID_INTEL_RPP_S_AUDIO_1		0x7a50
+#define PCI_DID_INTEL_RPP_S_AUDIO_2		0x7a51
+#define PCI_DID_INTEL_RPP_S_AUDIO_3		0x7a52
+#define PCI_DID_INTEL_RPP_S_AUDIO_4		0x7a53
+#define PCI_DID_INTEL_RPP_S_AUDIO_5		0x7a54
+#define PCI_DID_INTEL_RPP_S_AUDIO_6		0x7a55
+#define PCI_DID_INTEL_RPP_S_AUDIO_7		0x7a56
+#define PCI_DID_INTEL_RPP_S_AUDIO_8		0x7a57
 
 #define PCI_DID_INTEL_ADP_M_N_AUDIO_1		0x54c8
 #define PCI_DID_INTEL_ADP_M_N_AUDIO_2		0x54c9
@@ -4302,7 +4342,6 @@
 #define PCI_DID_INTEL_LWB_CSE1_SUPER		0xa23b
 #define PCI_DID_INTEL_LWB_CSE2_SUPER		0xa23e
 #define PCI_DID_INTEL_CNP_H_CSE0		0xa360
-#define PCI_DID_INTEL_ICL_CSE0			0x34e0
 #define PCI_DID_INTEL_CMP_CSE0			0x02e0
 #define PCI_DID_INTEL_CMP_H_CSE0		0x06e0
 #define PCI_DID_INTEL_TGL_CSE0			0xa0e0
@@ -4327,6 +4366,10 @@
 #define PCI_DID_INTEL_ADP_M_CSE1		0x54e1
 #define PCI_DID_INTEL_ADP_M_CSE2		0x54e4
 #define PCI_DID_INTEL_ADP_M_CSE3		0x54e5
+#define PCI_DID_INTEL_RPP_S_CSE0		0x7a68
+#define PCI_DID_INTEL_RPP_S_CSE1		0x7a69
+#define PCI_DID_INTEL_RPP_S_CSE2		0x7a6c
+#define PCI_DID_INTEL_RPP_S_CSE3		0x7a6d
 #define PCI_DID_INTEL_MTL_CSE0			0x7e70
 
 /* Intel XDCI device Ids */
@@ -4350,6 +4393,7 @@
 #define PCI_DID_INTEL_MTL_XDCI			0x7e7e
 #define PCI_DID_INTEL_MTL_M_TCSS_XDCI		0x7eb1
 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI		0x7ec1
+#define PCI_DID_INTEL_RPP_S_XDCI		0x7a61
 
 /* Intel SD device Ids */
 #define PCI_DID_INTEL_LPT_LP_SD			0x9c35
@@ -4358,7 +4402,6 @@
 #define PCI_DID_INTEL_SKL_SD			0x9d2d
 #define PCI_DID_INTEL_CNL_SD			0x9df5
 #define PCI_DID_INTEL_CNP_H_SD			0xa375
-#define PCI_DID_INTEL_ICL_SD			0x34f8
 #define PCI_DID_INTEL_CMP_SD			0x02f5
 #define PCI_DID_INTEL_CMP_H_SD			0x06f5
 #define PCI_DID_INTEL_MCC_SD			0x4b48
@@ -4456,7 +4499,6 @@
 #define PCI_DID_INTEL_CNL_LP_CNVI_WIFI		0x9df0
 #define PCI_DID_INTEL_CNL_H_CNVI_WIFI		0xa370
 #define PCI_DID_INTEL_GLK_CNVI_WIFI		0x31dc
-#define PCI_DID_INTEL_ICL_CNVI_WIFI		0x34f0
 #define PCI_DID_INTEL_JSL_CNVI_WIFI_0		0x4df0
 #define PCI_DID_INTEL_JSL_CNVI_WIFI_1		0x4df1
 #define PCI_DID_INTEL_JSL_CNVI_WIFI_2		0x4df2
@@ -4492,6 +4534,10 @@
 #define PCI_DID_INTEL_MTL_CNVI_WIFI_1		0x7e41
 #define PCI_DID_INTEL_MTL_CNVI_WIFI_2		0x7e42
 #define PCI_DID_INTEL_MTL_CNVI_WIFI_3		0x7e43
+#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_0		0x7a70
+#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1		0x7a71
+#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2		0x7a72
+#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_3		0x7a73
 
 /* Intel Crashlog */
 #define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM		0x9a0d
@@ -4502,6 +4548,7 @@
 #define PCI_DID_INTEL_TGP_PMC_CRASHLOG_SRAM		0xa0ef
 #define PCI_DID_INTEL_MTL_CRASHLOG_SRAM			0x7d0d
 #define PCI_DID_INTEL_RPL_CPU_CRASHLOG_SRAM		0xa77d
+#define PCI_DID_INTEL_RPP_S_PMC_CRASHLOG_SRAM		0x7a27
 
 /* Intel Ethernet Controller device Ids */
 #define PCI_DID_INTEL_EHL_GBE_HOST		0x4B32

src/include/spd_bin.h

@@ -35,6 +35,18 @@
 #define DDR4_SPD_PART_OFF	329
 #define DDR4_SPD_PART_LEN	20
 #define DDR4_SPD_SN_OFF		325
+#define MAX_SPD_PAGE_SIZE_SPD5	128
+#define MAX_SPD_SIZE		(SPD_PAGE_LEN * SPD_SN_LEN)
+#define SPD_HUB_MEMREG(addr)	((u8)(0x80 | (addr)))
+#define SPD5_MR11		0x0B
+#define SPD5_MR0		0x00
+#define SPD5_MEMREG_REG(addr)	((u8)((~0x80) & (addr)))
+#define SPD5_MR0_SPD5_HUB_DEV	0x51
+
+struct spd_offset_table {
+	u16 start;		/* Offset 0 */
+	u16 end;		/* Offset 2 */
+};
 
 struct spd_block {
 	u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */

src/lib/spd_cache.c

@@ -209,7 +209,7 @@ enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk)
 
 	dram_type = *(spd_cache + SC_SPD_OFFSET(i) + SPD_DRAM_TYPE);
 
-	if (dram_type == SPD_DRAM_DDR4)
+	if (dram_type == SPD_DRAM_DDR4 || dram_type == SPD_DRAM_DDR5)
 		blk->len = SPD_PAGE_LEN_DDR4;
 	else
 		blk->len = SPD_PAGE_LEN;

src/mainboard/google/brya/Kconfig

@@ -19,7 +19,6 @@ config BOARD_GOOGLE_BRYA_COMMON
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_ESPI
-	select EC_GOOGLE_CHROMEEC_MUX
 	select EC_GOOGLE_CHROMEEC_SKUID
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI

src/mainboard/google/brya/acpi/nvpcf.asl

@@ -50,10 +50,12 @@ Method (NPCF, 2, Serialized)
 				/* Dynamic Params Table Header (1 controller entry, 0x1c bytes) */
 				0x22, 0x05, 0x10, 0x1c, 0x01 }
 
-			CreateWordField (Local0, 0x05, TGPA)
+			CreateWordField (Local0, 0x1d, MAGA)
+			CreateWordField (Local0, 0x19, TPPA)
 			CreateDWordField (Local0, 0x15, CEO0)
 
-			TGPA = 0x50	/* TGP on AC = 10W in 1/8-Watt increments */
+			MAGA = 0x50	/* TGP on AC = 10W in 1/8-Watt increments */
+                        TPPA = 0xc8	/* TPPA = 25W in 1/8-Watt increments */
 			CEO0 = 0x200	/* [7:0] Controller index
 					   [8:8] Disable controller on AC
 					   [9:9] Disable controller on DC */

src/mainboard/google/brya/variants/brya0/overridetree.cb

@@ -804,24 +804,7 @@ chip soc/intel/alderlake
 				use conn0 as mux_conn[0]
 				use conn1 as mux_conn[1]
 				use conn2 as mux_conn[2]
-				use ecmux0 as retimer_conn[0]
-				use ecmux1 as retimer_conn[1]
-				use ecmux2 as retimer_conn[2]
-				device pnp 0c09.0 on
-					chip ec/google/chromeec/mux
-						device generic 0 on
-							chip ec/google/chromeec/mux/conn
-								device generic 0 alias ecmux0 on end
-							end
-							chip ec/google/chromeec/mux/conn
-								device generic 1 alias ecmux1 on end
-							end
-							chip ec/google/chromeec/mux/conn
-								device generic 2 alias ecmux2 on end
-							end
-						end
-					end
-				end
+				device pnp 0c09.0 on end
 			end
 		end
 		device ref pmc hidden

src/mainboard/google/brya/variants/gaelin/gpio.c

@@ -26,15 +26,15 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_NC(GPP_B3, NONE),
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
-	/* B7  : ISH_12C1_SDA ==> NC */
-	PAD_NC(GPP_B7, NONE),
-	/* B8  : ISH_I2C1_SCL ==> NC */
-	PAD_NC(GPP_B8, NONE),
+	/* B7  : ISH_I2C1_SDA ==> I2C_TCHSCR_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8  : ISH_I2C1_SCL ==> I2C_TCHSCR_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
 
-	/* C6  : SML1CLK ==> USI_RST_L */
-	PAD_CFG_GPO(GPP_C6, 0, DEEP),
+	/* C6  : SML1CLK ==> USI_EN_PWR */
+	PAD_CFG_GPO(GPP_C6, 1, DEEP),
 	/* C7  : SML1DATA ==> USI_INT_L */
-	PAD_CFG_GPO(GPP_C7, 0, DEEP),
+	PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE),
 
 	/* D0  : ISH_GP0 ==> NC */
 	PAD_NC(GPP_D0, NONE),

src/mainboard/google/brya/variants/gaelin/overridetree.cb

@@ -13,7 +13,7 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
 		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3] = PchSerialIoPci,
 		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
 	}"
@@ -41,6 +41,7 @@ chip soc/intel/alderlake
 	#| I2C1              | cr50 TPM. Early init is   |
 	#|                   | required to set up a BAR  |
 	#|                   | for TPM communication     |
+	#| I2C3              | TouchScreen               |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
 		.i2c[0] = {
@@ -53,6 +54,12 @@ chip soc/intel/alderlake
 			.fall_time_ns = 400,
 			.data_hold_time_ns = 50,
 		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 600,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
 	}"
 
 	device domain 0 on
@@ -184,6 +191,18 @@ chip soc/intel/alderlake
 				device i2c 1a on end
 			end # Audio Nau8825
 		end # I2C0
+		device ref i2c3 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""LM230001""
+				register "generic.desc" = ""LM238 Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C6)"
+				register "generic.enable_delay_ms" = "6"
+				register "generic.has_power_resource" = "1"
+				device i2c 34 on end
+			end
+		end # I2C3
 		device ref pcie_rp5 on
 			# Enable PCIE 5 using clk 2
 			register "pch_pcie_rp[PCH_RP(5)]" = "{

src/mainboard/google/brya/variants/marasov/overridetree.cb

@@ -66,6 +66,8 @@ chip soc/intel/alderlake
 	}"
 	register "sagv" = "SaGv_Enabled"
 
+	register "skip_mbp_hob" = "1"
+
 	register "ext_fivr_settings" = "{
 		.configure_ext_fivr = 1,
 		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
@@ -284,15 +286,8 @@ chip soc/intel/alderlake
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 			chip drivers/wifi/generic
-				register "wake" = "GPE0_DW1_03"
 				device pci 00.0 on end
 			end
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
-				register "srcclk_pin" = "2"
-				device generic 0 on end
-			end
 		end
 		device ref pcie_rp8 off end
 		device ref pcie_rp11 on

src/mainboard/google/drallion/variants/drallion/include/variant/variant.h

@@ -12,7 +12,7 @@ typedef struct {
 	const char *name;
 } sku_info;
 
-const static sku_info skus[] = {
+static const sku_info skus[] = {
 	// Drallion 360
 	{ .id = 1, .name = "sku1" },
 	// Drallion

src/mainboard/google/rex/variants/rex0/overridetree.cb

@@ -70,8 +70,6 @@ chip soc/intel/meteorlake
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
 
-	register "skip_mbp_hob" = "1"
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |

src/mainboard/google/skyrim/Kconfig

@@ -58,6 +58,12 @@ config DRIVER_TPM_I2C_ADDR
 	hex
 	default 0x50
 
+config AMDFW_CONFIG_FILE
+	string
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/amdfw.cfg"
+	help
+	  Custom firmware list excluding the fwTPM binary.
+
 config HAVE_SPL_FILE
 	bool
 	default y
@@ -125,6 +131,7 @@ config EFS_SPI_READ_MODE
 	default 4                                 # Dual IO (1-2-2)
 
 config EFS_SPI_SPEED
+	default 4 if BOARD_GOOGLE_WINTERHOLD
 	default 0	# 66MHz
 
 config EFS_SPI_MICRON_FLAG
@@ -134,6 +141,7 @@ config NORMAL_READ_SPI_SPEED
 	default 1	# 33MHz
 
 config ALT_SPI_SPEED
+	default 4 if BOARD_GOOGLE_WINTERHOLD
 	default 0	# 66MHz
 
 endif # !EM100

src/mainboard/google/skyrim/amdfw.cfg

@@ -0,0 +1,38 @@
+# PSP fw config file
+
+FIRMWARE_LOCATION          3rdparty/amd_blobs/mendocino/PSP
+
+# type                       file
+# PSP
+AMD_PUBKEY_FILE            TypeId0x00_MendocinoRoot.tkn
+PSPBTLDR_AB_STAGE1_FILE    TypeId0x01_PspBootLoader1_MDN.sbin
+PSPSECUREOS_FILE           TypeId0x02_PspOS_MDN.sbin
+PSP_SMUFW1_SUB0_FILE       TypeId0x08_SmuFirmware_MDN.sbin
+PSPSECUREDEBUG_FILE        TypeId0x09_Mendocino-SDU.stkn
+PSP_SMUFW2_SUB0_FILE       TypeId0x12_SmuFirmware2_MDN.sbin
+PSP_SEC_DEBUG_FILE         TypeId0x13_PspEarlyUnlock_MDN.sbin
+PSP_HW_IPCFG_FILE          TypeId0x20_HwIpCfg_MDN.sbin
+PSP_IKEK_FILE              TypeId0x21_PspiKek_MDN.bin
+PSP_SECG0_FILE             TypeId0x24_SecPolicy_MDN.sbin
+PSP_MP2FW0_FILE            TypeId0x25_Mp2Fw_MDN.sbin
+AMD_DRIVER_ENTRIES         TypeId0x28_PspSystemDriver_MDN.sbin
+PSP_S0I3_FILE              TypeId0x2D_AgesaRunTimeDrv_MDN.sbin
+PSP_ABL0_FILE              TypeId0x30_AgesaBootloaderU_MDN_LPDDR5.sbin
+VBIOS_BTLOADER_FILE        TypeId0x3C_VbiosBootLoader_MDN.sbin
+SECURE_POLICY_L1_FILE      TypeId0x45_SecPolicytOS_MDN.sbin
+UNIFIEDUSB_FILE            TypeId0x44_UnifiedUsb_MDN.sbin
+KEYDBBL_FILE               TypeId0x50_KeyDbBl_MDN.sbin
+KEYDB_TOS_FILE             TypeId0x51_KeyDbTos_MDN.sbin
+SPL_TABLE_FILE             TypeId0x55_SplTableBl_MDN.sbin
+MSMU_FILE                  TypeId0x5A_Msmu_MDN.sbin
+SPIROM_CONFIG_FILE         TypeId0x5C_SpiRomConfig_MDN_Dual66.sbin
+DMCUB_FILE                 TypeId0x71_DmcubFw_MDN.sbin
+PSPBTLDR_AB_FILE           TypeId0x73_PspBootLoader2_MDN.sbin
+TA_IKEK_FILE               TypeId0x8D_IkekTa_MDN.bin
+
+# BDT
+PSP_PMUI_FILE_SUB0_INS1    TypeId0x64_Appb_MDN_Lpddr5Imem1.csbin
+PSP_PMUD_FILE_SUB0_INS1    TypeId0x65_Appb_MDN_Lpddr5Dmem1.csbin
+PSP_PMUI_FILE_SUB0_INS2    TypeId0x64_Appb_MDN_Lpddr5Imem2.csbin
+PSP_PMUD_FILE_SUB0_INS2    TypeId0x65_Appb_MDN_Lpddr5Dmem2.csbin
+PSP_MP2CFG_FILE            TypeId0x6a_Mp2FwConfig_MDN.sbin

src/mainboard/google/skyrim/variants/frostflow/overridetree.cb

@@ -22,11 +22,15 @@ chip soc/amd/mendocino
 		.speed_config[0] = {
 			.speed = I2C_SPEED_FAST,
 			.scl_hcnt = 120,
-			.scl_lcnt = 215,
+			.scl_lcnt = 220,
+			.sda_hold = 90,
 		}
 	}"
 
 	device domain 0 on
+
+		register "dxio_tx_vboost_enable" = "1"
+
 		device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
 			device ref xhci_1 on # XHCI1 controller
 				chip drivers/usb/acpi

src/mainboard/google/skyrim/variants/markarth/overridetree.cb

@@ -3,6 +3,9 @@
 chip soc/amd/mendocino
 
 	device domain 0 on
+
+		register "dxio_tx_vboost_enable" = "1"
+
 		device ref gpp_bridge_1 on
 			# Required so the NVMe gets placed into D3 when entering S0i3.
 			chip drivers/pcie/rtd3/device

src/mainboard/intel/adlrvp/spd/Makefile.inc

@@ -1,10 +1,10 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-SPD_SOURCES =  adlrvp_lp4 	# 0b000
+SPD_SOURCES =  adlrvp_lp4	# 0b000
 SPD_SOURCES += adlrvp_m_lp4	# 0b001
-SPD_SOURCES += adlrvp_m_lp5    	# 0b002
-SPD_SOURCES += adlrvp_lp5 	# 0b003
-SPD_SOURCES += empty      	# 0b004
-SPD_SOURCES += empty      	# 0b005
+SPD_SOURCES += adlrvp_m_lp5	# 0b002
+SPD_SOURCES += adlrvp_lp5	# 0b003
+SPD_SOURCES += empty		# 0b004
+SPD_SOURCES += empty		# 0b005
 SPD_SOURCES += adlrvp_ddr5_mr	# 0b006
-SPD_SOURCES += adlrvp_n_lp5 	# 0b007
+SPD_SOURCES += adlrvp_n_lp5	# 0b007

src/mainboard/intel/icelake_rvp/Kconfig

@@ -1,52 +0,0 @@
-if BOARD_INTEL_ICELAKE_RVPU || BOARD_INTEL_ICELAKE_RVPY
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select BOARD_ROMSIZE_KB_16384
-	select EC_ACPI
-	select HAVE_SPD_IN_CBFS
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select MAINBOARD_HAS_CHROMEOS
-	select HAVE_SPD_IN_CBFS
-	select DRIVERS_I2C_HID
-	select DRIVERS_I2C_GENERIC
-	select DRIVERS_SPI_ACPI
-	select DRIVERS_USB_ACPI
-	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select SOC_INTEL_ICELAKE
-	select MAINBOARD_USES_IFD_EC_REGION
-	select INTEL_LPSS_UART_FOR_CONSOLE
-
-config MAINBOARD_DIR
-	default "intel/icelake_rvp"
-
-config VARIANT_DIR
-	default "icl_u" if BOARD_INTEL_ICELAKE_RVPU
-	default "icl_y" if BOARD_INTEL_ICELAKE_RVPY
-
-config MAINBOARD_PART_NUMBER
-	default "Icelake RVP"
-
-config MAINBOARD_FAMILY
-	string
-	default "Intel_icelake_rvp"
-
-config MAX_CPUS
-	int
-	default 8
-
-config DEVICETREE
-	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
-
-config DIMM_SPD_SIZE
-	default 512
-
-config VBOOT
-	select VBOOT_LID_SWITCH
-	select VBOOT_MOCK_SECDATA
-
-config UART_FOR_CONSOLE
-	int
-	default 2
-endif

src/mainboard/intel/icelake_rvp/Kconfig.name

@@ -1,4 +0,0 @@
-config BOARD_INTEL_ICELAKE_RVPU
-	bool "Icelake U DDR4/LPDDR4 RVP"
-config BOARD_INTEL_ICELAKE_RVPY
-	bool "Icelake Y LPDDR4 RVP"

src/mainboard/intel/icelake_rvp/Makefile.inc

@@ -1,22 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-subdirs-y += spd
-
-bootblock-y += bootblock.c
-bootblock-$(CONFIG_CHROMEOS) += chromeos.c
-
-verstage-$(CONFIG_CHROMEOS) += chromeos.c
-
-romstage-$(CONFIG_CHROMEOS) += chromeos.c
-romstage-y += romstage_fsp_params.c
-romstage-y += board_id.c
-
-ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
-ramstage-y += mainboard.c
-ramstage-y += board_id.c
-
-subdirs-y += variants/baseboard
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
-
-subdirs-y += variants/$(VARIANT_DIR)

src/mainboard/intel/icelake_rvp/board_id.c

@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-#include "board_id.h"
-#include <boardid.h>
-#include <ec/acpi/ec.h>
-#include <stdint.h>
-#include <ec/google/chromeec/ec.h>
-
-static int get_board_id_via_ext_ec(void)
-{
-	uint32_t id = BOARD_ID_INIT;
-
-	if (google_chromeec_get_board_version(&id))
-		id = BOARD_ID_UNKNOWN;
-
-	return id;
-}
-
-/* Get Board ID via EC I/O port write/read */
-int get_board_id(void)
-{
-	MAYBE_STATIC_NONZERO int id = -1;
-
-	if (id < 0) {
-		if (CONFIG(EC_GOOGLE_CHROMEEC))
-			id = get_board_id_via_ext_ec();
-		else{
-			uint8_t buffer[2];
-			uint8_t index;
-			if (send_ec_command(EC_FAB_ID_CMD) == 0) {
-				for (index = 0; index < sizeof(buffer); index++)
-					buffer[index] = recv_ec_data();
-				id = (buffer[0] << 8) | buffer[1];
-			}
-		}
-	}
-
-	return id;
-}

src/mainboard/intel/icelake_rvp/board_id.h

@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _MAINBOARD_BOARD_ID_H_
-#define _MAINBOARD_BOARD_ID_H_
-
-/* Board/FAB ID Command */
-#define EC_FAB_ID_CMD	0x0D
-
-/*
- * Returns board information (board id[15:8] and
- * Fab info[7:0]) on success and < 0 on error
- */
-int get_board_id(void);
-
-#endif /* _MAINBOARD_BOARD_ID_H_ */

src/mainboard/intel/icelake_rvp/board_info.txt

@@ -1,6 +0,0 @@
-Vendor name: Intel
-Board name: Icelake rvp
-Category: eval
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y

src/mainboard/intel/icelake_rvp/bootblock.c

@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/gpio.h>
-#include <baseboard/variants.h>
-#include <bootblock_common.h>
-#include <soc/gpio.h>
-
-void bootblock_mainboard_early_init(void)
-{
-	const struct pad_config *pads;
-	size_t num;
-
-	pads = variant_early_gpio_table(&num);
-	gpio_configure_pads(pads, num);
-}

src/mainboard/intel/icelake_rvp/chromeos.c

@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/gpio.h>
-#include <bootmode.h>
-#include <boot/coreboot_tables.h>
-#include <gpio.h>
-#include <types.h>
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
-	struct lb_gpio chromeos_gpios[] = {
-		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
-		{-1, ACTIVE_HIGH, 0, "power"},
-		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
-	};
-	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
-
-int get_lid_switch(void)
-{
-	/* Lid always open */
-	return 1;
-}
-
-int get_recovery_mode_switch(void)
-{
-	return 0;
-}
-
-int get_write_protect_state(void)
-{
-	/* No write protect */
-	return 0;
-}

src/mainboard/intel/icelake_rvp/chromeos.fmd

@@ -1,44 +0,0 @@
-FLASH@0xff000000 0x1000000 {
-	SI_ALL@0x0 0x3F0000 {
-		SI_DESC@0x0 0x1000
-		SI_EC@0x1000 0x80000
-		SI_ME@0x81000 0x36F000
-	}
-	SI_BIOS@0x400000 0xC00000 {
-		RW_SECTION_A@0x0 0x2d0000 {
-			VBLOCK_A@0x0 0x10000
-			FW_MAIN_A(CBFS)@0x10000 0x2bffc0
-			RW_FWID_A@0x2cffc0 0x40
-		}
-		RW_SECTION_B@0x2d0000 0x2d0000 {
-			VBLOCK_B@0x0 0x10000
-			FW_MAIN_B(CBFS)@0x10000 0x2bffc0
-			RW_FWID_B@0x2cffc0 0x40
-		}
-		RW_MISC@0x5a0000 0x30000 {
-			UNIFIED_MRC_CACHE@0x0 0x20000 {
-				RECOVERY_MRC_CACHE@0x0 0x10000
-				RW_MRC_CACHE@0x10000 0x10000
-			}
-			RW_ELOG(PRESERVE)@0x20000 0x4000
-			RW_SHARED@0x24000 0x4000 {
-				SHARED_DATA@0x0 0x2000
-				VBLOCK_DEV@0x2000 0x2000
-			}
-			RW_VPD(PRESERVE)@0x28000 0x2000
-			RW_NVRAM(PRESERVE)@0x2a000 0x6000
-		}
-		SMMSTORE(PRESERVE)@0x5d0000 0x40000
-		RW_LEGACY(CBFS)@0x610000 0x1c0000
-		WP_RO@0x7d0000 0x430000 {
-			RO_VPD(PRESERVE)@0x0 0x4000
-			RO_SECTION@0x4000 0x42c000 {
-				FMAP@0x0 0x800
-				RO_FRID@0x800 0x40
-				RO_FRID_PAD@0x840 0x7c0
-				GBB@0x1000 0xef000
-				COREBOOT(CBFS)@0xf0000 0x33c000
-			}
-		}
-	}
-}

src/mainboard/intel/icelake_rvp/dsdt.asl

@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi.h>
-#include <baseboard/ec.h>
-#include <baseboard/gpio.h>
-
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20110725
-)
-{
-	#include <acpi/dsdt_top.asl>
-	#include <soc/intel/common/block/acpi/acpi/platform.asl>
-
-	// global NVS and variables
-	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
-
-	// CPU
-	#include <cpu/intel/common/acpi/cpu.asl>
-
-	Scope (\_SB) {
-		Device (PCI0)
-		{
-			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
-			#include <soc/intel/icelake/acpi/southbridge.asl>
-		}
-	}
-
-#if CONFIG(EC_GOOGLE_CHROMEEC)
-	/* ChromeOS Embedded Controller */
-		Scope (\_SB.PCI0.LPCB)
-		{
-			/* ACPI code for EC SuperIO functions */
-			#include <ec/google/chromeec/acpi/superio.asl>
-			/* ACPI code for EC functions */
-			#include <ec/google/chromeec/acpi/ec.asl>
-		}
-#endif
-
-	#include <southbridge/intel/common/acpi/sleepstates.asl>
-}

src/mainboard/intel/icelake_rvp/hda_verb.c

@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-#include <baseboard/hda_verb.h>

src/mainboard/intel/icelake_rvp/mainboard.c

@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/gpio.h>
-#include <baseboard/variants.h>
-#include <device/device.h>
-#include <soc/gpio.h>
-
-static void mainboard_init(void *chip_info)
-{
-	const struct pad_config *pads;
-	size_t num;
-
-	pads = variant_gpio_table(&num);
-	gpio_configure_pads(pads, num);
-}
-
-struct chip_operations mainboard_ops = {
-	.init = mainboard_init,
-};

src/mainboard/intel/icelake_rvp/romstage_fsp_params.c

@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <fsp/api.h>
-#include <soc/romstage.h>
-#include <spd_bin.h>
-#include "board_id.h"
-#include "spd/spd.h"
-
-void mainboard_memory_init_params(FSPM_UPD *mupd)
-{
-	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
-	u8 spd_index = (get_board_id() & 0x1F) & 0x7;
-	printk(BIOS_DEBUG, "spd index is 0x%x\n", spd_index);
-
-	if (spd_index > 0 && spd_index != 2) {
-		mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
-
-		/* Memory leak is ok since we have memory mapped boot media */
-		mem_cfg->MemorySpdPtr00 = spd_cbfs_map(spd_index);
-		if (!mem_cfg->MemorySpdPtr00)
-			die("spd.bin not found\n");
-		mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
-
-		mem_cfg->SpdAddressTable[0] = 0x0;
-		mem_cfg->SpdAddressTable[1] = 0x0;
-		mem_cfg->SpdAddressTable[2] = 0x0;
-		mem_cfg->SpdAddressTable[3] = 0x0;
-	} else {
-		mem_cfg->MemorySpdPtr00 = 0;
-		mem_cfg->MemorySpdPtr01 = 0;
-		mem_cfg->MemorySpdPtr10 = 0;
-		mem_cfg->MemorySpdPtr11 = 0;
-
-		mem_cfg->SpdAddressTable[0] = 0xA0;
-		mem_cfg->SpdAddressTable[1] = 0xA2;
-		mem_cfg->SpdAddressTable[2] = 0xA4;
-		mem_cfg->SpdAddressTable[3] = 0xA6;
-	}
-	mem_cfg->DqPinsInterleaved = 0;
-	mem_cfg->CaVrefConfig = 0x2; /* VREF_CA->CHA/CHB */
-	mem_cfg->ECT = 1; /* Early Command Training Enabled */
-	mem_cfg->RefClk = 0; /* Auto Select CLK freq */
-
-	mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0);
-	mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1);
-	mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0);
-	mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1);
-	mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
-	mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
-}

src/mainboard/intel/icelake_rvp/spd/Makefile.inc

@@ -1,12 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-romstage-y += spd_util.c
-
-SPD_SOURCES = empty	# 0b000
-SPD_SOURCES += samsung_K4F6E304HBMGCJ	# 1b001
-SPD_SOURCES += empty	# 2b010
-SPD_SOURCES += empty	# 3b011
-SPD_SOURCES += samsung_K4F6E304HBMGCJ	# 4b100
-SPD_SOURCES += empty	# 5b101
-SPD_SOURCES += samsung_K4F6E304HBMGCJ	# 6b110
-SPD_SOURCES += empty	# 7b111

src/mainboard/intel/icelake_rvp/spd/spd.h

@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef MAINBOARD_SPD_H
-#define MAINBOARD_SPD_H
-
-void mainboard_fill_dq_map_ch0(void *dq_map_ptr);
-void mainboard_fill_dq_map_ch1(void *dq_map_ptr);
-void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr);
-void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr);
-void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
-void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
-#endif

src/mainboard/intel/icelake_rvp/spd/spd_util.c

@@ -1,129 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cpu/cpu.h>
-#include <intelblocks/mp_init.h>
-#include <stdint.h>
-#include <string.h>
-
-#include "../board_id.h"
-#include "spd.h"
-
-enum icl_dimm_type {
-	icl_u_ddr4 = 0,
-	icl_u_lpddr4 = 1,
-	icl_u_lpddr4_type_3 = 4,
-	icl_y_lpddr4 = 6
-};
-
-void mainboard_fill_dq_map_ch0(void *dq_map_ptr)
-{
-	/* DQ byte map Ch0 */
-	const u8 dq_map[12] = {
-		0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
-
-	memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
-}
-
-void mainboard_fill_dq_map_ch1(void *dq_map_ptr)
-{
-	const u8 dq_map[12] = {
-		0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
-
-	memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
-}
-
-static uint8_t get_spd_index(void)
-{
-	uint8_t spd_index = (get_board_id() & 0x1F) & 0x7;
-
-	return spd_index;
-}
-
-void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr)
-{
-	/* DQS CPU<>DRAM map Ch0 */
-	const u8 dqs_map_u_ddr[8] = { 2, 0, 1, 3, 6, 4, 7, 5 };
-	const u8 dqs_map_u_lpddr[8] = { 2, 3, 0, 1, 7, 6, 4, 5 };
-	const u8 dqs_map_u_lpddr_type_3[8] = { 2, 3, 1, 0, 7, 6, 4, 5 };
-	const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
-
-	switch (get_spd_index()) {
-	case icl_u_ddr4:
-		memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr));
-		break;
-	case icl_u_lpddr4:
-		memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr));
-		break;
-	case icl_u_lpddr4_type_3:
-		memcpy(dqs_map_ptr, dqs_map_u_lpddr_type_3,
-				 sizeof(dqs_map_u_lpddr_type_3));
-		break;
-	case icl_y_lpddr4:
-		memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr));
-		break;
-	default:
-		break;
-	}
-}
-
-void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr)
-{
-	/* DQS CPU<>DRAM map Ch1 */
-	const u8 dqs_map_u_ddr[8] = { 1, 3, 2, 0, 5, 7, 6, 4 };
-	const u8 dqs_map_u_lpddr[8] = { 1, 0, 3, 2, 5, 4, 7, 6  };
-	const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 5, 4, 7, 6 };
-
-	switch (get_spd_index()) {
-	case icl_u_ddr4:
-		memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr));
-		break;
-	case icl_u_lpddr4:
-	case icl_u_lpddr4_type_3:
-		memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr));
-		break;
-	case icl_y_lpddr4:
-		memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr));
-		break;
-	default:
-		break;
-	}
-}
-
-void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
-{
-	/* Rcomp resistor */
-	const u16 RcompResistor[3] = { 100, 100, 100 };
-	memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
-}
-
-void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
-{
-	/* Rcomp target */
-	static const u16 RcompTarget_DDR4[5] = {
-			100, 33, 32, 33, 28 };
-	static const u16 RcompTarget_LPDDR4_Ax[5] = {
-			80, 40, 40, 40, 30 };
-	static const u16 RcompTarget_LPDDR4_Bx[5] = {
-			60, 20, 20, 20, 20 };
-
-	switch (get_spd_index()) {
-	case icl_u_ddr4:
-		memcpy(rcomp_strength_ptr, RcompTarget_DDR4,
-				sizeof(RcompTarget_DDR4));
-		break;
-	case icl_y_lpddr4:
-	case icl_u_lpddr4:
-	case icl_u_lpddr4_type_3:
-		if (cpu_get_cpuid() == CPUID_ICELAKE_A0)
-			memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Ax,
-				sizeof(RcompTarget_LPDDR4_Ax));
-		else
-			memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Bx,
-				sizeof(RcompTarget_LPDDR4_Bx));
-		break;
-	default:
-		break;
-	}
-}

src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h

@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __BASEBOARD_EC_H__
-#define __BASEBOARD_EC_H__
-
-#include <ec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <baseboard/gpio.h>
-
-#define MAINBOARD_EC_SCI_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)       |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
-
-#define MAINBOARD_EC_SMI_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
-
-/* EC can wake from S5 with lid or power button */
-#define MAINBOARD_EC_S5_WAKE_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
-
-/*
- * EC can wake from S3 with lid or power button or key press or
- * mode change event.
- */
-#define MAINBOARD_EC_S3_WAKE_EVENTS \
-	(MAINBOARD_EC_S5_WAKE_EVENTS |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
-
-/* Log EC wake events plus EC shutdown events */
-#define MAINBOARD_EC_LOG_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
-
-/*
- * ACPI related definitions for ASL code.
- */
-
-/* Enable EC backed ALS device in ACPI */
-#define EC_ENABLE_ALS_DEVICE
-
-/* Enable EC backed PD MCU device in ACPI */
-#define EC_ENABLE_PD_MCU_DEVICE
-
-/* Enable LID switch and provide wake pin for EC */
-#define EC_ENABLE_LID_SWITCH
-#define EC_ENABLE_WAKE_PIN	GPE_EC_WAKE
-
-#define SIO_EC_MEMMAP_ENABLE	/* EC Memory Map Resources */
-#define SIO_EC_HOST_ENABLE	/* EC Host Interface Resources */
-#define SIO_EC_ENABLE_PS2K      /* Enable PS/2 Keyboard */
-
-#endif /* __BASEBOARD_EC_H__ */

src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h

@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __BASEBOARD_GPIO_H__
-#define __BASEBOARD_GPIO_H__
-
-#include <soc/gpe.h>
-#include <soc/gpio.h>
-
-/* eSPI virtual wire reporting */
-#define EC_SCI_GPI	GPE0_ESPI
-
-/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
-#define GPE_EC_WAKE	GPE0_LAN_WAK
-
-#endif /* __BASEBOARD_GPIO_H__ */

src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h

@@ -1,687 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef HDA_VERB_H
-#define HDA_VERB_H
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
-	/* ALC 700 */
-	0x10EC0700,
-	0xFFFFFFFF,
-	0x00000023,
-
-	AZALIA_SUBVENDOR(0, 0x10EC10F2),
-	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
-	AZALIA_PIN_CFG(0, 0x12, 0x40000000),
-	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
-	AZALIA_PIN_CFG(0, 0x14, 0x411111F0),
-	AZALIA_PIN_CFG(0, 0x15, 0x411111F0),
-	AZALIA_PIN_CFG(0, 0x16, 0x411111F0),
-	AZALIA_PIN_CFG(0, 0x17, 0x90170110),
-	AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
-	AZALIA_PIN_CFG(0, 0x19, 0x04A11030),
-	AZALIA_PIN_CFG(0, 0x1A, 0x411111F0),
-	AZALIA_PIN_CFG(0, 0x1B, 0x411111F0),
-	AZALIA_PIN_CFG(0, 0x1D, 0x40622005),
-	AZALIA_PIN_CFG(0, 0x1E, 0x411111F0),
-	AZALIA_PIN_CFG(0, 0x1F, 0x411111F0),
-	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
-	AZALIA_PIN_CFG(0, 0x29, 0x411111F0),
-
-	/* Widget node 0x20 */
-	0x02050045,
-	0x02045289,
-	0x0205004A,
-	0x0204201B,
-	/* Widget node 0x20 - 1 */
-	0x05850000,
-	0x05843888,
-	0x0205006F,
-	0x02042C0B,
-
-	//Widget node 0X20 for ALC1305   20160603 update
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040000,
-	0x02050028,
-	0x02040000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040004,
-	0x02050028,
-	0x02040600,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204003C,
-	0x02050028,
-	0x0204FFD0,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040080,
-	0x02050028,
-	0x02040080,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040080,
-	0x02050028,
-	0x02040880,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204003A,
-	0x02050028,
-	0x02040DFE,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204006A,
-	0x02050028,
-	0x0204005D,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204006C,
-	0x02050028,
-	0x02040442,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040005,
-	0x02050028,
-	0x02040880,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040006,
-	0x02050028,
-	0x02040000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040008,
-	0x02050028,
-	0x0204B000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204002E,
-	0x02050028,
-	0x02040800,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204006A,
-	0x02050028,
-	0x020400C3,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204006C,
-	0x02050028,
-	0x0204D4A0,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204006A,
-	0x02050028,
-	0x020400CC,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204006C,
-	0x02050028,
-	0x0204400A,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204006A,
-	0x02050028,
-	0x020400C1,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204006C,
-	0x02050028,
-	0x02040320,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040039,
-	0x02050028,
-	0x02040000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204003B,
-	0x02050028,
-	0x0204FFFF,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204003C,
-	0x02050028,
-	0x0204FC20,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204003A,
-	0x02050028,
-	0x02041DFE,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400C0,
-	0x02050028,
-	0x020401FA,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400C1,
-	0x02050028,
-	0x0204DE23,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400C2,
-	0x02050028,
-	0x02041C00,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400C3,
-	0x02050028,
-	0x02040000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400C4,
-	0x02050028,
-	0x02040200,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400C5,
-	0x02050028,
-	0x02040000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400C6,
-	0x02050028,
-	0x020403F5,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400C7,
-	0x02050028,
-	0x0204AF1B,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400C8,
-	0x02050028,
-	0x02041E0A,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400C9,
-	0x02050028,
-	0x0204368E,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400CA,
-	0x02050028,
-	0x020401FA,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400CB,
-	0x02050028,
-	0x0204DE23,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400CC,
-	0x02050028,
-	0x02041C00,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400CD,
-	0x02050028,
-	0x02040000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400CE,
-	0x02050028,
-	0x02040200,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400CF,
-	0x02050028,
-	0x02040000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400D0,
-	0x02050028,
-	0x020403F5,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400D1,
-	0x02050028,
-	0x0204AF1B,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400D2,
-	0x02050028,
-	0x02041E0A,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x020400D3,
-	0x02050028,
-	0x0204368E,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040040,
-	0x02050028,
-	0x0204800F,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040062,
-	0x02050028,
-	0x02048000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040063,
-	0x02050028,
-	0x02044848,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040064,
-	0x02050028,
-	0x02040800,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040065,
-	0x02050028,
-	0x02040000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040066,
-	0x02050028,
-	0x02044004,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040067,
-	0x02050028,
-	0x02040802,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040068,
-	0x02050028,
-	0x0204890F,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040069,
-	0x02050028,
-	0x0204E021,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040070,
-	0x02050028,
-	0x02040000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040071,
-	0x02050000,
-	0x02043330,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040072,
-	0x02050000,
-	0x02043333,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040073,
-	0x02050028,
-	0x02040000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040074,
-	0x02050028,
-	0x02040000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040075,
-	0x02050028,
-	0x02040000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040076,
-	0x02050028,
-	0x02040000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040050,
-	0x02050028,
-	0x020402EC,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040051,
-	0x02050028,
-	0x02044909,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040052,
-	0x02050028,
-	0x020440B0,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040046,
-	0x02050028,
-	0x0204C22E,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040047,
-	0x02050028,
-	0x02040C00,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040048,
-	0x02050028,
-	0x02040000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040049,
-	0x02050028,
-	0x02040000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204004A,
-	0x02050028,
-	0x02040000,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204004B,
-	0x02050028,
-	0x02041C00,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204006A,
-	0x02050028,
-	0x02040090,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204006C,
-	0x02050028,
-	0x0204721F,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x0204009E,
-	0x02050028,
-	0x02040001,
-	0x02050029,
-	0x0204B024,
-
-	0x02050024,
-	0x02040010,
-	0x02050026,
-	0x02040004,
-	0x02050028,
-	0x02040500,
-	0x02050029,
-	0x0204B024
-};
-
-const u32 pc_beep_verbs[] = {
-};
-AZALIA_ARRAY_SIZES;
-#endif

src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h

@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __BASEBOARD_VARIANTS_H__
-#define __BASEBOARD_VARIANTS_H__
-
-#include <soc/gpio.h>
-
-/* The next set of functions return the gpio table and fill in the number of
- * entries for each table. */
-
-const struct pad_config *variant_gpio_table(size_t *num);
-const struct pad_config *variant_early_gpio_table(size_t *num);
-
-#endif /*__BASEBOARD_VARIANTS_H__ */

src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc

@@ -1,5 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += gpio.c
-
-ramstage-y += gpio.c

src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb

@@ -1,345 +0,0 @@
-chip soc/intel/icelake
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
-	# GPE configuration
-	# Note that GPE events called out in ASL code rely on this
-	# route. i.e. If this route changes then the affected GPE
-	# offset bits also need to be changed.
-	register "gpe0_dw0" = "GPP_B"
-	register "gpe0_dw1" = "GPP_D"
-	register "gpe0_dw2" = "GPP_E"
-
-	# FSP configuration
-	register "SaGv" = "SaGv_Enabled"
-	register "SmbusEnable" = "1"
-	register "ScsEmmcHs400Enabled" = "1"
-	register "SdCardPowerEnableActiveHigh" = "1"
-
-	register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"	# USB3/2 Type A port1
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# USB2 WWAN
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# USB2 Bluetooth
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"	# Type-C Port1
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"	# Type-C Port2
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"	# Type-C Port3
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC3)"	# Type-C Port4
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"	# USB3/2 Type A port2
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"	# USB2 Type A port1
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC3)"	# USB2 Type A port2
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 WLAN
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# UNUSED
-	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# UNUSED
-	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# UNUSED
-
-	# Enable Pch iSCLK
-	register "pch_isclk" = "1"
-
-	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
-	register "gen1_dec" = "0x00fc0801"
-	register "gen2_dec" = "0x000c0201"
-	# EC memory map range is 0x900-0x9ff
-	register "gen3_dec" = "0x00fc0901"
-
-	register "PchHdaDspEnable" = "1"
-	register "PchHdaAudioLinkHda" = "1"
-
-	register "PcieRpEnable[0]" = "1"
-	register "PcieRpEnable[1]" = "1"
-	register "PcieRpEnable[2]" = "1"
-	register "PcieRpEnable[3]" = "1"
-	register "PcieRpEnable[4]" = "1"
-	register "PcieRpEnable[5]" = "1"
-	register "PcieRpEnable[6]" = "1"
-	register "PcieRpEnable[7]" = "1"
-	register "PcieRpEnable[8]" = "1"
-	register "PcieRpEnable[9]" = "1"
-	register "PcieRpEnable[10]" = "1"
-	register "PcieRpEnable[11]" = "1"
-	register "PcieRpEnable[12]" = "1"
-	register "PcieRpEnable[13]" = "1"
-	register "PcieRpEnable[14]" = "1"
-	register "PcieRpEnable[15]" = "1"
-
-	register "PcieClkSrcUsage[0]" = "2"
-	register "PcieClkSrcUsage[1]" = "8"
-	register "PcieClkSrcUsage[2]" = "0xC"
-	register "PcieClkSrcUsage[3]" = "0x70"
-	register "PcieClkSrcUsage[4]" = "4"
-	register "PcieClkSrcUsage[5]" = "0xE"
-	register "PcieClkSrcUsage[6]" = "0x80"
-	register "PcieClkSrcUsage[7]" = "0x80"
-	register "PcieClkSrcUsage[8]" = "0x80"
-	register "PcieClkSrcUsage[9]" = "0x80"
-	register "PcieClkSrcUsage[10]" = "0x80"
-	register "PcieClkSrcUsage[11]" = "0x80"
-	register "PcieClkSrcUsage[12]" = "0x80"
-	register "PcieClkSrcUsage[13]" = "0x80"
-	register "PcieClkSrcUsage[14]" = "0x80"
-	register "PcieClkSrcUsage[15]" = "0x80"
-
-	register "PcieClkSrcClkReq[0]" = "0"
-	register "PcieClkSrcClkReq[1]" = "1"
-	register "PcieClkSrcClkReq[2]" = "2"
-	register "PcieClkSrcClkReq[3]" = "3"
-	register "PcieClkSrcClkReq[4]" = "4"
-	register "PcieClkSrcClkReq[5]" = "5"
-	register "PcieClkSrcClkReq[6]" = "6"
-	register "PcieClkSrcClkReq[7]" = "7"
-	register "PcieClkSrcClkReq[8]" = "8"
-	register "PcieClkSrcClkReq[9]" = "9"
-	register "PcieClkSrcClkReq[10]" = "10"
-	register "PcieClkSrcClkReq[11]" = "11"
-	register "PcieClkSrcClkReq[12]" = "12"
-	register "PcieClkSrcClkReq[13]" = "13"
-	register "PcieClkSrcClkReq[14]" = "14"
-	register "PcieClkSrcClkReq[15]" = "15"
-
-	register "SataEnable" = "1"
-	register "SataSalpSupport" = "1"
-	register "SataPortsEnable[0]" = "1"
-	register "SataPortsEnable[1]" = "1"
-	register "SataPortsEnable[2]" = "1"
-	register "SataPortsEnable[3]" = "1"
-	register "SataPortsEnable[4]" = "1"
-	register "SataPortsEnable[5]" = "1"
-	register "SataPortsEnable[6]" = "1"
-	register "SataPortsEnable[7]" = "1"
-
-	register "SataPortsDevSlp[0]" = "1"
-	register "SataPortsDevSlp[1]" = "1"
-	register "SataPortsDevSlp[2]" = "1"
-	register "SataPortsDevSlp[3]" = "1"
-	register "SataPortsDevSlp[4]" = "1"
-	register "SataPortsDevSlp[5]" = "1"
-	register "SataPortsDevSlp[6]" = "1"
-	register "SataPortsDevSlp[7]" = "1"
-
-	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
-	}"
-
-	register "SerialIoGSpiMode" = "{
-		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
-		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
-		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
-	}"
-
-	register "SerialIoGSpiCsMode" = "{
-		[PchSerialIoIndexGSPI0] = 1,
-		[PchSerialIoIndexGSPI1] = 1,
-		[PchSerialIoIndexGSPI2] = 1,
-	}"
-
-	register "SerialIoGSpiCsState" = "{
-		[PchSerialIoIndexGSPI0] = 0,
-		[PchSerialIoIndexGSPI1] = 0,
-		[PchSerialIoIndexGSPI2] = 0,
-	}"
-
-	register "SerialIoUartMode" = "{
-		[PchSerialIoIndexUART0] = PchSerialIoDisabled,
-		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
-		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
-	}"
-
-	# Enable DPTF
-	register "dptf_enable" = "1"
-
-	# GPIO for SD card detect
-	register "sdcard_cd_gpio" = "GPP_G5"
-
-	# Enable S0ix
-	register "s0ix_enable" = "0"
-
-	# Intel Common SoC Config
-	#+-------------------+---------------------------+
-	#| Field             |  Value                    |
-	#+-------------------+---------------------------+
-	#| GSPI1             | cr50 TPM. Early init is   |
-	#|                   | required to set up a BAR  |
-	#|                   | for TPM communication     |
-	#|                   | before memory is up       |
-	#+-------------------+---------------------------+
-
-	register "common_soc_config" = "{
-		.gspi[1] = {
-			.speed_mhz = 1,
-			.early_init = 1,
-		},
-	}"
-
-	device domain 0 on
-		device pci 00.0 on  end # Host Bridge
-		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 04.0 off end # SA Thermal device
-		device pci 12.0 off end # Thermal Subsystem
-		device pci 12.5 off end # UFS SCS
-		device pci 12.6 off end # GSPI #2
-		device pci 14.0 on
-			chip drivers/usb/acpi
-				register "desc" = ""Root Hub""
-				register "type" = "UPC_TYPE_HUB"
-				device usb 0.0 on
-					chip drivers/usb/acpi
-						register "desc" = ""USB3/2 Type-A Left Lower""
-						register "type" = "UPC_TYPE_A"
-						device usb 2.0 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""WWAN""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.1 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""Bluetooth""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.2 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB C Connector 1""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						device usb 2.3 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB C Connector 2""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						device usb 2.4 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB C Connector 3""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						device usb 2.5 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB C Connector 4""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						device usb 2.6 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3/2 Type-A Left Upper""
-						register "type" = "UPC_TYPE_A"
-						device usb 2.7 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB2 Type-A Right Lower""
-						register "type" = "UPC_TYPE_A"
-						device usb 2.8 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB2 Type-A Right Upper""
-						register "type" = "UPC_TYPE_A"
-						device usb 2.9 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3/2 Type-A Left Lower""
-						register "type" = "UPC_TYPE_A"
-						device usb 3.0 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3/2 Type-A Left Upper""
-						register "type" = "UPC_TYPE_A"
-						device usb 3.1 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""WLAN""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.2 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3 Port Unused1""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.3 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3 Port Unused2""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.4 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3 Port Unused3""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.5 on end
-					end
-				end
-			end
-		end # USB xHCI
-		device pci 14.1 off end # USB xDCI (OTG)
-		device pci 14.2 off end # PMC SRAM
-		device pci 14.3 on
-			chip drivers/wifi/generic
-				register "wake" = "GPE0_PME_B0"
-				device generic 0 on end
-			end
-		end # CNVi wifi
-		device pci 14.5 on  end # SDCard
-		device pci 15.0 on
-			chip drivers/i2c/hid
-				register "generic.hid" = ""ALPS0000""
-				register "generic.desc" = ""Touchpad""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)"
-				register "hid_desc_reg_offset" = "0x20"
-				device i2c 2c on end
-			end
-		end # I2C 0
-		device pci 15.1 on  end # I2C #1
-		device pci 15.2 on  end # I2C #2
-		device pci 15.3 on  end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Interface 3
-		device pci 16.5 off end # Management Engine Interface 4
-		device pci 17.0 on  end # SATA
-		device pci 19.0 on  end # I2C #4
-		device pci 19.1 off end # I2C #5
-		device pci 19.2 on  end # UART #2
-		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on
-			chip drivers/wifi/generic
-				register "wake" = "GPE0_PCI_EXP"
-				device pci 00.0 on end
-			end
-		end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 off end # PCI Express Port 14
-		device pci 1d.6 off end # PCI Express Port 15
-		device pci 1d.7 off end # PCI Express Port 16
-		device pci 1e.0 on  end # UART #0
-		device pci 1e.1 off end # UART #1
-		device pci 1e.2 off end # GSPI #0
-		device pci 1e.3 on
-			chip drivers/spi/acpi
-				register "hid" = "ACPI_DT_NAMESPACE_HID"
-				register "compat_string" = ""google,cr50""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
-				device spi 0 on end
-			end
-		end # GSPI #1
-		device pci 1f.0 on  end # eSPI Interface
-		device pci 1f.1 on  end # P2SB
-		device pci 1f.2 on  end # Power Management Controller
-		device pci 1f.3 on  end # Intel HDA
-		device pci 1f.4 on  end # SMBus
-		device pci 1f.5 on  end # PCH SPI
-		device pci 1f.6 off end # GbE
-	end
-end

src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c

@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/gpio.h>
-#include <baseboard/variants.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-/* Pad configuration in ramstage */
-static const struct pad_config gpio_table[] = {
-/* I2S2_SCLK */
-PAD_CFG_GPI(GPP_A7, NONE, PLTRST),
-/* I2S2_RXD */
-PAD_CFG_GPI(GPP_A10, NONE, PLTRST),
-/* TCH_PNL2_RST_N */
-PAD_CFG_GPO(GPP_A13, 1, DEEP),
-/* ONBOARD_X4_PCIE_SLOT1_PWREN_N */
-PAD_CFG_GPO(GPP_A14, 0, DEEP),
-/* TCH_PNL2_INT_N */
-PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST),
-/* TC_RETIMER_FORCE_PWR */
-PAD_CFG_GPO(GPP_B4, 0, DEEP),
-/* FPS_RST_N */
-PAD_CFG_GPO(GPP_B14, 1, DEEP),
-/* WIFI_RF_KILL_N */
-PAD_CFG_GPO(GPP_B15, 1, PLTRST),
-/* M2_SSD_PWREN_N */
-PAD_CFG_GPO(GPP_B16, 1, DEEP),
-/* WWAN_PERST_N */
-PAD_CFG_GPO(GPP_B17, 1, DEEP),
-/* BT_RF_KILL_N */
-PAD_CFG_GPO(GPP_B18, 1, PLTRST),
-/* CRD_CAM_PWREN_1 */
-PAD_CFG_GPO(GPP_B23, 1, PLTRST),
-/* WF_CAM_CLK_EN */
-PAD_CFG_GPO(GPP_C2, 1, PLTRST),
-/* ONBOARD_X4_PCIE_SLOT1_RESET_N */
-PAD_CFG_GPO(GPP_C5, 1, DEEP),
-/* TCH_PAD_INT_N */
-PAD_CFG_GPI_APIC_EDGE_LOW(GPP_C8, NONE, PLTRST),
-/* WWAN_RST_N */
-PAD_CFG_GPO(GPP_C10, 1, DEEP),
-/* WWAN_FCP_OFF_N */
-PAD_CFG_GPO(GPP_C11, 1, DEEP),
-/* CODEC_INT_N */
-PAD_CFG_GPI_APIC_LOW(GPP_C12, NONE, PLTRST),
-/* SPKR_PD_N */
-PAD_CFG_GPO(GPP_C13, 1, PLTRST),
-/* WF_CAM_RST_N */
-PAD_CFG_GPO(GPP_C15, 1, PLTRST),
-/* CRD_CAM_STROBE_1 */
-PAD_CFG_GPO(GPP_C22, 0, PLTRST),
-/* CRD_CAM_PRIVACY_LED_1 */
-PAD_CFG_GPO(GPP_C23, 0, PLTRST),
-/* FLASH_DES_SEC_OVERRIDEs */
-PAD_CFG_GPO(GPP_D13, 0, DEEP),
-/* TCH_PAD_LS_EN */
-PAD_CFG_GPO(GPP_D14, 1, PLTRST),
-/* ONBOARD_X4_PCIE_SLOT1_DGPU_SEL */
-PAD_CFG_GPO(GPP_D15, 0, DEEP),
-/* MFR_MODE_DET_STRAP */
-PAD_CFG_GPI(GPP_D16, NONE, PLTRST),
-/* TBT_CIO_PWR_EN */
-PAD_CFG_GPO(GPP_E0, 1, DEEP),
-/* FPS_INT */
-PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, NONE),
-/* EC_SLP_S0_CS_N */
-PAD_CFG_GPO(GPP_E6, 1, DEEP),
-/* EC_SMI_N */
-PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE),
-/* TBT_CIO_PLUG_EVENT_N */
-PAD_CFG_GPI_SCI(GPP_E17, NONE, DEEP, EDGE_SINGLE, NONE),
-/* DISP_AUX_P_BIAS_GPIO */
-PAD_CFG_GPO(GPP_E22, 0, PLTRST),
-/* DISP_AUX_N_BIAS_GPIO */
-PAD_CFG_GPO(GPP_E23, 1, DEEP),
-/* SATA_HDD_PWREN */
-PAD_CFG_GPO(GPP_F4, 1, PLTRST),
-/* BIOS_REC */
-PAD_CFG_GPI(GPP_F5, NONE, PLTRST),
-/* SD_CD# */
-PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1),
-/* SD_WP */
-PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1),
-/* M2_SSD_RST_N */
-PAD_CFG_GPO(GPP_H0, 1, DEEP),
-};
-
-/* Early pad configuration in bootblock */
-static const struct pad_config early_gpio_table[] = {
-	/* UART2 RX */
-	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-	/* UART2 TX */
-	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
-};
-
-const struct pad_config *variant_gpio_table(size_t *num)
-{
-	*num = ARRAY_SIZE(gpio_table);
-	return gpio_table;
-}
-
-const struct pad_config *variant_early_gpio_table(size_t *num)
-{
-	*num = ARRAY_SIZE(early_gpio_table);
-	return early_gpio_table;
-}
-
-static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
-};
-
-DECLARE_CROS_GPIOS(cros_gpios);

src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc

@@ -1,5 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += gpio.c
-
-ramstage-y += gpio.c

src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb

@@ -1,345 +0,0 @@
-chip soc/intel/icelake
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
-	# GPE configuration
-	# Note that GPE events called out in ASL code rely on this
-	# route. i.e. If this route changes then the affected GPE
-	# offset bits also need to be changed.
-	register "gpe0_dw0" = "GPP_B"
-	register "gpe0_dw1" = "GPP_D"
-	register "gpe0_dw2" = "GPP_E"
-
-	# FSP configuration
-	register "SaGv" = "SaGv_Enabled"
-	register "SmbusEnable" = "1"
-	register "ScsEmmcHs400Enabled" = "1"
-	register "SdCardPowerEnableActiveHigh" = "1"
-
-	register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"	# USB3/2 Type A port1
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# USB3/2 Type A port2
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"	# Type-C Port1
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"	# Type-C Port2
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"	# Type-C Port3
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# UNUSED
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# UNUSED
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# USB2 Type A port1
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# USB2 Type A port2
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 WLAN
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# UNUSED
-	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# UNUSED
-	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# UNUSED
-
-	# Enable Pch iSCLK
-	register "pch_isclk" = "1"
-
-	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
-	register "gen1_dec" = "0x00fc0801"
-	register "gen2_dec" = "0x000c0201"
-	# EC memory map range is 0x900-0x9ff
-	register "gen3_dec" = "0x00fc0901"
-
-	register "PchHdaDspEnable" = "1"
-	register "PchHdaAudioLinkHda" = "1"
-
-	register "PcieRpEnable[0]" = "1"
-	register "PcieRpEnable[1]" = "1"
-	register "PcieRpEnable[2]" = "1"
-	register "PcieRpEnable[3]" = "1"
-	register "PcieRpEnable[4]" = "1"
-	register "PcieRpEnable[5]" = "1"
-	register "PcieRpEnable[6]" = "1"
-	register "PcieRpEnable[7]" = "1"
-	register "PcieRpEnable[8]" = "1"
-	register "PcieRpEnable[9]" = "1"
-	register "PcieRpEnable[10]" = "1"
-	register "PcieRpEnable[11]" = "1"
-	register "PcieRpEnable[12]" = "1"
-	register "PcieRpEnable[13]" = "1"
-	register "PcieRpEnable[14]" = "1"
-	register "PcieRpEnable[15]" = "1"
-
-	register "PcieClkSrcUsage[0]" = "0x80"
-	register "PcieClkSrcUsage[1]" = "8"
-	register "PcieClkSrcUsage[2]" = "0xC"
-	register "PcieClkSrcUsage[3]" = "0x70"
-	register "PcieClkSrcUsage[4]" = "4"
-	register "PcieClkSrcUsage[5]" = "2"
-	register "PcieClkSrcUsage[6]" = "0x80"
-	register "PcieClkSrcUsage[7]" = "0x80"
-	register "PcieClkSrcUsage[8]" = "0x80"
-	register "PcieClkSrcUsage[9]" = "0x80"
-	register "PcieClkSrcUsage[10]" = "0x80"
-	register "PcieClkSrcUsage[11]" = "0x80"
-	register "PcieClkSrcUsage[12]" = "0x80"
-	register "PcieClkSrcUsage[13]" = "0x80"
-	register "PcieClkSrcUsage[14]" = "0x80"
-	register "PcieClkSrcUsage[15]" = "0x80"
-
-	register "PcieClkSrcClkReq[0]" = "0"
-	register "PcieClkSrcClkReq[1]" = "1"
-	register "PcieClkSrcClkReq[2]" = "2"
-	register "PcieClkSrcClkReq[3]" = "3"
-	register "PcieClkSrcClkReq[4]" = "4"
-	register "PcieClkSrcClkReq[5]" = "5"
-	register "PcieClkSrcClkReq[6]" = "6"
-	register "PcieClkSrcClkReq[7]" = "7"
-	register "PcieClkSrcClkReq[8]" = "8"
-	register "PcieClkSrcClkReq[9]" = "9"
-	register "PcieClkSrcClkReq[10]" = "10"
-	register "PcieClkSrcClkReq[11]" = "11"
-	register "PcieClkSrcClkReq[12]" = "12"
-	register "PcieClkSrcClkReq[13]" = "13"
-	register "PcieClkSrcClkReq[14]" = "14"
-	register "PcieClkSrcClkReq[15]" = "15"
-
-	register "SataEnable" = "1"
-	register "SataSalpSupport" = "1"
-	register "SataPortsEnable[0]" = "1"
-	register "SataPortsEnable[1]" = "1"
-	register "SataPortsEnable[2]" = "1"
-	register "SataPortsEnable[3]" = "1"
-	register "SataPortsEnable[4]" = "1"
-	register "SataPortsEnable[5]" = "1"
-	register "SataPortsEnable[6]" = "1"
-	register "SataPortsEnable[7]" = "1"
-
-	register "SataPortsDevSlp[0]" = "1"
-	register "SataPortsDevSlp[1]" = "1"
-	register "SataPortsDevSlp[2]" = "1"
-	register "SataPortsDevSlp[3]" = "1"
-	register "SataPortsDevSlp[4]" = "1"
-	register "SataPortsDevSlp[5]" = "1"
-	register "SataPortsDevSlp[6]" = "1"
-	register "SataPortsDevSlp[7]" = "1"
-
-	register "SerialIoI2cMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
-	}"
-
-	register "SerialIoGSpiMode" = "{
-		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
-		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
-		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
-	}"
-
-	register "SerialIoGSpiCsMode" = "{
-		[PchSerialIoIndexGSPI0] = 1,
-		[PchSerialIoIndexGSPI1] = 1,
-		[PchSerialIoIndexGSPI2] = 1,
-	}"
-
-	register "SerialIoGSpiCsState" = "{
-		[PchSerialIoIndexGSPI0] = 0,
-		[PchSerialIoIndexGSPI1] = 0,
-		[PchSerialIoIndexGSPI2] = 0,
-	}"
-
-	register "SerialIoUartMode" = "{
-		[PchSerialIoIndexUART0] = PchSerialIoDisabled,
-		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
-		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
-	}"
-
-	# Enable DPTF
-	register "dptf_enable" = "1"
-
-	# GPIO for SD card detect
-	register "sdcard_cd_gpio" = "GPP_G5"
-
-	# Enable S0ix
-	register "s0ix_enable" = "0"
-
-	# Intel Common SoC Config
-	#+-------------------+---------------------------+
-	#| Field             |  Value                    |
-	#+-------------------+---------------------------+
-	#| GSPI1         | cr50 TPM. Early init is        |
-	#|                   | required to set up a BAR    |
-	#|                   | for TPM communication     |
-	#|                   | before memory is up          |
-	#+-------------------+---------------------------+
-
-	register "common_soc_config" = "{
-		.gspi[1] = {
-			.speed_mhz = 1,
-			.early_init = 1,
-		},
-	}"
-
-	device domain 0 on
-		device pci 00.0 on  end # Host Bridge
-		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 04.0 off  end # SA Thermal device
-		device pci 12.0 off  end # Thermal Subsystem
-		device pci 12.5 off end # UFS SCS
-		device pci 12.6 off end # GSPI #2
-		device pci 14.0 on
-			chip drivers/usb/acpi
-				register "desc" = ""Root Hub""
-				register "type" = "UPC_TYPE_HUB"
-				device usb 0.0 on
-					chip drivers/usb/acpi
-						register "desc" = ""USB3-2 Type-A Left Lower""
-						register "type" = "UPC_TYPE_A"
-						device usb 2.0 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3-2 Type-A Left Upper""
-						register "type" = "UPC_TYPE_A"
-						device usb 2.1 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""Bluetooth""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.2 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB C Connector 1""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						device usb 2.3 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB C Connector 2""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						device usb 2.4 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB C Connector 3""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						device usb 2.5 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB2 Port Unused 1""
-						register "type" = "UPC_TYPE_UNUSED"
-						device usb 2.6 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB2 Port Unused 2""
-						register "type" = "UPC_TYPE_UNUSED"
-						device usb 2.7 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB2 Type-A Right Lower""
-						register "type" = "UPC_TYPE_A"
-						device usb 2.8 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB2 Type-A Right Upper""
-						register "type" = "UPC_TYPE_A"
-						device usb 2.9 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3/2 Type-A Left Lower""
-						register "type" = "UPC_TYPE_A"
-						device usb 3.0 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3/2 Type-A Left Upper""
-						register "type" = "UPC_TYPE_A"
-						device usb 3.1 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""WLAN""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.2 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3 Port Unused1""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.3 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3 Port Unused2""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.4 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3 Port Unused3""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.5 on end
-					end
-				end
-			end
-		end # USB xHCI
-		device pci 14.1 off end # USB xDCI (OTG)
-		device pci 14.2 off end # PMC SRAM
-		device pci 14.3 on
-			chip drivers/wifi/generic
-				register "wake" = "GPE0_PME_B0"
-				device generic 0 on end
-			end
-		end # CNVi wifi
-		device pci 14.5 on  end # SDCard
-		device pci 15.0 on
-			chip drivers/i2c/hid
-				register "generic.hid" = ""ALPS0000""
-				register "generic.desc" = ""Touchpad""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)"
-				register "hid_desc_reg_offset" = "0x20"
-				device i2c 2c on end
-			end
-		end # I2C 0
-		device pci 15.1 on  end # I2C #1
-		device pci 15.2 on end # I2C #2
-		device pci 15.3 on end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Interface 3
-		device pci 16.5 off end # Management Engine Interface 4
-		device pci 17.0 on  end # SATA
-		device pci 19.0 on  end # I2C #4
-		device pci 19.1 off end # I2C #5
-		device pci 19.2 on  end # UART #2
-		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on
-			chip drivers/wifi/generic
-				register "wake" = "GPE0_PCI_EXP"
-				device pci 00.0 on end
-			end
-		end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 off end # PCI Express Port 14
-		device pci 1d.6 off end # PCI Express Port 15
-		device pci 1d.7 off end # PCI Express Port 16
-		device pci 1e.0 on  end # UART #0
-		device pci 1e.1 off end # UART #1
-		device pci 1e.2 off end # GSPI #0
-		device pci 1e.3 on
-			chip drivers/spi/acpi
-				register "hid" = "ACPI_DT_NAMESPACE_HID"
-				register "compat_string" = ""google,cr50""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
-				device spi 0 on end
-			end
-		end # GSPI #1
-		device pci 1f.0 on end # eSPI Interface
-		device pci 1f.1 on  end # P2SB
-		device pci 1f.2 on  end # Power Management Controller
-		device pci 1f.3 on  end # Intel HDA
-		device pci 1f.4 on  end # SMBus
-		device pci 1f.5 on  end # PCH SPI
-		device pci 1f.6 off end # GbE
-	end
-end

src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c

@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/gpio.h>
-#include <baseboard/variants.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-/* Pad configuration in ramstage */
-static const struct pad_config gpio_table[] = {
-/* I2S2_SCLK */
-PAD_CFG_GPI(GPP_A7, NONE, PLTRST),
-/* I2S2_RXD */
-PAD_CFG_GPI(GPP_A10, NONE, PLTRST),
-/* TCH_PNL2_RST_N */
-PAD_CFG_GPO(GPP_A13, 1, DEEP),
-/* ONBOARD_X4_PCIE_SLOT1_PWREN_N */
-PAD_CFG_GPO(GPP_A14, 0, DEEP),
-/* TCH_PNL2_INT_N */
-PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST),
-/* TC_RETIMER_FORCE_PWR */
-PAD_CFG_GPO(GPP_B4, 0, DEEP),
-/* FPS_RST_N */
-PAD_CFG_GPO(GPP_B14, 1, DEEP),
-/* WIFI_RF_KILL_N */
-PAD_CFG_GPO(GPP_B15, 1, PLTRST),
-/* M2_SSD_PWREN_N */
-PAD_CFG_GPO(GPP_B16, 1, DEEP),
-/* WWAN_PERST_N */
-PAD_CFG_GPO(GPP_B17, 1, DEEP),
-/* BT_RF_KILL_N */
-PAD_CFG_GPO(GPP_B18, 1, PLTRST),
-/* CRD_CAM_PWREN_1 */
-PAD_CFG_GPO(GPP_B23, 1, PLTRST),
-/* WF_CAM_CLK_EN */
-PAD_CFG_GPO(GPP_C2, 1, PLTRST),
-/* ONBOARD_X4_PCIE_SLOT1_RESET_N */
-PAD_CFG_GPO(GPP_C5, 1, DEEP),
-/* TCH_PAD_INT_N */
-PAD_CFG_GPI_APIC_EDGE_LOW(GPP_C8, NONE, PLTRST),
-/* WWAN_RST_N */
-PAD_CFG_GPO(GPP_C10, 1, DEEP),
-/* WWAN_FCP_OFF_N */
-PAD_CFG_GPO(GPP_C11, 1, DEEP),
-/* CODEC_INT_N */
-PAD_CFG_GPI_APIC_LOW(GPP_C12, NONE, PLTRST),
-/* SPKR_PD_N */
-PAD_CFG_GPO(GPP_C13, 1, PLTRST),
-/* WF_CAM_RST_N */
-PAD_CFG_GPO(GPP_C15, 1, PLTRST),
-/* CRD_CAM_STROBE_1 */
-PAD_CFG_GPO(GPP_C22, 0, PLTRST),
-/* CRD_CAM_PRIVACY_LED_1 */
-PAD_CFG_GPO(GPP_C23, 0, PLTRST),
-/* FLASH_DES_SEC_OVERRIDEs */
-PAD_CFG_GPO(GPP_D13, 0, DEEP),
-/* TCH_PAD_LS_EN */
-PAD_CFG_GPO(GPP_D14, 1, PLTRST),
-/* ONBOARD_X4_PCIE_SLOT1_DGPU_SEL */
-PAD_CFG_GPO(GPP_D15, 0, DEEP),
-/* MFR_MODE_DET_STRAP */
-PAD_CFG_GPI(GPP_D16, NONE, PLTRST),
-/* TBT_CIO_PWR_EN */
-PAD_CFG_GPO(GPP_E0, 1, DEEP),
-/* FPS_INT */
-PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, NONE),
-/* EC_SLP_S0_CS_N */
-PAD_CFG_GPO(GPP_E6, 1, DEEP),
-/* EC_SMI_N */
-PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE),
-/* TBT_CIO_PLUG_EVENT_N */
-PAD_CFG_GPI_SCI(GPP_E17, NONE, DEEP, EDGE_SINGLE, NONE),
-/* DISP_AUX_P_BIAS_GPIO */
-PAD_CFG_GPO(GPP_E22, 0, PLTRST),
-/* DISP_AUX_N_BIAS_GPIO */
-PAD_CFG_GPO(GPP_E23, 1, DEEP),
-/* SATA_HDD_PWREN */
-PAD_CFG_GPO(GPP_F4, 1, PLTRST),
-/* BIOS_REC */
-PAD_CFG_GPI(GPP_F5, NONE, PLTRST),
-/* SD_CD# */
-PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1),
-/* SD_WP */
-PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1),
-/* M2_SSD_RST_N */
-PAD_CFG_GPO(GPP_H0, 1, DEEP),
-};
-
-/* Early pad configuration in bootblock */
-static const struct pad_config early_gpio_table[] = {
-	/* UART2 RX */
-	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-	/* UART2 TX */
-	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
-};
-
-const struct pad_config *variant_gpio_table(size_t *num)
-{
-	*num = ARRAY_SIZE(gpio_table);
-	return gpio_table;
-}
-
-const struct pad_config *variant_early_gpio_table(size_t *num)
-{
-	*num = ARRAY_SIZE(early_gpio_table);
-	return early_gpio_table;
-}
-
-static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
-};
-
-DECLARE_CROS_GPIOS(cros_gpios);