oryp11: Fix TBT RP
Change-Id: I18f04fcfab73ae1144dc9f1625a55af0b708ba36 Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
committed by
Jeremy Soller
parent
626b3c47bf
commit
64ceb34f0c
@@ -74,7 +74,7 @@ chip soc/intel/alderlake
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device ref pcie_rp25 on
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# PCH RP#25 x4, Clock 15 (TBT)
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register "pch_pcie_rp[PCH_RP(21)]" = "{
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register "pch_pcie_rp[PCH_RP(25)]" = "{
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.clk_src = 15,
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.clk_req = 15,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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