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oryp11: Fix TBT RP

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Change-Id: I18f04fcfab73ae1144dc9f1625a55af0b708ba36
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2023-02-09 09:16:18 -07:00
committed by Jeremy Soller
parent 626b3c47bf
commit 64ceb34f0c
1 changed files with 1 additions and 1 deletions
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src/mainboard/system76/rpl/variants/oryp11/overridetree.cb
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@@ -74,7 +74,7 @@ chip soc/intel/alderlake
device ref pcie_rp25 on
# PCH RP#25 x4, Clock 15 (TBT)
register "pch_pcie_rp[PCH_RP(21)]" = "{
register "pch_pcie_rp[PCH_RP(25)]" = "{
.clk_src = 15,
.clk_req = 15,
.flags = PCIE_RP_LTR | PCIE_RP_AER,