mb/system76/adl: Add Oryx Pro 11 as a variant
Change-Id: Ib9cf93dc88cd51d429222540ce0721c6e5f4013a Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
committed by
Jeremy Soller
Jeremy Soller
parent
6d61eca2fa
commit
d55060d2b0
@ -57,6 +57,14 @@ config BOARD_SYSTEM76_ORYP10
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select EC_SYSTEM76_EC_COLOR_KEYBOARD
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select EC_SYSTEM76_EC_DGPU
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config BOARD_SYSTEM76_ORYP11
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def_bool n
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select BOARD_SYSTEM76_ADL_COMMON
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select DRIVERS_GFX_NVIDIA
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select EC_SYSTEM76_EC_COLOR_KEYBOARD
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select EC_SYSTEM76_EC_DGPU
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select SOC_INTEL_RAPTORLAKE
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if BOARD_SYSTEM76_ADL_COMMON
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config MAINBOARD_DIR
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@ -69,6 +77,7 @@ config VARIANT_DIR
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default "lemp11" if BOARD_SYSTEM76_LEMP11
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default "oryp9" if BOARD_SYSTEM76_ORYP9
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default "oryp10" if BOARD_SYSTEM76_ORYP10
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default "oryp11" if BOARD_SYSTEM76_ORYP11
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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@ -80,13 +89,14 @@ config MAINBOARD_PART_NUMBER
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default "lemp11" if BOARD_SYSTEM76_LEMP11
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default "oryp9" if BOARD_SYSTEM76_ORYP9
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default "oryp10" if BOARD_SYSTEM76_ORYP10
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default "oryp11" if BOARD_SYSTEM76_ORYP11
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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default "Darter Pro" if BOARD_SYSTEM76_DARP8
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default "Galago Pro" if BOARD_SYSTEM76_GALP6
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default "Gazelle" if BOARD_SYSTEM76_GAZE18_3050
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default "Lemur Pro" if BOARD_SYSTEM76_LEMP11
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default "Oryx Pro" if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
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default "Oryx Pro" if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10 || BOARD_SYSTEM76_ORYP11
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config MAINBOARD_VERSION
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default "darp8" if BOARD_SYSTEM76_DARP8
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@ -95,6 +105,7 @@ config MAINBOARD_VERSION
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default "lemp11" if BOARD_SYSTEM76_LEMP11
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default "oryp9" if BOARD_SYSTEM76_ORYP9
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default "oryp10" if BOARD_SYSTEM76_ORYP10
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default "oryp11" if BOARD_SYSTEM76_ORYP11
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config CBFS_SIZE
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default 0x1000000
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@ -15,3 +15,6 @@ config BOARD_SYSTEM76_ORYP9
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config BOARD_SYSTEM76_ORYP10
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bool "oryp10"
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config BOARD_SYSTEM76_ORYP11
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bool "oryp11"
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@ -0,0 +1,2 @@
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Board name: oryp11
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Release year: 2023
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BIN
src/mainboard/system76/adl/variants/oryp11/data.vbt
Normal file
BIN
src/mainboard/system76/adl/variants/oryp11/data.vbt
Normal file
Binary file not shown.
294
src/mainboard/system76/adl/variants/oryp11/gpio.c
Normal file
294
src/mainboard/system76/adl/variants/oryp11/gpio.c
Normal file
@ -0,0 +1,294 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <mainboard/gpio.h>
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#include <soc/gpio.h>
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPD ------- */
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PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // BATLOW_N
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PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
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PAD_CFG_GPO(GPD2, 0, DEEP), // PCH_LAKE_WAKE#
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PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
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PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
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PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
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PAD_NC(GPD6, NONE),
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PAD_CFG_GPO(GPD7, 0, DEEP), // GPD_7 (Strap)
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PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // CNVI_SUSCLK
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PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
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PAD_NC(GPD10, NONE),
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PAD_NC(GPD11, NONE),
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PAD_NC(GPD12, NONE),
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/* ------- GPIO Group GPP_A ------- */
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PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
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PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
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PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
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PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
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PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
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PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET#
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PAD_NC(GPP_A7, NONE),
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PAD_NC(GPP_A8, NONE),
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PAD_NC(GPP_A9, NONE),
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PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), // ESPI_ALRT0#
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PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // GPIO4_GC6_NVVDD_EN_R
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PAD_NC(GPP_A12, NONE),
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PAD_NC(GPP_A13, NONE),
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PAD_NC(GPP_A14, NONE),
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/* ------- GPIO Group GPP_B ------- */
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_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000), // TPM_PIRQ#
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PAD_NC(GPP_B1, NONE),
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PAD_CFG_GPI(GPP_B2, NONE, DEEP), // CNVI_WAKE#
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PAD_CFG_GPO(GPP_B3, 1, PLTRST), // PCH_BT_EN
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PAD_NC(GPP_B4, NONE),
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PAD_NC(GPP_B5, NONE),
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PAD_NC(GPP_B6, NONE),
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PAD_NC(GPP_B7, NONE),
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PAD_NC(GPP_B8, NONE),
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PAD_NC(GPP_B9, NONE),
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PAD_NC(GPP_B10, NONE),
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PAD_NC(GPP_B11, NONE),
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PAD_NC(GPP_B12, NONE),
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR
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PAD_NC(GPP_B15, NONE),
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PAD_NC(GPP_B16, NONE),
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PAD_NC(GPP_B17, NONE),
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PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1), // GPP_B18_PMCALERT#
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PAD_NC(GPP_B19, NONE),
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PAD_CFG_GPO(GPP_B20, 0, DEEP), // GPIO_LANRTD3
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_PAD_CFG_STRUCT(GPP_B21, 0x42880100, 0x0000), // GPP_B21_TBT_WAKE#
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PAD_CFG_GPO(GPP_B22, 0, DEEP), // LAN_EC_RST#
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PAD_CFG_GPI(GPP_B23, NONE, DEEP), // Crystal frequency strap
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/* ------- GPIO Group GPP_C ------- */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
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PAD_NC(GPP_C2, NONE), // PCH_PORT80_LED (TLS confidentiality strap)
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3), // GPPB_I2C2_SDA (Pantone)
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3), // GPPB_I2C2_SCL (Pantone)
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PAD_NC(GPP_C5, NONE), // eSPI disable strap
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PAD_CFG_GPI(GPP_C6, NONE, DEEP), // I2C3_SDA (PD controller)
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PAD_CFG_GPI(GPP_C7, NONE, DEEP), // I2C3_SCL (PD controller)
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PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET
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PAD_NC(GPP_C9, NONE),
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PAD_NC(GPP_C10, NONE),
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PAD_NC(GPP_C11, NONE),
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PAD_NC(GPP_C12, NONE),
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PAD_NC(GPP_C13, NONE),
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PAD_NC(GPP_C14, NONE),
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PAD_NC(GPP_C15, NONE),
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // PCH_I2C_SDA
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // PCH_I2C_SCL
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// GPP_C20 (UART2_RX) configured in bootblock
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// GPP_C21 (UART2_TX) configured in bootblock
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PAD_NC(GPP_C22, NONE),
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PAD_NC(GPP_C23, NONE),
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/* ------- GPIO Group GPP_D ------- */
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PAD_NC(GPP_D0, NONE),
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PAD_NC(GPP_D1, NONE),
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PAD_NC(GPP_D2, NONE),
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PAD_CFG_GPO(GPP_D3, 0, DEEP), // GFX_DETECT_STRAP
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PAD_NC(GPP_D4, NONE),
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PAD_CFG_GPO(GPP_D5, 0, DEEP), // M.2_BT_PCMFRM_CRF_RST_N
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PAD_CFG_GPO(GPP_D6, 0, DEEP), // M.2_BT_PCMOUT_CLKREQ0
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PAD_CFG_GPO(GPP_D7, 0, DEEP), // M.2_BT_PCMIN
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PAD_NC(GPP_D8, NONE), // M.2_BT_PCMCLK
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PAD_NC(GPP_D9, NONE),
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PAD_NC(GPP_D10, NONE),
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PAD_NC(GPP_D11, NONE),
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PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), // SSD_CLKREQ#
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PAD_NC(GPP_D13, NONE),
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PAD_NC(GPP_D14, NONE),
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PAD_NC(GPP_D15, NONE),
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PAD_NC(GPP_D16, NONE),
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PAD_NC(GPP_D17, NONE),
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PAD_NC(GPP_D18, NONE),
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PAD_NC(GPP_D19, NONE),
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PAD_NC(GPP_D20, NONE),
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PAD_NC(GPP_D21, NONE),
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PAD_NC(GPP_D22, NONE),
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PAD_NC(GPP_D23, NONE),
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/* ------- GPIO Group GPP_E ------- */
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PAD_NC(GPP_E0, NONE),
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PAD_NC(GPP_E1, NONE),
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PAD_CFG_GPI(GPP_E2, NONE, DEEP), // SWI#
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PAD_CFG_GPI(GPP_E3, NONE, DEEP), // SMI#
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PAD_NC(GPP_E4, NONE),
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PAD_NC(GPP_E5, NONE),
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PAD_NC(GPP_E6, NONE),
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_PAD_CFG_STRUCT(GPP_E7, 0x80100100, 0x0000), // TP_ATTN#
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PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
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PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0#
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PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1#
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PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2#
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PAD_CFG_GPI(GPP_E12, NONE, DEEP), // USB_OC3#
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PAD_NC(GPP_E13, NONE),
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PAD_NC(GPP_E14, NONE),
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PAD_CFG_GPO(GPP_E15, 0, DEEP), // ROM_I2C_EN
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PAD_NC(GPP_E16, NONE),
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PAD_CFG_GPI(GPP_E17, NONE, DEEP), // SB_KBCRST#
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PAD_CFG_GPO(GPP_E18, 1, DEEP), // SB_BLON
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PAD_NC(GPP_E19, NONE),
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PAD_NC(GPP_E20, NONE),
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PAD_NC(GPP_E21, NONE),
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/* ------- GPIO Group GPP_F ------- */
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PAD_CFG_NF(GPP_F0, UP_20K, DEEP, NF1), // M.2_SSD_SATA_DET_N
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PAD_NC(GPP_F1, NONE),
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PAD_CFG_GPO(GPP_F2, 1, DEEP), // GPP_F2_TBT_RST#
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PAD_NC(GPP_F3, NONE),
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PAD_NC(GPP_F4, NONE),
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PAD_NC(GPP_F5, NONE), // SSD_SATA_DEVSLP
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PAD_NC(GPP_F6, NONE),
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PAD_CFG_GPI(GPP_F7, NONE, DEEP), // INTP_8851
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PAD_CFG_GPI(GPP_F8, NONE, PLTRST), // GC6_FB_EN_PCH
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// GPP_F9 (DGPU_PWR_EN) configured in bootblock
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PAD_CFG_GPI(GPP_F10, NONE, DEEP), // Recovery strap
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PAD_NC(GPP_F11, NONE),
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PAD_NC(GPP_F12, NONE),
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PAD_NC(GPP_F13, NONE),
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PAD_NC(GPP_F14, NONE),
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PAD_CFG_GPI(GPP_F15, NONE, DEEP), // K_SKTOCC_N
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PAD_NC(GPP_F16, NONE),
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PAD_NC(GPP_F17, NONE),
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PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP#
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NV_ENAVDD
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
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PAD_NC(GPP_F22, NONE),
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PAD_NC(GPP_F23, NONE),
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/* ------- GPIO Group GPP_G ------- */
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PAD_NC(GPP_G0, NONE),
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PAD_NC(GPP_G1, NONE),
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PAD_NC(GPP_G2, NONE),
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PAD_CFG_GPI(GPP_G3, NONE, DEEP), // MB det (MB1/MB2)
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PAD_CFG_GPI(GPP_G4, NONE, DEEP), // MB det (15"/17")
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PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), // SLP_DRAM_N
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PAD_CFG_GPI(GPP_G6, NONE, DEEP), // MB det (G-SYNC)
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PAD_CFG_GPI(GPP_G7, NONE, DEEP), // MB det (Pantone)
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/* ------- GPIO Group GPP_H ------- */
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PAD_CFG_GPI(GPP_H0, NONE, DEEP), // VAL_SV_ADVANCE_STRAP
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PAD_NC(GPP_H1, NONE),
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PAD_CFG_GPI(GPP_H2, NONE, DEEP), // WLAN_GPIO_WAKE_N
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PAD_NC(GPP_H3, NONE),
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD_SATA_CLKREQ#
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // WLAN_CLKREQ#
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // CARD_CLKREQ#
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // GLAN_CLKREQ#
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PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // PEG_CLKREQ#
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PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // TBT_CLKREQ#
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PAD_NC(GPP_H10, NONE),
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PAD_NC(GPP_H11, NONE),
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PAD_NC(GPP_H12, NONE), // eSPI flash sharing mode strap
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PAD_NC(GPP_H13, NONE),
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PAD_NC(GPP_H14, NONE),
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PAD_NC(GPP_H15, NONE), // JTAG ODT disable strap
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PAD_NC(GPP_H16, NONE),
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PAD_NC(GPP_H17, NONE),
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PAD_NC(GPP_H18, NONE), // 1.8V VCCPSPI strap
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PAD_NC(GPP_H19, NONE),
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PAD_NC(GPP_H20, NONE),
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PAD_NC(GPP_H21, NONE),
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PAD_NC(GPP_H22, NONE),
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PAD_NC(GPP_H23, NONE),
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/* ------- GPIO Group GPP_I ------- */
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_PAD_CFG_STRUCT(GPP_I0, 0x86880100, 0x0000), // DP_F_HPD
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PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // CPU_DP_B_HPD
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_PAD_CFG_STRUCT(GPP_I2, 0x86880100, 0x0000), // HDMI_HPD
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PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), // CPU_DP_D_HPD
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_PAD_CFG_STRUCT(GPP_I4, 0x86880100, 0x0000), // G_DP_DHPD_E
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PAD_CFG_GPO(GPP_I5, 0, DEEP), // GPIO_TBT_RESET
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PAD_NC(GPP_I6, NONE),
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PAD_NC(GPP_I7, NONE),
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PAD_NC(GPP_I8, NONE),
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PAD_NC(GPP_I9, NONE),
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PAD_NC(GPP_I10, NONE),
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PAD_CFG_GPI(GPP_I11, NONE, DEEP), // USB_OC4#
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PAD_CFG_GPI(GPP_I12, NONE, DEEP), // USB_OC5#
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PAD_CFG_GPI(GPP_I13, NONE, DEEP), // USB_OC6#
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PAD_CFG_GPI(GPP_I14, NONE, DEEP), // USB_OC7#
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PAD_NC(GPP_I15, NONE),
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PAD_NC(GPP_I16, NONE),
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PAD_NC(GPP_I17, NONE),
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PAD_NC(GPP_I18, NONE), // NO REBOOT strap
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PAD_NC(GPP_I19, NONE),
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PAD_NC(GPP_I20, NONE),
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PAD_NC(GPP_I21, NONE),
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PAD_NC(GPP_I22, NONE), // BOOT BIOS strap
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/* ------- GPIO Group GPP_J ------- */
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PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
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PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_C10_GATE_N
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PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT_R
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PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
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PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT_R
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PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
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PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
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PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
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PAD_CFG_GPI(GPP_J8, NONE, DEEP), // VAL_TEST_SETUP_MENU
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PAD_NC(GPP_J9, NONE),
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PAD_NC(GPP_J10, NONE),
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PAD_NC(GPP_J11, NONE),
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/* ------- GPIO Group GPP_K ------- */
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_PAD_CFG_STRUCT(GPP_K0, 0x42800100, 0x0000), // TBCIO_PLUG_EVENT#
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PAD_NC(GPP_K1, NONE),
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PAD_NC(GPP_K2, NONE),
|
||||
PAD_CFG_GPO(GPP_K3, 1, PLTRST), // TBT_RTD3_PWR_EN_R
|
||||
PAD_CFG_GPO(GPP_K4, 0, PWROK), // TBT_FORCE_PWR_R
|
||||
PAD_NC(GPP_K5, NONE),
|
||||
// GPP_K6 doesn't exist
|
||||
// GPP_K7 doesn't exist
|
||||
PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // VCCIN_AUX_VID0
|
||||
PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // VCCIN_AUX_VID1
|
||||
// GPP_K10 doesn't exist
|
||||
PAD_NC(GPP_K11, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_R ------- */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#_R
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD_R
|
||||
PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // EDP_HPD
|
||||
PAD_NC(GPP_R10, NONE),
|
||||
PAD_NC(GPP_R11, NONE),
|
||||
PAD_NC(GPP_R12, NONE),
|
||||
PAD_NC(GPP_R13, NONE),
|
||||
PAD_NC(GPP_R14, NONE),
|
||||
PAD_NC(GPP_R15, NONE),
|
||||
// GPP_R16 (DGPU_RST#_PCH) configured in bootblock
|
||||
PAD_NC(GPP_R17, NONE),
|
||||
PAD_NC(GPP_R18, NONE),
|
||||
PAD_CFG_GPI(GPP_R19, NONE, DEEP), // SCI#
|
||||
PAD_NC(GPP_R20, NONE),
|
||||
PAD_NC(GPP_R21, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_S ------- */
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
PAD_NC(GPP_S4, NONE), // GPPS_DMIC_CLK
|
||||
PAD_NC(GPP_S5, NONE), // GPPS_DMIC_DATA
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
};
|
||||
|
||||
void mainboard_configure_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
16
src/mainboard/system76/adl/variants/oryp11/gpio_early.c
Normal file
16
src/mainboard/system76/adl/variants/oryp11/gpio_early.c
Normal file
@ -0,0 +1,16 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <mainboard/gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
|
||||
PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RX
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TX
|
||||
};
|
||||
|
||||
void mainboard_configure_early_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
27
src/mainboard/system76/adl/variants/oryp11/hda_verb.c
Normal file
27
src/mainboard/system76/adl/variants/oryp11/hda_verb.c
Normal file
@ -0,0 +1,27 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x1558d502, /* Subsystem ID */
|
||||
13, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x1558d502),
|
||||
AZALIA_RESET(1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -0,0 +1,13 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#define DGPU_RST_N GPP_R16
|
||||
#define DGPU_PWR_EN GPP_F9
|
||||
#define DGPU_GC6 GPP_A11
|
||||
#define DGPU_SSID 0xd5021558
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,5 @@
|
||||
chip soc/intel/alderlake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0xd502 inherit
|
||||
end
|
||||
end
|
||||
41
src/mainboard/system76/adl/variants/oryp11/romstage.c
Normal file
41
src/mainboard/system76/adl/variants/oryp11/romstage.c
Normal file
@ -0,0 +1,41 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <drivers/gfx/nvidia/gpu.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
const struct mb_cfg board_cfg = {
|
||||
.type = MEM_TYPE_DDR5,
|
||||
.rcomp = { .resistor = 100, },
|
||||
.ect = true,
|
||||
.LpDdrDqDqsReTraining = 1,
|
||||
};
|
||||
const struct mem_spd spd_info = {
|
||||
.topo = MEM_TOPO_DIMM_MODULE,
|
||||
.smbus = {
|
||||
[0] = { .addr_dimm[0] = 0x50, },
|
||||
[1] = { .addr_dimm[0] = 0x52, },
|
||||
},
|
||||
};
|
||||
const bool half_populated = false;
|
||||
|
||||
const struct nvidia_gpu_config config = {
|
||||
.power_gpio = DGPU_PWR_EN,
|
||||
.reset_gpio = DGPU_RST_N,
|
||||
.enable = true,
|
||||
};
|
||||
// Enable dGPU power
|
||||
nvidia_set_power(&config);
|
||||
|
||||
// Set primary display to internal graphics
|
||||
mupd->FspmConfig.PrimaryDisplay = 0;
|
||||
|
||||
mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
|
||||
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
|
||||
mupd->FspmConfig.GpioOverride = 0;
|
||||
|
||||
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
|
||||
}
|
||||
Reference in New Issue
Block a user