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mb/system76/adl-p: oryp10: Remove RTD3 configs

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Change-Id: I009a57c7af371e3e073fc1190526356fe8300d8e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2023-01-03 15:26:02 -07:00
committed by Tim Crawford
parent 05584923bf
commit 38a0553447
1 changed files with 0 additions and 20 deletions
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20
src/mainboard/system76/adl/variants/oryp10/overridetree.cb
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@@ -150,12 +150,6 @@ chip soc/intel/alderlake
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "2" # WLAN_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp6 on
# PCIe RP#6 x1, Clock 6 (CARD)
@@ -164,12 +158,6 @@ chip soc/intel/alderlake
.clk_req = 6,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: Enable connected directly to 3.3VS?
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "6" # CARD_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp8 on
# PCIe RP#8 x1, Clock 5 (GLAN)
@@ -178,15 +166,7 @@ chip soc/intel/alderlake
.clk_req = 5,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: Enable connected directly to VDD3?
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "5" # GLAN_CLKREQ#
device generic 0 on end
end
end
device ref pmc hidden
chip drivers/intel/pmc_mux
device generic 0 on