mb/system76: Remove PL4 values

System76 EC sets PL4 values through PECI based on AC state [1]. Remove
the static PL4 values from coreboot since they won't be used. This will
result in sysfs reporting the package default for PL4.

[1]: https://github.com/system76/ec/pull/353

Change-Id: If33eb38a20febaf8c71615f0d1a640d3991f42ff
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2023-05-17 12:23:56 -06:00
committed by Tim Crawford
parent a524d587e6
commit a01838681e
7 changed files with 0 additions and 11 deletions

View File

@@ -1,10 +1,7 @@
chip soc/intel/alderlake
# HACK: Limit PL4 to PL2 to prevent power-off when system is booted on
# battery power. This seems to only happen with the i7 units.
register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
.tdp_pl1_override = 20,
.tdp_pl2_override = 56,
.tdp_pl4 = 56, // FIXME: Set to 65
}"
# GPE configuration

View File

@@ -2,7 +2,6 @@ chip soc/intel/alderlake
register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
.tdp_pl1_override = 28,
.tdp_pl2_override = 60,
.tdp_pl4 = 90,
}"
# GPE configuration

View File

@@ -2,7 +2,6 @@ chip soc/intel/alderlake
register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 46,
.tdp_pl4 = 65,
}"
# GPE configuration

View File

@@ -1,10 +1,8 @@
chip soc/intel/alderlake
# HACK: Limit PL4 to prevent power off on battery power.
register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
.tdp_pl1_override = 45,
.tdp_pl2_override = 115,
.tdp_psyspl2 = 135,
.tdp_pl4 = 72,
}"
# Thermal

View File

@@ -1,10 +1,8 @@
chip soc/intel/alderlake
# HACK: Limit PL4 to prevent power off on battery power.
register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
.tdp_pl1_override = 45,
.tdp_pl2_override = 115,
.tdp_psyspl2 = 135,
.tdp_pl4 = 72,
}"
# Thermal

View File

@@ -2,7 +2,6 @@ chip soc/intel/alderlake
register "power_limits_config[RPL_P_682_642_482_45W_CORE]" = "{
.tdp_pl1_override = 45,
.tdp_pl2_override = 78,
.tdp_pl4 = 90,
}"
device domain 0 on

View File

@@ -2,7 +2,6 @@ chip soc/intel/alderlake
register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 46,
.tdp_pl4 = 65,
}"
device domain 0 on