mb/system76: Enable dGPUs

Change-Id: I4ca91ff631dd4badbfba72e69651f03753323a54
Signed-off-by: Tim Crawford <tcrawford@system76.com>

Makefile.mk

@@ -501,7 +501,8 @@ CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
 CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie
 CFLAGS_common += -Wstring-compare
 ifeq ($(CONFIG_COMPILER_GCC),y)
-CFLAGS_common += -Wold-style-declaration
+CFLAGS_common += -Wold-style-declaration -Wflex-array-member-not-at-end
+CFLAGS_common += -Wcalloc-transposed-args
 # Don't add these GCC specific flags when running scan-build
 ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
 CFLAGS_common += -Wno-packed-not-aligned

payloads/Makefile.mk

@@ -28,7 +28,6 @@ payloads/external/edk2 \
 payloads/external/GRUB2 \
 payloads/external/LinuxBoot \
 payloads/external/skiboot \
-payloads/external/leanefi \
 payloads/external/coreDOOM \
 
 force-payload:

payloads/external/Makefile.mk

@@ -436,13 +436,6 @@ payloads/external/skiboot/build/skiboot.elf:
 	$(MAKE) -C payloads/external/skiboot all \
 		CONFIG_SKIBOOT_GIT_REPO=$(CONFIG_SKIBOOT_GIT_REPO) \
 		CONFIG_SKIBOOT_REVISION=$(CONFIG_SKIBOOT_REVISION)
-
-# leanefi
-
-payloads/external/leanefi/leanefi/build/leanefi.elf: FORCE $(DOTCONFIG)
-	$(MAKE) -C payloads/external/leanefi
-FORCE: ;
-
 # COREDOOM
 
 payloads/external/coreDOOM/coredoom/doomgeneric/coredoom.elf coredoom:

payloads/external/leanefi/Kconfig

@@ -1,58 +0,0 @@
-if PAYLOAD_LEANEFI
-
-menu "leanEFI configuration"
-
-config PAYLOAD_FILE
-	string
-	default "payloads/external/leanefi/leanefi/build/leanefi.elf"
-
-config LEANEFI_EFI_ECPT
-	bool
-	default y if ARCH_ARM64
-
-config LEANEFI_HEAP_SIZE
-	int "Heap size"
-	default 131072
-	help
-	  This is the heap size (malloc'able size) available
-	  to the payload.
-
-	  If unsure, set to 131072 (128K)
-
-config LEANEFI_STACK_SIZE
-	int "Stack size"
-	default 16384
-	help
-	  This is the stack size available to the payload.
-
-	  If unsure, set to 16384 (16K)
-
-config LEANEFI_BASE_ADDRESS
-	hex "Base address"
-	default 0x62000000 if BOARD_EMULATION_QEMU_AARCH64
-	#default 0x10023300000 if BOARD_EMULATION_QEMU_SBSA
-	help
-	  This is the base address for the payload.
-
-config LEANEFI_PAYLOAD
-	bool "Add a payload"
-	default y
-	help
-	  If selected leanEFI will start a payload.
-	  This option should only be unselected for debug purposes.
-
-config LEANEFI_PAYLOAD_PATH
-	string "path to leanefi payload"
-	depends on LEANEFI_PAYLOAD
-
-config LEANEFI_FDT
-	bool "Add an FDT that is propagated as EFI configuration table"
-	default y if BOARD_EMULATION_QEMU_AARCH64
-
-config LEANEFI_FDT_PATH
-	string "path to FDT"
-	depends on LEANEFI_FDT
-
-endmenu
-
-endif

payloads/external/leanefi/Kconfig.name

@@ -1,6 +0,0 @@
-config PAYLOAD_LEANEFI
-	bool "leanefi"
-	depends on ARCH_ARM64
-	help
-	  Select this option if you want to build a coreboot image
-	  with an leanefi payload.

payloads/external/leanefi/Makefile

@@ -1,22 +0,0 @@
-
-unexport KCONFIG_AUTOHEADER
-unexport KCONFIG_AUTOCONFIG
-unexport KCONFIG_DEPENDENCIES
-unexport KCONFIG_SPLITCONFIG
-unexport KCONFIG_TRISTATE
-unexport KCONFIG_NEGATIVES
-unexport $(COREBOOT_EXPORTS)
-
-build: leanefi
-	$(MAKE) -C leanefi
-
-leanefi:
-	git clone "https://review.coreboot.org/leanefi"
-
-distclean:
-	rm -rf leanefi
-
-clean:
-	rm -rf leanefi/build
-
-.PHONY: build clean distclean

src/arch/arm64/smbios.c

@@ -66,8 +66,8 @@ int smbios_write_type4(unsigned long *current, int handle)
 	smbios_processor_id(t->processor_id);
 	t->processor_manufacturer = smbios_processor_manufacturer(t->eos);
 	t->processor_version = smbios_processor_name(t->eos);
-	t->processor_family = SMBIOS_PROCESSOR_FAMILY_FROM_FAMILY2;
+	t->processor_family = 0xfe; /* Use processor_family2 field */
-	t->processor_family2 = SMBIOS_PROCESSOR_FAMILY2_ARMV8;
+	t->processor_family2 = 0x101; /* ARMv8 */
 	t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL;
 
 	smbios_cpu_get_core_counts(&t->core_count2, &t->thread_count2);

src/arch/x86/smbios.c

@@ -68,7 +68,7 @@ static int get_socket_type(void)
 
 unsigned int __weak smbios_processor_family(struct cpuid_result res)
 {
-	return (res.eax > 0) ? SMBIOS_PROCESSOR_FAMILY_PENTIUM_PRO : SMBIOS_PROCESSOR_FAMILY_INTEL486;
+	return (res.eax > 0) ? 0x0c : 0x6;
 }
 
 static size_t get_number_of_caches(size_t max_logical_cpus_sharing_cache)

src/drivers/gfx/nvidia/Kconfig

@@ -0,0 +1,38 @@
+config DRIVERS_GFX_NVIDIA
+	bool
+	default n
+	help
+	  Support for NVIDIA Optimus graphics
+
+config DRIVERS_GFX_NVIDIA_BRIDGE
+	hex "PCI bridge for the GPU device"
+	default 0x01
+	depends on DRIVERS_GFX_NVIDIA
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	depends on DRIVERS_GFX_NVIDIA
+	bool
+	default n
+	help
+	  Support for NVIDIA Dynamic Boost
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
+	int "Total processor power offset from default TGP in watts"
+	default 45
+	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	help
+	  This identifies the available power for the CPU or GPU boost
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN
+	int "Minimum TGP offset from default TGP in watts"
+	default 0
+	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	help
+	  This is used to transfer power from the GPU to the CPU
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
+	int "Maximum TGP offset from default TGP in watts"
+	default 0
+	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	help
+	  This is used to transfer power from the CPU to the GPU

src/drivers/gfx/nvidia/Makefile.mk

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
+
+ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c

src/drivers/gfx/nvidia/acpi/coffeelake.asl

@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* NVIDIA GC6 on CFL and CML CPU PCIe ports */
+
+// Memory mapped PCI express config space
+OperationRegion (PCIC, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + (CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15), 0x1000)
+
+Field (PCIC, ByteAcc, NoLock, Preserve) {
+	PVID,   16,
+	PDID,   16,
+
+	Offset (0x248),
+		,   7,
+	L23E,   1,      /* L23_Rdy Entry Request */
+	L23R,   1,      /* L23_Rdy to Detect Transition */
+
+	Offset (0xC20),
+		,   4,
+	P0AP,   2,      /* Additional power savings */
+
+	Offset (0xC38),
+		,   3,
+	P0RM,   1,      /* Robust squelch mechanism */
+}
+
+// Enter L23
+Method (DL23, 0, Serialized) {
+	Printf("      GPU PORT DL23 START")
+
+	L23E = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23E) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+
+	P0RM = 1
+	P0AP = 3
+
+	Printf("      GPU PORT DL23 FINISH")
+}
+
+// Exit L23
+Method (L23D, 0, Serialized) {
+	Printf("      GPU PORT L23D START")
+
+	L23R = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23R) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+
+	P0RM = 0
+	P0AP = 0
+
+	Printf("      GPU PORT L23D FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PORT PWRR._ON")
+
+		^^DEV0._ON()
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PORT PWRR._OFF")
+
+		^^DEV0._OFF()
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
+
+#include "common/gpu.asl"

src/drivers/gfx/nvidia/acpi/common/dsm.asl

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define NV_ERROR_SUCCESS 0x0
+#define NV_ERROR_UNSPECIFIED 0x80000001
+#define NV_ERROR_UNSUPPORTED 0x80000002
+
+#include "gps.asl"
+#include "nvjt.asl"
+
+Method (_DSM, 4, Serialized) {
+	Printf("GPU _DSM")
+	If (Arg0 == ToUUID (JT_DSM_GUID)) {
+		If (ToInteger(Arg1) >= JT_REVISION_ID_MIN) {
+			Return (NVJT(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported JT revision: %o", SFST(Arg1))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	} ElseIf (Arg0 == ToUUID (GPS_DSM_GUID)) {
+		If (ToInteger(Arg1) == GPS_REVISION_ID) {
+			Return (GPS(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported GPS revision: %o", SFST(Arg1))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	} Else {
+		Printf("  Unsupported GUID: %o", IDST(Arg0))
+		Return (NV_ERROR_UNSPECIFIED)
+	}
+}

src/drivers/gfx/nvidia/acpi/common/gps.asl

@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define GPS_DSM_GUID "A3132D01-8CDA-49BA-A52E-BC9D46DF6B81"
+#define GPS_REVISION_ID 0x00000200
+#define GPS_FUNC_SUPPORT 0x00000000
+#define GPS_FUNC_PSHARESTATUS 0x00000020
+#define GPS_FUNC_PSHAREPARAMS 0x0000002A
+
+Method(GPS, 2, Serialized) {
+	Printf("  GPU GPS")
+	Switch(ToInteger(Arg0)) {
+		Case(GPS_FUNC_SUPPORT) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << GPS_FUNC_SUPPORT) |
+				(1 << GPS_FUNC_PSHARESTATUS) |
+				(1 << GPS_FUNC_PSHAREPARAMS)
+			))
+		}
+		Case(GPS_FUNC_PSHARESTATUS) {
+			Printf("    Power Share Status")
+			Return(ITOB(0))
+		}
+		Case(GPS_FUNC_PSHAREPARAMS) {
+			Printf("    Power Share Parameters")
+
+			CreateField(Arg1, 0, 4, QTYP) // Query type
+
+			Name(GPSP, Buffer(36) { 0x00 })
+			CreateDWordField(GPSP, 0, RSTS) // Response status
+			CreateDWordField(GPSP, 4, VERS) // Version
+
+			// Set query type of response
+			RSTS = QTYP
+			// Set version of response
+			VERS = 0x00010000
+
+			Switch(ToInteger(QTYP)) {
+				Case(0) {
+					Printf("      Request Current Information")
+					// No required information
+					Return(GPSP)
+				}
+				Case(1) {
+					Printf("      Request Supported Fields")
+					// Support GPU temperature field
+					RSTS |= (1 << 8)
+					Return(GPSP)
+				}
+				Case(2) {
+					Printf("      Request Current Limits")
+					// No required limits
+					Return(GPSP)
+				}
+				Default {
+					Printf("      Unknown Query: %o", SFST(QTYP))
+					Return(NV_ERROR_UNSUPPORTED)
+				}
+			}
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return(NV_ERROR_UNSUPPORTED)
+		}
+	}
+}

src/drivers/gfx/nvidia/acpi/common/gpu.asl

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (DEV0) {
+	Name(_ADR, 0x00000000)
+
+	#include "utility.asl"
+	#include "dsm.asl"
+	#include "power.asl"
+}
+
+#if CONFIG(DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST)
+Scope (\_SB) {
+	Device(NPCF) {
+		#include "utility.asl"
+		#include "nvpcf.asl"
+	}
+}
+#endif

src/drivers/gfx/nvidia/acpi/common/nvjt.asl

@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define JT_DSM_GUID "CBECA351-067B-4924-9CBD-B46B00B86F34"
+#define JT_REVISION_ID_MIN 0x00000100
+#define JT_REVISION_ID_MAX 0x00000200
+#define JT_FUNC_SUPPORT 0x00000000
+#define JT_FUNC_CAPS 0x00000001
+#define JT_FUNC_POWERCONTROL 0x00000003
+
+//TODO: SMI traps and EGIN/XCLM
+#define JT_GPC_GSS 0 // Get current GPU GCx sleep status
+#define JT_GPC_EGNS 1 // Enter GC6 without self-refresh
+#define JT_GPC_EGIS 2 // Enter GC6 with self-refresh
+#define JT_GPC_XGXS 3 // Exit GC6 and stop self-refresh
+#define JT_GPC_XGIS 4 // Exit GC6 for self-refresh update
+
+#define JT_DFGC_NONE 0 // Handle request immediately
+#define JT_DFGC_DEFER 1 // Defer GPC and GPCX
+//TODO #define JT_DFGC_CLEAR 2 // Clear pending requests
+
+// Deferred GC6 enter/exit until D3-cold (saved DFGC)
+Name(DFEN, 0)
+
+// Deferred GC6 enter control (saved GPC)
+Name(DFCI, 0)
+
+// Deferred GC6 exit control (saved GPCX)
+Name(DFCO, 0)
+
+Method (NVJT, 2, Serialized) {
+	Printf("  GPU NVJT")
+	Switch (ToInteger(Arg0)) {
+		Case (JT_FUNC_SUPPORT) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << JT_FUNC_SUPPORT) |
+				(1 << JT_FUNC_CAPS) |
+				(1 << JT_FUNC_POWERCONTROL)
+			))
+		}
+		Case (JT_FUNC_CAPS) {
+			Printf("    Capabilities")
+			Return(ITOB(
+				(1 << 0) | // G-SYNC NSVR power-saving features are enabled
+				(1 << 1) | // NVSR disabled
+				(2 << 3) | // Panel power and backlight are on the suspend rail
+				(0 << 5) | // self-refresh controller remains powered while panel is powered
+				(0 << 6) | // FB is not on the suspend rail but is powered on in GC6
+				(0 << 8) | // Combined power rail for all GPUs
+				(0 << 10) | // External SPI ROM
+				(1 << 11) | // No SMI handler for kernel panic exit while in GC6
+				(0 << 12) | // Supports notify on GC6 state done
+				(1 << 13) | // Support deferred GC6
+				(1 << 14) | // Support fine-grained root port control
+				(2 << 15) | // GC6 version is GC6-R
+				(0 << 17) | // GC6 exit ISR is not supported
+				(0 << 18) | // GC6 self wakeup not supported
+				(JT_REVISION_ID_MAX << 20) // Highest revision supported
+			))
+		}
+		Case (JT_FUNC_POWERCONTROL) {
+			Printf("    Power Control: %o", SFST(Arg1))
+
+			CreateField (Arg1, 0, 3, GPC) // GPU power control
+			CreateField (Arg1, 4, 1, PPC) // Panel power control
+			CreateField (Arg1, 14, 2, DFGC) // Defer GC6 enter/exit until D3 cold
+			CreateField (Arg1, 16, 3, GPCX) // Deferred GC6 exit control
+
+			// Save deferred GC6 request
+			If ((ToInteger(GPC) != 0) || (ToInteger(DFGC) != 0)) {
+				DFEN = DFGC
+				DFCI = GPC
+				DFCO = GPCX
+			}
+
+			// Buffer to cache current state
+			Name (JTBF, Buffer (4) { 0, 0, 0, 0 })
+			CreateField (JTBF, 0, 3, CGCS) // Current GC state
+			CreateField (JTBF, 3, 1, CGPS) // Current GPU power status
+			CreateField (JTBF, 7, 1, CPSS) // Current panel and SRC state (0 when on)
+
+			// If doing deferred GC6 request, return now
+			If (ToInteger(DFGC) != 0) {
+				CGCS = 1
+				CGPS = 1
+				Return (JTBF)
+			}
+
+			// Apply requested state
+			Switch (ToInteger(GPC)) {
+				Case (JT_GPC_GSS) {
+					Printf("    Get current GPU GCx sleep status")
+					//TODO: include transitions!
+					If (GTXS(DGPU_RST_N)) {
+						// GPU powered on
+						CGCS = 1
+						CGPS = 1
+					} ElseIf (GTXS(DGPU_PWR_EN)) {
+						// GPU powered off, GC6
+						CGCS = 3
+						CGPS = 0
+					} Else {
+						// GPU powered off, D3 cold
+						CGCS = 2
+						CGPS = 0
+					}
+				}
+				Case (JT_GPC_EGNS) {
+					Printf("    Enter GC6 without self-refresh")
+					GC6I()
+					CPSS = 1
+				}
+				Case (JT_GPC_EGIS) {
+					Printf("    Enter GC6 with self-refresh")
+					GC6I()
+					If (ToInteger(PPC) == 0) {
+						CPSS = 0
+					}
+				}
+				Case (JT_GPC_XGXS) {
+					Printf("    Exit GC6 and stop self-refresh")
+					GC6O()
+
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger(PPC) != 0) {
+						CPSS = 0
+					}
+				}
+				Case (JT_GPC_XGIS) {
+					Printf("    Exit GC6 for self-refresh update")
+					GC6O()
+
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger(PPC) != 0) {
+						CPSS = 0
+					}
+				}
+				Default {
+					Printf("    Unsupported GPU power control: %o", SFST(GPC))
+				}
+			}
+
+			Return (JTBF)
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	}
+}

src/drivers/gfx/nvidia/acpi/common/nvpcf.asl

@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define NVPCF_DSM_GUID "36b49710-2483-11e7-9598-0800200c9a66"
+#define NVPCF_REVISION_ID 0x00000200
+#define NVPCF_ERROR_SUCCESS 0x0
+#define NVPCF_ERROR_GENERIC 0x80000001
+#define NVPCF_ERROR_UNSUPPORTED 0x80000002
+#define NVPCF_FUNC_GET_SUPPORTED 0x00000000
+#define NVPCF_FUNC_GET_STATIC_CONFIG_TABLES 0x00000001
+#define NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS 0x00000002
+
+Name(_HID, "NVDA0820")
+
+Name(_UID, "NPCF")
+
+Method(_DSM, 4, Serialized) {
+	Printf("NVPCF _DSM")
+	If (Arg0 == ToUUID(NVPCF_DSM_GUID)) {
+		If (ToInteger(Arg1) == NVPCF_REVISION_ID) {
+			Return(NPCF(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported NVPCF revision: %o", SFST(Arg1))
+			Return(NVPCF_ERROR_GENERIC)
+		}
+	} Else {
+		Printf("  Unsupported GUID: %o", IDST(Arg0))
+		Return(NVPCF_ERROR_GENERIC)
+	}
+}
+
+Method(NPCF, 2, Serialized) {
+	Printf("  NVPCF NPCF")
+	Switch(ToInteger(Arg0)) {
+		Case(NVPCF_FUNC_GET_SUPPORTED) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << NVPCF_FUNC_GET_SUPPORTED) |
+				(1 << NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) |
+				(1 << NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS)
+			))
+		}
+		Case(NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) {
+			Printf("    Get Static Config")
+			Return(Buffer(14) {
+				// Device table header
+				0x20, 0x03, 0x01,
+				// Intel + NVIDIA
+				0x00,
+				// Controller table header
+				0x23, 0x04, 0x05, 0x01,
+				// Dynamic boost controller
+				0x01,
+				// Supports DC
+				0x01,
+				// Reserved
+				0x00, 0x00, 0x00,
+				// Checksum
+				0xAD
+			})
+		}
+		Case(NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS) {
+			Printf("    Update Dynamic Boost")
+
+			CreateField(Arg1, 0x28, 2, ICMD) // Input command
+
+			Name(PCFP, Buffer(49) {
+				// Table version
+				0x23,
+				// Table header size
+				0x05,
+				// Size of common status in bytes
+				0x10,
+				// Size of controller entry in bytes
+				0x1C,
+				// Other fields filled in later
+			})
+			CreateByteField(PCFP, 0x04, CCNT) // Controller count
+			CreateWordField(PCFP, 0x19, ATPP) // AC TPP offset
+			CreateWordField(PCFP, 0x1D, AMXP) // AC maximum TGP offset
+			CreateWordField(PCFP, 0x21, AMNP) // AC minimum TGP offset
+
+			Switch(ToInteger(ICMD)) {
+				Case(0) {
+					Printf("      Get Controller Params")
+					// Number of controllers
+					CCNT = 1
+					// AC total processor power offset from default TGP in 1/8 watt units
+					ATPP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP << 3)
+					// AC maximum TGP offset from default TGP in 1/8 watt units
+					AMXP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX << 3)
+					// AC minimum TGP offset from default TGP in 1/8 watt units
+					AMNP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN << 3)
+					Printf("PCFP: %o", SFST(PCFP))
+					Return(PCFP)
+				}
+				Case(1) {
+					Printf("      Set Controller Status")
+					//TODO
+					Printf("PCFP: %o", SFST(PCFP))
+					Return(PCFP)
+				}
+				Default {
+					Printf("      Unknown Input Command: %o", SFST(ICMD))
+					Return(NV_ERROR_UNSUPPORTED)
+				}
+			}
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return(NVPCF_ERROR_UNSUPPORTED)
+		}
+	}
+}

src/drivers/gfx/nvidia/acpi/common/power.asl

@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+//TODO: evaluate sleeps
+
+OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
+Field (PCIC, DwordAcc, NoLock, Preserve) {
+	Offset (0x40),
+	SSID, 32, // Subsystem vendor and product ID
+}
+
+// Enter GC6
+Method(GC6I, 0, Serialized) {
+	Printf("    GPU GC6I START")
+
+	// Enter L23
+	^^DL23()
+	Sleep(5)
+
+	// Put GPU into reset
+	Printf("      Put GPU into reset")
+	CTXS(DGPU_RST_N)
+	Sleep(5)
+
+	Printf("    GPU GC6I FINISH")
+}
+
+// Exit GC6
+Method(GC6O, 0, Serialized) {
+	Printf("    GPU GC6O START")
+
+	// Bring GPU out of reset
+	Printf("      Bring GPU out of reset")
+	STXS(DGPU_RST_N)
+	Sleep(5)
+
+	// Exit L23
+	^^L23D()
+	Sleep(5)
+
+	Printf("    GPU GC6O FINISH")
+}
+
+Method (_ON, 0, Serialized) {
+	Printf("  GPU _ON START")
+
+	If (DFEN == JT_DFGC_DEFER) {
+		Switch (ToInteger(DFCO)) {
+			Case (JT_GPC_XGXS) {
+				Printf("    Exit GC6 and stop self-refresh")
+				GC6O()
+			}
+			Default {
+				Printf("    Unsupported DFCO: %o", SFST(DFCO))
+			}
+		}
+		DFEN = JT_DFGC_NONE
+	} Else {
+		Printf("    Standard RTD3 power on")
+		STXS(DGPU_PWR_EN)
+		Sleep(5)
+		GC6O()
+	}
+
+	Printf("  GPU _ON FINISH")
+}
+
+Method (_OFF, 0, Serialized) {
+	Printf("  GPU _OFF START")
+
+	If (DFEN == JT_DFGC_DEFER) {
+		Switch (ToInteger(DFCI)) {
+			Case (JT_GPC_EGNS) {
+				Printf("    Enter GC6 without self-refresh")
+				GC6I()
+			}
+			Case (JT_GPC_EGIS) {
+				Printf("    Enter GC6 with self-refresh")
+				GC6I()
+			}
+			Default {
+				Printf("    Unsupported DFCI: %o", SFST(DFCI))
+			}
+		}
+		DFEN = JT_DFGC_NONE
+	} Else {
+		Printf("    Standard RTD3 power off")
+		GC6I()
+		CTXS(DGPU_PWR_EN)
+		Sleep(5)
+	}
+
+	Printf("  GPU _OFF FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PWRR._ON")
+
+		// Restore SSID
+		^^SSID = DGPU_SSID
+		Printf("  Restore SSID: %o", SFST(^^SSID))
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PWRR._OFF")
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })

src/drivers/gfx/nvidia/acpi/common/utility.asl

@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Convert a byte to a hex string, trimming extra parts
+Method (BHEX, 1) {
+	Local0 = ToHexString(Arg0)
+	Return (Mid(Local0, SizeOf(Local0) - 2, 2))
+}
+
+// UUID to string
+Method (IDST, 1) {
+	Local0 = ""
+	Fprintf(
+		Local0,
+		"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
+		BHEX(DerefOf(Arg0[3])),
+		BHEX(DerefOf(Arg0[2])),
+		BHEX(DerefOf(Arg0[1])),
+		BHEX(DerefOf(Arg0[0])),
+		BHEX(DerefOf(Arg0[5])),
+		BHEX(DerefOf(Arg0[4])),
+		BHEX(DerefOf(Arg0[7])),
+		BHEX(DerefOf(Arg0[6])),
+		BHEX(DerefOf(Arg0[8])),
+		BHEX(DerefOf(Arg0[9])),
+		BHEX(DerefOf(Arg0[10])),
+		BHEX(DerefOf(Arg0[11])),
+		BHEX(DerefOf(Arg0[12])),
+		BHEX(DerefOf(Arg0[13])),
+		BHEX(DerefOf(Arg0[14])),
+		BHEX(DerefOf(Arg0[15]))
+	)
+	Return (Local0)
+}
+
+// Safe hex conversion, checks type first
+Method (SFST, 1) {
+	Local0 = ObjectType(Arg0)
+	If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
+		Return (ToHexString(Arg0))
+	} Else {
+		Return (Concatenate("Type: ", Arg0))
+	}
+}
+
+// Convert from 4-byte buffer to 32-bit integer
+Method (BTOI, 1) {
+	Return(
+		DerefOf(Arg0[0]) |
+		(DerefOf(Arg0[1]) << 8) |
+		(DerefOf(Arg0[2]) << 16) |
+		(DerefOf(Arg0[3]) << 24)
+	)
+}
+
+// Convert from 32-bit integer to 4-byte buffer
+Method (ITOB, 1) {
+	Local0 = Buffer(4) { 0, 0, 0, 0 }
+	Local0[0] = Arg0 & 0xFF
+	Local0[1] = (Arg0 >> 8) & 0xFF
+	Local0[2] = (Arg0 >> 16) & 0xFF
+	Local0[3] = (Arg0 >> 24) & 0xFF
+	Return (Local0)
+}

src/drivers/gfx/nvidia/acpi/tigerlake.asl

@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* NVIDIA GC6 on (TGL and ADL) (CPU and PCH) PCIe ports */
+
+// Port mapped PCI express config space
+OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
+
+Field (PCIC, AnyAcc, NoLock, Preserve) {
+	Offset(0x52),  /* LSTS - Link Status Register */
+	, 13,
+	LASX, 1,       /* 0, Link Active Status */
+
+	Offset(0x60),  /* RSTS - Root Status Register */
+	, 16,
+	PSPX, 1,       /* 16,  PME Status */
+
+	Offset(0xD8),  /* 0xD8, MPC - Miscellaneous Port Configuration Register */
+	, 30,
+	HPEX, 1,       /* 30,  Hot Plug SCI Enable */
+	PMEX, 1,       /* 31,  Power Management SCI Enable */
+
+	Offset (0xE0), /* 0xE0, SPR - Scratch Pad Register */
+	SCB0, 1,       /* Scratch bit 0 */
+
+	Offset(0xE2),  /* 0xE2, RPPGEN - Root Port Power Gating Enable */
+	, 2,
+	L23E, 1,       /* 2,   L23_Rdy Entry Request (L23ER) */
+	L23R, 1,       /* 3,   L23_Rdy to Detect Transition (L23R2DT) */
+}
+
+Field (PCIC, AnyAcc, NoLock, WriteAsZeros) {
+	Offset(0xDC),  /* 0xDC, SMSCS - SMI/SCI Status Register */
+	, 30,
+	HPSX, 1,       /* 30,  Hot Plug SCI Status */
+	PMSX, 1        /* 31,  Power Management SCI Status */
+}
+
+// Enter L23
+Method (DL23, 0, Serialized) {
+	Printf("      GPU PORT DL23 START")
+
+	L23E = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23E) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+	SCB0 = 1
+
+	Printf("      GPU PORT DL23 FINISH")
+}
+
+// Exit L23
+Method (L23D, 0, Serialized) {
+	Printf("      GPU PORT L23D START")
+
+	If ((SCB0 == 1)) {
+		L23R = 1
+		Local0 = 0
+		While (L23R) {
+			If ((Local0 > 4)) {
+				Break
+			}
+			Sleep (16)
+			Local0++
+		}
+
+		SCB0 = 0
+		Local0 = 0
+		While ((LASX == 0)) {
+			If ((Local0 > 8)) {
+				Break
+			}
+			Sleep (16)
+			Local0++
+		}
+	}
+
+	Printf("      GPU PORT L23D FINISH")
+}
+
+Method (HPME, 0, Serialized) {
+	Printf("  GPU PORT HPME START")
+
+	If (PMSX == 1) {
+		Printf("    Notify GPU driver of PME SCI")
+		Notify(DEV0, 0x2)
+		Printf("    Clear PME SCI")
+		PMSX = 1
+		Printf("    Consume PME notification")
+		PSPX = 1
+	}
+
+	Printf("  GPU PORT HPME FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PORT PWRR._ON")
+
+		HPME();
+		If (PMEX == 1) {
+			Printf("  Disable power management SCI")
+			PMEX = 0
+		}
+
+		^^DEV0._ON()
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PORT PWRR._OFF")
+
+		^^DEV0._OFF()
+
+		If (PMEX == 0) {
+			Printf("  Enable power management SCI")
+			PMEX = 1
+			HPME()
+		}
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
+
+#include "common/gpu.asl"

src/drivers/gfx/nvidia/chip.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_
+#define _DRIVERS_GFX_NVIDIA_CHIP_H_
+
+struct drivers_gfx_nvidia_config {
+	/* TODO: Set GPIOs in devicetree? */
+};
+
+#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */

src/drivers/gfx/nvidia/gpu.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_
+#define _DRIVERS_GFX_NVIDIA_GPU_H_
+
+#include <stdbool.h>
+
+struct nvidia_gpu_config {
+	/* GPIO for GPU_PWR_EN */
+	unsigned int power_gpio;
+	/* GPIO for GPU_RST# */
+	unsigned int reset_gpio;
+	/* Enable or disable GPU power */
+	bool enable;
+};
+
+void nvidia_set_power(const struct nvidia_gpu_config *config);
+
+#endif /* _DRIVERS_NVIDIA_GPU_H_ */

src/drivers/gfx/nvidia/nvidia.c

@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40
+
+static void nvidia_read_resources(struct device *dev)
+{
+	printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev));
+
+	pci_dev_read_resources(dev);
+
+	// Find all BARs on GPU, mark them above 4g if prefetchable
+	for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
+		struct resource *res = probe_resource(dev, bar);
+
+		if (res) {
+			if (res->flags & IORESOURCE_PREFETCH) {
+				printk(BIOS_INFO, "  BAR at 0x%02x marked above 4g\n", bar);
+				res->flags |= IORESOURCE_ABOVE_4G;
+			} else {
+				printk(BIOS_DEBUG, "  BAR at 0x%02x not prefetch\n", bar);
+			}
+		} else {
+			printk(BIOS_DEBUG, "  BAR at 0x%02x not found\n", bar);
+		}
+	}
+}
+
+static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
+{
+	pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations nvidia_device_ops_pci = {
+	.set_subsystem = nvidia_set_subsystem,
+};
+
+static struct device_operations nvidia_device_ops = {
+	.read_resources   = nvidia_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.write_acpi_tables = pci_rom_write_acpi_tables,
+	.acpi_fill_ssdt    = pci_rom_ssdt,
+#endif
+	.init             = pci_dev_init,
+	.ops_pci          = &nvidia_device_ops_pci,
+
+};
+
+static void nvidia_enable(struct device *dev)
+{
+	if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
+		return;
+
+	if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_NVIDIA)
+		return;
+
+	dev->ops = &nvidia_device_ops;
+}
+
+struct chip_operations drivers_gfx_nvidia_ops = {
+	.name = "NVIDIA Optimus Graphics Device",
+	.enable_dev = nvidia_enable
+};

src/drivers/gfx/nvidia/romstage.c

@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <gpio.h>
+#include "chip.h"
+#include "gpu.h"
+
+void nvidia_set_power(const struct nvidia_gpu_config *config)
+{
+	if (!config->power_gpio || !config->reset_gpio) {
+		printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__);
+		return;
+	}
+
+	printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio);
+	printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio);
+
+	gpio_set(config->reset_gpio, 0);
+	mdelay(10);
+
+	if (config->enable) {
+		gpio_set(config->power_gpio, 1);
+		mdelay(25);
+		gpio_set(config->reset_gpio, 1);
+	} else {
+		gpio_set(config->power_gpio, 0);
+	}
+
+	mdelay(10);
+}

src/ec/dasharo/ec/Kconfig

@@ -1,21 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-config EC_DASHARO_EC
-	bool
-	help
-	  Dasharo EC
-
-config EC_DASHARO_EC_BAT_THRESHOLDS
-	depends on EC_DASHARO_EC
-	bool
-	default y
-
-config EC_DASHARO_EC_DGPU
-	depends on EC_DASHARO_EC
-	bool
-	default n
-
-config EC_DASHARO_EC_OLED
-	depends on EC_DASHARO_EC
-	bool
-	default n

src/ec/dasharo/ec/Makefile.mk

@@ -1,10 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-ifeq ($(CONFIG_EC_DASHARO_EC),y)
-
-all-y += dasharo_ec.c
-
-ramstage-y += smbios.c
-
-smm-$(CONFIG_DEBUG_SMI) += dasharo_ec.c
-
-endif

src/ec/dasharo/ec/acpi/ac.asl

@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Device (AC)
-{
-	Name (_HID, "ACPI0003" /* Power Source Device */)
-	Name (_PCL, Package (0x01)  // _PCL: Power Consumer List
-	{
-		_SB
-	})
-
-	Name (ACFG, 1)
-
-	Method (_PSR, 0, NotSerialized)  // _PSR: Power Source
-	{
-		Return (ACFG)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		Return (0x0F)
-	}
-}

src/ec/dasharo/ec/acpi/battery.asl

@@ -1,248 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Device (BAT0)
-{
-	Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */)
-	Name (_UID, 0)
-	Name (_PCL, Package (0x01)  // _PCL: Power Consumer List
-	{
-		_SB
-	})
-	Name (BFCC, 0)
-	Method (_STA, 0, NotSerialized)
-	{
-		If (^^PCI0.LPCB.EC0.ECOK)
-		{
-			If (^^PCI0.LPCB.EC0.BAT0)
-			{
-				Return (0x1F)
-			}
-			Else
-			{
-				Return (0x0F)
-			}
-		}
-		Else
-		{
-			Return (0x0F)
-		}
-	}
-
-	Name (PBIF, Package (0x0D)
-	{
-		1, // 0 - Power Unit
-		0xFFFFFFFF, // 1 - Design Capacity
-		0xFFFFFFFF, // 2 - Last Full Charge Capacity
-		1, // 3 - Battery Technology
-		0xFFFFFFFF, // 4 - Design Voltage
-		0, // 5 - Design Capacity of Warning
-		0, // 6 - Design Capacity of Low
-		0x40, // 7 - Battery Capacity Granularity 1
-		0x40, // 8 - Battery Capacity Granularity 2
-		" ", // 9 - Model Number
-		" ", // 10 - Serial Number
-		" ", // 11 - Battery Type
-		" " // 12 - OEM Information
-	})
-	Method (IVBI, 0, NotSerialized)
-	{
-		PBIF [1] = 0xFFFFFFFF
-		PBIF [2] = 0xFFFFFFFF
-		PBIF [4] = 0xFFFFFFFF
-		PBIF [9] = " "
-		PBIF [10] = " "
-		PBIF [11] = " "
-		PBIF [12] = " "
-		BFCC = 0
-	}
-
-	Method (UPBI, 0, NotSerialized)
-	{
-		If (^^PCI0.LPCB.EC0.BAT0)
-		{
-			Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
-			PBIF [1] = Local0
-			Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
-			PBIF [2] = Local0
-			BFCC = Local0
-			Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
-			PBIF [4] = Local0
-			Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
-			PBIF [5] = Local0
-			Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
-			PBIF [6] = Local0
-			PBIF [9] = "BAT"
-			PBIF [10] = "0001"
-			PBIF [11] = "LION"
-			PBIF [12] = "Notebook"
-		}
-		Else
-		{
-			IVBI ()
-		}
-	}
-
-	Method (_BIF, 0, NotSerialized)  // _BIF: Battery Information
-	{
-		If (^^PCI0.LPCB.EC0.ECOK)
-		{
-			UPBI ()
-		}
-		Else
-		{
-			IVBI ()
-		}
-
-		Return (PBIF) /* \_SB_.BAT0.PBIF */
-	}
-
-	Name (PBIX, Package ()
-	{
-		0, // 0 - Revision
-		1, // 1 - Power Unit: mAh
-		0xFFFFFFFF, // 2 - Design Capacity
-		0xFFFFFFFF, // 3 - Last Full Charge Capacity
-		1, // 4 - Battery Technology: Rechargeable
-		0xFFFFFFFF, // 5 - Design Voltage
-		0, // 6 - Design Capacity of Warning
-		0, // 7 - Design Capacity of Low
-		0, // 8 - Cycle Count
-		98000, // 9 - Measurement Accuracy
-		0xFFFFFFFF, // 10 - Max Sampling Time
-		0xFFFFFFFF, // 11 - Min Sampling Time
-		0xFFFFFFFF, // 12 - Max Averaging Interval
-		0xFFFFFFFF, // 13 - Min Averaging Interval
-		0x40, // 14 - Battery Capacity Granularity 1
-		0x40, // 15 - Battery Capacity Granularity 2
-		" ", // 16 - Model Number
-		" ", // 17 - Serial Number
-		" ", // 18 - Battery Type
-		" " // 19 - OEM Information
-	})
-
-	Method (IVBX, 0, NotSerialized)
-	{
-		PBIX [2] = 0xFFFFFFFF
-		PBIX [3] = 0xFFFFFFFF
-		PBIX [5] = 0xFFFFFFFF
-		PBIX [16] = " "
-		PBIX [17] = " "
-		PBIX [18] = " "
-		PBIX [19] = " "
-		BFCC = 0
-	}
-
-	Method (UPBX, 0, NotSerialized)
-	{
-		If (^^PCI0.LPCB.EC0.BAT0)
-		{
-			Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
-			PBIX [2] = Local0
-			Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
-			PBIX [3] = Local0
-			BFCC = Local0
-			Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
-			PBIX [5] = Local0
-			Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
-			PBIX [6] = Local0
-			Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
-			PBIX [7] = Local0
-			LOCAL0 = ^^PCI0.LPCB.EC0.CYC0
-			PBIX [8] = LOCAL0
-			PBIX [16] = "BAT"
-			PBIX [17] = "0001"
-			PBIX [18] = "LION"
-			PBIX [19] = "Notebook"
-		}
-		Else
-		{
-			IVBX ()
-		}
-	}
-
-	// _BIX: Battery Information Extended
-	Method (_BIX, 0, NotSerialized)
-	{
-		If (^^PCI0.LPCB.EC0.ECOK)
-		{
-			UPBX ()
-		}
-		Else
-		{
-			IVBX ()
-		}
-		Return (PBIX) /* \_SB_.BAT0.PBIX */
-	}
-
-	Name (PBST, Package (0x04)
-	{
-		0, // 0 - Battery state
-		0xFFFFFFFF, // 1 - Battery present rate
-		0xFFFFFFFF, // 2 - Battery remaining capacity
-		0xFFFFFFFF // 3 - Battery present voltage
-	})
-	Method (IVBS, 0, NotSerialized)
-	{
-		PBST [0] = 0
-		PBST [1] = 0xFFFFFFFF
-		PBST [2] = 0xFFFFFFFF
-		PBST [3] = 0xFFFFFFFF
-	}
-
-	Method (UPBS, 0, NotSerialized)
-	{
-		If (^^PCI0.LPCB.EC0.BAT0)
-		{
-			Local0 = 0
-			Local1 = 0
-			If (^^AC.ACFG)
-			{
-				If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02))
-				{
-					Local0 |= 0x02
-					Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
-				}
-			}
-			Else
-			{
-				Local0 |= 1
-				Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
-			}
-
-			Local7 = (Local1 & 0x8000)
-			If ((Local7 == 0x8000))
-			{
-				Local1 ^= 0xFFFF
-			}
-
-			Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF)
-			Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF)
-			PBST [0] = Local0
-			PBST [1] = Local1
-			PBST [2] = Local2
-			PBST [3] = Local3
-			If ((BFCC != ^^PCI0.LPCB.EC0.BFC0))
-			{
-				Notify (BAT0, 0x81) // Information Change
-			}
-		}
-		Else
-		{
-			IVBS ()
-		}
-	}
-
-	Method (_BST, 0, NotSerialized)  // _BST: Battery Status
-	{
-		If (^^PCI0.LPCB.EC0.ECOK)
-		{
-			UPBS ()
-		}
-		Else
-		{
-			IVBS ()
-		}
-
-		Return (PBST) /* \_SB_.BAT0.PBST */
-	}
-}

src/ec/dasharo/ec/acpi/battery_thresholds.asl

@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Field (ERAM, ByteAcc, Lock, Preserve)
-{
-	Offset (0xBC),
-	BTL0,   8,      /* BAT0 charging start threshold */
-	BTH0,   8,      /* BAT0 charging end threshold */
-}
-
-/*
- * Get battery charging threshold
- *
- * Arg0: 0: Start threshold
- *       1: Stop threshold
- */
-Method (GBCT, 1, NotSerialized)
-{
-	If (Arg0 == 0) {
-		Return (BTL0)
-	}
-
-	If (Arg0 == 1) {
-		Return (BTH0)
-	}
-
-	Return (0xFF)
-}
-
-/*
- * Set battery charging threshold
- *
- * Arg0: 0: Start threshold
- *       1: Stop threshold
- * Arg1: Percentage
- */
-Method (SBCT, 2, NotSerialized)
-{
-	If (Arg1 <= 100) {
-		If (Arg0 == 0) {
-			BTL0 = Arg1
-		}
-		If (Arg0 == 1) {
-			BTH0 = Arg1
-		}
-	}
-}

src/ec/dasharo/ec/acpi/buttons.asl

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Device (PWRB)
-{
-	Name (_HID, EisaId ("PNP0C0C"))
-	Name (_PRW, Package () { EC_GPE_SWI, 3 })
-}
-
-Device (SLPB)
-{
-	Name (_HID, EisaId ("PNP0C0E"))
-	Name (_PRW, Package () { EC_GPE_SWI, 3 })
-}

src/ec/dasharo/ec/acpi/ec.asl

@@ -1,241 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope (\_SB) {
-	#include "ac.asl"
-	#include "battery.asl"
-	#include "buttons.asl"
-	#include "hid.asl"
-	#include "lid.asl"
-	#include "s76.asl"
-}
-
-Device (\_SB.PCI0.LPCB.EC0)
-{
-	Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */)
-	Name (_GPE, EC_GPE_SCI)  // _GPE: General Purpose Events
-	Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-	{
-		IO (Decode16,
-			0x0062,             // Range Minimum
-			0x0062,             // Range Maximum
-			0x00,               // Alignment
-			0x01,               // Length
-			)
-		IO (Decode16,
-			0x0066,             // Range Minimum
-			0x0066,             // Range Maximum
-			0x00,               // Alignment
-			0x01,               // Length
-			)
-	})
-
-	#include "ec_ram.asl"
-
-	Name (ECOK, 0)
-	Method (_REG, 2, Serialized)  // _REG: Region Availability
-	{
-		Printf ("EC: _REG %o %o", ToHexString(Arg0), ToHexString(Arg1))
-		If ((Arg0 == 0x03) && (Arg1 == 1)) {
-			// Enable hardware touchpad lock, airplane mode, and keyboard backlight keys
-			ECOS = 1
-
-			// Enable software display brightness keys
-			WINF = 1
-
-			// Set current AC state
-			^^^^AC.ACFG = ADP
-			// Update battery information and status
-			^^^^BAT0.UPBI()
-			^^^^BAT0.UPBS()
-
-			// Notify of changes
-			Notify(^^^^AC, 0)
-			Notify(^^^^BAT0, 0)
-
-			PNOT ()
-
-			// EC is now available
-			ECOK = Arg1
-
-			// Reset Dasharo Device
-			^^^^S76D.RSET()
-		}
-	}
-
-	Name (S3OS, 0)
-	Method (PTS, 1, Serialized) {
-		Printf ("EC: PTS: %o", ToHexString(Arg0))
-		If (ECOK) {
-			// Save ECOS during sleep
-			S3OS = ECOS
-
-			// Clear wake cause
-			WFNO = 0
-		}
-	}
-
-	Method (WAK, 1, Serialized) {
-		Printf ("EC: WAK: %o", ToHexString(Arg0))
-		If (ECOK) {
-			// Restore ECOS after sleep
-			ECOS = S3OS
-
-			// Set current AC state
-			^^^^AC.ACFG = ADP
-
-			// Update battery information and status
-			^^^^BAT0.UPBI()
-			^^^^BAT0.UPBS()
-
-			// Notify of changes
-			Notify(^^^^AC, 0)
-			Notify(^^^^BAT0, 0)
-		}
-	}
-
-	Method (_Q0A, 0, NotSerialized) // Touchpad Toggle
-	{
-		Printf ("EC: Touchpad Toggle")
-	}
-
-	Method (_Q0B, 0, NotSerialized) // Screen Toggle
-	{
-		Printf ("EC: Screen Toggle")
-#if CONFIG(EC_DASHARO_EC_OLED)
-		Notify (^^^^S76D, 0x85)
-#endif // CONFIG(EC_DASHARO_EC_OLED)
-	}
-
-	Method (_Q0C, 0, NotSerialized)  // Mute
-	{
-		Printf ("EC: Mute")
-	}
-
-	Method (_Q0D, 0, NotSerialized) // Keyboard Backlight
-	{
-		Printf ("EC: Keyboard Backlight")
-	}
-
-	Method (_Q0E, 0, NotSerialized) // Volume Down
-	{
-		Printf ("EC: Volume Down")
-	}
-
-	Method (_Q0F, 0, NotSerialized) // Volume Up
-	{
-		Printf ("EC: Volume Up")
-	}
-
-	Method (_Q10, 0, NotSerialized) // Switch Video Mode
-	{
-		Printf ("EC: Switch Video Mode")
-	}
-
-	Method (_Q11, 0, NotSerialized) // Brightness Down
-	{
-		Printf ("EC: Brightness Down")
-		if (^^^^HIDD.HRDY) {
-			^^^^HIDD.HPEM (20)
-		}
-	}
-
-	Method (_Q12, 0, NotSerialized) // Brightness Up
-	{
-		Printf ("EC: Brightness Up")
-		if (^^^^HIDD.HRDY) {
-			^^^^HIDD.HPEM (19)
-		}
-	}
-
-	Method (_Q13, 0, NotSerialized) // Camera Toggle
-	{
-		Printf ("EC: Camera Toggle")
-	}
-
-	Method (_Q14, 0, NotSerialized) // Airplane Mode
-	{
-		Printf ("EC: Airplane Mode")
-		if (^^^^HIDD.HRDY) {
-			^^^^HIDD.HPEM (8)
-		}
-		// TODO: hardware airplane mode
-	}
-
-	Method (_Q15, 0, NotSerialized) // Suspend Button
-	{
-		Printf ("EC: Suspend Button")
-		Notify (SLPB, 0x80)
-	}
-
-	Method (_Q16, 0, NotSerialized) // AC Detect
-	{
-		Printf ("EC: AC Detect")
-		^^^^AC.ACFG = ADP
-		Notify (AC, 0x80) // Status Change
-		If (BAT0)
-		{
-			Notify (^^^^BAT0, 0x81) // Information Change
-			Notify (^^^^BAT0, 0x80) // Status Change
-		}
-	}
-
-	Method (_Q17, 0, NotSerialized)  // BAT0 Update
-	{
-		Printf ("EC: BAT0 Update (17)")
-		Notify (^^^^BAT0, 0x81) // Information Change
-	}
-
-	Method (_Q19, 0, NotSerialized)  // BAT0 Update
-	{
-		Printf ("EC: BAT0 Update (19)")
-		Notify (^^^^BAT0, 0x81) // Information Change
-	}
-
-	Method (_Q1B, 0, NotSerialized) // Lid Close
-	{
-		Printf ("EC: Lid Close")
-		Notify (LID0, 0x80)
-	}
-
-	Method (_Q1C, 0, NotSerialized) // Thermal Trip
-	{
-		Printf ("EC: Thermal Trip")
-		/* TODO
-		Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change
-		Notify (\_TZ.TZ0, 0x80) // Thermal Status Change
-		*/
-	}
-
-	Method (_Q1D, 0, NotSerialized) // Power Button
-	{
-		Printf ("EC: Power Button")
-		Notify (PWRB, 0x80)
-	}
-
-	Method (_Q50, 0, NotSerialized) // Other Events
-	{
-		Local0 = OEM4
-		If (Local0 == 0x8A) {
-			Printf ("EC: White Keyboard Backlight")
-			Notify (^^^^S76D, 0x80)
-		} ElseIf (Local0 == 0x9F) {
-			Printf ("EC: Color Keyboard Toggle")
-			Notify (^^^^S76D, 0x81)
-		} ElseIf (Local0 == 0x81) {
-			Printf ("EC: Color Keyboard Down")
-			Notify (^^^^S76D, 0x82)
-		} ElseIf (Local0 == 0x82) {
-			Printf ("EC: Color Keyboard Up")
-			Notify (^^^^S76D, 0x83)
-		} ElseIf (Local0 == 0x80) {
-			Printf ("EC: Color Keyboard Color Change")
-			Notify (^^^^S76D, 0x84)
-		} Else {
-			Printf ("EC: Other: %o", ToHexString(Local0))
-		}
-	}
-
-	#if CONFIG(EC_DASHARO_EC_BAT_THRESHOLDS)
-	#include "battery_thresholds.asl"
-	#endif
-}

src/ec/dasharo/ec/acpi/ec_ram.asl

@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-OperationRegion (ERAM, EmbeddedControl, 0, 0xFF)
-Field (ERAM, ByteAcc, Lock, Preserve)
-{
-	Offset (0x03),
-	LSTE, 1,	// Lid is open
-	, 1,
-	LWKE, 1,	// Lid wake
-	, 5,
-	Offset (0x07),
-	TMP1, 8,	// CPU temperature
-	Offset (0x10),
-	ADP, 1,		// AC adapter connected
-	, 1,
-	BAT0, 1,	// Battery connected
-	, 5,
-	WFNO, 8,	// Wake cause (not implemented)
-	Offset (0x16),
-	BDC0, 32,	// Battery design capacity
-	BFC0, 32,	// Battery full capacity
-	Offset (0x22),
-	BDV0, 32,	// Battery design voltage
-	BST0, 32,	// Battery status
-	BPR0, 32,	// Battery current
-	BRC0, 32,	// Battery remaining capacity
-	BPV0, 32,	// Battery voltage
-	Offset (0x3A),
-	BCW0, 32,
-	BCL0, 32,
-	CYC0, 16,	// Battery cycle count
-	Offset (0x68),
-	ECOS, 8,	// Detected OS, 0 = no ACPI, 1 = ACPI but no driver, 2 = ACPI with driver
-	Offset (0xC8),
-	OEM1, 8,
-	OEM2, 8,
-	OEM3, 16,
-	OEM4, 8,	// Extra SCI data
-	Offset (0xCD),
-	TMP2, 8,	// GPU temperature
-	DUT1, 8,	// Fan 1 duty
-	DUT2, 8,	// Fan 2 duty
-	RPM1, 16,	// Fan 1 RPM
-	RPM2, 16,	// Fan 2 RPM
-	Offset (0xD9),
-	AIRP, 8,	// Airplane mode LED
-	WINF, 8,	// Enable ACPI brightness controls
-	Offset (0xF8),
-	FCMD, 8,
-	FDAT, 8,
-	FBUF, 8,
-	FBF1, 8,
-	FBF2, 8,
-	FBF3, 8,
-}

src/ec/dasharo/ec/acpi/hid.asl

@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Device (HIDD)
-{
-	Name (_HID, "INT33D5")
-	Name (HBSY, 0)
-	Name (HIDX, 0)
-	Name (HRDY, 0)
-
-	Method (HDEM, 0, Serialized)
-	{
-		HBSY = 0
-		Return (HIDX)
-	}
-
-	Method (HDMM, 0, Serialized)
-	{
-		Return (0)
-	}
-
-	Method (HDSM, 1, Serialized)
-	{
-		HRDY = Arg0
-	}
-
-	Method (HPEM, 1, Serialized)
-	{
-		HBSY = 1
-		HIDX = Arg0
-
-		Notify (HIDD, 0xC0)
-		Local0 = 0
-		While ((Local0 < 0xFA) && HBSY)
-		{
-			Sleep (0x04)
-			Local0++
-		}
-
-		If (HBSY == 1)
-		{
-			HBSY = 0
-			HIDX = 0
-			Return (1)
-		}
-		Else
-		{
-			Return (0)
-		}
-	}
-}

src/ec/dasharo/ec/acpi/lid.asl

@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Device (LID0)
-{
-	Name (_HID, EisaId ("PNP0C0D"))
-	Name (_PRW, Package () { EC_GPE_SWI, 3 })
-
-	Method (_LID, 0, NotSerialized) {
-		Printf ("LID: _LID")
-		If (^^PCI0.LPCB.EC0.ECOK) {
-			Return (^^PCI0.LPCB.EC0.LSTE)
-		} Else {
-			Return (1)
-		}
-	}
-
-	Method (_PSW, 1, NotSerialized) {
-		Printf ("LID: _PSW: %o", ToHexString(Arg0))
-		If (^^PCI0.LPCB.EC0.ECOK) {
-			^^PCI0.LPCB.EC0.LWKE = Arg0
-		}
-	}
-}

src/ec/dasharo/ec/acpi/s76.asl

@@ -1,178 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// Notifications:
-//   0x80 - hardware backlight toggle
-//   0x81 - backlight toggle
-//   0x82 - backlight down
-//   0x83 - backlight up
-//   0x84 - backlight color change
-//   0x85 - OLED screen toggle
-Device (S76D) {
-	Name (_HID, "17761776")
-	Name (_UID, 0)
-	// Hide the device so that Windows does not warn about a missing driver.
-	Name (_STA, 0xB)
-
-	Method (RSET, 0, Serialized) {
-		Printf ("S76D: RSET")
-		SAPL(0)
-		SKBB(0)
-		SKBC(0xFFFFFF)
-	}
-
-	Method (INIT, 0, Serialized) {
-		Printf ("S76D: INIT")
-		RSET()
-		If (^^PCI0.LPCB.EC0.ECOK) {
-			// Set flags to use software control
-			^^PCI0.LPCB.EC0.ECOS = 2
-			Return (0)
-		} Else {
-			Return (1)
-		}
-	}
-
-	Method (FINI, 0, Serialized) {
-		Printf ("S76D: FINI")
-		RSET()
-		If (^^PCI0.LPCB.EC0.ECOK) {
-			// Set flags to use hardware control
-			^^PCI0.LPCB.EC0.ECOS = 1
-			Return (0)
-		} Else {
-			Return (1)
-		}
-	}
-
-	// Get Airplane LED
-	Method (GAPL, 0, Serialized) {
-		If (^^PCI0.LPCB.EC0.ECOK) {
-			If (^^PCI0.LPCB.EC0.AIRP & 0x40) {
-				Return (1)
-			}
-		}
-		Return (0)
-	}
-
-	// Set Airplane LED
-	Method (SAPL, 1, Serialized) {
-		If (^^PCI0.LPCB.EC0.ECOK) {
-			If (Arg0) {
-				^^PCI0.LPCB.EC0.AIRP |= 0x40
-			} Else {
-				^^PCI0.LPCB.EC0.AIRP &= 0xBF
-			}
-		}
-	}
-
-	// Get Keyboard Backlight Kind
-	// 0 - No backlight
-	// 1 - White backlight
-	// 2 - RGB backlight
-	Method (GKBK, 0, Serialized) {
-		Local0 = 0
-		If (^^PCI0.LPCB.EC0.ECOK) {
-			^^PCI0.LPCB.EC0.FDAT = 2
-			^^PCI0.LPCB.EC0.FCMD = 0xCA
-			Local0 = ^^PCI0.LPCB.EC0.FBUF
-		}
-		Return (Local0)
-	}
-
-	// Get Keyboard Brightness
-	Method (GKBB, 0, Serialized) {
-		Local0 = 0
-		If (^^PCI0.LPCB.EC0.ECOK) {
-			^^PCI0.LPCB.EC0.FDAT = 1
-			^^PCI0.LPCB.EC0.FCMD = 0xCA
-			Local0 = ^^PCI0.LPCB.EC0.FBUF
-		}
-		Return (Local0)
-	}
-
-	// Set Keyboard Brightness
-	Method (SKBB, 1, Serialized) {
-		If (^^PCI0.LPCB.EC0.ECOK) {
-			^^PCI0.LPCB.EC0.FDAT = 0
-			^^PCI0.LPCB.EC0.FBUF = Arg0
-			^^PCI0.LPCB.EC0.FCMD = 0xCA
-		}
-	}
-
-	// Get Keyboard Color
-	Method (GKBC, 0, Serialized) {
-		Local0 = 0
-		If (^^PCI0.LPCB.EC0.ECOK) {
-			^^PCI0.LPCB.EC0.FDAT = 4
-			^^PCI0.LPCB.EC0.FCMD = 0xCA
-			Local0 = ^^PCI0.LPCB.EC0.FBUF
-			Local0 |= (^^PCI0.LPCB.EC0.FBF1) << 16
-			Local0 |= (^^PCI0.LPCB.EC0.FBF2) << 8
-		}
-		Return (Local0)
-	}
-
-	// Set Keyboard Color
-	Method (SKBC, 1, Serialized) {
-		If (^^PCI0.LPCB.EC0.ECOK) {
-			^^PCI0.LPCB.EC0.FDAT = 3
-			^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF)
-			^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF)
-			^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF)
-			^^PCI0.LPCB.EC0.FCMD = 0xCA
-		}
-	}
-
-	// Fan names
-	Method (NFAN, 0, Serialized) {
-		Return (Package() {
-			"CPU fan",
-#if CONFIG(EC_DASHARO_EC_DGPU)
-			"GPU fan",
-#endif
-		})
-	}
-
-	// Get fan duty cycle and RPM as a single value
-	Method (GFAN, 1, Serialized) {
-		Local0 = 0
-		Local1 = 0
-		If (^^PCI0.LPCB.EC0.ECOK) {
-			If (Arg0 == 0) {
-				Local0 = ^^PCI0.LPCB.EC0.DUT1
-				Local1 = ^^PCI0.LPCB.EC0.RPM1
-			} ElseIf (Arg0 == 1) {
-				Local0 = ^^PCI0.LPCB.EC0.DUT2
-				Local1 = ^^PCI0.LPCB.EC0.RPM2
-			}
-		}
-		If (Local1 != 0) {
-			// 60 * (EC frequency / 120) / 2
-			Local1 = 2156250 / Local1
-		}
-		Return ((Local1 << 8) | Local0)
-	}
-
-	// Temperature names
-	Method (NTMP, 0, Serialized) {
-		Return (Package() {
-			"CPU temp",
-#if CONFIG(EC_DASHARO_EC_DGPU)
-			"GPU temp",
-#endif
-		})
-	}
-
-	// Get temperature
-	Method (GTMP, 1, Serialized) {
-		Local0 = 0;
-		If (^^PCI0.LPCB.EC0.ECOK) {
-			If (Arg0 == 0) {
-				Local0 = ^^PCI0.LPCB.EC0.TMP1
-			} ElseIf (Arg0 == 1) {
-				Local0 = ^^PCI0.LPCB.EC0.TMP2
-			}
-		}
-		Return (Local0)
-	}
-}

src/ec/dasharo/ec/dasharo_ec.c

@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include "dasharo_ec.h"
-#include <arch/io.h>
-#include <console/dasharo_ec.h>
-#include <console/console.h>
-#include <timer.h>
-
-// This is the command region for Dasharo EC firmware. It must be
-// enabled for LPC in the mainboard.
-#define DASHARO_EC_BASE 0x0E00
-#define DASHARO_EC_SIZE 256
-
-#define REG_CMD 0
-#define REG_RESULT 1
-#define REG_DATA 2	// Start of command data
-
-// When command register is 0, command is complete
-#define CMD_FINISHED 0
-
-#define RESULT_OK 0
-
-// Print command. Registers are unique for each command
-#define CMD_PRINT 4
-#define CMD_PRINT_REG_FLAGS 2
-#define CMD_PRINT_REG_LEN 3
-#define CMD_PRINT_REG_DATA 4
-
-static inline uint8_t dasharo_ec_read(uint8_t addr)
-{
-	return inb(DASHARO_EC_BASE + (uint16_t)addr);
-}
-
-static inline void dasharo_ec_write(uint8_t addr, uint8_t data)
-{
-	outb(data, DASHARO_EC_BASE + (uint16_t)addr);
-}
-
-void dasharo_ec_init(void)
-{
-	// Clear entire command region
-	for (int i = 0; i < DASHARO_EC_SIZE; i++)
-		dasharo_ec_write((uint8_t)i, 0);
-}
-
-void dasharo_ec_flush(void)
-{
-	dasharo_ec_write(REG_CMD, CMD_PRINT);
-
-	// Wait for command completion, for up to 10 milliseconds, with a
-	// test period of 1 microsecond
-	wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED);
-
-	dasharo_ec_write(CMD_PRINT_REG_LEN, 0);
-}
-
-void dasharo_ec_print(uint8_t byte)
-{
-	uint8_t len = dasharo_ec_read(CMD_PRINT_REG_LEN);
-	dasharo_ec_write(CMD_PRINT_REG_DATA + len, byte);
-	dasharo_ec_write(CMD_PRINT_REG_LEN, len + 1);
-
-	// If we hit the end of the buffer, or were given a newline, flush
-	if (byte == '\n' || len >= (DASHARO_EC_SIZE - CMD_PRINT_REG_DATA))
-		dasharo_ec_flush();
-}
-
-bool dasharo_ec_cmd(uint8_t cmd, const uint8_t *request_data,
-	uint8_t request_size, uint8_t *reply_data, uint8_t reply_size)
-{
-	if (request_size > DASHARO_EC_SIZE - REG_DATA ||
-		reply_size > DASHARO_EC_SIZE - REG_DATA) {
-		printk(BIOS_ERR, "EC command %d too long - request size %u, reply size %u\n",
-			cmd, request_size, reply_size);
-		return false;
-	}
-
-	/* If any data were buffered by dasharo_ec_print(), flush it first */
-	uint8_t buffered_len = dasharo_ec_read(CMD_PRINT_REG_LEN);
-	if (buffered_len > 0)
-		dasharo_ec_flush();
-
-	/* Write the data */
-	uint8_t i;
-	for (i = 0; i < request_size; ++i)
-		dasharo_ec_write(REG_DATA + i, request_data[i]);
-
-	/* Write the command */
-	dasharo_ec_write(REG_CMD, cmd);
-
-	/* Wait for the command to complete */
-	bool ret = true;
-	int elapsed = wait_ms(1000, dasharo_ec_read(REG_CMD) == CMD_FINISHED);
-	if (elapsed == 0) {
-		/* Timed out: fail the command, don't attempt to read a reply. */
-		printk(BIOS_WARNING, "EC command %d timed out - request size %d, reply size %d\n",
-			cmd, request_size, reply_size);
-		ret = false;
-	} else {
-		/* Read the reply */
-		for (i = 0; i < reply_size; ++i)
-			reply_data[i] = dasharo_ec_read(REG_DATA+i);
-		/* Check the reply status */
-		ret = (dasharo_ec_read(REG_RESULT) == RESULT_OK);
-	}
-
-	/* Reset the flags and length so we can buffer console prints again */
-	dasharo_ec_write(CMD_PRINT_REG_FLAGS, 0);
-	dasharo_ec_write(CMD_PRINT_REG_LEN, 0);
-
-	return ret;
-}

src/ec/dasharo/ec/dasharo_ec.h

@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef DASHARO_EC_H
-#define DASHARO_EC_H
-
-#include <stdbool.h>
-#include <stdint.h>
-
-/*
- * Send a command to the EC.  request_data/request_size are the request payload,
- * request_data can be NULL if request_size is 0.  reply_data/reply_size are
- * the reply payload, reply_data can be NULL if reply_size is 0.
- */
-bool dasharo_ec_cmd(uint8_t cmd, const uint8_t *request_data,
-	uint8_t request_size, uint8_t *reply_data, uint8_t reply_size);
-
-#endif

src/ec/dasharo/ec/smbios.c

@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <smbios.h>
-
-smbios_wakeup_type smbios_system_wakeup_type(void)
-{
-	// TODO: Read wake source from EC.
-	return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
-}

src/include/device_tree.h

@@ -129,12 +129,6 @@ u32 fdt_find_node_by_alias(const void *blob, const char *alias_name,
  */
 int fdt_next_node_name(const void *blob, uint32_t node_offset, const char **name);
 
- /* Read memory regions from a flat device-tree. */
-size_t fdt_read_memory_regions(const void *blob, struct device_tree_region regions[],
-			       size_t regions_count);
- /* Find top of memory from a flat device-tree. */
-uint64_t fdt_get_memory_top(const void *blob);
-
 /* Read a flattened device tree into a hierarchical structure which refers to
    the contents of the flattened tree in place. Modifying the flat tree
    invalidates the unflattened one. */

src/include/smbios.h

@@ -584,13 +584,7 @@ enum smbios_processor_upgrade_field {
 /* defines for processor family */
 #define SMBIOS_PROCESSOR_FAMILY_OTHER			0x01
 #define SMBIOS_PROCESSOR_FAMILY_UNKNOWN			0x02
-#define SMBIOS_PROCESSOR_FAMILY_INTEL486		0x06
-#define SMBIOS_PROCESSOR_FAMILY_PENTIUM_PRO		0x0c
 #define SMBIOS_PROCESSOR_FAMILY_XEON			0xb3
-#define SMBIOS_PROCESSOR_FAMILY_FROM_FAMILY2		0xfe
-
-/* defines for processor family 2 */
-#define SMBIOS_PROCESSOR_FAMILY2_ARMV8			0x101
 
 /* defines for processor characteristics */
 #define PROCESSOR_64BIT_CAPABLE				(1 << 2)

src/lib/Makefile.mk

@@ -160,12 +160,10 @@ ramstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
 ramstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 ramstage-y += b64_decode.c
 ramstage-$(CONFIG_ACPI_NHLT) += nhlt.c
+ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c
 ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit.c
 ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c
 
-romstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c
-ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c
-
 romstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c
 ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c
 

src/lib/device_tree.c

@@ -12,12 +12,9 @@
 #include <string.h>
 #include <stddef.h>
 #include <stdlib.h>
-#include <limits.h>
 
 #define FDT_PATH_MAX_DEPTH 10 // should be a good enough upper bound
 #define FDT_PATH_MAX_LEN 128 // should be a good enough upper bound
-#define FDT_MAX_MEMORY_NODES 4 // should be a good enough upper bound
-#define FDT_MAX_MEMORY_REGIONS 16 // should be a good enough upper bound
 
 /*
  * Functions for picking apart flattened trees.
@@ -506,96 +503,6 @@ void fdt_print_node(const void *blob, uint32_t offset)
 	print_flat_node(blob, offset, 0);
 }
 
-/*
- * fdt_read_memory_regions finds memory ranges from a flat device-tree
- *
- * @params blob	          address of FDT
- * @params regions        all regions that are read inside the reg property of
- *                        memory nodes are saved inside this array
- * @params regions_count  maximum number of entries that can be saved inside
- *                        the regions array.
- *
- * Returns: Either 0 on error or returns the number of regions put into the regions array.
- */
-size_t fdt_read_memory_regions(const void *blob,
-			       struct device_tree_region regions[],
-			       size_t regions_count)
-{
-	u32 node, root, addrcp, sizecp;
-	u32 nodes[FDT_MAX_MEMORY_NODES] = {0};
-	size_t region_idx = 0;
-	size_t node_count = 0;
-
-	if (!fdt_is_valid(blob))
-		return 0;
-
-	node = fdt_find_node_by_path(blob, "/memory",  &addrcp, &sizecp);
-	if (node) {
-		region_idx += fdt_read_reg_prop(blob, node, addrcp, sizecp,
-						regions, regions_count);
-		if (region_idx >= regions_count) {
-			printk(BIOS_WARNING, "FDT: Too many memory regions\n");
-			goto out;
-		}
-	}
-
-	root = fdt_find_node_by_path(blob, "/",  &addrcp, &sizecp);
-	node_count = fdt_find_subnodes_by_prefix(blob, root, "memory@",
-						 &addrcp, &sizecp, nodes,
-						 FDT_MAX_MEMORY_NODES);
-	if (node_count >= FDT_MAX_MEMORY_NODES) {
-		printk(BIOS_WARNING, "FDT: Too many memory nodes\n");
-		/* Can still reading the regions for those we got */
-	}
-
-	for (size_t i = 0; i < MIN(node_count, FDT_MAX_MEMORY_NODES); i++) {
-		region_idx += fdt_read_reg_prop(blob, nodes[i], addrcp, sizecp,
-						&regions[region_idx],
-						regions_count - region_idx);
-		if (region_idx >= regions_count) {
-			printk(BIOS_WARNING, "FDT: Too many memory regions\n");
-			goto out;
-		}
-	}
-
-out:
-	for (size_t i = 0; i < MIN(region_idx, regions_count); i++) {
-		printk(BIOS_DEBUG, "FDT: Memory region [%#llx - %#llx]\n",
-		       regions[i].addr, regions[i].addr + regions[i].size);
-	}
-
-	return region_idx;
-}
-
-/*
- * fdt_get_memory_top finds top of memory from a flat device-tree
- *
- * @params blob	          address of FDT
- *
- * Returns: Either 0 on error or returns the maximum memory address
- */
-uint64_t fdt_get_memory_top(const void *blob)
-{
-	struct device_tree_region regions[FDT_MAX_MEMORY_REGIONS] = {0};
-	uint64_t top = 0;
-	uint64_t total = 0;
-	size_t count;
-
-	if (!fdt_is_valid(blob))
-		return 0;
-
-	count = fdt_read_memory_regions(blob, regions, FDT_MAX_MEMORY_REGIONS);
-	for (size_t i = 0; i < MIN(count, FDT_MAX_MEMORY_REGIONS); i++) {
-		top = MAX(top, regions[i].addr + regions[i].size);
-		total += regions[i].size;
-	}
-
-	printk(BIOS_DEBUG, "FDT: Found %u MiB of RAM\n",
-	       (uint32_t)(total / MiB));
-
-	return top;
-}
-
 /*
  * Functions to turn a flattened tree into an unflattened one.
  */
@@ -701,7 +608,7 @@ struct device_tree *fdt_unflatten(const void *blob)
 	const struct fdt_header *header = (const struct fdt_header *)blob;
 	tree->header = header;
 
-	if (!fdt_is_valid(blob))
+	if (fdt_is_valid(blob))
 		return NULL;
 
 	uint32_t struct_offset = be32toh(header->structure_offset);

src/mainboard/google/brya/variants/bujia/overridetree.cb

@@ -159,15 +159,14 @@ chip soc/intel/alderlake
 		end
 		device ref i2c0 on
 			chip drivers/i2c/generic
-				register "hid" = ""RTL5682""
+				register "hid" = ""10EC5650""
 				register "name" = ""RT58""
-				register "desc" = ""Headset Codec""
+				register "desc" = ""Realtek RT5650""
 				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
-				# Set the jd_src to RT5668_JD1 for jack detection
 				register "property_count" = "1"
 				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
-				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].name" = ""realtek,jd-mode""
-				register "property_list[0].integer" = "1"
+				register "property_list[0].integer" = "2"
 				device i2c 1a on end
 			end
 		end # I2C0

src/mainboard/google/brya/variants/xol/memory.c

@@ -63,8 +63,6 @@ static const struct mb_cfg variant_memcfg = {
 		.ccc_config = 0xff,
 	},
 
-	.LpDdrDqDqsReTraining = 1,
-
 	.ect = 1, /* Early Command Training */
 
 	.UserBd = BOARD_TYPE_ULT_ULX,

src/mainboard/google/rex/Kconfig

@@ -122,11 +122,6 @@ config BOARD_GOOGLE_OVIS4ES
 config BOARD_GOOGLE_REX0
 	select BOARD_GOOGLE_MODEL_REX
 
-config BOARD_GOOGLE_REX64
-	select BOARD_GOOGLE_MODEL_REX
-	select HAVE_X86_64_SUPPORT
-	select USE_X86_64_SUPPORT
-
 config BOARD_GOOGLE_REX_EC_ISH
 	select BOARD_GOOGLE_MODEL_REX_EC_ISH
 
@@ -187,7 +182,6 @@ config MAINBOARD_FAMILY
 
 config MAINBOARD_PART_NUMBER
 	default "Rex" if BOARD_GOOGLE_REX0
-	default "Rex64" if BOARD_GOOGLE_REX64
 	default "Rex_Ec_Ish" if BOARD_GOOGLE_REX_EC_ISH
 	default "Rex4ES" if BOARD_GOOGLE_REX4ES
 	default "Rex4ES_Ec_Ish" if BOARD_GOOGLE_REX4ES_EC_ISH

src/mainboard/google/rex/Kconfig.name

@@ -32,9 +32,6 @@ config BOARD_GOOGLE_REX4ES
 config BOARD_GOOGLE_REX4ES_EC_ISH
 	bool "-> Rex4ES EC ISH"
 
-config BOARD_GOOGLE_REX64
-	bool "-> Rex 64"
-
 config BOARD_GOOGLE_SCREEBO
 	bool "->  Screebo"
 

src/mainboard/razer/blade_stealth_kbl/Kconfig

@@ -1,12 +1,16 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-config BOARD_RAZER_BLADE_STEALTH_KBL
+if BOARD_RAZER_BLADE_STEALTH_KBL
-	bool
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
 	select SYSTEM_TYPE_LAPTOP
 	select BOARD_ROMSIZE_KB_8192
 	select SUPERIO_ITE_IT8528E
 	select SOC_INTEL_KABYLAKE
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select MEMORY_MAPPED_TPM
+	select MAINBOARD_HAS_TPM2
 	select MAINBOARD_HAS_LIBGFXINIT
 	select HAVE_SPD_IN_CBFS
 	select DRIVERS_I2C_HID
@@ -14,31 +18,6 @@ config BOARD_RAZER_BLADE_STEALTH_KBL
 	select HAVE_ACPI_TABLES
 	select DRIVERS_GENERIC_CBFS_SERIAL
 
-config BOARD_RAZER_BLADE_H2U
-	select BOARD_RAZER_BLADE_STEALTH_KBL
-	select MEMORY_MAPPED_TPM
-	select MAINBOARD_HAS_TPM2
-
-config BOARD_RAZER_BLADE_H3Q
-	select BOARD_RAZER_BLADE_STEALTH_KBL
-
-if BOARD_RAZER_BLADE_STEALTH_KBL
-
-config VARIANT_DIR
-	default "h2u" if BOARD_RAZER_BLADE_H2U
-	default "h3q" if BOARD_RAZER_BLADE_H3Q
-
-config OVERRIDE_DEVICETREE
-	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-
-config MAINBOARD_FAMILY
-	string
-	default "BLADE_STEALTH"
-
-config MAINBOARD_PART_NUMBER
-	default "H2U: RZ09-01962" if BOARD_RAZER_BLADE_H2U
-	default "H3Q: RZ09-01963/RZ09-01964" if BOARD_RAZER_BLADE_H3Q
-
 # For now no way to choose the correct the available RAM
 config BOARD_RAZER_BLADE_STEALTH_KBL_16GB
 	bool "16GB RAM (4x MT52L1G32D4PG)"
@@ -48,6 +27,13 @@ config VGA_BIOS_ID
 	string
 	default "8086,5916"
 
+config MAINBOARD_FAMILY
+	string
+	default "BLADE_STEALTH"
+
+config MAINBOARD_PART_NUMBER
+	default "H2U"
+
 config MAINBOARD_VERSION
 	string
 	default "1.0"

src/mainboard/razer/blade_stealth_kbl/Kconfig.name

@@ -1,7 +1,4 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-config BOARD_RAZER_BLADE_H2U
+config BOARD_RAZER_BLADE_STEALTH_KBL
-	bool "Razer Blade Stealth KabyLake (2016, RZ09-01962, 12.5\")"
+	bool "Razer Blade Stealth KabyLake (2016)"
-
-config BOARD_RAZER_BLADE_H3Q
-	bool "Razer Blade Stealth KabyLake (Mid 2017, RZ09-01963/RZ09-10964, 13.3\")"

src/mainboard/razer/blade_stealth_kbl/Makefile.mk

@@ -3,8 +3,6 @@
 subdirs-y += spd
 
 ramstage-y += ramstage.c
-ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-y += hda_verb.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

src/mainboard/razer/blade_stealth_kbl/board_info.txt

@@ -1,5 +1,5 @@
 Vendor name: RAZER
-Board name: Blade Stealth KabyLake
+Board name: Blade Stealth KabyLake (H2U)
 Category: laptop
 ROM package: SOIC8
 ROM protocol: SPI

src/mainboard/razer/blade_stealth_kbl/devicetree.cb

@@ -126,6 +126,24 @@ chip soc/intel/skylake
 
 	register "PcieRpHotPlug[4]" = "1"
 
+	register "usb2_ports" = "{
+		[0] = USB2_PORT_MID(OC1),	/* Type-A Port (right) */
+		[1] = USB2_PORT_MID(OC1),	/* Type-A Port (left) */
+		[2] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
+		[3] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
+		[4] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
+		[5] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
+		[6] = USB2_PORT_FLEX(OC2),	/* Camera */
+		[7] = USB2_PORT_FLEX(OC2),	/* Keyboard */
+		[8] = USB2_PORT_FLEX(OC2),	/* Touchscreen */
+	}"
+
+	register "usb3_ports" = "{
+		[0] = USB3_PORT_DEFAULT(OC1),	/* Type-A Port (left) */
+		[1] = USB3_PORT_DEFAULT(OC1),	/* Type-A Port (right) */
+		[5] = USB3_PORT_DEFAULT(OC1),	/* TODO Unknown. Maybe USBC? */
+	}"
+
 	# PL1 override 25W
 	# PL2 override 44W
 	register "power_limits_config" = "{
@@ -173,6 +191,9 @@ chip soc/intel/skylake
 		device ref pcie_rp5	on  end
 		device ref pcie_rp9	on  end
 		device ref lpc_espi	on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
 			chip superio/ite/it8528e
 				device pnp 6e.1 off end
 				device pnp 6e.2 off end

src/mainboard/razer/blade_stealth_kbl/hda_verb.c

@@ -20,7 +20,7 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
 	AZALIA_PIN_CFG(0, 0x21, 0x03211020),
 
-	/* Intel, Kaby Lake HDMI */
+	/* Intel, KabylakeHDMI */
 	0x8086280b, /* Vendor ID */
 	0x80860101, /* Subsystem ID */
 	4, /* Number of entries */

src/mainboard/razer/blade_stealth_kbl/ramstage.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <soc/ramstage.h>
-#include <variant/gpio.h>
+#include "gpio.h"
 
 void mainboard_silicon_init_params(FSP_SIL_UPD *params)
 {

src/mainboard/razer/blade_stealth_kbl/spd/spd.h

@@ -4,6 +4,7 @@
 #define MAINBOARD_SPD_H
 
 #include <gpio.h>
+#include "../gpio.h"
 
 void mainboard_fill_dq_map_data(void *dq_map_ptr);
 void mainboard_fill_dqs_map_data(void *dqs_map_ptr);

src/mainboard/razer/blade_stealth_kbl/variants/h2u/board_info.txt

@@ -1,9 +0,0 @@
-Vendor name: RAZER
-Board name: Blade Stealth KabyLake (H2U: RZ09-01962)
-Board URL: https://mysupport.razer.com/app/answers/detail/a_id/3698/
-Category: laptop
-ROM package: SOIC8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
-Release year: 2016

src/mainboard/razer/blade_stealth_kbl/variants/h2u/overridetree.cb

@@ -1,31 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-chip soc/intel/skylake
-	device domain 0 on
-		device ref south_xhci on
-			register "usb2_ports" = "{
-				[0] = USB2_PORT_MID(OC1),	/* Type-A Port (right) */
-				[1] = USB2_PORT_MID(OC1),	/* Type-A Port (left) */
-				[2] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
-				[3] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
-				[4] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
-				[5] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
-				[6] = USB2_PORT_FLEX(OC2),	/* Camera */
-				[7] = USB2_PORT_FLEX(OC2),	/* Keyboard */
-				[8] = USB2_PORT_FLEX(OC2),	/* Touchscreen */
-			}"
-
-			register "usb3_ports" = "{
-				[0] = USB3_PORT_DEFAULT(OC1),	/* Type-A Port (left) */
-				[1] = USB3_PORT_DEFAULT(OC1),	/* Type-A Port (right) */
-				[5] = USB3_PORT_DEFAULT(OC1),	/* TODO Unknown. Maybe USBC? */
-			}"
-		end
-
-		device ref lpc_espi on
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-		end
-	end
-end

src/mainboard/razer/blade_stealth_kbl/variants/h3q/board_info.txt

@@ -1,9 +0,0 @@
-Vendor name: RAZER
-Board name: Blade Stealth KabyLake (H3Q: RZ09-01963 / RZ09-01964)
-Board URL: https://mysupport.razer.com/app/answers/detail/a_id/3694/
-Category: laptop
-ROM package: SOIC8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
-Release year: 2017

src/mainboard/razer/blade_stealth_kbl/variants/h3q/hda_verb.c

@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
-	/* Realtek, ALC298 */
-	0x10ec0298, /* Vendor ID */
-	0x1a586753, /* Subsystem ID */
-	12, /* Number of entries */
-	AZALIA_SUBVENDOR(0, 0x1a586753),
-	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
-	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
-	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
-	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
-	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x1d, 0x4075812d),
-	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
-
-	/* Intel, Kaby Lake HDMI */
-	0x8086280b, /* Vendor ID */
-	0x80860101, /* Subsystem ID */
-	4, /* Number of entries */
-	AZALIA_SUBVENDOR(2, 0x80860101),
-	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
-	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
-	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
-};
-
-const u32 pc_beep_verbs[] = {};
-AZALIA_ARRAY_SIZES;

src/mainboard/razer/blade_stealth_kbl/variants/h3q/include/variant/gpio.h

@@ -1,200 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef CFG_GPIO_H
-#define CFG_GPIO_H
-
-#include <gpio.h>
-
-/* Pad configuration was generated automatically using intelp2m utility */
-static const struct pad_config gpio_table[] = {
-
-	/* ------- GPIO Community 0 ------- */
-
-	/* ------- GPIO Group GPP_A ------- */
-	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
-	PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI),
-	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
-	PAD_CFG_GPO(GPP_A11, 0, DEEP),
-	PAD_NC(GPP_A12, NONE),
-	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_A14, 0, DEEP),
-	PAD_CFG_GPO(GPP_A15, 0, DEEP),
-	PAD_CFG_GPO(GPP_A16, 0, DEEP),
-	PAD_CFG_GPO(GPP_A17, 0, DEEP),
-	PAD_CFG_GPO(GPP_A18, 0, DEEP),
-	PAD_CFG_GPO(GPP_A19, 0, DEEP),
-	PAD_CFG_GPO(GPP_A20, 0, DEEP),
-	PAD_CFG_GPO(GPP_A21, 0, DEEP),
-	PAD_CFG_GPO(GPP_A22, 0, DEEP),
-	PAD_CFG_GPO(GPP_A23, 0, DEEP),
-
-	/* ------- GPIO Group GPP_B ------- */
-	PAD_CFG_GPO(GPP_B0, 0, DEEP),
-	PAD_CFG_GPO(GPP_B1, 0, DEEP),
-	PAD_CFG_GPO(GPP_B2, 0, DEEP),
-	PAD_CFG_GPO(GPP_B3, 0, DEEP),
-	PAD_CFG_GPO(GPP_B4, 0, DEEP),
-	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_B8, 0, DEEP),
-	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_B10, 0, DEEP),
-	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-	PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP),
-	PAD_CFG_GPO(GPP_B15, 0, DEEP),
-	PAD_CFG_GPO(GPP_B16, 0, DEEP),
-	PAD_CFG_GPO(GPP_B17, 0, DEEP),
-	PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),
-	PAD_NC(GPP_B19, NONE),
-	PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1),
-	PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
-
-	/* ------- GPIO Community 1 ------- */
-
-	/* ------- GPIO Group GPP_C ------- */
-	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),
-	PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),
-	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
-	PAD_CFG_GPI_APIC_LOW(GPP_C5, DN_20K, DEEP),
-	/* GPP_C6 - RESERVED */
-	/* GPP_C7 - RESERVED */
-	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_C10, 0, DEEP),
-	PAD_CFG_GPO(GPP_C11, 0, DEEP),
-	PAD_CFG_GPO(GPP_C12, 0, DEEP),
-	PAD_CFG_GPO(GPP_C13, 0, DEEP),
-	PAD_CFG_GPO(GPP_C14, 0, DEEP),
-	PAD_CFG_GPO(GPP_C15, 0, DEEP),
-	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_C22, 0, DEEP),
-	PAD_CFG_GPO(GPP_C23, 0, DEEP),
-
-	/* ------- GPIO Group GPP_D ------- */
-	PAD_CFG_GPO(GPP_D0, 0, DEEP),
-	PAD_CFG_GPO(GPP_D1, 0, DEEP),
-	PAD_CFG_GPO(GPP_D2, 0, DEEP),
-	PAD_CFG_GPO(GPP_D3, 0, DEEP),
-	PAD_CFG_GPO(GPP_D4, 0, DEEP),
-	PAD_CFG_GPO(GPP_D5, 0, DEEP),
-	PAD_CFG_GPO(GPP_D6, 0, DEEP),
-	PAD_CFG_GPO(GPP_D7, 0, DEEP),
-	PAD_CFG_GPO(GPP_D8, 0, DEEP),
-	PAD_CFG_GPO(GPP_D9, 0, DEEP),
-	PAD_CFG_GPO(GPP_D10, 0, DEEP),
-	PAD_CFG_GPO(GPP_D11, 0, DEEP),
-	PAD_CFG_GPO(GPP_D12, 0, DEEP),
-	PAD_CFG_GPO(GPP_D13, 0, DEEP),
-	PAD_CFG_GPO(GPP_D14, 0, DEEP),
-	PAD_CFG_GPO(GPP_D15, 0, DEEP),
-	PAD_CFG_GPO(GPP_D16, 0, DEEP),
-	PAD_CFG_GPO(GPP_D17, 0, DEEP),
-	PAD_CFG_GPO(GPP_D18, 0, DEEP),
-	PAD_CFG_GPO(GPP_D19, 0, DEEP),
-	PAD_CFG_GPO(GPP_D20, 0, DEEP),
-	PAD_CFG_GPO(GPP_D21, 0, DEEP),
-	PAD_CFG_GPO(GPP_D22, 0, DEEP),
-	PAD_CFG_GPO(GPP_D23, 0, DEEP),
-
-	/* ------- GPIO Group GPP_E ------- */
-	PAD_CFG_GPO(GPP_E0, 0, DEEP),
-	PAD_CFG_GPO(GPP_E1, 0, DEEP),
-	PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_E3, 0, DEEP),
-	PAD_CFG_GPO(GPP_E4, 0, DEEP),
-	PAD_CFG_GPI_SCI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT),
-	PAD_CFG_GPO(GPP_E6, 0, DEEP),
-	PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI),
-	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_E9, 0, DEEP),
-	PAD_CFG_TERM_GPO(GPP_E10, 1, DN_20K, DEEP),
-	PAD_CFG_TERM_GPO(GPP_E11, 1, DN_20K, DEEP),
-	PAD_NC(GPP_E12, NONE),
-	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
-	PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT),
-	PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT),
-	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),
-	PAD_CFG_GPO(GPP_E22, 0, DEEP),
-	PAD_CFG_TERM_GPO(GPP_E23, 0, DN_20K, PLTRST),
-
-	/* ------- GPIO Community 2 ------- */
-
-	/* -------- GPIO Group GPD -------- */
-	PAD_CFG_NF(GPD0, NONE, PWROK, NF1),
-	PAD_CFG_NF(GPD1, NONE, PWROK, NF1),
-	PAD_CFG_NF(GPD2, NONE, PWROK, NF1),
-	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
-	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
-	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
-	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
-	PAD_CFG_GPO(GPD7, 0, DEEP),
-	PAD_NC(GPD8, NONE),
-	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
-	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
-	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
-
-	/* ------- GPIO Community 3 ------- */
-
-	/* ------- GPIO Group GPP_F ------- */
-	PAD_CFG_GPO(GPP_F0, 0, DEEP),
-	PAD_CFG_GPO(GPP_F1, 0, DEEP),
-	PAD_CFG_GPO(GPP_F2, 0, DEEP),
-	PAD_CFG_GPO(GPP_F3, 0, DEEP),
-	PAD_CFG_GPO(GPP_F4, 0, DEEP),
-	PAD_CFG_GPO(GPP_F5, 0, DEEP),
-	PAD_CFG_GPO(GPP_F6, 0, DEEP),
-	PAD_CFG_GPO(GPP_F7, 0, DEEP),
-	PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_F10, 0, DEEP),
-	PAD_CFG_GPO(GPP_F11, 0, DEEP),
-	PAD_CFG_GPO(GPP_F12, 0, DEEP),
-	PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI),
-	PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI),
-	PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI),
-	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_F17, 0, DEEP),
-	PAD_CFG_GPO(GPP_F18, 0, DEEP),
-	PAD_CFG_GPO(GPP_F19, 0, DEEP),
-	PAD_CFG_GPO(GPP_F20, 0, DEEP),
-	PAD_CFG_GPO(GPP_F21, 0, DEEP),
-	PAD_CFG_GPO(GPP_F22, 0, DEEP),
-	PAD_CFG_GPO(GPP_F23, 0, DEEP),
-
-	/* ------- GPIO Group GPP_G ------- */
-	PAD_CFG_GPO(GPP_G0, 0, DEEP),
-	PAD_CFG_GPO(GPP_G1, 0, DEEP),
-	PAD_CFG_GPO(GPP_G2, 0, DEEP),
-	PAD_CFG_GPO(GPP_G3, 0, DEEP),
-	PAD_CFG_GPO(GPP_G4, 0, DEEP),
-	PAD_CFG_GPO(GPP_G5, 0, DEEP),
-	PAD_CFG_GPO(GPP_G6, 0, DEEP),
-	PAD_CFG_GPO(GPP_G7, 0, DEEP),
-};
-
-#endif /* CFG_GPIO_H */

src/mainboard/razer/blade_stealth_kbl/variants/h3q/overridetree.cb

@@ -1,23 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-chip soc/intel/skylake
-	device domain 0 on
-		device ref south_xhci on
-			# NOTE: TYPE-C port is controlled by Intel Thunderbolt
-
-			register "usb2_ports" = "{
-				[0] = USB2_PORT_MID(OC0),	/* Type-A Port (right) */
-				[1] = USB2_PORT_MID(OC0),	/* Type-A Port (left) */
-				[5] = USB2_PORT_SHORT(OC2),	/* M.2 Slot (Bluetooth) */
-				[6] = USB2_PORT_FLEX(OC3),	/* Camera */
-				[7] = USB2_PORT_FLEX(OC3),	/* Keyboard */
-				[8] = USB2_PORT_FLEX(OC_SKIP),	/* Touchscreen */
-			}"
-
-			register "usb3_ports" = "{
-				[0] = USB3_PORT_DEFAULT(OC0),	/* Type-A Port (left) */
-				[1] = USB3_PORT_DEFAULT(OC0),	/* Type-A Port (right) */
-			}"
-		end
-	end
-end

src/mainboard/system76/addw1/Kconfig

@@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC

src/mainboard/system76/addw1/Makefile.mk

@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

src/mainboard/system76/addw1/acpi/mainboard.asl

@@ -1,11 +1,19 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
+	}
 }
 
 Scope (\_GPE) {

src/mainboard/system76/addw1/devicetree.cb

@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
 chip soc/intel/cannonlake
 	register "common_soc_config" = "{
 		// Touchpad I2C bus
@@ -58,6 +56,12 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 on      # SA Thermal device

src/mainboard/system76/addw1/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@@ -20,5 +22,17 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
 }

src/mainboard/system76/addw1/variants/addw1/include/variant/gpio.h

@@ -3,7 +3,16 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+#define DGPU_SSID	0x65d11558
+
+#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
+#endif
 
 #endif

src/mainboard/system76/addw1/variants/addw1/overridetree.cb

@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
 chip soc/intel/cannonlake
 	# Serial I/O
 	register "SerialIoDevMode" = "{

src/mainboard/system76/addw1/variants/addw2/include/variant/gpio.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+#define DGPU_SSID	0x65e11558
+
+#ifndef __ACPI__
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+#endif
+
+#endif

src/mainboard/system76/addw1/variants/addw2/overridetree.cb

@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
 chip soc/intel/cannonlake
 	# Serial I/O
 	register "SerialIoDevMode" = "{

src/mainboard/system76/adl/Kconfig

@@ -35,10 +35,12 @@ config BOARD_SYSTEM76_GALP6
 
 config BOARD_SYSTEM76_GAZE17_3050
 	select BOARD_SYSTEM76_ADL_COMMON
+	select DRIVERS_GFX_NVIDIA
 	select EC_SYSTEM76_EC_DGPU
 
 config BOARD_SYSTEM76_GAZE17_3060_B
 	select BOARD_SYSTEM76_ADL_COMMON
+	select DRIVERS_GFX_NVIDIA
 	select EC_SYSTEM76_EC_DGPU
 	select MAINBOARD_USES_IFD_GBE_REGION
 
@@ -48,11 +50,15 @@ config BOARD_SYSTEM76_LEMP11
 
 config BOARD_SYSTEM76_ORYP9
 	select BOARD_SYSTEM76_ADL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC_DGPU
 
 config BOARD_SYSTEM76_ORYP10
 	select BOARD_SYSTEM76_ADL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select EC_SYSTEM76_EC_DGPU
 
 if BOARD_SYSTEM76_ADL_COMMON
@@ -103,6 +109,12 @@ config CONSOLE_POST
 config D3COLD_SUPPORT
 	default n
 
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
+	default 45 if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
+	default 25 if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
+
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
 

src/mainboard/system76/adl/Makefile.mk

@@ -2,6 +2,10 @@
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
+ifeq ($(CONFIG_DRIVERS_GFX_NVIDIA),y)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+endif
+
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
 

src/mainboard/system76/adl/acpi/mainboard.asl

@@ -1,5 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#if CONFIG(DRIVERS_GFX_NVIDIA)
+#include <variant/gpio.h>
+#endif
+
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,5 +12,11 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+
+#if CONFIG(DRIVERS_GFX_NVIDIA)
+		Scope (PEG2) {
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
+#endif
 	}
 }

src/mainboard/system76/adl/devicetree.cb

@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
 chip soc/intel/alderlake
 	register "common_soc_config" = "{
 		// Touchpad I2C bus

src/mainboard/system76/adl/variants/darp8/overridetree.cb

@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
 chip soc/intel/alderlake
 	register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
 		.tdp_pl1_override = 20,

src/mainboard/system76/adl/variants/galp6/overridetree.cb

@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
 chip soc/intel/alderlake
 	register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
 		.tdp_pl1_override = 28,

src/mainboard/system76/adl/variants/gaze17-3050/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_F13
+#define DGPU_SSID	0x866d1558
+
+#endif

src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb

@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
 chip soc/intel/alderlake
 	# FIVR configuration
 	#   Read EXT_RAIL_CONFIG to determine bitmaps
@@ -40,6 +38,10 @@ chip soc/intel/alderlake
 				.clk_req = 3,
 				.flags = PCIE_RP_LTR,
 			}"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+			end
 		end
 		device ref pcie4_0 on
 			# PCIe PEG0 x4, Clock 0 (SSD2)

src/mainboard/system76/adl/variants/gaze17-3050/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -17,6 +19,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/adl/variants/gaze17-3060-b/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_F13
+#define DGPU_SSID	0x867c1558
+
+#endif

src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb

@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
 chip soc/intel/alderlake
 	# FIVR configuration
 	#   Read EXT_RAIL_CONFIG to determine bitmaps
@@ -40,6 +38,10 @@ chip soc/intel/alderlake
 				.clk_req = 3,
 				.flags = PCIE_RP_LTR,
 			}"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+			end
 		end
 		device ref igpu on
 			# DDIA is eDP

src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -17,6 +19,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/adl/variants/lemp11/overridetree.cb

@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
 chip soc/intel/alderlake
 	register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{
 		.tdp_pl1_override = 15,

src/mainboard/system76/adl/variants/oryp10/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_A7
+#define DGPU_SSID	0x65f51558
+
+#endif

src/mainboard/system76/adl/variants/oryp10/overridetree.cb

@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
 chip soc/intel/alderlake
 	register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
 		.tdp_pl1_override = 45,
@@ -25,6 +23,10 @@ chip soc/intel/alderlake
 				.clk_req = 3,
 				.flags = PCIE_RP_LTR,
 			}"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+			end
 		end
 		device ref igpu on
 			register "ddi_portA_config" = "1"

src/mainboard/system76/adl/variants/oryp10/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -20,6 +22,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/adl/variants/oryp9/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_A7
+#define DGPU_SSID	0x65f51558
+
+#endif

src/mainboard/system76/adl/variants/oryp9/overridetree.cb

@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
 chip soc/intel/alderlake
 	register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
 		.tdp_pl1_override = 45,
@@ -25,6 +23,10 @@ chip soc/intel/alderlake
 				.clk_req = 3,
 				.flags = PCIE_RP_LTR,
 			}"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+			end
 		end
 		device ref igpu on
 			register "ddi_portA_config" = "1"

src/mainboard/system76/adl/variants/oryp9/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -17,6 +19,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/bonw14/Kconfig

@@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_DGPU

src/mainboard/system76/bonw14/devicetree.cb

@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
 chip soc/intel/cannonlake
 	register "common_soc_config" = "{
 		// Touchpad I2C bus
@@ -61,12 +59,13 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU)
 			register "PcieClkSrcUsage[7]" = "0x40"
 			register "PcieClkSrcClkReq[7]" = "7"
-
+			chip drivers/gfx/nvidia
 				device pci 00.0 on end # VGA controller
 				device pci 00.1 on end # Audio device
 				device pci 00.2 on end # USB xHCI Host controller
 				device pci 00.3 on end # USB Type-C UCSI controller
 			end
+		end
 		# TODO: is this enough to disable iGPU?
 		device pci 02.0 off end # Integrated Graphics Device
 		device pci 04.0 on  end # SA Thermal device

src/mainboard/system76/cml-u/devicetree.cb

@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
 chip soc/intel/cannonlake
 	register "common_soc_config" = "{
 		/* Touchpad */

src/mainboard/system76/cml-u/variants/darp6/overridetree.cb

@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
 chip soc/intel/cannonlake
 	device domain 0 on
 		subsystemid 0x1558 0x1404 inherit

src/mainboard/system76/cml-u/variants/galp4/overridetree.cb

@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
 chip soc/intel/cannonlake
 	device domain 0 on
 		subsystemid 0x1558 0x1403 inherit

src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb

@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
 chip soc/intel/cannonlake
 	device domain 0 on
 		subsystemid 0x1558 0x1401 inherit

src/mainboard/system76/gaze15/Kconfig

@@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_DGPU

src/mainboard/system76/gaze15/Makefile.mk

@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

src/mainboard/system76/gaze15/acpi/mainboard.asl

@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,6 +10,10 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
 	}
 }
 

src/mainboard/system76/gaze15/devicetree.cb

@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
 chip soc/intel/cannonlake
 	register "common_soc_config" = "{
 		// Touchpad I2C bus
@@ -57,6 +55,12 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on      # Integrated Graphics Device
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"

src/mainboard/system76/gaze15/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@@ -20,5 +22,17 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
 }

src/mainboard/system76/gaze15/variants/gaze14/include/variant/gpio.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+#define DGPU_SSID	0x85501558
+
+#ifndef __ACPI__
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+#endif
+
+#endif