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upstream-8
Author | SHA1 | Date | |
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|
1d52b376a5 |
@@ -501,7 +501,8 @@ CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
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CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie
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CFLAGS_common += -Wstring-compare
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ifeq ($(CONFIG_COMPILER_GCC),y)
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CFLAGS_common += -Wold-style-declaration
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CFLAGS_common += -Wold-style-declaration -Wflex-array-member-not-at-end
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CFLAGS_common += -Wcalloc-transposed-args
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# Don't add these GCC specific flags when running scan-build
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ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
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CFLAGS_common += -Wno-packed-not-aligned
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@@ -28,7 +28,6 @@ payloads/external/edk2 \
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payloads/external/GRUB2 \
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payloads/external/LinuxBoot \
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payloads/external/skiboot \
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payloads/external/leanefi \
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payloads/external/coreDOOM \
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force-payload:
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7
payloads/external/Makefile.mk
vendored
7
payloads/external/Makefile.mk
vendored
@@ -436,13 +436,6 @@ payloads/external/skiboot/build/skiboot.elf:
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$(MAKE) -C payloads/external/skiboot all \
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CONFIG_SKIBOOT_GIT_REPO=$(CONFIG_SKIBOOT_GIT_REPO) \
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CONFIG_SKIBOOT_REVISION=$(CONFIG_SKIBOOT_REVISION)
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# leanefi
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payloads/external/leanefi/leanefi/build/leanefi.elf: FORCE $(DOTCONFIG)
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$(MAKE) -C payloads/external/leanefi
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FORCE: ;
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# COREDOOM
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payloads/external/coreDOOM/coredoom/doomgeneric/coredoom.elf coredoom:
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58
payloads/external/leanefi/Kconfig
vendored
58
payloads/external/leanefi/Kconfig
vendored
@@ -1,58 +0,0 @@
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if PAYLOAD_LEANEFI
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menu "leanEFI configuration"
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config PAYLOAD_FILE
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string
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default "payloads/external/leanefi/leanefi/build/leanefi.elf"
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config LEANEFI_EFI_ECPT
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bool
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default y if ARCH_ARM64
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config LEANEFI_HEAP_SIZE
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int "Heap size"
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default 131072
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help
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This is the heap size (malloc'able size) available
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to the payload.
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If unsure, set to 131072 (128K)
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config LEANEFI_STACK_SIZE
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int "Stack size"
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default 16384
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help
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This is the stack size available to the payload.
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If unsure, set to 16384 (16K)
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config LEANEFI_BASE_ADDRESS
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hex "Base address"
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default 0x62000000 if BOARD_EMULATION_QEMU_AARCH64
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#default 0x10023300000 if BOARD_EMULATION_QEMU_SBSA
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help
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This is the base address for the payload.
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config LEANEFI_PAYLOAD
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bool "Add a payload"
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default y
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help
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If selected leanEFI will start a payload.
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This option should only be unselected for debug purposes.
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config LEANEFI_PAYLOAD_PATH
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string "path to leanefi payload"
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depends on LEANEFI_PAYLOAD
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config LEANEFI_FDT
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bool "Add an FDT that is propagated as EFI configuration table"
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default y if BOARD_EMULATION_QEMU_AARCH64
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config LEANEFI_FDT_PATH
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string "path to FDT"
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depends on LEANEFI_FDT
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endmenu
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endif
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6
payloads/external/leanefi/Kconfig.name
vendored
6
payloads/external/leanefi/Kconfig.name
vendored
@@ -1,6 +0,0 @@
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config PAYLOAD_LEANEFI
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bool "leanefi"
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depends on ARCH_ARM64
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help
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Select this option if you want to build a coreboot image
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with an leanefi payload.
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22
payloads/external/leanefi/Makefile
vendored
22
payloads/external/leanefi/Makefile
vendored
@@ -1,22 +0,0 @@
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unexport KCONFIG_AUTOHEADER
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unexport KCONFIG_AUTOCONFIG
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unexport KCONFIG_DEPENDENCIES
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unexport KCONFIG_SPLITCONFIG
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unexport KCONFIG_TRISTATE
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unexport KCONFIG_NEGATIVES
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unexport $(COREBOOT_EXPORTS)
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build: leanefi
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$(MAKE) -C leanefi
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leanefi:
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git clone "https://review.coreboot.org/leanefi"
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distclean:
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rm -rf leanefi
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clean:
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rm -rf leanefi/build
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.PHONY: build clean distclean
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@@ -66,8 +66,8 @@ int smbios_write_type4(unsigned long *current, int handle)
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smbios_processor_id(t->processor_id);
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t->processor_manufacturer = smbios_processor_manufacturer(t->eos);
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t->processor_version = smbios_processor_name(t->eos);
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t->processor_family = SMBIOS_PROCESSOR_FAMILY_FROM_FAMILY2;
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t->processor_family2 = SMBIOS_PROCESSOR_FAMILY2_ARMV8;
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t->processor_family = 0xfe; /* Use processor_family2 field */
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t->processor_family2 = 0x101; /* ARMv8 */
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t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL;
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smbios_cpu_get_core_counts(&t->core_count2, &t->thread_count2);
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@@ -68,7 +68,7 @@ static int get_socket_type(void)
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unsigned int __weak smbios_processor_family(struct cpuid_result res)
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{
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return (res.eax > 0) ? SMBIOS_PROCESSOR_FAMILY_PENTIUM_PRO : SMBIOS_PROCESSOR_FAMILY_INTEL486;
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return (res.eax > 0) ? 0x0c : 0x6;
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}
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static size_t get_number_of_caches(size_t max_logical_cpus_sharing_cache)
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@@ -1,21 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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config EC_DASHARO_EC
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bool
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help
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Dasharo EC
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config EC_DASHARO_EC_BAT_THRESHOLDS
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depends on EC_DASHARO_EC
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bool
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default y
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config EC_DASHARO_EC_DGPU
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depends on EC_DASHARO_EC
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bool
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default n
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config EC_DASHARO_EC_OLED
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depends on EC_DASHARO_EC
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bool
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default n
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@@ -1,10 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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ifeq ($(CONFIG_EC_DASHARO_EC),y)
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all-y += dasharo_ec.c
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ramstage-y += smbios.c
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smm-$(CONFIG_DEBUG_SMI) += dasharo_ec.c
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endif
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@@ -1,22 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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Device (AC)
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{
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Name (_HID, "ACPI0003" /* Power Source Device */)
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Name (_PCL, Package (0x01) // _PCL: Power Consumer List
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{
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_SB
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})
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Name (ACFG, 1)
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Method (_PSR, 0, NotSerialized) // _PSR: Power Source
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{
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Return (ACFG)
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}
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0F)
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}
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}
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@@ -1,248 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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Device (BAT0)
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{
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Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */)
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Name (_UID, 0)
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Name (_PCL, Package (0x01) // _PCL: Power Consumer List
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{
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_SB
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})
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Name (BFCC, 0)
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Method (_STA, 0, NotSerialized)
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{
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If (^^PCI0.LPCB.EC0.ECOK)
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{
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If (^^PCI0.LPCB.EC0.BAT0)
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{
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Return (0x1F)
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}
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Else
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{
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Return (0x0F)
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}
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}
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Else
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{
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Return (0x0F)
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}
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}
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Name (PBIF, Package (0x0D)
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{
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1, // 0 - Power Unit
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0xFFFFFFFF, // 1 - Design Capacity
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0xFFFFFFFF, // 2 - Last Full Charge Capacity
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1, // 3 - Battery Technology
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0xFFFFFFFF, // 4 - Design Voltage
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0, // 5 - Design Capacity of Warning
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0, // 6 - Design Capacity of Low
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0x40, // 7 - Battery Capacity Granularity 1
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0x40, // 8 - Battery Capacity Granularity 2
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" ", // 9 - Model Number
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" ", // 10 - Serial Number
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" ", // 11 - Battery Type
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" " // 12 - OEM Information
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})
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Method (IVBI, 0, NotSerialized)
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{
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PBIF [1] = 0xFFFFFFFF
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PBIF [2] = 0xFFFFFFFF
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PBIF [4] = 0xFFFFFFFF
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PBIF [9] = " "
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PBIF [10] = " "
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PBIF [11] = " "
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PBIF [12] = " "
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BFCC = 0
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}
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Method (UPBI, 0, NotSerialized)
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{
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If (^^PCI0.LPCB.EC0.BAT0)
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{
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Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
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PBIF [1] = Local0
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Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
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PBIF [2] = Local0
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BFCC = Local0
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Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
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PBIF [4] = Local0
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Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
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PBIF [5] = Local0
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Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
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PBIF [6] = Local0
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PBIF [9] = "BAT"
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PBIF [10] = "0001"
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PBIF [11] = "LION"
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PBIF [12] = "Notebook"
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}
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Else
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{
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IVBI ()
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}
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}
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Method (_BIF, 0, NotSerialized) // _BIF: Battery Information
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{
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If (^^PCI0.LPCB.EC0.ECOK)
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{
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UPBI ()
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}
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Else
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{
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IVBI ()
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}
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Return (PBIF) /* \_SB_.BAT0.PBIF */
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}
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Name (PBIX, Package ()
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{
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0, // 0 - Revision
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1, // 1 - Power Unit: mAh
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0xFFFFFFFF, // 2 - Design Capacity
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0xFFFFFFFF, // 3 - Last Full Charge Capacity
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1, // 4 - Battery Technology: Rechargeable
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0xFFFFFFFF, // 5 - Design Voltage
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0, // 6 - Design Capacity of Warning
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0, // 7 - Design Capacity of Low
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0, // 8 - Cycle Count
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98000, // 9 - Measurement Accuracy
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0xFFFFFFFF, // 10 - Max Sampling Time
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0xFFFFFFFF, // 11 - Min Sampling Time
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0xFFFFFFFF, // 12 - Max Averaging Interval
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0xFFFFFFFF, // 13 - Min Averaging Interval
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0x40, // 14 - Battery Capacity Granularity 1
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0x40, // 15 - Battery Capacity Granularity 2
|
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" ", // 16 - Model Number
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" ", // 17 - Serial Number
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" ", // 18 - Battery Type
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" " // 19 - OEM Information
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})
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Method (IVBX, 0, NotSerialized)
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{
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PBIX [2] = 0xFFFFFFFF
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PBIX [3] = 0xFFFFFFFF
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PBIX [5] = 0xFFFFFFFF
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PBIX [16] = " "
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PBIX [17] = " "
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PBIX [18] = " "
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PBIX [19] = " "
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BFCC = 0
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}
|
||||
|
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Method (UPBX, 0, NotSerialized)
|
||||
{
|
||||
If (^^PCI0.LPCB.EC0.BAT0)
|
||||
{
|
||||
Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
|
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PBIX [2] = Local0
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Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
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PBIX [3] = Local0
|
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BFCC = Local0
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Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
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PBIX [5] = Local0
|
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Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
|
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PBIX [6] = Local0
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Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
|
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PBIX [7] = Local0
|
||||
LOCAL0 = ^^PCI0.LPCB.EC0.CYC0
|
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PBIX [8] = LOCAL0
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PBIX [16] = "BAT"
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PBIX [17] = "0001"
|
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PBIX [18] = "LION"
|
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PBIX [19] = "Notebook"
|
||||
}
|
||||
Else
|
||||
{
|
||||
IVBX ()
|
||||
}
|
||||
}
|
||||
|
||||
// _BIX: Battery Information Extended
|
||||
Method (_BIX, 0, NotSerialized)
|
||||
{
|
||||
If (^^PCI0.LPCB.EC0.ECOK)
|
||||
{
|
||||
UPBX ()
|
||||
}
|
||||
Else
|
||||
{
|
||||
IVBX ()
|
||||
}
|
||||
Return (PBIX) /* \_SB_.BAT0.PBIX */
|
||||
}
|
||||
|
||||
Name (PBST, Package (0x04)
|
||||
{
|
||||
0, // 0 - Battery state
|
||||
0xFFFFFFFF, // 1 - Battery present rate
|
||||
0xFFFFFFFF, // 2 - Battery remaining capacity
|
||||
0xFFFFFFFF // 3 - Battery present voltage
|
||||
})
|
||||
Method (IVBS, 0, NotSerialized)
|
||||
{
|
||||
PBST [0] = 0
|
||||
PBST [1] = 0xFFFFFFFF
|
||||
PBST [2] = 0xFFFFFFFF
|
||||
PBST [3] = 0xFFFFFFFF
|
||||
}
|
||||
|
||||
Method (UPBS, 0, NotSerialized)
|
||||
{
|
||||
If (^^PCI0.LPCB.EC0.BAT0)
|
||||
{
|
||||
Local0 = 0
|
||||
Local1 = 0
|
||||
If (^^AC.ACFG)
|
||||
{
|
||||
If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02))
|
||||
{
|
||||
Local0 |= 0x02
|
||||
Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
|
||||
}
|
||||
}
|
||||
Else
|
||||
{
|
||||
Local0 |= 1
|
||||
Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
|
||||
}
|
||||
|
||||
Local7 = (Local1 & 0x8000)
|
||||
If ((Local7 == 0x8000))
|
||||
{
|
||||
Local1 ^= 0xFFFF
|
||||
}
|
||||
|
||||
Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF)
|
||||
Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF)
|
||||
PBST [0] = Local0
|
||||
PBST [1] = Local1
|
||||
PBST [2] = Local2
|
||||
PBST [3] = Local3
|
||||
If ((BFCC != ^^PCI0.LPCB.EC0.BFC0))
|
||||
{
|
||||
Notify (BAT0, 0x81) // Information Change
|
||||
}
|
||||
}
|
||||
Else
|
||||
{
|
||||
IVBS ()
|
||||
}
|
||||
}
|
||||
|
||||
Method (_BST, 0, NotSerialized) // _BST: Battery Status
|
||||
{
|
||||
If (^^PCI0.LPCB.EC0.ECOK)
|
||||
{
|
||||
UPBS ()
|
||||
}
|
||||
Else
|
||||
{
|
||||
IVBS ()
|
||||
}
|
||||
|
||||
Return (PBST) /* \_SB_.BAT0.PBST */
|
||||
}
|
||||
}
|
@@ -1,46 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Field (ERAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
Offset (0xBC),
|
||||
BTL0, 8, /* BAT0 charging start threshold */
|
||||
BTH0, 8, /* BAT0 charging end threshold */
|
||||
}
|
||||
|
||||
/*
|
||||
* Get battery charging threshold
|
||||
*
|
||||
* Arg0: 0: Start threshold
|
||||
* 1: Stop threshold
|
||||
*/
|
||||
Method (GBCT, 1, NotSerialized)
|
||||
{
|
||||
If (Arg0 == 0) {
|
||||
Return (BTL0)
|
||||
}
|
||||
|
||||
If (Arg0 == 1) {
|
||||
Return (BTH0)
|
||||
}
|
||||
|
||||
Return (0xFF)
|
||||
}
|
||||
|
||||
/*
|
||||
* Set battery charging threshold
|
||||
*
|
||||
* Arg0: 0: Start threshold
|
||||
* 1: Stop threshold
|
||||
* Arg1: Percentage
|
||||
*/
|
||||
Method (SBCT, 2, NotSerialized)
|
||||
{
|
||||
If (Arg1 <= 100) {
|
||||
If (Arg0 == 0) {
|
||||
BTL0 = Arg1
|
||||
}
|
||||
If (Arg0 == 1) {
|
||||
BTH0 = Arg1
|
||||
}
|
||||
}
|
||||
}
|
@@ -1,13 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Device (PWRB)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0C"))
|
||||
Name (_PRW, Package () { EC_GPE_SWI, 3 })
|
||||
}
|
||||
|
||||
Device (SLPB)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0E"))
|
||||
Name (_PRW, Package () { EC_GPE_SWI, 3 })
|
||||
}
|
@@ -1,241 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Scope (\_SB) {
|
||||
#include "ac.asl"
|
||||
#include "battery.asl"
|
||||
#include "buttons.asl"
|
||||
#include "hid.asl"
|
||||
#include "lid.asl"
|
||||
#include "s76.asl"
|
||||
}
|
||||
|
||||
Device (\_SB.PCI0.LPCB.EC0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */)
|
||||
Name (_GPE, EC_GPE_SCI) // _GPE: General Purpose Events
|
||||
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
|
||||
{
|
||||
IO (Decode16,
|
||||
0x0062, // Range Minimum
|
||||
0x0062, // Range Maximum
|
||||
0x00, // Alignment
|
||||
0x01, // Length
|
||||
)
|
||||
IO (Decode16,
|
||||
0x0066, // Range Minimum
|
||||
0x0066, // Range Maximum
|
||||
0x00, // Alignment
|
||||
0x01, // Length
|
||||
)
|
||||
})
|
||||
|
||||
#include "ec_ram.asl"
|
||||
|
||||
Name (ECOK, 0)
|
||||
Method (_REG, 2, Serialized) // _REG: Region Availability
|
||||
{
|
||||
Printf ("EC: _REG %o %o", ToHexString(Arg0), ToHexString(Arg1))
|
||||
If ((Arg0 == 0x03) && (Arg1 == 1)) {
|
||||
// Enable hardware touchpad lock, airplane mode, and keyboard backlight keys
|
||||
ECOS = 1
|
||||
|
||||
// Enable software display brightness keys
|
||||
WINF = 1
|
||||
|
||||
// Set current AC state
|
||||
^^^^AC.ACFG = ADP
|
||||
// Update battery information and status
|
||||
^^^^BAT0.UPBI()
|
||||
^^^^BAT0.UPBS()
|
||||
|
||||
// Notify of changes
|
||||
Notify(^^^^AC, 0)
|
||||
Notify(^^^^BAT0, 0)
|
||||
|
||||
PNOT ()
|
||||
|
||||
// EC is now available
|
||||
ECOK = Arg1
|
||||
|
||||
// Reset Dasharo Device
|
||||
^^^^S76D.RSET()
|
||||
}
|
||||
}
|
||||
|
||||
Name (S3OS, 0)
|
||||
Method (PTS, 1, Serialized) {
|
||||
Printf ("EC: PTS: %o", ToHexString(Arg0))
|
||||
If (ECOK) {
|
||||
// Save ECOS during sleep
|
||||
S3OS = ECOS
|
||||
|
||||
// Clear wake cause
|
||||
WFNO = 0
|
||||
}
|
||||
}
|
||||
|
||||
Method (WAK, 1, Serialized) {
|
||||
Printf ("EC: WAK: %o", ToHexString(Arg0))
|
||||
If (ECOK) {
|
||||
// Restore ECOS after sleep
|
||||
ECOS = S3OS
|
||||
|
||||
// Set current AC state
|
||||
^^^^AC.ACFG = ADP
|
||||
|
||||
// Update battery information and status
|
||||
^^^^BAT0.UPBI()
|
||||
^^^^BAT0.UPBS()
|
||||
|
||||
// Notify of changes
|
||||
Notify(^^^^AC, 0)
|
||||
Notify(^^^^BAT0, 0)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_Q0A, 0, NotSerialized) // Touchpad Toggle
|
||||
{
|
||||
Printf ("EC: Touchpad Toggle")
|
||||
}
|
||||
|
||||
Method (_Q0B, 0, NotSerialized) // Screen Toggle
|
||||
{
|
||||
Printf ("EC: Screen Toggle")
|
||||
#if CONFIG(EC_DASHARO_EC_OLED)
|
||||
Notify (^^^^S76D, 0x85)
|
||||
#endif // CONFIG(EC_DASHARO_EC_OLED)
|
||||
}
|
||||
|
||||
Method (_Q0C, 0, NotSerialized) // Mute
|
||||
{
|
||||
Printf ("EC: Mute")
|
||||
}
|
||||
|
||||
Method (_Q0D, 0, NotSerialized) // Keyboard Backlight
|
||||
{
|
||||
Printf ("EC: Keyboard Backlight")
|
||||
}
|
||||
|
||||
Method (_Q0E, 0, NotSerialized) // Volume Down
|
||||
{
|
||||
Printf ("EC: Volume Down")
|
||||
}
|
||||
|
||||
Method (_Q0F, 0, NotSerialized) // Volume Up
|
||||
{
|
||||
Printf ("EC: Volume Up")
|
||||
}
|
||||
|
||||
Method (_Q10, 0, NotSerialized) // Switch Video Mode
|
||||
{
|
||||
Printf ("EC: Switch Video Mode")
|
||||
}
|
||||
|
||||
Method (_Q11, 0, NotSerialized) // Brightness Down
|
||||
{
|
||||
Printf ("EC: Brightness Down")
|
||||
if (^^^^HIDD.HRDY) {
|
||||
^^^^HIDD.HPEM (20)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_Q12, 0, NotSerialized) // Brightness Up
|
||||
{
|
||||
Printf ("EC: Brightness Up")
|
||||
if (^^^^HIDD.HRDY) {
|
||||
^^^^HIDD.HPEM (19)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_Q13, 0, NotSerialized) // Camera Toggle
|
||||
{
|
||||
Printf ("EC: Camera Toggle")
|
||||
}
|
||||
|
||||
Method (_Q14, 0, NotSerialized) // Airplane Mode
|
||||
{
|
||||
Printf ("EC: Airplane Mode")
|
||||
if (^^^^HIDD.HRDY) {
|
||||
^^^^HIDD.HPEM (8)
|
||||
}
|
||||
// TODO: hardware airplane mode
|
||||
}
|
||||
|
||||
Method (_Q15, 0, NotSerialized) // Suspend Button
|
||||
{
|
||||
Printf ("EC: Suspend Button")
|
||||
Notify (SLPB, 0x80)
|
||||
}
|
||||
|
||||
Method (_Q16, 0, NotSerialized) // AC Detect
|
||||
{
|
||||
Printf ("EC: AC Detect")
|
||||
^^^^AC.ACFG = ADP
|
||||
Notify (AC, 0x80) // Status Change
|
||||
If (BAT0)
|
||||
{
|
||||
Notify (^^^^BAT0, 0x81) // Information Change
|
||||
Notify (^^^^BAT0, 0x80) // Status Change
|
||||
}
|
||||
}
|
||||
|
||||
Method (_Q17, 0, NotSerialized) // BAT0 Update
|
||||
{
|
||||
Printf ("EC: BAT0 Update (17)")
|
||||
Notify (^^^^BAT0, 0x81) // Information Change
|
||||
}
|
||||
|
||||
Method (_Q19, 0, NotSerialized) // BAT0 Update
|
||||
{
|
||||
Printf ("EC: BAT0 Update (19)")
|
||||
Notify (^^^^BAT0, 0x81) // Information Change
|
||||
}
|
||||
|
||||
Method (_Q1B, 0, NotSerialized) // Lid Close
|
||||
{
|
||||
Printf ("EC: Lid Close")
|
||||
Notify (LID0, 0x80)
|
||||
}
|
||||
|
||||
Method (_Q1C, 0, NotSerialized) // Thermal Trip
|
||||
{
|
||||
Printf ("EC: Thermal Trip")
|
||||
/* TODO
|
||||
Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change
|
||||
Notify (\_TZ.TZ0, 0x80) // Thermal Status Change
|
||||
*/
|
||||
}
|
||||
|
||||
Method (_Q1D, 0, NotSerialized) // Power Button
|
||||
{
|
||||
Printf ("EC: Power Button")
|
||||
Notify (PWRB, 0x80)
|
||||
}
|
||||
|
||||
Method (_Q50, 0, NotSerialized) // Other Events
|
||||
{
|
||||
Local0 = OEM4
|
||||
If (Local0 == 0x8A) {
|
||||
Printf ("EC: White Keyboard Backlight")
|
||||
Notify (^^^^S76D, 0x80)
|
||||
} ElseIf (Local0 == 0x9F) {
|
||||
Printf ("EC: Color Keyboard Toggle")
|
||||
Notify (^^^^S76D, 0x81)
|
||||
} ElseIf (Local0 == 0x81) {
|
||||
Printf ("EC: Color Keyboard Down")
|
||||
Notify (^^^^S76D, 0x82)
|
||||
} ElseIf (Local0 == 0x82) {
|
||||
Printf ("EC: Color Keyboard Up")
|
||||
Notify (^^^^S76D, 0x83)
|
||||
} ElseIf (Local0 == 0x80) {
|
||||
Printf ("EC: Color Keyboard Color Change")
|
||||
Notify (^^^^S76D, 0x84)
|
||||
} Else {
|
||||
Printf ("EC: Other: %o", ToHexString(Local0))
|
||||
}
|
||||
}
|
||||
|
||||
#if CONFIG(EC_DASHARO_EC_BAT_THRESHOLDS)
|
||||
#include "battery_thresholds.asl"
|
||||
#endif
|
||||
}
|
@@ -1,55 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
OperationRegion (ERAM, EmbeddedControl, 0, 0xFF)
|
||||
Field (ERAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
Offset (0x03),
|
||||
LSTE, 1, // Lid is open
|
||||
, 1,
|
||||
LWKE, 1, // Lid wake
|
||||
, 5,
|
||||
Offset (0x07),
|
||||
TMP1, 8, // CPU temperature
|
||||
Offset (0x10),
|
||||
ADP, 1, // AC adapter connected
|
||||
, 1,
|
||||
BAT0, 1, // Battery connected
|
||||
, 5,
|
||||
WFNO, 8, // Wake cause (not implemented)
|
||||
Offset (0x16),
|
||||
BDC0, 32, // Battery design capacity
|
||||
BFC0, 32, // Battery full capacity
|
||||
Offset (0x22),
|
||||
BDV0, 32, // Battery design voltage
|
||||
BST0, 32, // Battery status
|
||||
BPR0, 32, // Battery current
|
||||
BRC0, 32, // Battery remaining capacity
|
||||
BPV0, 32, // Battery voltage
|
||||
Offset (0x3A),
|
||||
BCW0, 32,
|
||||
BCL0, 32,
|
||||
CYC0, 16, // Battery cycle count
|
||||
Offset (0x68),
|
||||
ECOS, 8, // Detected OS, 0 = no ACPI, 1 = ACPI but no driver, 2 = ACPI with driver
|
||||
Offset (0xC8),
|
||||
OEM1, 8,
|
||||
OEM2, 8,
|
||||
OEM3, 16,
|
||||
OEM4, 8, // Extra SCI data
|
||||
Offset (0xCD),
|
||||
TMP2, 8, // GPU temperature
|
||||
DUT1, 8, // Fan 1 duty
|
||||
DUT2, 8, // Fan 2 duty
|
||||
RPM1, 16, // Fan 1 RPM
|
||||
RPM2, 16, // Fan 2 RPM
|
||||
Offset (0xD9),
|
||||
AIRP, 8, // Airplane mode LED
|
||||
WINF, 8, // Enable ACPI brightness controls
|
||||
Offset (0xF8),
|
||||
FCMD, 8,
|
||||
FDAT, 8,
|
||||
FBUF, 8,
|
||||
FBF1, 8,
|
||||
FBF2, 8,
|
||||
FBF3, 8,
|
||||
}
|
@@ -1,50 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Device (HIDD)
|
||||
{
|
||||
Name (_HID, "INT33D5")
|
||||
Name (HBSY, 0)
|
||||
Name (HIDX, 0)
|
||||
Name (HRDY, 0)
|
||||
|
||||
Method (HDEM, 0, Serialized)
|
||||
{
|
||||
HBSY = 0
|
||||
Return (HIDX)
|
||||
}
|
||||
|
||||
Method (HDMM, 0, Serialized)
|
||||
{
|
||||
Return (0)
|
||||
}
|
||||
|
||||
Method (HDSM, 1, Serialized)
|
||||
{
|
||||
HRDY = Arg0
|
||||
}
|
||||
|
||||
Method (HPEM, 1, Serialized)
|
||||
{
|
||||
HBSY = 1
|
||||
HIDX = Arg0
|
||||
|
||||
Notify (HIDD, 0xC0)
|
||||
Local0 = 0
|
||||
While ((Local0 < 0xFA) && HBSY)
|
||||
{
|
||||
Sleep (0x04)
|
||||
Local0++
|
||||
}
|
||||
|
||||
If (HBSY == 1)
|
||||
{
|
||||
HBSY = 0
|
||||
HIDX = 0
|
||||
Return (1)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (0)
|
||||
}
|
||||
}
|
||||
}
|
@@ -1,23 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Device (LID0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0D"))
|
||||
Name (_PRW, Package () { EC_GPE_SWI, 3 })
|
||||
|
||||
Method (_LID, 0, NotSerialized) {
|
||||
Printf ("LID: _LID")
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
Return (^^PCI0.LPCB.EC0.LSTE)
|
||||
} Else {
|
||||
Return (1)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PSW, 1, NotSerialized) {
|
||||
Printf ("LID: _PSW: %o", ToHexString(Arg0))
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.LWKE = Arg0
|
||||
}
|
||||
}
|
||||
}
|
@@ -1,178 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
// Notifications:
|
||||
// 0x80 - hardware backlight toggle
|
||||
// 0x81 - backlight toggle
|
||||
// 0x82 - backlight down
|
||||
// 0x83 - backlight up
|
||||
// 0x84 - backlight color change
|
||||
// 0x85 - OLED screen toggle
|
||||
Device (S76D) {
|
||||
Name (_HID, "17761776")
|
||||
Name (_UID, 0)
|
||||
// Hide the device so that Windows does not warn about a missing driver.
|
||||
Name (_STA, 0xB)
|
||||
|
||||
Method (RSET, 0, Serialized) {
|
||||
Printf ("S76D: RSET")
|
||||
SAPL(0)
|
||||
SKBB(0)
|
||||
SKBC(0xFFFFFF)
|
||||
}
|
||||
|
||||
Method (INIT, 0, Serialized) {
|
||||
Printf ("S76D: INIT")
|
||||
RSET()
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
// Set flags to use software control
|
||||
^^PCI0.LPCB.EC0.ECOS = 2
|
||||
Return (0)
|
||||
} Else {
|
||||
Return (1)
|
||||
}
|
||||
}
|
||||
|
||||
Method (FINI, 0, Serialized) {
|
||||
Printf ("S76D: FINI")
|
||||
RSET()
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
// Set flags to use hardware control
|
||||
^^PCI0.LPCB.EC0.ECOS = 1
|
||||
Return (0)
|
||||
} Else {
|
||||
Return (1)
|
||||
}
|
||||
}
|
||||
|
||||
// Get Airplane LED
|
||||
Method (GAPL, 0, Serialized) {
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
If (^^PCI0.LPCB.EC0.AIRP & 0x40) {
|
||||
Return (1)
|
||||
}
|
||||
}
|
||||
Return (0)
|
||||
}
|
||||
|
||||
// Set Airplane LED
|
||||
Method (SAPL, 1, Serialized) {
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
If (Arg0) {
|
||||
^^PCI0.LPCB.EC0.AIRP |= 0x40
|
||||
} Else {
|
||||
^^PCI0.LPCB.EC0.AIRP &= 0xBF
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Get Keyboard Backlight Kind
|
||||
// 0 - No backlight
|
||||
// 1 - White backlight
|
||||
// 2 - RGB backlight
|
||||
Method (GKBK, 0, Serialized) {
|
||||
Local0 = 0
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.FDAT = 2
|
||||
^^PCI0.LPCB.EC0.FCMD = 0xCA
|
||||
Local0 = ^^PCI0.LPCB.EC0.FBUF
|
||||
}
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
// Get Keyboard Brightness
|
||||
Method (GKBB, 0, Serialized) {
|
||||
Local0 = 0
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.FDAT = 1
|
||||
^^PCI0.LPCB.EC0.FCMD = 0xCA
|
||||
Local0 = ^^PCI0.LPCB.EC0.FBUF
|
||||
}
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
// Set Keyboard Brightness
|
||||
Method (SKBB, 1, Serialized) {
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.FDAT = 0
|
||||
^^PCI0.LPCB.EC0.FBUF = Arg0
|
||||
^^PCI0.LPCB.EC0.FCMD = 0xCA
|
||||
}
|
||||
}
|
||||
|
||||
// Get Keyboard Color
|
||||
Method (GKBC, 0, Serialized) {
|
||||
Local0 = 0
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.FDAT = 4
|
||||
^^PCI0.LPCB.EC0.FCMD = 0xCA
|
||||
Local0 = ^^PCI0.LPCB.EC0.FBUF
|
||||
Local0 |= (^^PCI0.LPCB.EC0.FBF1) << 16
|
||||
Local0 |= (^^PCI0.LPCB.EC0.FBF2) << 8
|
||||
}
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
// Set Keyboard Color
|
||||
Method (SKBC, 1, Serialized) {
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.FDAT = 3
|
||||
^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF)
|
||||
^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF)
|
||||
^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF)
|
||||
^^PCI0.LPCB.EC0.FCMD = 0xCA
|
||||
}
|
||||
}
|
||||
|
||||
// Fan names
|
||||
Method (NFAN, 0, Serialized) {
|
||||
Return (Package() {
|
||||
"CPU fan",
|
||||
#if CONFIG(EC_DASHARO_EC_DGPU)
|
||||
"GPU fan",
|
||||
#endif
|
||||
})
|
||||
}
|
||||
|
||||
// Get fan duty cycle and RPM as a single value
|
||||
Method (GFAN, 1, Serialized) {
|
||||
Local0 = 0
|
||||
Local1 = 0
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
If (Arg0 == 0) {
|
||||
Local0 = ^^PCI0.LPCB.EC0.DUT1
|
||||
Local1 = ^^PCI0.LPCB.EC0.RPM1
|
||||
} ElseIf (Arg0 == 1) {
|
||||
Local0 = ^^PCI0.LPCB.EC0.DUT2
|
||||
Local1 = ^^PCI0.LPCB.EC0.RPM2
|
||||
}
|
||||
}
|
||||
If (Local1 != 0) {
|
||||
// 60 * (EC frequency / 120) / 2
|
||||
Local1 = 2156250 / Local1
|
||||
}
|
||||
Return ((Local1 << 8) | Local0)
|
||||
}
|
||||
|
||||
// Temperature names
|
||||
Method (NTMP, 0, Serialized) {
|
||||
Return (Package() {
|
||||
"CPU temp",
|
||||
#if CONFIG(EC_DASHARO_EC_DGPU)
|
||||
"GPU temp",
|
||||
#endif
|
||||
})
|
||||
}
|
||||
|
||||
// Get temperature
|
||||
Method (GTMP, 1, Serialized) {
|
||||
Local0 = 0;
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
If (Arg0 == 0) {
|
||||
Local0 = ^^PCI0.LPCB.EC0.TMP1
|
||||
} ElseIf (Arg0 == 1) {
|
||||
Local0 = ^^PCI0.LPCB.EC0.TMP2
|
||||
}
|
||||
}
|
||||
Return (Local0)
|
||||
}
|
||||
}
|
@@ -1,112 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include "dasharo_ec.h"
|
||||
#include <arch/io.h>
|
||||
#include <console/dasharo_ec.h>
|
||||
#include <console/console.h>
|
||||
#include <timer.h>
|
||||
|
||||
// This is the command region for Dasharo EC firmware. It must be
|
||||
// enabled for LPC in the mainboard.
|
||||
#define DASHARO_EC_BASE 0x0E00
|
||||
#define DASHARO_EC_SIZE 256
|
||||
|
||||
#define REG_CMD 0
|
||||
#define REG_RESULT 1
|
||||
#define REG_DATA 2 // Start of command data
|
||||
|
||||
// When command register is 0, command is complete
|
||||
#define CMD_FINISHED 0
|
||||
|
||||
#define RESULT_OK 0
|
||||
|
||||
// Print command. Registers are unique for each command
|
||||
#define CMD_PRINT 4
|
||||
#define CMD_PRINT_REG_FLAGS 2
|
||||
#define CMD_PRINT_REG_LEN 3
|
||||
#define CMD_PRINT_REG_DATA 4
|
||||
|
||||
static inline uint8_t dasharo_ec_read(uint8_t addr)
|
||||
{
|
||||
return inb(DASHARO_EC_BASE + (uint16_t)addr);
|
||||
}
|
||||
|
||||
static inline void dasharo_ec_write(uint8_t addr, uint8_t data)
|
||||
{
|
||||
outb(data, DASHARO_EC_BASE + (uint16_t)addr);
|
||||
}
|
||||
|
||||
void dasharo_ec_init(void)
|
||||
{
|
||||
// Clear entire command region
|
||||
for (int i = 0; i < DASHARO_EC_SIZE; i++)
|
||||
dasharo_ec_write((uint8_t)i, 0);
|
||||
}
|
||||
|
||||
void dasharo_ec_flush(void)
|
||||
{
|
||||
dasharo_ec_write(REG_CMD, CMD_PRINT);
|
||||
|
||||
// Wait for command completion, for up to 10 milliseconds, with a
|
||||
// test period of 1 microsecond
|
||||
wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED);
|
||||
|
||||
dasharo_ec_write(CMD_PRINT_REG_LEN, 0);
|
||||
}
|
||||
|
||||
void dasharo_ec_print(uint8_t byte)
|
||||
{
|
||||
uint8_t len = dasharo_ec_read(CMD_PRINT_REG_LEN);
|
||||
dasharo_ec_write(CMD_PRINT_REG_DATA + len, byte);
|
||||
dasharo_ec_write(CMD_PRINT_REG_LEN, len + 1);
|
||||
|
||||
// If we hit the end of the buffer, or were given a newline, flush
|
||||
if (byte == '\n' || len >= (DASHARO_EC_SIZE - CMD_PRINT_REG_DATA))
|
||||
dasharo_ec_flush();
|
||||
}
|
||||
|
||||
bool dasharo_ec_cmd(uint8_t cmd, const uint8_t *request_data,
|
||||
uint8_t request_size, uint8_t *reply_data, uint8_t reply_size)
|
||||
{
|
||||
if (request_size > DASHARO_EC_SIZE - REG_DATA ||
|
||||
reply_size > DASHARO_EC_SIZE - REG_DATA) {
|
||||
printk(BIOS_ERR, "EC command %d too long - request size %u, reply size %u\n",
|
||||
cmd, request_size, reply_size);
|
||||
return false;
|
||||
}
|
||||
|
||||
/* If any data were buffered by dasharo_ec_print(), flush it first */
|
||||
uint8_t buffered_len = dasharo_ec_read(CMD_PRINT_REG_LEN);
|
||||
if (buffered_len > 0)
|
||||
dasharo_ec_flush();
|
||||
|
||||
/* Write the data */
|
||||
uint8_t i;
|
||||
for (i = 0; i < request_size; ++i)
|
||||
dasharo_ec_write(REG_DATA + i, request_data[i]);
|
||||
|
||||
/* Write the command */
|
||||
dasharo_ec_write(REG_CMD, cmd);
|
||||
|
||||
/* Wait for the command to complete */
|
||||
bool ret = true;
|
||||
int elapsed = wait_ms(1000, dasharo_ec_read(REG_CMD) == CMD_FINISHED);
|
||||
if (elapsed == 0) {
|
||||
/* Timed out: fail the command, don't attempt to read a reply. */
|
||||
printk(BIOS_WARNING, "EC command %d timed out - request size %d, reply size %d\n",
|
||||
cmd, request_size, reply_size);
|
||||
ret = false;
|
||||
} else {
|
||||
/* Read the reply */
|
||||
for (i = 0; i < reply_size; ++i)
|
||||
reply_data[i] = dasharo_ec_read(REG_DATA+i);
|
||||
/* Check the reply status */
|
||||
ret = (dasharo_ec_read(REG_RESULT) == RESULT_OK);
|
||||
}
|
||||
|
||||
/* Reset the flags and length so we can buffer console prints again */
|
||||
dasharo_ec_write(CMD_PRINT_REG_FLAGS, 0);
|
||||
dasharo_ec_write(CMD_PRINT_REG_LEN, 0);
|
||||
|
||||
return ret;
|
||||
}
|
@@ -1,17 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef DASHARO_EC_H
|
||||
#define DASHARO_EC_H
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Send a command to the EC. request_data/request_size are the request payload,
|
||||
* request_data can be NULL if request_size is 0. reply_data/reply_size are
|
||||
* the reply payload, reply_data can be NULL if reply_size is 0.
|
||||
*/
|
||||
bool dasharo_ec_cmd(uint8_t cmd, const uint8_t *request_data,
|
||||
uint8_t request_size, uint8_t *reply_data, uint8_t reply_size);
|
||||
|
||||
#endif
|
@@ -1,9 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <smbios.h>
|
||||
|
||||
smbios_wakeup_type smbios_system_wakeup_type(void)
|
||||
{
|
||||
// TODO: Read wake source from EC.
|
||||
return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
|
||||
}
|
@@ -129,12 +129,6 @@ u32 fdt_find_node_by_alias(const void *blob, const char *alias_name,
|
||||
*/
|
||||
int fdt_next_node_name(const void *blob, uint32_t node_offset, const char **name);
|
||||
|
||||
/* Read memory regions from a flat device-tree. */
|
||||
size_t fdt_read_memory_regions(const void *blob, struct device_tree_region regions[],
|
||||
size_t regions_count);
|
||||
/* Find top of memory from a flat device-tree. */
|
||||
uint64_t fdt_get_memory_top(const void *blob);
|
||||
|
||||
/* Read a flattened device tree into a hierarchical structure which refers to
|
||||
the contents of the flattened tree in place. Modifying the flat tree
|
||||
invalidates the unflattened one. */
|
||||
|
@@ -584,13 +584,7 @@ enum smbios_processor_upgrade_field {
|
||||
/* defines for processor family */
|
||||
#define SMBIOS_PROCESSOR_FAMILY_OTHER 0x01
|
||||
#define SMBIOS_PROCESSOR_FAMILY_UNKNOWN 0x02
|
||||
#define SMBIOS_PROCESSOR_FAMILY_INTEL486 0x06
|
||||
#define SMBIOS_PROCESSOR_FAMILY_PENTIUM_PRO 0x0c
|
||||
#define SMBIOS_PROCESSOR_FAMILY_XEON 0xb3
|
||||
#define SMBIOS_PROCESSOR_FAMILY_FROM_FAMILY2 0xfe
|
||||
|
||||
/* defines for processor family 2 */
|
||||
#define SMBIOS_PROCESSOR_FAMILY2_ARMV8 0x101
|
||||
|
||||
/* defines for processor characteristics */
|
||||
#define PROCESSOR_64BIT_CAPABLE (1 << 2)
|
||||
|
@@ -160,12 +160,10 @@ ramstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
|
||||
ramstage-$(CONFIG_GENERIC_UDELAY) += timer.c
|
||||
ramstage-y += b64_decode.c
|
||||
ramstage-$(CONFIG_ACPI_NHLT) += nhlt.c
|
||||
ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c
|
||||
ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit.c
|
||||
ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c
|
||||
|
||||
romstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c
|
||||
ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c
|
||||
|
||||
romstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c
|
||||
ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c
|
||||
|
||||
|
@@ -12,12 +12,9 @@
|
||||
#include <string.h>
|
||||
#include <stddef.h>
|
||||
#include <stdlib.h>
|
||||
#include <limits.h>
|
||||
|
||||
#define FDT_PATH_MAX_DEPTH 10 // should be a good enough upper bound
|
||||
#define FDT_PATH_MAX_LEN 128 // should be a good enough upper bound
|
||||
#define FDT_MAX_MEMORY_NODES 4 // should be a good enough upper bound
|
||||
#define FDT_MAX_MEMORY_REGIONS 16 // should be a good enough upper bound
|
||||
|
||||
/*
|
||||
* Functions for picking apart flattened trees.
|
||||
@@ -506,96 +503,6 @@ void fdt_print_node(const void *blob, uint32_t offset)
|
||||
print_flat_node(blob, offset, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* fdt_read_memory_regions finds memory ranges from a flat device-tree
|
||||
*
|
||||
* @params blob address of FDT
|
||||
* @params regions all regions that are read inside the reg property of
|
||||
* memory nodes are saved inside this array
|
||||
* @params regions_count maximum number of entries that can be saved inside
|
||||
* the regions array.
|
||||
*
|
||||
* Returns: Either 0 on error or returns the number of regions put into the regions array.
|
||||
*/
|
||||
size_t fdt_read_memory_regions(const void *blob,
|
||||
struct device_tree_region regions[],
|
||||
size_t regions_count)
|
||||
{
|
||||
u32 node, root, addrcp, sizecp;
|
||||
u32 nodes[FDT_MAX_MEMORY_NODES] = {0};
|
||||
size_t region_idx = 0;
|
||||
size_t node_count = 0;
|
||||
|
||||
if (!fdt_is_valid(blob))
|
||||
return 0;
|
||||
|
||||
node = fdt_find_node_by_path(blob, "/memory", &addrcp, &sizecp);
|
||||
if (node) {
|
||||
region_idx += fdt_read_reg_prop(blob, node, addrcp, sizecp,
|
||||
regions, regions_count);
|
||||
if (region_idx >= regions_count) {
|
||||
printk(BIOS_WARNING, "FDT: Too many memory regions\n");
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
root = fdt_find_node_by_path(blob, "/", &addrcp, &sizecp);
|
||||
node_count = fdt_find_subnodes_by_prefix(blob, root, "memory@",
|
||||
&addrcp, &sizecp, nodes,
|
||||
FDT_MAX_MEMORY_NODES);
|
||||
if (node_count >= FDT_MAX_MEMORY_NODES) {
|
||||
printk(BIOS_WARNING, "FDT: Too many memory nodes\n");
|
||||
/* Can still reading the regions for those we got */
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < MIN(node_count, FDT_MAX_MEMORY_NODES); i++) {
|
||||
region_idx += fdt_read_reg_prop(blob, nodes[i], addrcp, sizecp,
|
||||
®ions[region_idx],
|
||||
regions_count - region_idx);
|
||||
if (region_idx >= regions_count) {
|
||||
printk(BIOS_WARNING, "FDT: Too many memory regions\n");
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
for (size_t i = 0; i < MIN(region_idx, regions_count); i++) {
|
||||
printk(BIOS_DEBUG, "FDT: Memory region [%#llx - %#llx]\n",
|
||||
regions[i].addr, regions[i].addr + regions[i].size);
|
||||
}
|
||||
|
||||
return region_idx;
|
||||
}
|
||||
|
||||
/*
|
||||
* fdt_get_memory_top finds top of memory from a flat device-tree
|
||||
*
|
||||
* @params blob address of FDT
|
||||
*
|
||||
* Returns: Either 0 on error or returns the maximum memory address
|
||||
*/
|
||||
uint64_t fdt_get_memory_top(const void *blob)
|
||||
{
|
||||
struct device_tree_region regions[FDT_MAX_MEMORY_REGIONS] = {0};
|
||||
uint64_t top = 0;
|
||||
uint64_t total = 0;
|
||||
size_t count;
|
||||
|
||||
if (!fdt_is_valid(blob))
|
||||
return 0;
|
||||
|
||||
count = fdt_read_memory_regions(blob, regions, FDT_MAX_MEMORY_REGIONS);
|
||||
for (size_t i = 0; i < MIN(count, FDT_MAX_MEMORY_REGIONS); i++) {
|
||||
top = MAX(top, regions[i].addr + regions[i].size);
|
||||
total += regions[i].size;
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "FDT: Found %u MiB of RAM\n",
|
||||
(uint32_t)(total / MiB));
|
||||
|
||||
return top;
|
||||
}
|
||||
|
||||
/*
|
||||
* Functions to turn a flattened tree into an unflattened one.
|
||||
*/
|
||||
@@ -701,7 +608,7 @@ struct device_tree *fdt_unflatten(const void *blob)
|
||||
const struct fdt_header *header = (const struct fdt_header *)blob;
|
||||
tree->header = header;
|
||||
|
||||
if (!fdt_is_valid(blob))
|
||||
if (fdt_is_valid(blob))
|
||||
return NULL;
|
||||
|
||||
uint32_t struct_offset = be32toh(header->structure_offset);
|
||||
|
@@ -159,15 +159,14 @@ chip soc/intel/alderlake
|
||||
end
|
||||
device ref i2c0 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""RTL5682""
|
||||
register "hid" = ""10EC5650""
|
||||
register "name" = ""RT58""
|
||||
register "desc" = ""Headset Codec""
|
||||
register "desc" = ""Realtek RT5650""
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
|
||||
# Set the jd_src to RT5668_JD1 for jack detection
|
||||
register "property_count" = "1"
|
||||
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||
register "property_list[0].name" = ""realtek,jd-src""
|
||||
register "property_list[0].integer" = "1"
|
||||
register "property_list[0].name" = ""realtek,jd-mode""
|
||||
register "property_list[0].integer" = "2"
|
||||
device i2c 1a on end
|
||||
end
|
||||
end # I2C0
|
||||
|
@@ -63,8 +63,6 @@ static const struct mb_cfg variant_memcfg = {
|
||||
.ccc_config = 0xff,
|
||||
},
|
||||
|
||||
.LpDdrDqDqsReTraining = 1,
|
||||
|
||||
.ect = 1, /* Early Command Training */
|
||||
|
||||
.UserBd = BOARD_TYPE_ULT_ULX,
|
||||
|
@@ -122,11 +122,6 @@ config BOARD_GOOGLE_OVIS4ES
|
||||
config BOARD_GOOGLE_REX0
|
||||
select BOARD_GOOGLE_MODEL_REX
|
||||
|
||||
config BOARD_GOOGLE_REX64
|
||||
select BOARD_GOOGLE_MODEL_REX
|
||||
select HAVE_X86_64_SUPPORT
|
||||
select USE_X86_64_SUPPORT
|
||||
|
||||
config BOARD_GOOGLE_REX_EC_ISH
|
||||
select BOARD_GOOGLE_MODEL_REX_EC_ISH
|
||||
|
||||
@@ -187,7 +182,6 @@ config MAINBOARD_FAMILY
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
default "Rex" if BOARD_GOOGLE_REX0
|
||||
default "Rex64" if BOARD_GOOGLE_REX64
|
||||
default "Rex_Ec_Ish" if BOARD_GOOGLE_REX_EC_ISH
|
||||
default "Rex4ES" if BOARD_GOOGLE_REX4ES
|
||||
default "Rex4ES_Ec_Ish" if BOARD_GOOGLE_REX4ES_EC_ISH
|
||||
|
@@ -32,9 +32,6 @@ config BOARD_GOOGLE_REX4ES
|
||||
config BOARD_GOOGLE_REX4ES_EC_ISH
|
||||
bool "-> Rex4ES EC ISH"
|
||||
|
||||
config BOARD_GOOGLE_REX64
|
||||
bool "-> Rex 64"
|
||||
|
||||
config BOARD_GOOGLE_SCREEBO
|
||||
bool "-> Screebo"
|
||||
|
||||
|
@@ -1,12 +1,16 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
config BOARD_RAZER_BLADE_STEALTH_KBL
|
||||
bool
|
||||
if BOARD_RAZER_BLADE_STEALTH_KBL
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select SYSTEM_TYPE_LAPTOP
|
||||
select BOARD_ROMSIZE_KB_8192
|
||||
select SUPERIO_ITE_IT8528E
|
||||
select SOC_INTEL_KABYLAKE
|
||||
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
|
||||
select MEMORY_MAPPED_TPM
|
||||
select MAINBOARD_HAS_TPM2
|
||||
select MAINBOARD_HAS_LIBGFXINIT
|
||||
select HAVE_SPD_IN_CBFS
|
||||
select DRIVERS_I2C_HID
|
||||
@@ -14,31 +18,6 @@ config BOARD_RAZER_BLADE_STEALTH_KBL
|
||||
select HAVE_ACPI_TABLES
|
||||
select DRIVERS_GENERIC_CBFS_SERIAL
|
||||
|
||||
config BOARD_RAZER_BLADE_H2U
|
||||
select BOARD_RAZER_BLADE_STEALTH_KBL
|
||||
select MEMORY_MAPPED_TPM
|
||||
select MAINBOARD_HAS_TPM2
|
||||
|
||||
config BOARD_RAZER_BLADE_H3Q
|
||||
select BOARD_RAZER_BLADE_STEALTH_KBL
|
||||
|
||||
if BOARD_RAZER_BLADE_STEALTH_KBL
|
||||
|
||||
config VARIANT_DIR
|
||||
default "h2u" if BOARD_RAZER_BLADE_H2U
|
||||
default "h3q" if BOARD_RAZER_BLADE_H3Q
|
||||
|
||||
config OVERRIDE_DEVICETREE
|
||||
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
|
||||
config MAINBOARD_FAMILY
|
||||
string
|
||||
default "BLADE_STEALTH"
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
default "H2U: RZ09-01962" if BOARD_RAZER_BLADE_H2U
|
||||
default "H3Q: RZ09-01963/RZ09-01964" if BOARD_RAZER_BLADE_H3Q
|
||||
|
||||
# For now no way to choose the correct the available RAM
|
||||
config BOARD_RAZER_BLADE_STEALTH_KBL_16GB
|
||||
bool "16GB RAM (4x MT52L1G32D4PG)"
|
||||
@@ -48,6 +27,13 @@ config VGA_BIOS_ID
|
||||
string
|
||||
default "8086,5916"
|
||||
|
||||
config MAINBOARD_FAMILY
|
||||
string
|
||||
default "BLADE_STEALTH"
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
default "H2U"
|
||||
|
||||
config MAINBOARD_VERSION
|
||||
string
|
||||
default "1.0"
|
||||
|
@@ -1,7 +1,4 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
config BOARD_RAZER_BLADE_H2U
|
||||
bool "Razer Blade Stealth KabyLake (2016, RZ09-01962, 12.5\")"
|
||||
|
||||
config BOARD_RAZER_BLADE_H3Q
|
||||
bool "Razer Blade Stealth KabyLake (Mid 2017, RZ09-01963/RZ09-10964, 13.3\")"
|
||||
config BOARD_RAZER_BLADE_STEALTH_KBL
|
||||
bool "Razer Blade Stealth KabyLake (2016)"
|
||||
|
@@ -3,8 +3,6 @@
|
||||
subdirs-y += spd
|
||||
|
||||
ramstage-y += ramstage.c
|
||||
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
|
||||
ramstage-y += hda_verb.c
|
||||
|
||||
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
|
||||
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
|
||||
|
@@ -1,5 +1,5 @@
|
||||
Vendor name: RAZER
|
||||
Board name: Blade Stealth KabyLake
|
||||
Board name: Blade Stealth KabyLake (H2U)
|
||||
Category: laptop
|
||||
ROM package: SOIC8
|
||||
ROM protocol: SPI
|
||||
|
@@ -126,6 +126,24 @@ chip soc/intel/skylake
|
||||
|
||||
register "PcieRpHotPlug[4]" = "1"
|
||||
|
||||
register "usb2_ports" = "{
|
||||
[0] = USB2_PORT_MID(OC1), /* Type-A Port (right) */
|
||||
[1] = USB2_PORT_MID(OC1), /* Type-A Port (left) */
|
||||
[2] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
[3] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
[4] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
[5] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
[6] = USB2_PORT_FLEX(OC2), /* Camera */
|
||||
[7] = USB2_PORT_FLEX(OC2), /* Keyboard */
|
||||
[8] = USB2_PORT_FLEX(OC2), /* Touchscreen */
|
||||
}"
|
||||
|
||||
register "usb3_ports" = "{
|
||||
[0] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (left) */
|
||||
[1] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (right) */
|
||||
[5] = USB3_PORT_DEFAULT(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
}"
|
||||
|
||||
# PL1 override 25W
|
||||
# PL2 override 44W
|
||||
register "power_limits_config" = "{
|
||||
@@ -173,6 +191,9 @@ chip soc/intel/skylake
|
||||
device ref pcie_rp5 on end
|
||||
device ref pcie_rp9 on end
|
||||
device ref lpc_espi on
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
chip superio/ite/it8528e
|
||||
device pnp 6e.1 off end
|
||||
device pnp 6e.2 off end
|
||||
|
@@ -20,7 +20,7 @@ const u32 cim_verb_data[] = {
|
||||
AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x03211020),
|
||||
|
||||
/* Intel, Kaby Lake HDMI */
|
||||
/* Intel, KabylakeHDMI */
|
||||
0x8086280b, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
@@ -1,7 +1,7 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include <variant/gpio.h>
|
||||
#include "gpio.h"
|
||||
|
||||
void mainboard_silicon_init_params(FSP_SIL_UPD *params)
|
||||
{
|
||||
|
@@ -4,6 +4,7 @@
|
||||
#define MAINBOARD_SPD_H
|
||||
|
||||
#include <gpio.h>
|
||||
#include "../gpio.h"
|
||||
|
||||
void mainboard_fill_dq_map_data(void *dq_map_ptr);
|
||||
void mainboard_fill_dqs_map_data(void *dqs_map_ptr);
|
||||
|
@@ -1,9 +0,0 @@
|
||||
Vendor name: RAZER
|
||||
Board name: Blade Stealth KabyLake (H2U: RZ09-01962)
|
||||
Board URL: https://mysupport.razer.com/app/answers/detail/a_id/3698/
|
||||
Category: laptop
|
||||
ROM package: SOIC8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
Release year: 2016
|
@@ -1,31 +0,0 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/skylake
|
||||
device domain 0 on
|
||||
device ref south_xhci on
|
||||
register "usb2_ports" = "{
|
||||
[0] = USB2_PORT_MID(OC1), /* Type-A Port (right) */
|
||||
[1] = USB2_PORT_MID(OC1), /* Type-A Port (left) */
|
||||
[2] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
[3] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
[4] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
[5] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
[6] = USB2_PORT_FLEX(OC2), /* Camera */
|
||||
[7] = USB2_PORT_FLEX(OC2), /* Keyboard */
|
||||
[8] = USB2_PORT_FLEX(OC2), /* Touchscreen */
|
||||
}"
|
||||
|
||||
register "usb3_ports" = "{
|
||||
[0] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (left) */
|
||||
[1] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (right) */
|
||||
[5] = USB3_PORT_DEFAULT(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
}"
|
||||
end
|
||||
|
||||
device ref lpc_espi on
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
@@ -1,9 +0,0 @@
|
||||
Vendor name: RAZER
|
||||
Board name: Blade Stealth KabyLake (H3Q: RZ09-01963 / RZ09-01964)
|
||||
Board URL: https://mysupport.razer.com/app/answers/detail/a_id/3694/
|
||||
Category: laptop
|
||||
ROM package: SOIC8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
Release year: 2017
|
@@ -1,34 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC298 */
|
||||
0x10ec0298, /* Vendor ID */
|
||||
0x1a586753, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x1a586753),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x4075812d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x04211020),
|
||||
|
||||
/* Intel, Kaby Lake HDMI */
|
||||
0x8086280b, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x07, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
AZALIA_ARRAY_SIZES;
|
@@ -1,200 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef CFG_GPIO_H
|
||||
#define CFG_GPIO_H
|
||||
|
||||
#include <gpio.h>
|
||||
|
||||
/* Pad configuration was generated automatically using intelp2m utility */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
|
||||
/* ------- GPIO Community 0 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_A ------- */
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A11, 0, DEEP),
|
||||
PAD_NC(GPP_A12, NONE),
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A23, 0, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_B ------- */
|
||||
PAD_CFG_GPO(GPP_B0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B4, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B8, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B10, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP),
|
||||
PAD_CFG_GPO(GPP_B15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B17, 0, DEEP),
|
||||
PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
|
||||
|
||||
/* ------- GPIO Community 1 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_C ------- */
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI_APIC_LOW(GPP_C5, DN_20K, DEEP),
|
||||
/* GPP_C6 - RESERVED */
|
||||
/* GPP_C7 - RESERVED */
|
||||
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C15, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C23, 0, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_D ------- */
|
||||
PAD_CFG_GPO(GPP_D0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D23, 0, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_E ------- */
|
||||
PAD_CFG_GPO(GPP_E0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E1, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E4, 0, DEEP),
|
||||
PAD_CFG_GPI_SCI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT),
|
||||
PAD_CFG_GPO(GPP_E6, 0, DEEP),
|
||||
PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E9, 0, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_E10, 1, DN_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_E11, 1, DN_20K, DEEP),
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT),
|
||||
PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT),
|
||||
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E22, 0, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_E23, 0, DN_20K, PLTRST),
|
||||
|
||||
/* ------- GPIO Community 2 ------- */
|
||||
|
||||
/* -------- GPIO Group GPD -------- */
|
||||
PAD_CFG_NF(GPD0, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD2, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD7, 0, DEEP),
|
||||
PAD_NC(GPD8, NONE),
|
||||
PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
|
||||
|
||||
/* ------- GPIO Community 3 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_F ------- */
|
||||
PAD_CFG_GPO(GPP_F0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F7, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F12, 0, DEEP),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F23, 0, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_G ------- */
|
||||
PAD_CFG_GPO(GPP_G0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G7, 0, DEEP),
|
||||
};
|
||||
|
||||
#endif /* CFG_GPIO_H */
|
@@ -1,23 +0,0 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/skylake
|
||||
device domain 0 on
|
||||
device ref south_xhci on
|
||||
# NOTE: TYPE-C port is controlled by Intel Thunderbolt
|
||||
|
||||
register "usb2_ports" = "{
|
||||
[0] = USB2_PORT_MID(OC0), /* Type-A Port (right) */
|
||||
[1] = USB2_PORT_MID(OC0), /* Type-A Port (left) */
|
||||
[5] = USB2_PORT_SHORT(OC2), /* M.2 Slot (Bluetooth) */
|
||||
[6] = USB2_PORT_FLEX(OC3), /* Camera */
|
||||
[7] = USB2_PORT_FLEX(OC3), /* Keyboard */
|
||||
[8] = USB2_PORT_FLEX(OC_SKIP), /* Touchscreen */
|
||||
}"
|
||||
|
||||
register "usb3_ports" = "{
|
||||
[0] = USB3_PORT_DEFAULT(OC0), /* Type-A Port (left) */
|
||||
[1] = USB3_PORT_DEFAULT(OC0), /* Type-A Port (right) */
|
||||
}"
|
||||
end
|
||||
end
|
||||
end
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
register "common_soc_config" = "{
|
||||
// Touchpad I2C bus
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
# Serial I/O
|
||||
register "SerialIoDevMode" = "{
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
# Serial I/O
|
||||
register "SerialIoDevMode" = "{
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "common_soc_config" = "{
|
||||
// Touchpad I2C bus
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
|
||||
.tdp_pl1_override = 20,
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
|
||||
.tdp_pl1_override = 28,
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
# FIVR configuration
|
||||
# Read EXT_RAIL_CONFIG to determine bitmaps
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
# FIVR configuration
|
||||
# Read EXT_RAIL_CONFIG to determine bitmaps
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{
|
||||
.tdp_pl1_override = 15,
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
|
||||
.tdp_pl1_override = 45,
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
|
||||
.tdp_pl1_override = 45,
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
register "common_soc_config" = "{
|
||||
// Touchpad I2C bus
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
register "common_soc_config" = "{
|
||||
/* Touchpad */
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x1404 inherit
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x1403 inherit
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x1401 inherit
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
register "common_soc_config" = "{
|
||||
// Touchpad I2C bus
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
# Serial I/O
|
||||
register "SerialIoDevMode" = "{
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
# Serial I/O
|
||||
register "SerialIoDevMode" = "{
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/skylake
|
||||
# Send an extra VR mailbox command for the PS4 exit issue
|
||||
register "SendVrMbxCmd" = "2"
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/skylake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x1303 inherit
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/skylake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x1413 inherit
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/skylake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x1313 inherit
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
register "common_soc_config" = "{
|
||||
// Touchpad I2C bus
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
register "common_soc_config" = "{
|
||||
// Touchpad I2C bus
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x50d3 inherit
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x65e5 inherit
|
||||
|
@@ -4,7 +4,7 @@ config BOARD_SYSTEM76_ADDW3
|
||||
bool "addw3"
|
||||
|
||||
config BOARD_SYSTEM76_ADDW4
|
||||
bool "addw4"
|
||||
bool "addw3"
|
||||
|
||||
config BOARD_SYSTEM76_BONW15
|
||||
bool "bonw15"
|
||||
|
@@ -10,6 +10,5 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c
|
||||
ramstage-y += ramstage.c
|
||||
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
|
||||
ramstage-y += variants/$(VARIANT_DIR)/gpio.c
|
||||
ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
|
||||
|
||||
SPD_SOURCES = samsung-M425R1GB4BB0-CQKOD
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "common_soc_config" = "{
|
||||
// Touchpad I2C bus
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
# Support 5600 MT/s memory
|
||||
register "max_dram_speed_mts" = "5600"
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
# Support 5600 MT/s memory
|
||||
register "max_dram_speed_mts" = "5600"
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{
|
||||
.tdp_pl1_override = 20,
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "power_limits_config[RPL_P_682_642_482_45W_CORE]" = "{
|
||||
.tdp_pl1_override = 45,
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x5630 inherit
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
|
||||
.tdp_pl1_override = 15,
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x66a2 inherit
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
# Support 5600 MT/s memory
|
||||
register "max_dram_speed_mts" = "5600"
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/tigerlake
|
||||
register "common_soc_config" = "{
|
||||
// Touchpad I2C bus
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/tigerlake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x5015 inherit
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/tigerlake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x50e1 inherit
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/tigerlake
|
||||
# Power limits
|
||||
register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/tigerlake
|
||||
register "common_soc_config" = "{
|
||||
// Touchpad I2C bus
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/tigerlake
|
||||
# Power limits
|
||||
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/tigerlake
|
||||
# Power limits
|
||||
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/tigerlake
|
||||
# Power limits
|
||||
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
# Lock Down
|
||||
register "common_soc_config" = "{
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x1325 inherit
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x1323 inherit
|
||||
|
@@ -11,6 +11,7 @@
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <intelblocks/cse.h>
|
||||
#include <intelblocks/fast_spi.h>
|
||||
#include <intelblocks/me.h>
|
||||
#include <intelblocks/pmclib.h>
|
||||
#include <intelblocks/post_codes.h>
|
||||
@@ -1310,10 +1311,17 @@ static void cse_set_state(struct device *dev)
|
||||
|
||||
size_t enable_reply_size;
|
||||
|
||||
/* Function Start */
|
||||
|
||||
int send;
|
||||
int result;
|
||||
|
||||
/* Function Start */
|
||||
|
||||
if (fast_spi_flash_descriptor_override()) {
|
||||
printk(BIOS_WARNING, "HECI: not setting ME state because "
|
||||
"flash descriptor override is enabled\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if the CMOS value "me_state" exists, if it doesn't, then
|
||||
* don't do anything.
|
||||
|
@@ -4,6 +4,7 @@
|
||||
#include <bootstate.h>
|
||||
#include <console/console.h>
|
||||
#include <intelblocks/cse.h>
|
||||
#include <intelblocks/fast_spi.h>
|
||||
#include <intelblocks/pmc_ipc.h>
|
||||
#include <security/vboot/vboot_common.h>
|
||||
#include <soc/intel/common/reset.h>
|
||||
@@ -243,6 +244,11 @@ static void do_send_end_of_post(bool wait_for_completion)
|
||||
return;
|
||||
}
|
||||
|
||||
if (fast_spi_flash_descriptor_override()) {
|
||||
printk(BIOS_WARNING, "CSE: not sending EOP because flash descriptor override is enabled\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (!eop_sent) {
|
||||
set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE);
|
||||
timestamp_add_now(TS_ME_END_OF_POST_START);
|
||||
|
@@ -483,6 +483,15 @@ void fast_spi_clear_outstanding_status(void)
|
||||
write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS);
|
||||
}
|
||||
|
||||
/* Check if flash descriptor override is asserted */
|
||||
bool fast_spi_flash_descriptor_override(void)
|
||||
{
|
||||
void *spibar = fast_spi_get_bar();
|
||||
uint32_t hsfsts = read32(spibar + SPIBAR_HSFSTS_CTL);
|
||||
printk(BIOS_DEBUG, "HSFSTS: 0x%X\n", hsfsts);
|
||||
return !(hsfsts & SPIBAR_HSFSTS_FDOPSS);
|
||||
}
|
||||
|
||||
|
||||
/* As there is no official ACPI ID for this controller use the generic PNP ID for now. */
|
||||
static const char *fast_spi_acpi_hid(const struct device *dev)
|
||||
|
@@ -111,5 +111,7 @@ void fast_spi_set_bde(void);
|
||||
* Set FAST_SPIBAR Vendor Component Lock bit.
|
||||
*/
|
||||
void fast_spi_set_vcl(void);
|
||||
/* Check if flash descriptor override is asserted */
|
||||
bool fast_spi_flash_descriptor_override(void);
|
||||
|
||||
#endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */
|
||||
|
@@ -373,7 +373,7 @@ bool generate_pin_irq_map(void)
|
||||
if (!cached_entries)
|
||||
return false;
|
||||
|
||||
pin_irq_map = calloc(MAX_SLOTS * PCI_INT_MAX, sizeof(struct slot_pin_irq_map));
|
||||
pin_irq_map = calloc(MAX_SLOTS, sizeof(struct slot_pin_irq_map) * PCI_INT_MAX);
|
||||
|
||||
pirq_map.type = PIRQ_GSI;
|
||||
legacy_pirq_routing = lpc_get_pic_pirq_routing(&pirq_routes);
|
||||
|
@@ -247,7 +247,6 @@ struct soc_intel_meteorlake_config {
|
||||
uint16_t sata_ports_dito_val[8];
|
||||
|
||||
/* Audio related */
|
||||
uint8_t pch_hda_audio_link_hda_enable;
|
||||
uint8_t pch_hda_dsp_enable;
|
||||
|
||||
bool pch_hda_sdi_enable[MAX_HD_AUDIO_SDI_LINKS];
|
||||
|
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Reference in New Issue
Block a user