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rebase-24.
...
upstream-8
Author | SHA1 | Date | |
---|---|---|---|
|
1d52b376a5 |
36
.gitmodules
vendored
36
.gitmodules
vendored
@@ -1,70 +1,70 @@
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[submodule "3rdparty/blobs"]
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path = 3rdparty/blobs
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url = https://review.coreboot.org/blobs.git
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url = ../blobs.git
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update = none
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ignore = dirty
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[submodule "util/nvidia-cbootimage"]
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path = util/nvidia/cbootimage
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url = https://review.coreboot.org/nvidia-cbootimage.git
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url = ../nvidia-cbootimage.git
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[submodule "vboot"]
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path = 3rdparty/vboot
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url = https://review.coreboot.org/vboot.git
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url = ../vboot.git
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branch = main
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[submodule "arm-trusted-firmware"]
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path = 3rdparty/arm-trusted-firmware
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url = https://review.coreboot.org/arm-trusted-firmware.git
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url = ../arm-trusted-firmware.git
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[submodule "3rdparty/chromeec"]
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path = 3rdparty/chromeec
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url = https://review.coreboot.org/chrome-ec.git
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url = ../chrome-ec.git
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[submodule "libhwbase"]
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path = 3rdparty/libhwbase
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url = https://review.coreboot.org/libhwbase.git
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url = ../libhwbase.git
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[submodule "libgfxinit"]
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path = 3rdparty/libgfxinit
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url = https://review.coreboot.org/libgfxinit.git
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url = ../libgfxinit.git
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[submodule "3rdparty/fsp"]
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path = 3rdparty/fsp
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url = https://review.coreboot.org/fsp.git
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url = ../fsp.git
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update = none
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ignore = dirty
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[submodule "opensbi"]
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path = 3rdparty/opensbi
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url = https://review.coreboot.org/opensbi.git
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url = ../opensbi.git
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[submodule "intel-microcode"]
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path = 3rdparty/intel-microcode
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url = https://review.coreboot.org/intel-microcode.git
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url = ../intel-microcode.git
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update = none
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ignore = dirty
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branch = main
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[submodule "3rdparty/ffs"]
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path = 3rdparty/ffs
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url = https://review.coreboot.org/ffs.git
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url = ../ffs.git
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[submodule "3rdparty/amd_blobs"]
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path = 3rdparty/amd_blobs
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url = https://review.coreboot.org/amd_blobs
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url = ../amd_blobs
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update = none
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ignore = dirty
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[submodule "3rdparty/cmocka"]
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path = 3rdparty/cmocka
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url = https://review.coreboot.org/cmocka.git
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url = ../cmocka.git
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update = none
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branch = stable-1.1
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[submodule "3rdparty/qc_blobs"]
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path = 3rdparty/qc_blobs
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url = https://review.coreboot.org/qc_blobs.git
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url = ../qc_blobs.git
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update = none
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ignore = dirty
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[submodule "3rdparty/intel-sec-tools"]
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path = 3rdparty/intel-sec-tools
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url = https://review.coreboot.org/9esec-security-tooling.git
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url = ../9esec-security-tooling.git
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[submodule "3rdparty/stm"]
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path = 3rdparty/stm
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url = https://review.coreboot.org/STM
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url = ../STM
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branch = stmpe
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[submodule "util/goswid"]
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path = util/goswid
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url = https://review.coreboot.org/goswid.git
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url = ../goswid
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branch = trunk
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[submodule "src/vendorcode/amd/opensil/genoa_poc/opensil"]
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path = src/vendorcode/amd/opensil/genoa_poc/opensil
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url = https://review.coreboot.org/opensil_genoa_poc.git
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url = ../opensil_genoa_poc.git
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|
@@ -501,7 +501,8 @@ CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
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CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie
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CFLAGS_common += -Wstring-compare
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ifeq ($(CONFIG_COMPILER_GCC),y)
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CFLAGS_common += -Wold-style-declaration
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CFLAGS_common += -Wold-style-declaration -Wflex-array-member-not-at-end
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CFLAGS_common += -Wcalloc-transposed-args
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# Don't add these GCC specific flags when running scan-build
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ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
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CFLAGS_common += -Wno-packed-not-aligned
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|
@@ -66,8 +66,8 @@ int smbios_write_type4(unsigned long *current, int handle)
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smbios_processor_id(t->processor_id);
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t->processor_manufacturer = smbios_processor_manufacturer(t->eos);
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t->processor_version = smbios_processor_name(t->eos);
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t->processor_family = SMBIOS_PROCESSOR_FAMILY_FROM_FAMILY2;
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t->processor_family2 = SMBIOS_PROCESSOR_FAMILY2_ARMV8;
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t->processor_family = 0xfe; /* Use processor_family2 field */
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t->processor_family2 = 0x101; /* ARMv8 */
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t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL;
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smbios_cpu_get_core_counts(&t->core_count2, &t->thread_count2);
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|
@@ -68,7 +68,7 @@ static int get_socket_type(void)
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unsigned int __weak smbios_processor_family(struct cpuid_result res)
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{
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return (res.eax > 0) ? SMBIOS_PROCESSOR_FAMILY_PENTIUM_PRO : SMBIOS_PROCESSOR_FAMILY_INTEL486;
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return (res.eax > 0) ? 0x0c : 0x6;
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}
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static size_t get_number_of_caches(size_t max_logical_cpus_sharing_cache)
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|
@@ -1,38 +0,0 @@
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config DRIVERS_GFX_NVIDIA
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bool
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default n
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help
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Support for NVIDIA Optimus graphics
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config DRIVERS_GFX_NVIDIA_BRIDGE
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hex "PCI bridge for the GPU device"
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default 0x01
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depends on DRIVERS_GFX_NVIDIA
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config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
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depends on DRIVERS_GFX_NVIDIA
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bool
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default n
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help
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Support for NVIDIA Dynamic Boost
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config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
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int "Total processor power offset from default TGP in watts"
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default 45
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depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
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help
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This identifies the available power for the CPU or GPU boost
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config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN
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int "Minimum TGP offset from default TGP in watts"
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default 0
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depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
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help
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This is used to transfer power from the GPU to the CPU
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config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
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int "Maximum TGP offset from default TGP in watts"
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default 0
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depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
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help
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This is used to transfer power from the CPU to the GPU
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@@ -1,5 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
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ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c
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@@ -1,96 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* NVIDIA GC6 on CFL and CML CPU PCIe ports */
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// Memory mapped PCI express config space
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OperationRegion (PCIC, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + (CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15), 0x1000)
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Field (PCIC, ByteAcc, NoLock, Preserve) {
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PVID, 16,
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PDID, 16,
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Offset (0x248),
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, 7,
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L23E, 1, /* L23_Rdy Entry Request */
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L23R, 1, /* L23_Rdy to Detect Transition */
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Offset (0xC20),
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, 4,
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P0AP, 2, /* Additional power savings */
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Offset (0xC38),
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, 3,
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P0RM, 1, /* Robust squelch mechanism */
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}
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// Enter L23
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Method (DL23, 0, Serialized) {
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Printf(" GPU PORT DL23 START")
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L23E = 1
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Sleep (16)
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Local0 = 0
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While (L23E) {
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If ((Local0 > 4)) {
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Break
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}
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Sleep (16)
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Local0++
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}
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P0RM = 1
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P0AP = 3
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Printf(" GPU PORT DL23 FINISH")
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}
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// Exit L23
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Method (L23D, 0, Serialized) {
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Printf(" GPU PORT L23D START")
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L23R = 1
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Sleep (16)
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Local0 = 0
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While (L23R) {
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If ((Local0 > 4)) {
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Break
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}
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Sleep (16)
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Local0++
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}
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P0RM = 0
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P0AP = 0
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Printf(" GPU PORT L23D FINISH")
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}
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// Main power resource
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PowerResource (PWRR, 0, 0) {
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Name (_STA, 1)
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Method (_ON, 0, Serialized) {
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Printf("GPU PORT PWRR._ON")
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^^DEV0._ON()
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_STA = 1
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}
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Method (_OFF, 0, Serialized) {
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Printf("GPU PORT PWRR._OFF")
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^^DEV0._OFF()
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_STA = 0
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}
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}
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// Power resources for entering D0
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Name (_PR0, Package () { PWRR })
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// Power resources for entering D3
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Name (_PR3, Package () { PWRR })
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#include "common/gpu.asl"
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@@ -1,30 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#define NV_ERROR_SUCCESS 0x0
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#define NV_ERROR_UNSPECIFIED 0x80000001
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#define NV_ERROR_UNSUPPORTED 0x80000002
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#include "gps.asl"
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#include "nvjt.asl"
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Method (_DSM, 4, Serialized) {
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Printf("GPU _DSM")
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If (Arg0 == ToUUID (JT_DSM_GUID)) {
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If (ToInteger(Arg1) >= JT_REVISION_ID_MIN) {
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Return (NVJT(Arg2, Arg3))
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} Else {
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Printf(" Unsupported JT revision: %o", SFST(Arg1))
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Return (NV_ERROR_UNSUPPORTED)
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}
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} ElseIf (Arg0 == ToUUID (GPS_DSM_GUID)) {
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If (ToInteger(Arg1) == GPS_REVISION_ID) {
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Return (GPS(Arg2, Arg3))
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} Else {
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Printf(" Unsupported GPS revision: %o", SFST(Arg1))
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Return (NV_ERROR_UNSUPPORTED)
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}
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} Else {
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Printf(" Unsupported GUID: %o", IDST(Arg0))
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Return (NV_ERROR_UNSPECIFIED)
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}
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}
|
@@ -1,66 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
|
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|
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#define GPS_DSM_GUID "A3132D01-8CDA-49BA-A52E-BC9D46DF6B81"
|
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#define GPS_REVISION_ID 0x00000200
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#define GPS_FUNC_SUPPORT 0x00000000
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#define GPS_FUNC_PSHARESTATUS 0x00000020
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#define GPS_FUNC_PSHAREPARAMS 0x0000002A
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Method(GPS, 2, Serialized) {
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Printf(" GPU GPS")
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Switch(ToInteger(Arg0)) {
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Case(GPS_FUNC_SUPPORT) {
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Printf(" Supported Functions")
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Return(ITOB(
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(1 << GPS_FUNC_SUPPORT) |
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(1 << GPS_FUNC_PSHARESTATUS) |
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(1 << GPS_FUNC_PSHAREPARAMS)
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))
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}
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Case(GPS_FUNC_PSHARESTATUS) {
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Printf(" Power Share Status")
|
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Return(ITOB(0))
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}
|
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Case(GPS_FUNC_PSHAREPARAMS) {
|
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Printf(" Power Share Parameters")
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CreateField(Arg1, 0, 4, QTYP) // Query type
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|
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Name(GPSP, Buffer(36) { 0x00 })
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CreateDWordField(GPSP, 0, RSTS) // Response status
|
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CreateDWordField(GPSP, 4, VERS) // Version
|
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|
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// Set query type of response
|
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RSTS = QTYP
|
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// Set version of response
|
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VERS = 0x00010000
|
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|
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Switch(ToInteger(QTYP)) {
|
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Case(0) {
|
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Printf(" Request Current Information")
|
||||
// No required information
|
||||
Return(GPSP)
|
||||
}
|
||||
Case(1) {
|
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Printf(" Request Supported Fields")
|
||||
// Support GPU temperature field
|
||||
RSTS |= (1 << 8)
|
||||
Return(GPSP)
|
||||
}
|
||||
Case(2) {
|
||||
Printf(" Request Current Limits")
|
||||
// No required limits
|
||||
Return(GPSP)
|
||||
}
|
||||
Default {
|
||||
Printf(" Unknown Query: %o", SFST(QTYP))
|
||||
Return(NV_ERROR_UNSUPPORTED)
|
||||
}
|
||||
}
|
||||
}
|
||||
Default {
|
||||
Printf(" Unsupported function: %o", SFST(Arg0))
|
||||
Return(NV_ERROR_UNSUPPORTED)
|
||||
}
|
||||
}
|
||||
}
|
@@ -1,18 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Device (DEV0) {
|
||||
Name(_ADR, 0x00000000)
|
||||
|
||||
#include "utility.asl"
|
||||
#include "dsm.asl"
|
||||
#include "power.asl"
|
||||
}
|
||||
|
||||
#if CONFIG(DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST)
|
||||
Scope (\_SB) {
|
||||
Device(NPCF) {
|
||||
#include "utility.asl"
|
||||
#include "nvpcf.asl"
|
||||
}
|
||||
}
|
||||
#endif
|
@@ -1,152 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#define JT_DSM_GUID "CBECA351-067B-4924-9CBD-B46B00B86F34"
|
||||
#define JT_REVISION_ID_MIN 0x00000100
|
||||
#define JT_REVISION_ID_MAX 0x00000200
|
||||
#define JT_FUNC_SUPPORT 0x00000000
|
||||
#define JT_FUNC_CAPS 0x00000001
|
||||
#define JT_FUNC_POWERCONTROL 0x00000003
|
||||
|
||||
//TODO: SMI traps and EGIN/XCLM
|
||||
#define JT_GPC_GSS 0 // Get current GPU GCx sleep status
|
||||
#define JT_GPC_EGNS 1 // Enter GC6 without self-refresh
|
||||
#define JT_GPC_EGIS 2 // Enter GC6 with self-refresh
|
||||
#define JT_GPC_XGXS 3 // Exit GC6 and stop self-refresh
|
||||
#define JT_GPC_XGIS 4 // Exit GC6 for self-refresh update
|
||||
|
||||
#define JT_DFGC_NONE 0 // Handle request immediately
|
||||
#define JT_DFGC_DEFER 1 // Defer GPC and GPCX
|
||||
//TODO #define JT_DFGC_CLEAR 2 // Clear pending requests
|
||||
|
||||
// Deferred GC6 enter/exit until D3-cold (saved DFGC)
|
||||
Name(DFEN, 0)
|
||||
|
||||
// Deferred GC6 enter control (saved GPC)
|
||||
Name(DFCI, 0)
|
||||
|
||||
// Deferred GC6 exit control (saved GPCX)
|
||||
Name(DFCO, 0)
|
||||
|
||||
Method (NVJT, 2, Serialized) {
|
||||
Printf(" GPU NVJT")
|
||||
Switch (ToInteger(Arg0)) {
|
||||
Case (JT_FUNC_SUPPORT) {
|
||||
Printf(" Supported Functions")
|
||||
Return(ITOB(
|
||||
(1 << JT_FUNC_SUPPORT) |
|
||||
(1 << JT_FUNC_CAPS) |
|
||||
(1 << JT_FUNC_POWERCONTROL)
|
||||
))
|
||||
}
|
||||
Case (JT_FUNC_CAPS) {
|
||||
Printf(" Capabilities")
|
||||
Return(ITOB(
|
||||
(1 << 0) | // G-SYNC NSVR power-saving features are enabled
|
||||
(1 << 1) | // NVSR disabled
|
||||
(2 << 3) | // Panel power and backlight are on the suspend rail
|
||||
(0 << 5) | // self-refresh controller remains powered while panel is powered
|
||||
(0 << 6) | // FB is not on the suspend rail but is powered on in GC6
|
||||
(0 << 8) | // Combined power rail for all GPUs
|
||||
(0 << 10) | // External SPI ROM
|
||||
(1 << 11) | // No SMI handler for kernel panic exit while in GC6
|
||||
(0 << 12) | // Supports notify on GC6 state done
|
||||
(1 << 13) | // Support deferred GC6
|
||||
(1 << 14) | // Support fine-grained root port control
|
||||
(2 << 15) | // GC6 version is GC6-R
|
||||
(0 << 17) | // GC6 exit ISR is not supported
|
||||
(0 << 18) | // GC6 self wakeup not supported
|
||||
(JT_REVISION_ID_MAX << 20) // Highest revision supported
|
||||
))
|
||||
}
|
||||
Case (JT_FUNC_POWERCONTROL) {
|
||||
Printf(" Power Control: %o", SFST(Arg1))
|
||||
|
||||
CreateField (Arg1, 0, 3, GPC) // GPU power control
|
||||
CreateField (Arg1, 4, 1, PPC) // Panel power control
|
||||
CreateField (Arg1, 14, 2, DFGC) // Defer GC6 enter/exit until D3 cold
|
||||
CreateField (Arg1, 16, 3, GPCX) // Deferred GC6 exit control
|
||||
|
||||
// Save deferred GC6 request
|
||||
If ((ToInteger(GPC) != 0) || (ToInteger(DFGC) != 0)) {
|
||||
DFEN = DFGC
|
||||
DFCI = GPC
|
||||
DFCO = GPCX
|
||||
}
|
||||
|
||||
// Buffer to cache current state
|
||||
Name (JTBF, Buffer (4) { 0, 0, 0, 0 })
|
||||
CreateField (JTBF, 0, 3, CGCS) // Current GC state
|
||||
CreateField (JTBF, 3, 1, CGPS) // Current GPU power status
|
||||
CreateField (JTBF, 7, 1, CPSS) // Current panel and SRC state (0 when on)
|
||||
|
||||
// If doing deferred GC6 request, return now
|
||||
If (ToInteger(DFGC) != 0) {
|
||||
CGCS = 1
|
||||
CGPS = 1
|
||||
Return (JTBF)
|
||||
}
|
||||
|
||||
// Apply requested state
|
||||
Switch (ToInteger(GPC)) {
|
||||
Case (JT_GPC_GSS) {
|
||||
Printf(" Get current GPU GCx sleep status")
|
||||
//TODO: include transitions!
|
||||
If (GTXS(DGPU_RST_N)) {
|
||||
// GPU powered on
|
||||
CGCS = 1
|
||||
CGPS = 1
|
||||
} ElseIf (GTXS(DGPU_PWR_EN)) {
|
||||
// GPU powered off, GC6
|
||||
CGCS = 3
|
||||
CGPS = 0
|
||||
} Else {
|
||||
// GPU powered off, D3 cold
|
||||
CGCS = 2
|
||||
CGPS = 0
|
||||
}
|
||||
}
|
||||
Case (JT_GPC_EGNS) {
|
||||
Printf(" Enter GC6 without self-refresh")
|
||||
GC6I()
|
||||
CPSS = 1
|
||||
}
|
||||
Case (JT_GPC_EGIS) {
|
||||
Printf(" Enter GC6 with self-refresh")
|
||||
GC6I()
|
||||
If (ToInteger(PPC) == 0) {
|
||||
CPSS = 0
|
||||
}
|
||||
}
|
||||
Case (JT_GPC_XGXS) {
|
||||
Printf(" Exit GC6 and stop self-refresh")
|
||||
GC6O()
|
||||
|
||||
CGCS = 1
|
||||
CGPS = 1
|
||||
If (ToInteger(PPC) != 0) {
|
||||
CPSS = 0
|
||||
}
|
||||
}
|
||||
Case (JT_GPC_XGIS) {
|
||||
Printf(" Exit GC6 for self-refresh update")
|
||||
GC6O()
|
||||
|
||||
CGCS = 1
|
||||
CGPS = 1
|
||||
If (ToInteger(PPC) != 0) {
|
||||
CPSS = 0
|
||||
}
|
||||
}
|
||||
Default {
|
||||
Printf(" Unsupported GPU power control: %o", SFST(GPC))
|
||||
}
|
||||
}
|
||||
|
||||
Return (JTBF)
|
||||
}
|
||||
Default {
|
||||
Printf(" Unsupported function: %o", SFST(Arg0))
|
||||
Return (NV_ERROR_UNSUPPORTED)
|
||||
}
|
||||
}
|
||||
}
|
@@ -1,113 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#define NVPCF_DSM_GUID "36b49710-2483-11e7-9598-0800200c9a66"
|
||||
#define NVPCF_REVISION_ID 0x00000200
|
||||
#define NVPCF_ERROR_SUCCESS 0x0
|
||||
#define NVPCF_ERROR_GENERIC 0x80000001
|
||||
#define NVPCF_ERROR_UNSUPPORTED 0x80000002
|
||||
#define NVPCF_FUNC_GET_SUPPORTED 0x00000000
|
||||
#define NVPCF_FUNC_GET_STATIC_CONFIG_TABLES 0x00000001
|
||||
#define NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS 0x00000002
|
||||
|
||||
Name(_HID, "NVDA0820")
|
||||
|
||||
Name(_UID, "NPCF")
|
||||
|
||||
Method(_DSM, 4, Serialized) {
|
||||
Printf("NVPCF _DSM")
|
||||
If (Arg0 == ToUUID(NVPCF_DSM_GUID)) {
|
||||
If (ToInteger(Arg1) == NVPCF_REVISION_ID) {
|
||||
Return(NPCF(Arg2, Arg3))
|
||||
} Else {
|
||||
Printf(" Unsupported NVPCF revision: %o", SFST(Arg1))
|
||||
Return(NVPCF_ERROR_GENERIC)
|
||||
}
|
||||
} Else {
|
||||
Printf(" Unsupported GUID: %o", IDST(Arg0))
|
||||
Return(NVPCF_ERROR_GENERIC)
|
||||
}
|
||||
}
|
||||
|
||||
Method(NPCF, 2, Serialized) {
|
||||
Printf(" NVPCF NPCF")
|
||||
Switch(ToInteger(Arg0)) {
|
||||
Case(NVPCF_FUNC_GET_SUPPORTED) {
|
||||
Printf(" Supported Functions")
|
||||
Return(ITOB(
|
||||
(1 << NVPCF_FUNC_GET_SUPPORTED) |
|
||||
(1 << NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) |
|
||||
(1 << NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS)
|
||||
))
|
||||
}
|
||||
Case(NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) {
|
||||
Printf(" Get Static Config")
|
||||
Return(Buffer(14) {
|
||||
// Device table header
|
||||
0x20, 0x03, 0x01,
|
||||
// Intel + NVIDIA
|
||||
0x00,
|
||||
// Controller table header
|
||||
0x23, 0x04, 0x05, 0x01,
|
||||
// Dynamic boost controller
|
||||
0x01,
|
||||
// Supports DC
|
||||
0x01,
|
||||
// Reserved
|
||||
0x00, 0x00, 0x00,
|
||||
// Checksum
|
||||
0xAD
|
||||
})
|
||||
}
|
||||
Case(NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS) {
|
||||
Printf(" Update Dynamic Boost")
|
||||
|
||||
CreateField(Arg1, 0x28, 2, ICMD) // Input command
|
||||
|
||||
Name(PCFP, Buffer(49) {
|
||||
// Table version
|
||||
0x23,
|
||||
// Table header size
|
||||
0x05,
|
||||
// Size of common status in bytes
|
||||
0x10,
|
||||
// Size of controller entry in bytes
|
||||
0x1C,
|
||||
// Other fields filled in later
|
||||
})
|
||||
CreateByteField(PCFP, 0x04, CCNT) // Controller count
|
||||
CreateWordField(PCFP, 0x19, ATPP) // AC TPP offset
|
||||
CreateWordField(PCFP, 0x1D, AMXP) // AC maximum TGP offset
|
||||
CreateWordField(PCFP, 0x21, AMNP) // AC minimum TGP offset
|
||||
|
||||
Switch(ToInteger(ICMD)) {
|
||||
Case(0) {
|
||||
Printf(" Get Controller Params")
|
||||
// Number of controllers
|
||||
CCNT = 1
|
||||
// AC total processor power offset from default TGP in 1/8 watt units
|
||||
ATPP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP << 3)
|
||||
// AC maximum TGP offset from default TGP in 1/8 watt units
|
||||
AMXP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX << 3)
|
||||
// AC minimum TGP offset from default TGP in 1/8 watt units
|
||||
AMNP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN << 3)
|
||||
Printf("PCFP: %o", SFST(PCFP))
|
||||
Return(PCFP)
|
||||
}
|
||||
Case(1) {
|
||||
Printf(" Set Controller Status")
|
||||
//TODO
|
||||
Printf("PCFP: %o", SFST(PCFP))
|
||||
Return(PCFP)
|
||||
}
|
||||
Default {
|
||||
Printf(" Unknown Input Command: %o", SFST(ICMD))
|
||||
Return(NV_ERROR_UNSUPPORTED)
|
||||
}
|
||||
}
|
||||
}
|
||||
Default {
|
||||
Printf(" Unsupported function: %o", SFST(Arg0))
|
||||
Return(NVPCF_ERROR_UNSUPPORTED)
|
||||
}
|
||||
}
|
||||
}
|
@@ -1,120 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
//TODO: evaluate sleeps
|
||||
|
||||
OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
|
||||
Field (PCIC, DwordAcc, NoLock, Preserve) {
|
||||
Offset (0x40),
|
||||
SSID, 32, // Subsystem vendor and product ID
|
||||
}
|
||||
|
||||
// Enter GC6
|
||||
Method(GC6I, 0, Serialized) {
|
||||
Printf(" GPU GC6I START")
|
||||
|
||||
// Enter L23
|
||||
^^DL23()
|
||||
Sleep(5)
|
||||
|
||||
// Put GPU into reset
|
||||
Printf(" Put GPU into reset")
|
||||
CTXS(DGPU_RST_N)
|
||||
Sleep(5)
|
||||
|
||||
Printf(" GPU GC6I FINISH")
|
||||
}
|
||||
|
||||
// Exit GC6
|
||||
Method(GC6O, 0, Serialized) {
|
||||
Printf(" GPU GC6O START")
|
||||
|
||||
// Bring GPU out of reset
|
||||
Printf(" Bring GPU out of reset")
|
||||
STXS(DGPU_RST_N)
|
||||
Sleep(5)
|
||||
|
||||
// Exit L23
|
||||
^^L23D()
|
||||
Sleep(5)
|
||||
|
||||
Printf(" GPU GC6O FINISH")
|
||||
}
|
||||
|
||||
Method (_ON, 0, Serialized) {
|
||||
Printf(" GPU _ON START")
|
||||
|
||||
If (DFEN == JT_DFGC_DEFER) {
|
||||
Switch (ToInteger(DFCO)) {
|
||||
Case (JT_GPC_XGXS) {
|
||||
Printf(" Exit GC6 and stop self-refresh")
|
||||
GC6O()
|
||||
}
|
||||
Default {
|
||||
Printf(" Unsupported DFCO: %o", SFST(DFCO))
|
||||
}
|
||||
}
|
||||
DFEN = JT_DFGC_NONE
|
||||
} Else {
|
||||
Printf(" Standard RTD3 power on")
|
||||
STXS(DGPU_PWR_EN)
|
||||
Sleep(5)
|
||||
GC6O()
|
||||
}
|
||||
|
||||
Printf(" GPU _ON FINISH")
|
||||
}
|
||||
|
||||
Method (_OFF, 0, Serialized) {
|
||||
Printf(" GPU _OFF START")
|
||||
|
||||
If (DFEN == JT_DFGC_DEFER) {
|
||||
Switch (ToInteger(DFCI)) {
|
||||
Case (JT_GPC_EGNS) {
|
||||
Printf(" Enter GC6 without self-refresh")
|
||||
GC6I()
|
||||
}
|
||||
Case (JT_GPC_EGIS) {
|
||||
Printf(" Enter GC6 with self-refresh")
|
||||
GC6I()
|
||||
}
|
||||
Default {
|
||||
Printf(" Unsupported DFCI: %o", SFST(DFCI))
|
||||
}
|
||||
}
|
||||
DFEN = JT_DFGC_NONE
|
||||
} Else {
|
||||
Printf(" Standard RTD3 power off")
|
||||
GC6I()
|
||||
CTXS(DGPU_PWR_EN)
|
||||
Sleep(5)
|
||||
}
|
||||
|
||||
Printf(" GPU _OFF FINISH")
|
||||
}
|
||||
|
||||
// Main power resource
|
||||
PowerResource (PWRR, 0, 0) {
|
||||
Name (_STA, 1)
|
||||
|
||||
Method (_ON, 0, Serialized) {
|
||||
Printf("GPU PWRR._ON")
|
||||
|
||||
// Restore SSID
|
||||
^^SSID = DGPU_SSID
|
||||
Printf(" Restore SSID: %o", SFST(^^SSID))
|
||||
|
||||
_STA = 1
|
||||
}
|
||||
|
||||
Method (_OFF, 0, Serialized) {
|
||||
Printf("GPU PWRR._OFF")
|
||||
|
||||
_STA = 0
|
||||
}
|
||||
}
|
||||
|
||||
// Power resources for entering D0
|
||||
Name (_PR0, Package () { PWRR })
|
||||
|
||||
// Power resources for entering D3
|
||||
Name (_PR3, Package () { PWRR })
|
@@ -1,63 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
// Convert a byte to a hex string, trimming extra parts
|
||||
Method (BHEX, 1) {
|
||||
Local0 = ToHexString(Arg0)
|
||||
Return (Mid(Local0, SizeOf(Local0) - 2, 2))
|
||||
}
|
||||
|
||||
// UUID to string
|
||||
Method (IDST, 1) {
|
||||
Local0 = ""
|
||||
Fprintf(
|
||||
Local0,
|
||||
"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
|
||||
BHEX(DerefOf(Arg0[3])),
|
||||
BHEX(DerefOf(Arg0[2])),
|
||||
BHEX(DerefOf(Arg0[1])),
|
||||
BHEX(DerefOf(Arg0[0])),
|
||||
BHEX(DerefOf(Arg0[5])),
|
||||
BHEX(DerefOf(Arg0[4])),
|
||||
BHEX(DerefOf(Arg0[7])),
|
||||
BHEX(DerefOf(Arg0[6])),
|
||||
BHEX(DerefOf(Arg0[8])),
|
||||
BHEX(DerefOf(Arg0[9])),
|
||||
BHEX(DerefOf(Arg0[10])),
|
||||
BHEX(DerefOf(Arg0[11])),
|
||||
BHEX(DerefOf(Arg0[12])),
|
||||
BHEX(DerefOf(Arg0[13])),
|
||||
BHEX(DerefOf(Arg0[14])),
|
||||
BHEX(DerefOf(Arg0[15]))
|
||||
)
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
// Safe hex conversion, checks type first
|
||||
Method (SFST, 1) {
|
||||
Local0 = ObjectType(Arg0)
|
||||
If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
|
||||
Return (ToHexString(Arg0))
|
||||
} Else {
|
||||
Return (Concatenate("Type: ", Arg0))
|
||||
}
|
||||
}
|
||||
|
||||
// Convert from 4-byte buffer to 32-bit integer
|
||||
Method (BTOI, 1) {
|
||||
Return(
|
||||
DerefOf(Arg0[0]) |
|
||||
(DerefOf(Arg0[1]) << 8) |
|
||||
(DerefOf(Arg0[2]) << 16) |
|
||||
(DerefOf(Arg0[3]) << 24)
|
||||
)
|
||||
}
|
||||
|
||||
// Convert from 32-bit integer to 4-byte buffer
|
||||
Method (ITOB, 1) {
|
||||
Local0 = Buffer(4) { 0, 0, 0, 0 }
|
||||
Local0[0] = Arg0 & 0xFF
|
||||
Local0[1] = (Arg0 >> 8) & 0xFF
|
||||
Local0[2] = (Arg0 >> 16) & 0xFF
|
||||
Local0[3] = (Arg0 >> 24) & 0xFF
|
||||
Return (Local0)
|
||||
}
|
@@ -1,140 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* NVIDIA GC6 on (TGL and ADL) (CPU and PCH) PCIe ports */
|
||||
|
||||
// Port mapped PCI express config space
|
||||
OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
|
||||
|
||||
Field (PCIC, AnyAcc, NoLock, Preserve) {
|
||||
Offset(0x52), /* LSTS - Link Status Register */
|
||||
, 13,
|
||||
LASX, 1, /* 0, Link Active Status */
|
||||
|
||||
Offset(0x60), /* RSTS - Root Status Register */
|
||||
, 16,
|
||||
PSPX, 1, /* 16, PME Status */
|
||||
|
||||
Offset(0xD8), /* 0xD8, MPC - Miscellaneous Port Configuration Register */
|
||||
, 30,
|
||||
HPEX, 1, /* 30, Hot Plug SCI Enable */
|
||||
PMEX, 1, /* 31, Power Management SCI Enable */
|
||||
|
||||
Offset (0xE0), /* 0xE0, SPR - Scratch Pad Register */
|
||||
SCB0, 1, /* Scratch bit 0 */
|
||||
|
||||
Offset(0xE2), /* 0xE2, RPPGEN - Root Port Power Gating Enable */
|
||||
, 2,
|
||||
L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */
|
||||
L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */
|
||||
}
|
||||
|
||||
Field (PCIC, AnyAcc, NoLock, WriteAsZeros) {
|
||||
Offset(0xDC), /* 0xDC, SMSCS - SMI/SCI Status Register */
|
||||
, 30,
|
||||
HPSX, 1, /* 30, Hot Plug SCI Status */
|
||||
PMSX, 1 /* 31, Power Management SCI Status */
|
||||
}
|
||||
|
||||
// Enter L23
|
||||
Method (DL23, 0, Serialized) {
|
||||
Printf(" GPU PORT DL23 START")
|
||||
|
||||
L23E = 1
|
||||
Sleep (16)
|
||||
Local0 = 0
|
||||
While (L23E) {
|
||||
If ((Local0 > 4)) {
|
||||
Break
|
||||
}
|
||||
|
||||
Sleep (16)
|
||||
Local0++
|
||||
}
|
||||
SCB0 = 1
|
||||
|
||||
Printf(" GPU PORT DL23 FINISH")
|
||||
}
|
||||
|
||||
// Exit L23
|
||||
Method (L23D, 0, Serialized) {
|
||||
Printf(" GPU PORT L23D START")
|
||||
|
||||
If ((SCB0 == 1)) {
|
||||
L23R = 1
|
||||
Local0 = 0
|
||||
While (L23R) {
|
||||
If ((Local0 > 4)) {
|
||||
Break
|
||||
}
|
||||
Sleep (16)
|
||||
Local0++
|
||||
}
|
||||
|
||||
SCB0 = 0
|
||||
Local0 = 0
|
||||
While ((LASX == 0)) {
|
||||
If ((Local0 > 8)) {
|
||||
Break
|
||||
}
|
||||
Sleep (16)
|
||||
Local0++
|
||||
}
|
||||
}
|
||||
|
||||
Printf(" GPU PORT L23D FINISH")
|
||||
}
|
||||
|
||||
Method (HPME, 0, Serialized) {
|
||||
Printf(" GPU PORT HPME START")
|
||||
|
||||
If (PMSX == 1) {
|
||||
Printf(" Notify GPU driver of PME SCI")
|
||||
Notify(DEV0, 0x2)
|
||||
Printf(" Clear PME SCI")
|
||||
PMSX = 1
|
||||
Printf(" Consume PME notification")
|
||||
PSPX = 1
|
||||
}
|
||||
|
||||
Printf(" GPU PORT HPME FINISH")
|
||||
}
|
||||
|
||||
// Main power resource
|
||||
PowerResource (PWRR, 0, 0) {
|
||||
Name (_STA, 1)
|
||||
|
||||
Method (_ON, 0, Serialized) {
|
||||
Printf("GPU PORT PWRR._ON")
|
||||
|
||||
HPME();
|
||||
If (PMEX == 1) {
|
||||
Printf(" Disable power management SCI")
|
||||
PMEX = 0
|
||||
}
|
||||
|
||||
^^DEV0._ON()
|
||||
|
||||
_STA = 1
|
||||
}
|
||||
|
||||
Method (_OFF, 0, Serialized) {
|
||||
Printf("GPU PORT PWRR._OFF")
|
||||
|
||||
^^DEV0._OFF()
|
||||
|
||||
If (PMEX == 0) {
|
||||
Printf(" Enable power management SCI")
|
||||
PMEX = 1
|
||||
HPME()
|
||||
}
|
||||
|
||||
_STA = 0
|
||||
}
|
||||
}
|
||||
|
||||
// Power resources for entering D0
|
||||
Name (_PR0, Package () { PWRR })
|
||||
|
||||
// Power resources for entering D3
|
||||
Name (_PR3, Package () { PWRR })
|
||||
|
||||
#include "common/gpu.asl"
|
@@ -1,10 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_
|
||||
#define _DRIVERS_GFX_NVIDIA_CHIP_H_
|
||||
|
||||
struct drivers_gfx_nvidia_config {
|
||||
/* TODO: Set GPIOs in devicetree? */
|
||||
};
|
||||
|
||||
#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */
|
@@ -1,19 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_
|
||||
#define _DRIVERS_GFX_NVIDIA_GPU_H_
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
struct nvidia_gpu_config {
|
||||
/* GPIO for GPU_PWR_EN */
|
||||
unsigned int power_gpio;
|
||||
/* GPIO for GPU_RST# */
|
||||
unsigned int reset_gpio;
|
||||
/* Enable or disable GPU power */
|
||||
bool enable;
|
||||
};
|
||||
|
||||
void nvidia_set_power(const struct nvidia_gpu_config *config);
|
||||
|
||||
#endif /* _DRIVERS_NVIDIA_GPU_H_ */
|
@@ -1,71 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include "chip.h"
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
|
||||
#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40
|
||||
|
||||
static void nvidia_read_resources(struct device *dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev));
|
||||
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
// Find all BARs on GPU, mark them above 4g if prefetchable
|
||||
for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
|
||||
struct resource *res = probe_resource(dev, bar);
|
||||
|
||||
if (res) {
|
||||
if (res->flags & IORESOURCE_PREFETCH) {
|
||||
printk(BIOS_INFO, " BAR at 0x%02x marked above 4g\n", bar);
|
||||
res->flags |= IORESOURCE_ABOVE_4G;
|
||||
} else {
|
||||
printk(BIOS_DEBUG, " BAR at 0x%02x not prefetch\n", bar);
|
||||
}
|
||||
} else {
|
||||
printk(BIOS_DEBUG, " BAR at 0x%02x not found\n", bar);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
|
||||
{
|
||||
pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET,
|
||||
((device & 0xffff) << 16) | (vendor & 0xffff));
|
||||
}
|
||||
|
||||
static struct pci_operations nvidia_device_ops_pci = {
|
||||
.set_subsystem = nvidia_set_subsystem,
|
||||
};
|
||||
|
||||
static struct device_operations nvidia_device_ops = {
|
||||
.read_resources = nvidia_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
#if CONFIG(HAVE_ACPI_TABLES)
|
||||
.write_acpi_tables = pci_rom_write_acpi_tables,
|
||||
.acpi_fill_ssdt = pci_rom_ssdt,
|
||||
#endif
|
||||
.init = pci_dev_init,
|
||||
.ops_pci = &nvidia_device_ops_pci,
|
||||
|
||||
};
|
||||
|
||||
static void nvidia_enable(struct device *dev)
|
||||
{
|
||||
if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
|
||||
return;
|
||||
|
||||
if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_NVIDIA)
|
||||
return;
|
||||
|
||||
dev->ops = &nvidia_device_ops;
|
||||
}
|
||||
|
||||
struct chip_operations drivers_gfx_nvidia_ops = {
|
||||
.name = "NVIDIA Optimus Graphics Device",
|
||||
.enable_dev = nvidia_enable
|
||||
};
|
@@ -1,33 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <gpio.h>
|
||||
#include "chip.h"
|
||||
#include "gpu.h"
|
||||
|
||||
void nvidia_set_power(const struct nvidia_gpu_config *config)
|
||||
{
|
||||
if (!config->power_gpio || !config->reset_gpio) {
|
||||
printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio);
|
||||
printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio);
|
||||
|
||||
gpio_set(config->reset_gpio, 0);
|
||||
mdelay(10);
|
||||
|
||||
if (config->enable) {
|
||||
gpio_set(config->power_gpio, 1);
|
||||
mdelay(25);
|
||||
gpio_set(config->reset_gpio, 1);
|
||||
} else {
|
||||
gpio_set(config->power_gpio, 0);
|
||||
}
|
||||
|
||||
mdelay(10);
|
||||
}
|
@@ -1,4 +0,0 @@
|
||||
config DRIVERS_INTEL_DTBT
|
||||
def_bool n
|
||||
help
|
||||
Support for discrete Thunderbolt controllers
|
@@ -1,3 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
ramstage-$(CONFIG_DRIVERS_INTEL_DTBT) += dtbt.c
|
@@ -1,8 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _DRIVERS_INTEL_DTBT_CHIP_H_
|
||||
#define _DRIVERS_INTEL_DTBT_CHIP_H_
|
||||
|
||||
struct drivers_intel_dtbt_config {};
|
||||
|
||||
#endif /* _DRIVERS_INTEL_DTBT_CHIP_H_ */
|
@@ -1,199 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include "chip.h"
|
||||
#include <acpi/acpigen.h>
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pciexp.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <timer.h>
|
||||
|
||||
#define PCIE2TBT 0x54C
|
||||
#define PCIE2TBT_VALID BIT(0)
|
||||
#define PCIE2TBT_GO2SX 2
|
||||
#define PCIE2TBT_GO2SX_NO_WAKE 3
|
||||
#define PCIE2TBT_SX_EXIT_TBT_CONNECTED 4
|
||||
#define PCIE2TBT_OS_UP 6
|
||||
#define PCIE2TBT_SET_SECURITY_LEVEL 8
|
||||
#define PCIE2TBT_GET_SECURITY_LEVEL 9
|
||||
#define PCIE2TBT_BOOT_ON 24
|
||||
#define PCIE2TBT_USB_ON 25
|
||||
#define PCIE2TBT_GET_ENUMERATION_METHOD 26
|
||||
#define PCIE2TBT_SET_ENUMERATION_METHOD 27
|
||||
#define PCIE2TBT_POWER_CYCLE 28
|
||||
#define PCIE2TBT_SX_START 29
|
||||
#define PCIE2TBT_ACL_BOOT 30
|
||||
#define PCIE2TBT_CONNECT_TOPOLOGY 31
|
||||
|
||||
#define TBT2PCIE 0x548
|
||||
#define TBT2PCIE_DONE BIT(0)
|
||||
|
||||
// Default timeout for mailbox commands unless otherwise specified.
|
||||
#define TIMEOUT_MS 1000
|
||||
// Default timeout for controller to ack GO2SX/GO2SX_NO_WAKE mailbox command.
|
||||
#define GO2SX_TIMEOUT_MS 600
|
||||
|
||||
static void dtbt_cmd(struct device *dev, u32 command, u32 data, u32 timeout)
|
||||
{
|
||||
u32 reg = (data << 8) | (command << 1) | PCIE2TBT_VALID;
|
||||
u32 status;
|
||||
|
||||
printk(BIOS_DEBUG, "dTBT send command %08x\n", command);
|
||||
pci_write_config32(dev, PCIE2TBT, reg);
|
||||
|
||||
if (!wait_ms(timeout, (status = pci_read_config32(dev, TBT2PCIE)) & TBT2PCIE_DONE)) {
|
||||
printk(BIOS_ERR, "dTBT command %08x send timeout %08x\n", command, status);
|
||||
}
|
||||
|
||||
pci_write_config32(dev, PCIE2TBT, 0);
|
||||
if (!wait_ms(timeout, !(pci_read_config32(dev, TBT2PCIE) & TBT2PCIE_DONE))) {
|
||||
printk(BIOS_ERR, "dTBT command %08x clear timeout\n", command);
|
||||
}
|
||||
}
|
||||
|
||||
static void dtbt_write_dsd(void)
|
||||
{
|
||||
struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
|
||||
|
||||
acpi_device_add_hotplug_support_in_d3(dsd);
|
||||
acpi_device_add_external_facing_port(dsd);
|
||||
acpi_dp_write(dsd);
|
||||
}
|
||||
|
||||
static void dtbt_write_opregion(const struct bus *bus)
|
||||
{
|
||||
uintptr_t mmconf_base = (uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS
|
||||
+ (((uintptr_t)(bus->secondary)) << 20);
|
||||
const struct opregion opregion = OPREGION("PXCS", SYSTEMMEMORY, mmconf_base, 0x1000);
|
||||
const struct fieldlist fieldlist[] = {
|
||||
FIELDLIST_OFFSET(TBT2PCIE),
|
||||
FIELDLIST_NAMESTR("TB2P", 32),
|
||||
FIELDLIST_OFFSET(PCIE2TBT),
|
||||
FIELDLIST_NAMESTR("P2TB", 32),
|
||||
};
|
||||
|
||||
acpigen_write_opregion(&opregion);
|
||||
acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist),
|
||||
FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE);
|
||||
}
|
||||
|
||||
static void dtbt_fill_ssdt(const struct device *dev)
|
||||
{
|
||||
struct bus *bus;
|
||||
struct device *parent;
|
||||
const char *parent_scope;
|
||||
const char *dev_name = acpi_device_name(dev);
|
||||
|
||||
bus = dev->upstream;
|
||||
if (!bus) {
|
||||
printk(BIOS_ERR, "dTBT bus invalid\n");
|
||||
return;
|
||||
}
|
||||
|
||||
parent = bus->dev;
|
||||
if (!parent || parent->path.type != DEVICE_PATH_PCI) {
|
||||
printk(BIOS_ERR, "dTBT parent invalid\n");
|
||||
return;
|
||||
}
|
||||
|
||||
parent_scope = acpi_device_path(parent);
|
||||
if (!parent_scope) {
|
||||
printk(BIOS_ERR, "dTBT parent scope not valid\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Scope */
|
||||
acpigen_write_scope(parent_scope);
|
||||
dtbt_write_dsd();
|
||||
|
||||
/* Device */
|
||||
acpigen_write_device(dev_name);
|
||||
acpigen_write_name_integer("_ADR", 0);
|
||||
dtbt_write_opregion(bus);
|
||||
|
||||
/* Method */
|
||||
acpigen_write_method_serialized("PTS", 0);
|
||||
|
||||
acpigen_write_debug_string("dTBT prepare to sleep");
|
||||
acpigen_write_store_int_to_namestr(PCIE2TBT_GO2SX_NO_WAKE << 1, "P2TB");
|
||||
acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", PCIE2TBT_GO2SX_NO_WAKE << 1);
|
||||
|
||||
acpigen_write_debug_namestr("TB2P");
|
||||
acpigen_write_store_int_to_namestr(0, "P2TB");
|
||||
acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", 0);
|
||||
acpigen_write_debug_namestr("TB2P");
|
||||
|
||||
acpigen_write_method_end();
|
||||
acpigen_write_device_end();
|
||||
acpigen_write_scope_end();
|
||||
|
||||
printk(BIOS_DEBUG, "dTBT fill SSDT\n");
|
||||
printk(BIOS_DEBUG, " Dev %s\n", dev_path(dev));
|
||||
//printk(BIOS_DEBUG, " Bus %s\n", bus_path(bus));
|
||||
printk(BIOS_DEBUG, " Parent %s\n", dev_path(parent));
|
||||
printk(BIOS_DEBUG, " Scope %s\n", parent_scope);
|
||||
printk(BIOS_DEBUG, " Device %s\n", dev_name);
|
||||
|
||||
// \.TBTS Method
|
||||
acpigen_write_scope("\\");
|
||||
acpigen_write_method("TBTS", 0);
|
||||
acpigen_emit_namestring(acpi_device_path_join(dev, "PTS"));
|
||||
acpigen_write_method_end();
|
||||
acpigen_write_scope_end();
|
||||
}
|
||||
|
||||
static const char *dtbt_acpi_name(const struct device *dev)
|
||||
{
|
||||
return "DTBT";
|
||||
}
|
||||
|
||||
static struct pci_operations dtbt_device_ops_pci = {
|
||||
.set_subsystem = 0,
|
||||
};
|
||||
|
||||
static struct device_operations dtbt_device_ops = {
|
||||
.read_resources = pci_bus_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_bus_enable_resources,
|
||||
.acpi_fill_ssdt = dtbt_fill_ssdt,
|
||||
.acpi_name = dtbt_acpi_name,
|
||||
.scan_bus = pciexp_scan_bridge,
|
||||
.reset_bus = pci_bus_reset,
|
||||
.ops_pci = &dtbt_device_ops_pci,
|
||||
};
|
||||
|
||||
static void dtbt_enable(struct device *dev)
|
||||
{
|
||||
if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
|
||||
return;
|
||||
|
||||
if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_INTEL)
|
||||
return;
|
||||
|
||||
// TODO: check device ID
|
||||
|
||||
dev->ops = &dtbt_device_ops;
|
||||
|
||||
printk(BIOS_INFO, "dTBT controller found at %s\n", dev_path(dev));
|
||||
|
||||
// XXX: Recommendation is to set SL1 ("User Authorization")
|
||||
printk(BIOS_DEBUG, "dTBT set security level SL0\n");
|
||||
dtbt_cmd(dev, PCIE2TBT_SET_SECURITY_LEVEL, 0, TIMEOUT_MS);
|
||||
// XXX: Must verify change or rollback all controllers
|
||||
|
||||
if (acpi_is_wakeup_s3()) {
|
||||
printk(BIOS_DEBUG, "dTBT SX exit\n");
|
||||
dtbt_cmd(dev, PCIE2TBT_SX_EXIT_TBT_CONNECTED, 0, TIMEOUT_MS);
|
||||
// TODO: "wait for fast link bring-up" loop (timeout: 5s)
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "dTBT boot on\n");
|
||||
dtbt_cmd(dev, PCIE2TBT_BOOT_ON, 0, TIMEOUT_MS);
|
||||
}
|
||||
}
|
||||
|
||||
struct chip_operations drivers_intel_dtbt_ops = {
|
||||
.name = "Intel Discrete Thunderbolt",
|
||||
.enable_dev = dtbt_enable,
|
||||
};
|
@@ -1,21 +0,0 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
config EC_DASHARO_EC
|
||||
bool
|
||||
help
|
||||
Dasharo EC
|
||||
|
||||
config EC_DASHARO_EC_BAT_THRESHOLDS
|
||||
depends on EC_DASHARO_EC
|
||||
bool
|
||||
default y
|
||||
|
||||
config EC_DASHARO_EC_DGPU
|
||||
depends on EC_DASHARO_EC
|
||||
bool
|
||||
default n
|
||||
|
||||
config EC_DASHARO_EC_OLED
|
||||
depends on EC_DASHARO_EC
|
||||
bool
|
||||
default n
|
@@ -1,10 +0,0 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
ifeq ($(CONFIG_EC_DASHARO_EC),y)
|
||||
|
||||
all-y += dasharo_ec.c
|
||||
|
||||
ramstage-y += smbios.c
|
||||
|
||||
smm-$(CONFIG_DEBUG_SMI) += dasharo_ec.c
|
||||
|
||||
endif
|
@@ -1,22 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Device (AC)
|
||||
{
|
||||
Name (_HID, "ACPI0003" /* Power Source Device */)
|
||||
Name (_PCL, Package (0x01) // _PCL: Power Consumer List
|
||||
{
|
||||
_SB
|
||||
})
|
||||
|
||||
Name (ACFG, 1)
|
||||
|
||||
Method (_PSR, 0, NotSerialized) // _PSR: Power Source
|
||||
{
|
||||
Return (ACFG)
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0F)
|
||||
}
|
||||
}
|
@@ -1,248 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Device (BAT0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */)
|
||||
Name (_UID, 0)
|
||||
Name (_PCL, Package (0x01) // _PCL: Power Consumer List
|
||||
{
|
||||
_SB
|
||||
})
|
||||
Name (BFCC, 0)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
If (^^PCI0.LPCB.EC0.ECOK)
|
||||
{
|
||||
If (^^PCI0.LPCB.EC0.BAT0)
|
||||
{
|
||||
Return (0x1F)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (0x0F)
|
||||
}
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (0x0F)
|
||||
}
|
||||
}
|
||||
|
||||
Name (PBIF, Package (0x0D)
|
||||
{
|
||||
1, // 0 - Power Unit
|
||||
0xFFFFFFFF, // 1 - Design Capacity
|
||||
0xFFFFFFFF, // 2 - Last Full Charge Capacity
|
||||
1, // 3 - Battery Technology
|
||||
0xFFFFFFFF, // 4 - Design Voltage
|
||||
0, // 5 - Design Capacity of Warning
|
||||
0, // 6 - Design Capacity of Low
|
||||
0x40, // 7 - Battery Capacity Granularity 1
|
||||
0x40, // 8 - Battery Capacity Granularity 2
|
||||
" ", // 9 - Model Number
|
||||
" ", // 10 - Serial Number
|
||||
" ", // 11 - Battery Type
|
||||
" " // 12 - OEM Information
|
||||
})
|
||||
Method (IVBI, 0, NotSerialized)
|
||||
{
|
||||
PBIF [1] = 0xFFFFFFFF
|
||||
PBIF [2] = 0xFFFFFFFF
|
||||
PBIF [4] = 0xFFFFFFFF
|
||||
PBIF [9] = " "
|
||||
PBIF [10] = " "
|
||||
PBIF [11] = " "
|
||||
PBIF [12] = " "
|
||||
BFCC = 0
|
||||
}
|
||||
|
||||
Method (UPBI, 0, NotSerialized)
|
||||
{
|
||||
If (^^PCI0.LPCB.EC0.BAT0)
|
||||
{
|
||||
Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
|
||||
PBIF [1] = Local0
|
||||
Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
|
||||
PBIF [2] = Local0
|
||||
BFCC = Local0
|
||||
Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
|
||||
PBIF [4] = Local0
|
||||
Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
|
||||
PBIF [5] = Local0
|
||||
Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
|
||||
PBIF [6] = Local0
|
||||
PBIF [9] = "BAT"
|
||||
PBIF [10] = "0001"
|
||||
PBIF [11] = "LION"
|
||||
PBIF [12] = "Notebook"
|
||||
}
|
||||
Else
|
||||
{
|
||||
IVBI ()
|
||||
}
|
||||
}
|
||||
|
||||
Method (_BIF, 0, NotSerialized) // _BIF: Battery Information
|
||||
{
|
||||
If (^^PCI0.LPCB.EC0.ECOK)
|
||||
{
|
||||
UPBI ()
|
||||
}
|
||||
Else
|
||||
{
|
||||
IVBI ()
|
||||
}
|
||||
|
||||
Return (PBIF) /* \_SB_.BAT0.PBIF */
|
||||
}
|
||||
|
||||
Name (PBIX, Package ()
|
||||
{
|
||||
0, // 0 - Revision
|
||||
1, // 1 - Power Unit: mAh
|
||||
0xFFFFFFFF, // 2 - Design Capacity
|
||||
0xFFFFFFFF, // 3 - Last Full Charge Capacity
|
||||
1, // 4 - Battery Technology: Rechargeable
|
||||
0xFFFFFFFF, // 5 - Design Voltage
|
||||
0, // 6 - Design Capacity of Warning
|
||||
0, // 7 - Design Capacity of Low
|
||||
0, // 8 - Cycle Count
|
||||
98000, // 9 - Measurement Accuracy
|
||||
0xFFFFFFFF, // 10 - Max Sampling Time
|
||||
0xFFFFFFFF, // 11 - Min Sampling Time
|
||||
0xFFFFFFFF, // 12 - Max Averaging Interval
|
||||
0xFFFFFFFF, // 13 - Min Averaging Interval
|
||||
0x40, // 14 - Battery Capacity Granularity 1
|
||||
0x40, // 15 - Battery Capacity Granularity 2
|
||||
" ", // 16 - Model Number
|
||||
" ", // 17 - Serial Number
|
||||
" ", // 18 - Battery Type
|
||||
" " // 19 - OEM Information
|
||||
})
|
||||
|
||||
Method (IVBX, 0, NotSerialized)
|
||||
{
|
||||
PBIX [2] = 0xFFFFFFFF
|
||||
PBIX [3] = 0xFFFFFFFF
|
||||
PBIX [5] = 0xFFFFFFFF
|
||||
PBIX [16] = " "
|
||||
PBIX [17] = " "
|
||||
PBIX [18] = " "
|
||||
PBIX [19] = " "
|
||||
BFCC = 0
|
||||
}
|
||||
|
||||
Method (UPBX, 0, NotSerialized)
|
||||
{
|
||||
If (^^PCI0.LPCB.EC0.BAT0)
|
||||
{
|
||||
Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
|
||||
PBIX [2] = Local0
|
||||
Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
|
||||
PBIX [3] = Local0
|
||||
BFCC = Local0
|
||||
Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
|
||||
PBIX [5] = Local0
|
||||
Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
|
||||
PBIX [6] = Local0
|
||||
Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
|
||||
PBIX [7] = Local0
|
||||
LOCAL0 = ^^PCI0.LPCB.EC0.CYC0
|
||||
PBIX [8] = LOCAL0
|
||||
PBIX [16] = "BAT"
|
||||
PBIX [17] = "0001"
|
||||
PBIX [18] = "LION"
|
||||
PBIX [19] = "Notebook"
|
||||
}
|
||||
Else
|
||||
{
|
||||
IVBX ()
|
||||
}
|
||||
}
|
||||
|
||||
// _BIX: Battery Information Extended
|
||||
Method (_BIX, 0, NotSerialized)
|
||||
{
|
||||
If (^^PCI0.LPCB.EC0.ECOK)
|
||||
{
|
||||
UPBX ()
|
||||
}
|
||||
Else
|
||||
{
|
||||
IVBX ()
|
||||
}
|
||||
Return (PBIX) /* \_SB_.BAT0.PBIX */
|
||||
}
|
||||
|
||||
Name (PBST, Package (0x04)
|
||||
{
|
||||
0, // 0 - Battery state
|
||||
0xFFFFFFFF, // 1 - Battery present rate
|
||||
0xFFFFFFFF, // 2 - Battery remaining capacity
|
||||
0xFFFFFFFF // 3 - Battery present voltage
|
||||
})
|
||||
Method (IVBS, 0, NotSerialized)
|
||||
{
|
||||
PBST [0] = 0
|
||||
PBST [1] = 0xFFFFFFFF
|
||||
PBST [2] = 0xFFFFFFFF
|
||||
PBST [3] = 0xFFFFFFFF
|
||||
}
|
||||
|
||||
Method (UPBS, 0, NotSerialized)
|
||||
{
|
||||
If (^^PCI0.LPCB.EC0.BAT0)
|
||||
{
|
||||
Local0 = 0
|
||||
Local1 = 0
|
||||
If (^^AC.ACFG)
|
||||
{
|
||||
If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02))
|
||||
{
|
||||
Local0 |= 0x02
|
||||
Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
|
||||
}
|
||||
}
|
||||
Else
|
||||
{
|
||||
Local0 |= 1
|
||||
Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
|
||||
}
|
||||
|
||||
Local7 = (Local1 & 0x8000)
|
||||
If ((Local7 == 0x8000))
|
||||
{
|
||||
Local1 ^= 0xFFFF
|
||||
}
|
||||
|
||||
Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF)
|
||||
Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF)
|
||||
PBST [0] = Local0
|
||||
PBST [1] = Local1
|
||||
PBST [2] = Local2
|
||||
PBST [3] = Local3
|
||||
If ((BFCC != ^^PCI0.LPCB.EC0.BFC0))
|
||||
{
|
||||
Notify (BAT0, 0x81) // Information Change
|
||||
}
|
||||
}
|
||||
Else
|
||||
{
|
||||
IVBS ()
|
||||
}
|
||||
}
|
||||
|
||||
Method (_BST, 0, NotSerialized) // _BST: Battery Status
|
||||
{
|
||||
If (^^PCI0.LPCB.EC0.ECOK)
|
||||
{
|
||||
UPBS ()
|
||||
}
|
||||
Else
|
||||
{
|
||||
IVBS ()
|
||||
}
|
||||
|
||||
Return (PBST) /* \_SB_.BAT0.PBST */
|
||||
}
|
||||
}
|
@@ -1,46 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Field (ERAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
Offset (0xBC),
|
||||
BTL0, 8, /* BAT0 charging start threshold */
|
||||
BTH0, 8, /* BAT0 charging end threshold */
|
||||
}
|
||||
|
||||
/*
|
||||
* Get battery charging threshold
|
||||
*
|
||||
* Arg0: 0: Start threshold
|
||||
* 1: Stop threshold
|
||||
*/
|
||||
Method (GBCT, 1, NotSerialized)
|
||||
{
|
||||
If (Arg0 == 0) {
|
||||
Return (BTL0)
|
||||
}
|
||||
|
||||
If (Arg0 == 1) {
|
||||
Return (BTH0)
|
||||
}
|
||||
|
||||
Return (0xFF)
|
||||
}
|
||||
|
||||
/*
|
||||
* Set battery charging threshold
|
||||
*
|
||||
* Arg0: 0: Start threshold
|
||||
* 1: Stop threshold
|
||||
* Arg1: Percentage
|
||||
*/
|
||||
Method (SBCT, 2, NotSerialized)
|
||||
{
|
||||
If (Arg1 <= 100) {
|
||||
If (Arg0 == 0) {
|
||||
BTL0 = Arg1
|
||||
}
|
||||
If (Arg0 == 1) {
|
||||
BTH0 = Arg1
|
||||
}
|
||||
}
|
||||
}
|
@@ -1,13 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Device (PWRB)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0C"))
|
||||
Name (_PRW, Package () { EC_GPE_SWI, 3 })
|
||||
}
|
||||
|
||||
Device (SLPB)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0E"))
|
||||
Name (_PRW, Package () { EC_GPE_SWI, 3 })
|
||||
}
|
@@ -1,241 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Scope (\_SB) {
|
||||
#include "ac.asl"
|
||||
#include "battery.asl"
|
||||
#include "buttons.asl"
|
||||
#include "hid.asl"
|
||||
#include "lid.asl"
|
||||
#include "s76.asl"
|
||||
}
|
||||
|
||||
Device (\_SB.PCI0.LPCB.EC0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */)
|
||||
Name (_GPE, EC_GPE_SCI) // _GPE: General Purpose Events
|
||||
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
|
||||
{
|
||||
IO (Decode16,
|
||||
0x0062, // Range Minimum
|
||||
0x0062, // Range Maximum
|
||||
0x00, // Alignment
|
||||
0x01, // Length
|
||||
)
|
||||
IO (Decode16,
|
||||
0x0066, // Range Minimum
|
||||
0x0066, // Range Maximum
|
||||
0x00, // Alignment
|
||||
0x01, // Length
|
||||
)
|
||||
})
|
||||
|
||||
#include "ec_ram.asl"
|
||||
|
||||
Name (ECOK, 0)
|
||||
Method (_REG, 2, Serialized) // _REG: Region Availability
|
||||
{
|
||||
Printf ("EC: _REG %o %o", ToHexString(Arg0), ToHexString(Arg1))
|
||||
If ((Arg0 == 0x03) && (Arg1 == 1)) {
|
||||
// Enable hardware touchpad lock, airplane mode, and keyboard backlight keys
|
||||
ECOS = 1
|
||||
|
||||
// Enable software display brightness keys
|
||||
WINF = 1
|
||||
|
||||
// Set current AC state
|
||||
^^^^AC.ACFG = ADP
|
||||
// Update battery information and status
|
||||
^^^^BAT0.UPBI()
|
||||
^^^^BAT0.UPBS()
|
||||
|
||||
// Notify of changes
|
||||
Notify(^^^^AC, 0)
|
||||
Notify(^^^^BAT0, 0)
|
||||
|
||||
PNOT ()
|
||||
|
||||
// EC is now available
|
||||
ECOK = Arg1
|
||||
|
||||
// Reset Dasharo Device
|
||||
^^^^S76D.RSET()
|
||||
}
|
||||
}
|
||||
|
||||
Name (S3OS, 0)
|
||||
Method (PTS, 1, Serialized) {
|
||||
Printf ("EC: PTS: %o", ToHexString(Arg0))
|
||||
If (ECOK) {
|
||||
// Save ECOS during sleep
|
||||
S3OS = ECOS
|
||||
|
||||
// Clear wake cause
|
||||
WFNO = 0
|
||||
}
|
||||
}
|
||||
|
||||
Method (WAK, 1, Serialized) {
|
||||
Printf ("EC: WAK: %o", ToHexString(Arg0))
|
||||
If (ECOK) {
|
||||
// Restore ECOS after sleep
|
||||
ECOS = S3OS
|
||||
|
||||
// Set current AC state
|
||||
^^^^AC.ACFG = ADP
|
||||
|
||||
// Update battery information and status
|
||||
^^^^BAT0.UPBI()
|
||||
^^^^BAT0.UPBS()
|
||||
|
||||
// Notify of changes
|
||||
Notify(^^^^AC, 0)
|
||||
Notify(^^^^BAT0, 0)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_Q0A, 0, NotSerialized) // Touchpad Toggle
|
||||
{
|
||||
Printf ("EC: Touchpad Toggle")
|
||||
}
|
||||
|
||||
Method (_Q0B, 0, NotSerialized) // Screen Toggle
|
||||
{
|
||||
Printf ("EC: Screen Toggle")
|
||||
#if CONFIG(EC_DASHARO_EC_OLED)
|
||||
Notify (^^^^S76D, 0x85)
|
||||
#endif // CONFIG(EC_DASHARO_EC_OLED)
|
||||
}
|
||||
|
||||
Method (_Q0C, 0, NotSerialized) // Mute
|
||||
{
|
||||
Printf ("EC: Mute")
|
||||
}
|
||||
|
||||
Method (_Q0D, 0, NotSerialized) // Keyboard Backlight
|
||||
{
|
||||
Printf ("EC: Keyboard Backlight")
|
||||
}
|
||||
|
||||
Method (_Q0E, 0, NotSerialized) // Volume Down
|
||||
{
|
||||
Printf ("EC: Volume Down")
|
||||
}
|
||||
|
||||
Method (_Q0F, 0, NotSerialized) // Volume Up
|
||||
{
|
||||
Printf ("EC: Volume Up")
|
||||
}
|
||||
|
||||
Method (_Q10, 0, NotSerialized) // Switch Video Mode
|
||||
{
|
||||
Printf ("EC: Switch Video Mode")
|
||||
}
|
||||
|
||||
Method (_Q11, 0, NotSerialized) // Brightness Down
|
||||
{
|
||||
Printf ("EC: Brightness Down")
|
||||
if (^^^^HIDD.HRDY) {
|
||||
^^^^HIDD.HPEM (20)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_Q12, 0, NotSerialized) // Brightness Up
|
||||
{
|
||||
Printf ("EC: Brightness Up")
|
||||
if (^^^^HIDD.HRDY) {
|
||||
^^^^HIDD.HPEM (19)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_Q13, 0, NotSerialized) // Camera Toggle
|
||||
{
|
||||
Printf ("EC: Camera Toggle")
|
||||
}
|
||||
|
||||
Method (_Q14, 0, NotSerialized) // Airplane Mode
|
||||
{
|
||||
Printf ("EC: Airplane Mode")
|
||||
if (^^^^HIDD.HRDY) {
|
||||
^^^^HIDD.HPEM (8)
|
||||
}
|
||||
// TODO: hardware airplane mode
|
||||
}
|
||||
|
||||
Method (_Q15, 0, NotSerialized) // Suspend Button
|
||||
{
|
||||
Printf ("EC: Suspend Button")
|
||||
Notify (SLPB, 0x80)
|
||||
}
|
||||
|
||||
Method (_Q16, 0, NotSerialized) // AC Detect
|
||||
{
|
||||
Printf ("EC: AC Detect")
|
||||
^^^^AC.ACFG = ADP
|
||||
Notify (AC, 0x80) // Status Change
|
||||
If (BAT0)
|
||||
{
|
||||
Notify (^^^^BAT0, 0x81) // Information Change
|
||||
Notify (^^^^BAT0, 0x80) // Status Change
|
||||
}
|
||||
}
|
||||
|
||||
Method (_Q17, 0, NotSerialized) // BAT0 Update
|
||||
{
|
||||
Printf ("EC: BAT0 Update (17)")
|
||||
Notify (^^^^BAT0, 0x81) // Information Change
|
||||
}
|
||||
|
||||
Method (_Q19, 0, NotSerialized) // BAT0 Update
|
||||
{
|
||||
Printf ("EC: BAT0 Update (19)")
|
||||
Notify (^^^^BAT0, 0x81) // Information Change
|
||||
}
|
||||
|
||||
Method (_Q1B, 0, NotSerialized) // Lid Close
|
||||
{
|
||||
Printf ("EC: Lid Close")
|
||||
Notify (LID0, 0x80)
|
||||
}
|
||||
|
||||
Method (_Q1C, 0, NotSerialized) // Thermal Trip
|
||||
{
|
||||
Printf ("EC: Thermal Trip")
|
||||
/* TODO
|
||||
Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change
|
||||
Notify (\_TZ.TZ0, 0x80) // Thermal Status Change
|
||||
*/
|
||||
}
|
||||
|
||||
Method (_Q1D, 0, NotSerialized) // Power Button
|
||||
{
|
||||
Printf ("EC: Power Button")
|
||||
Notify (PWRB, 0x80)
|
||||
}
|
||||
|
||||
Method (_Q50, 0, NotSerialized) // Other Events
|
||||
{
|
||||
Local0 = OEM4
|
||||
If (Local0 == 0x8A) {
|
||||
Printf ("EC: White Keyboard Backlight")
|
||||
Notify (^^^^S76D, 0x80)
|
||||
} ElseIf (Local0 == 0x9F) {
|
||||
Printf ("EC: Color Keyboard Toggle")
|
||||
Notify (^^^^S76D, 0x81)
|
||||
} ElseIf (Local0 == 0x81) {
|
||||
Printf ("EC: Color Keyboard Down")
|
||||
Notify (^^^^S76D, 0x82)
|
||||
} ElseIf (Local0 == 0x82) {
|
||||
Printf ("EC: Color Keyboard Up")
|
||||
Notify (^^^^S76D, 0x83)
|
||||
} ElseIf (Local0 == 0x80) {
|
||||
Printf ("EC: Color Keyboard Color Change")
|
||||
Notify (^^^^S76D, 0x84)
|
||||
} Else {
|
||||
Printf ("EC: Other: %o", ToHexString(Local0))
|
||||
}
|
||||
}
|
||||
|
||||
#if CONFIG(EC_DASHARO_EC_BAT_THRESHOLDS)
|
||||
#include "battery_thresholds.asl"
|
||||
#endif
|
||||
}
|
@@ -1,55 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
OperationRegion (ERAM, EmbeddedControl, 0, 0xFF)
|
||||
Field (ERAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
Offset (0x03),
|
||||
LSTE, 1, // Lid is open
|
||||
, 1,
|
||||
LWKE, 1, // Lid wake
|
||||
, 5,
|
||||
Offset (0x07),
|
||||
TMP1, 8, // CPU temperature
|
||||
Offset (0x10),
|
||||
ADP, 1, // AC adapter connected
|
||||
, 1,
|
||||
BAT0, 1, // Battery connected
|
||||
, 5,
|
||||
WFNO, 8, // Wake cause (not implemented)
|
||||
Offset (0x16),
|
||||
BDC0, 32, // Battery design capacity
|
||||
BFC0, 32, // Battery full capacity
|
||||
Offset (0x22),
|
||||
BDV0, 32, // Battery design voltage
|
||||
BST0, 32, // Battery status
|
||||
BPR0, 32, // Battery current
|
||||
BRC0, 32, // Battery remaining capacity
|
||||
BPV0, 32, // Battery voltage
|
||||
Offset (0x3A),
|
||||
BCW0, 32,
|
||||
BCL0, 32,
|
||||
CYC0, 16, // Battery cycle count
|
||||
Offset (0x68),
|
||||
ECOS, 8, // Detected OS, 0 = no ACPI, 1 = ACPI but no driver, 2 = ACPI with driver
|
||||
Offset (0xC8),
|
||||
OEM1, 8,
|
||||
OEM2, 8,
|
||||
OEM3, 16,
|
||||
OEM4, 8, // Extra SCI data
|
||||
Offset (0xCD),
|
||||
TMP2, 8, // GPU temperature
|
||||
DUT1, 8, // Fan 1 duty
|
||||
DUT2, 8, // Fan 2 duty
|
||||
RPM1, 16, // Fan 1 RPM
|
||||
RPM2, 16, // Fan 2 RPM
|
||||
Offset (0xD9),
|
||||
AIRP, 8, // Airplane mode LED
|
||||
WINF, 8, // Enable ACPI brightness controls
|
||||
Offset (0xF8),
|
||||
FCMD, 8,
|
||||
FDAT, 8,
|
||||
FBUF, 8,
|
||||
FBF1, 8,
|
||||
FBF2, 8,
|
||||
FBF3, 8,
|
||||
}
|
@@ -1,50 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Device (HIDD)
|
||||
{
|
||||
Name (_HID, "INT33D5")
|
||||
Name (HBSY, 0)
|
||||
Name (HIDX, 0)
|
||||
Name (HRDY, 0)
|
||||
|
||||
Method (HDEM, 0, Serialized)
|
||||
{
|
||||
HBSY = 0
|
||||
Return (HIDX)
|
||||
}
|
||||
|
||||
Method (HDMM, 0, Serialized)
|
||||
{
|
||||
Return (0)
|
||||
}
|
||||
|
||||
Method (HDSM, 1, Serialized)
|
||||
{
|
||||
HRDY = Arg0
|
||||
}
|
||||
|
||||
Method (HPEM, 1, Serialized)
|
||||
{
|
||||
HBSY = 1
|
||||
HIDX = Arg0
|
||||
|
||||
Notify (HIDD, 0xC0)
|
||||
Local0 = 0
|
||||
While ((Local0 < 0xFA) && HBSY)
|
||||
{
|
||||
Sleep (0x04)
|
||||
Local0++
|
||||
}
|
||||
|
||||
If (HBSY == 1)
|
||||
{
|
||||
HBSY = 0
|
||||
HIDX = 0
|
||||
Return (1)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (0)
|
||||
}
|
||||
}
|
||||
}
|
@@ -1,23 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Device (LID0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0D"))
|
||||
Name (_PRW, Package () { EC_GPE_SWI, 3 })
|
||||
|
||||
Method (_LID, 0, NotSerialized) {
|
||||
Printf ("LID: _LID")
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
Return (^^PCI0.LPCB.EC0.LSTE)
|
||||
} Else {
|
||||
Return (1)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PSW, 1, NotSerialized) {
|
||||
Printf ("LID: _PSW: %o", ToHexString(Arg0))
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.LWKE = Arg0
|
||||
}
|
||||
}
|
||||
}
|
@@ -1,178 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
// Notifications:
|
||||
// 0x80 - hardware backlight toggle
|
||||
// 0x81 - backlight toggle
|
||||
// 0x82 - backlight down
|
||||
// 0x83 - backlight up
|
||||
// 0x84 - backlight color change
|
||||
// 0x85 - OLED screen toggle
|
||||
Device (S76D) {
|
||||
Name (_HID, "17761776")
|
||||
Name (_UID, 0)
|
||||
// Hide the device so that Windows does not warn about a missing driver.
|
||||
Name (_STA, 0xB)
|
||||
|
||||
Method (RSET, 0, Serialized) {
|
||||
Printf ("S76D: RSET")
|
||||
SAPL(0)
|
||||
SKBB(0)
|
||||
SKBC(0xFFFFFF)
|
||||
}
|
||||
|
||||
Method (INIT, 0, Serialized) {
|
||||
Printf ("S76D: INIT")
|
||||
RSET()
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
// Set flags to use software control
|
||||
^^PCI0.LPCB.EC0.ECOS = 2
|
||||
Return (0)
|
||||
} Else {
|
||||
Return (1)
|
||||
}
|
||||
}
|
||||
|
||||
Method (FINI, 0, Serialized) {
|
||||
Printf ("S76D: FINI")
|
||||
RSET()
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
// Set flags to use hardware control
|
||||
^^PCI0.LPCB.EC0.ECOS = 1
|
||||
Return (0)
|
||||
} Else {
|
||||
Return (1)
|
||||
}
|
||||
}
|
||||
|
||||
// Get Airplane LED
|
||||
Method (GAPL, 0, Serialized) {
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
If (^^PCI0.LPCB.EC0.AIRP & 0x40) {
|
||||
Return (1)
|
||||
}
|
||||
}
|
||||
Return (0)
|
||||
}
|
||||
|
||||
// Set Airplane LED
|
||||
Method (SAPL, 1, Serialized) {
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
If (Arg0) {
|
||||
^^PCI0.LPCB.EC0.AIRP |= 0x40
|
||||
} Else {
|
||||
^^PCI0.LPCB.EC0.AIRP &= 0xBF
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Get Keyboard Backlight Kind
|
||||
// 0 - No backlight
|
||||
// 1 - White backlight
|
||||
// 2 - RGB backlight
|
||||
Method (GKBK, 0, Serialized) {
|
||||
Local0 = 0
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.FDAT = 2
|
||||
^^PCI0.LPCB.EC0.FCMD = 0xCA
|
||||
Local0 = ^^PCI0.LPCB.EC0.FBUF
|
||||
}
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
// Get Keyboard Brightness
|
||||
Method (GKBB, 0, Serialized) {
|
||||
Local0 = 0
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.FDAT = 1
|
||||
^^PCI0.LPCB.EC0.FCMD = 0xCA
|
||||
Local0 = ^^PCI0.LPCB.EC0.FBUF
|
||||
}
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
// Set Keyboard Brightness
|
||||
Method (SKBB, 1, Serialized) {
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.FDAT = 0
|
||||
^^PCI0.LPCB.EC0.FBUF = Arg0
|
||||
^^PCI0.LPCB.EC0.FCMD = 0xCA
|
||||
}
|
||||
}
|
||||
|
||||
// Get Keyboard Color
|
||||
Method (GKBC, 0, Serialized) {
|
||||
Local0 = 0
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.FDAT = 4
|
||||
^^PCI0.LPCB.EC0.FCMD = 0xCA
|
||||
Local0 = ^^PCI0.LPCB.EC0.FBUF
|
||||
Local0 |= (^^PCI0.LPCB.EC0.FBF1) << 16
|
||||
Local0 |= (^^PCI0.LPCB.EC0.FBF2) << 8
|
||||
}
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
// Set Keyboard Color
|
||||
Method (SKBC, 1, Serialized) {
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.FDAT = 3
|
||||
^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF)
|
||||
^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF)
|
||||
^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF)
|
||||
^^PCI0.LPCB.EC0.FCMD = 0xCA
|
||||
}
|
||||
}
|
||||
|
||||
// Fan names
|
||||
Method (NFAN, 0, Serialized) {
|
||||
Return (Package() {
|
||||
"CPU fan",
|
||||
#if CONFIG(EC_DASHARO_EC_DGPU)
|
||||
"GPU fan",
|
||||
#endif
|
||||
})
|
||||
}
|
||||
|
||||
// Get fan duty cycle and RPM as a single value
|
||||
Method (GFAN, 1, Serialized) {
|
||||
Local0 = 0
|
||||
Local1 = 0
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
If (Arg0 == 0) {
|
||||
Local0 = ^^PCI0.LPCB.EC0.DUT1
|
||||
Local1 = ^^PCI0.LPCB.EC0.RPM1
|
||||
} ElseIf (Arg0 == 1) {
|
||||
Local0 = ^^PCI0.LPCB.EC0.DUT2
|
||||
Local1 = ^^PCI0.LPCB.EC0.RPM2
|
||||
}
|
||||
}
|
||||
If (Local1 != 0) {
|
||||
// 60 * (EC frequency / 120) / 2
|
||||
Local1 = 2156250 / Local1
|
||||
}
|
||||
Return ((Local1 << 8) | Local0)
|
||||
}
|
||||
|
||||
// Temperature names
|
||||
Method (NTMP, 0, Serialized) {
|
||||
Return (Package() {
|
||||
"CPU temp",
|
||||
#if CONFIG(EC_DASHARO_EC_DGPU)
|
||||
"GPU temp",
|
||||
#endif
|
||||
})
|
||||
}
|
||||
|
||||
// Get temperature
|
||||
Method (GTMP, 1, Serialized) {
|
||||
Local0 = 0;
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
If (Arg0 == 0) {
|
||||
Local0 = ^^PCI0.LPCB.EC0.TMP1
|
||||
} ElseIf (Arg0 == 1) {
|
||||
Local0 = ^^PCI0.LPCB.EC0.TMP2
|
||||
}
|
||||
}
|
||||
Return (Local0)
|
||||
}
|
||||
}
|
@@ -1,112 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include "dasharo_ec.h"
|
||||
#include <arch/io.h>
|
||||
#include <console/dasharo_ec.h>
|
||||
#include <console/console.h>
|
||||
#include <timer.h>
|
||||
|
||||
// This is the command region for Dasharo EC firmware. It must be
|
||||
// enabled for LPC in the mainboard.
|
||||
#define DASHARO_EC_BASE 0x0E00
|
||||
#define DASHARO_EC_SIZE 256
|
||||
|
||||
#define REG_CMD 0
|
||||
#define REG_RESULT 1
|
||||
#define REG_DATA 2 // Start of command data
|
||||
|
||||
// When command register is 0, command is complete
|
||||
#define CMD_FINISHED 0
|
||||
|
||||
#define RESULT_OK 0
|
||||
|
||||
// Print command. Registers are unique for each command
|
||||
#define CMD_PRINT 4
|
||||
#define CMD_PRINT_REG_FLAGS 2
|
||||
#define CMD_PRINT_REG_LEN 3
|
||||
#define CMD_PRINT_REG_DATA 4
|
||||
|
||||
static inline uint8_t dasharo_ec_read(uint8_t addr)
|
||||
{
|
||||
return inb(DASHARO_EC_BASE + (uint16_t)addr);
|
||||
}
|
||||
|
||||
static inline void dasharo_ec_write(uint8_t addr, uint8_t data)
|
||||
{
|
||||
outb(data, DASHARO_EC_BASE + (uint16_t)addr);
|
||||
}
|
||||
|
||||
void dasharo_ec_init(void)
|
||||
{
|
||||
// Clear entire command region
|
||||
for (int i = 0; i < DASHARO_EC_SIZE; i++)
|
||||
dasharo_ec_write((uint8_t)i, 0);
|
||||
}
|
||||
|
||||
void dasharo_ec_flush(void)
|
||||
{
|
||||
dasharo_ec_write(REG_CMD, CMD_PRINT);
|
||||
|
||||
// Wait for command completion, for up to 10 milliseconds, with a
|
||||
// test period of 1 microsecond
|
||||
wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED);
|
||||
|
||||
dasharo_ec_write(CMD_PRINT_REG_LEN, 0);
|
||||
}
|
||||
|
||||
void dasharo_ec_print(uint8_t byte)
|
||||
{
|
||||
uint8_t len = dasharo_ec_read(CMD_PRINT_REG_LEN);
|
||||
dasharo_ec_write(CMD_PRINT_REG_DATA + len, byte);
|
||||
dasharo_ec_write(CMD_PRINT_REG_LEN, len + 1);
|
||||
|
||||
// If we hit the end of the buffer, or were given a newline, flush
|
||||
if (byte == '\n' || len >= (DASHARO_EC_SIZE - CMD_PRINT_REG_DATA))
|
||||
dasharo_ec_flush();
|
||||
}
|
||||
|
||||
bool dasharo_ec_cmd(uint8_t cmd, const uint8_t *request_data,
|
||||
uint8_t request_size, uint8_t *reply_data, uint8_t reply_size)
|
||||
{
|
||||
if (request_size > DASHARO_EC_SIZE - REG_DATA ||
|
||||
reply_size > DASHARO_EC_SIZE - REG_DATA) {
|
||||
printk(BIOS_ERR, "EC command %d too long - request size %u, reply size %u\n",
|
||||
cmd, request_size, reply_size);
|
||||
return false;
|
||||
}
|
||||
|
||||
/* If any data were buffered by dasharo_ec_print(), flush it first */
|
||||
uint8_t buffered_len = dasharo_ec_read(CMD_PRINT_REG_LEN);
|
||||
if (buffered_len > 0)
|
||||
dasharo_ec_flush();
|
||||
|
||||
/* Write the data */
|
||||
uint8_t i;
|
||||
for (i = 0; i < request_size; ++i)
|
||||
dasharo_ec_write(REG_DATA + i, request_data[i]);
|
||||
|
||||
/* Write the command */
|
||||
dasharo_ec_write(REG_CMD, cmd);
|
||||
|
||||
/* Wait for the command to complete */
|
||||
bool ret = true;
|
||||
int elapsed = wait_ms(1000, dasharo_ec_read(REG_CMD) == CMD_FINISHED);
|
||||
if (elapsed == 0) {
|
||||
/* Timed out: fail the command, don't attempt to read a reply. */
|
||||
printk(BIOS_WARNING, "EC command %d timed out - request size %d, reply size %d\n",
|
||||
cmd, request_size, reply_size);
|
||||
ret = false;
|
||||
} else {
|
||||
/* Read the reply */
|
||||
for (i = 0; i < reply_size; ++i)
|
||||
reply_data[i] = dasharo_ec_read(REG_DATA+i);
|
||||
/* Check the reply status */
|
||||
ret = (dasharo_ec_read(REG_RESULT) == RESULT_OK);
|
||||
}
|
||||
|
||||
/* Reset the flags and length so we can buffer console prints again */
|
||||
dasharo_ec_write(CMD_PRINT_REG_FLAGS, 0);
|
||||
dasharo_ec_write(CMD_PRINT_REG_LEN, 0);
|
||||
|
||||
return ret;
|
||||
}
|
@@ -1,17 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef DASHARO_EC_H
|
||||
#define DASHARO_EC_H
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Send a command to the EC. request_data/request_size are the request payload,
|
||||
* request_data can be NULL if request_size is 0. reply_data/reply_size are
|
||||
* the reply payload, reply_data can be NULL if reply_size is 0.
|
||||
*/
|
||||
bool dasharo_ec_cmd(uint8_t cmd, const uint8_t *request_data,
|
||||
uint8_t request_size, uint8_t *reply_data, uint8_t reply_size);
|
||||
|
||||
#endif
|
@@ -1,9 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <smbios.h>
|
||||
|
||||
smbios_wakeup_type smbios_system_wakeup_type(void)
|
||||
{
|
||||
// TODO: Read wake source from EC.
|
||||
return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
|
||||
}
|
@@ -15,11 +15,6 @@ config EC_SYSTEM76_EC_DGPU
|
||||
bool
|
||||
default n
|
||||
|
||||
config EC_SYSTEM76_EC_LOCKDOWN
|
||||
depends on EC_SYSTEM76_EC
|
||||
bool
|
||||
default n
|
||||
|
||||
config EC_SYSTEM76_EC_OLED
|
||||
depends on EC_SYSTEM76_EC
|
||||
bool
|
||||
|
@@ -4,7 +4,6 @@ ifeq ($(CONFIG_EC_SYSTEM76_EC),y)
|
||||
all-y += system76_ec.c
|
||||
|
||||
ramstage-y += smbios.c
|
||||
ramstage-$(CONFIG_EC_SYSTEM76_EC_LOCKDOWN) += lockdown.c
|
||||
|
||||
smm-$(CONFIG_DEBUG_SMI) += system76_ec.c
|
||||
|
||||
|
@@ -1,59 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include "system76_ec.h"
|
||||
#include <bootstate.h>
|
||||
#include <commonlib/region.h>
|
||||
#include <fmap.h>
|
||||
#include <spi_flash.h>
|
||||
|
||||
static int protect_region_by_name(const char *name)
|
||||
{
|
||||
int res;
|
||||
struct region region;
|
||||
|
||||
res = fmap_locate_area(name, ®ion);
|
||||
if (res < 0) {
|
||||
printk(BIOS_ERR, "fmap_locate_area '%s' failed: %d\n", name, res);
|
||||
return res;
|
||||
}
|
||||
|
||||
res = spi_flash_ctrlr_protect_region(
|
||||
boot_device_spi_flash(),
|
||||
®ion,
|
||||
WRITE_PROTECT
|
||||
);
|
||||
if (res < 0) {
|
||||
printk(BIOS_ERR, "spi_flash_ctrlr_protect_region '%s' failed: %d\n", name, res);
|
||||
return res;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "protected '%s'\n", name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void lock(void *unused)
|
||||
{
|
||||
uint8_t state = SYSTEM76_EC_SECURITY_STATE_UNLOCK;
|
||||
if (!system76_ec_security_get(&state)) {
|
||||
printk(BIOS_INFO, "failed to get security state, assuming unlocked\n");
|
||||
state = SYSTEM76_EC_SECURITY_STATE_UNLOCK;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "security state: %d\n", state);
|
||||
if (state != SYSTEM76_EC_SECURITY_STATE_UNLOCK) {
|
||||
// Protect WP_RO region, which should contain FMAP and COREBOOT
|
||||
protect_region_by_name("WP_RO");
|
||||
// Protect RW_MRC_CACHE region, this must be done after it is written
|
||||
protect_region_by_name("RW_MRC_CACHE");
|
||||
//TODO: protect entire flash except when in SMM?
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Keep in sync with mrc_cache.c
|
||||
*/
|
||||
#if CONFIG(MRC_WRITE_NV_LATE)
|
||||
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, lock, NULL);
|
||||
#else
|
||||
BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, lock, NULL);
|
||||
#endif
|
@@ -26,9 +26,6 @@
|
||||
#define CMD_PRINT_REG_LEN 3
|
||||
#define CMD_PRINT_REG_DATA 4
|
||||
|
||||
// Get security state command
|
||||
#define CMD_SECURITY_GET 20
|
||||
|
||||
static inline uint8_t system76_ec_read(uint8_t addr)
|
||||
{
|
||||
return inb(SYSTEM76_EC_BASE + (uint16_t)addr);
|
||||
@@ -113,9 +110,3 @@ bool system76_ec_cmd(uint8_t cmd, const uint8_t *request_data,
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool system76_ec_security_get(uint8_t *state)
|
||||
{
|
||||
*state = SYSTEM76_EC_SECURITY_STATE_LOCK;
|
||||
return system76_ec_cmd(CMD_SECURITY_GET, NULL, 0, state, sizeof(*state));
|
||||
}
|
||||
|
@@ -6,15 +6,6 @@
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
// Default value, flashing is prevented, cannot be set with CMD_SECURITY_SET
|
||||
#define SYSTEM76_EC_SECURITY_STATE_LOCK 0
|
||||
// Flashing is allowed, cannot be set with CMD_SECURITY_SET
|
||||
#define SYSTEM76_EC_SECURITY_STATE_UNLOCK 1
|
||||
// Flashing will be prevented on the next reboot
|
||||
#define SYSTEM76_EC_SECURITY_STATE_PREPARE_LOCK 2
|
||||
// Flashing will be allowed on the next reboot
|
||||
#define SYSTEM76_EC_SECURITY_STATE_PREPARE_UNLOCK 3
|
||||
|
||||
/*
|
||||
* Send a command to the EC. request_data/request_size are the request payload,
|
||||
* request_data can be NULL if request_size is 0. reply_data/reply_size are
|
||||
@@ -23,6 +14,4 @@
|
||||
bool system76_ec_cmd(uint8_t cmd, const uint8_t *request_data,
|
||||
uint8_t request_size, uint8_t *reply_data, uint8_t reply_size);
|
||||
|
||||
bool system76_ec_security_get(uint8_t *state);
|
||||
|
||||
#endif
|
||||
|
@@ -129,12 +129,6 @@ u32 fdt_find_node_by_alias(const void *blob, const char *alias_name,
|
||||
*/
|
||||
int fdt_next_node_name(const void *blob, uint32_t node_offset, const char **name);
|
||||
|
||||
/* Read memory regions from a flat device-tree. */
|
||||
size_t fdt_read_memory_regions(const void *blob, struct device_tree_region regions[],
|
||||
size_t regions_count);
|
||||
/* Find top of memory from a flat device-tree. */
|
||||
uint64_t fdt_get_memory_top(const void *blob);
|
||||
|
||||
/* Read a flattened device tree into a hierarchical structure which refers to
|
||||
the contents of the flattened tree in place. Modifying the flat tree
|
||||
invalidates the unflattened one. */
|
||||
|
@@ -584,13 +584,7 @@ enum smbios_processor_upgrade_field {
|
||||
/* defines for processor family */
|
||||
#define SMBIOS_PROCESSOR_FAMILY_OTHER 0x01
|
||||
#define SMBIOS_PROCESSOR_FAMILY_UNKNOWN 0x02
|
||||
#define SMBIOS_PROCESSOR_FAMILY_INTEL486 0x06
|
||||
#define SMBIOS_PROCESSOR_FAMILY_PENTIUM_PRO 0x0c
|
||||
#define SMBIOS_PROCESSOR_FAMILY_XEON 0xb3
|
||||
#define SMBIOS_PROCESSOR_FAMILY_FROM_FAMILY2 0xfe
|
||||
|
||||
/* defines for processor family 2 */
|
||||
#define SMBIOS_PROCESSOR_FAMILY2_ARMV8 0x101
|
||||
|
||||
/* defines for processor characteristics */
|
||||
#define PROCESSOR_64BIT_CAPABLE (1 << 2)
|
||||
|
@@ -36,18 +36,6 @@
|
||||
#define DDR4_SPD_PART_OFF 329
|
||||
#define DDR4_SPD_PART_LEN 20
|
||||
#define DDR4_SPD_SN_OFF 325
|
||||
#define MAX_SPD_PAGE_SIZE_SPD5 128
|
||||
#define MAX_SPD_SIZE (SPD_PAGE_LEN * 4)
|
||||
#define SPD_HUB_MEMREG(addr) ((u8)(0x80 | (addr)))
|
||||
#define SPD5_MR11 0x0B
|
||||
#define SPD5_MR0 0x00
|
||||
#define SPD5_MEMREG_REG(addr) ((u8)((~0x80) & (addr)))
|
||||
#define SPD5_MR0_SPD5_HUB_DEV 0x51
|
||||
|
||||
struct spd_offset_table {
|
||||
u16 start; /* Offset 0 */
|
||||
u16 end; /* Offset 2 */
|
||||
};
|
||||
|
||||
struct spd_block {
|
||||
u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */
|
||||
|
@@ -160,12 +160,10 @@ ramstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
|
||||
ramstage-$(CONFIG_GENERIC_UDELAY) += timer.c
|
||||
ramstage-y += b64_decode.c
|
||||
ramstage-$(CONFIG_ACPI_NHLT) += nhlt.c
|
||||
ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c
|
||||
ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit.c
|
||||
ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c
|
||||
|
||||
romstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c
|
||||
ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c
|
||||
|
||||
romstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c
|
||||
ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c
|
||||
|
||||
|
@@ -12,12 +12,9 @@
|
||||
#include <string.h>
|
||||
#include <stddef.h>
|
||||
#include <stdlib.h>
|
||||
#include <limits.h>
|
||||
|
||||
#define FDT_PATH_MAX_DEPTH 10 // should be a good enough upper bound
|
||||
#define FDT_PATH_MAX_LEN 128 // should be a good enough upper bound
|
||||
#define FDT_MAX_MEMORY_NODES 4 // should be a good enough upper bound
|
||||
#define FDT_MAX_MEMORY_REGIONS 16 // should be a good enough upper bound
|
||||
|
||||
/*
|
||||
* Functions for picking apart flattened trees.
|
||||
@@ -506,96 +503,6 @@ void fdt_print_node(const void *blob, uint32_t offset)
|
||||
print_flat_node(blob, offset, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* fdt_read_memory_regions finds memory ranges from a flat device-tree
|
||||
*
|
||||
* @params blob address of FDT
|
||||
* @params regions all regions that are read inside the reg property of
|
||||
* memory nodes are saved inside this array
|
||||
* @params regions_count maximum number of entries that can be saved inside
|
||||
* the regions array.
|
||||
*
|
||||
* Returns: Either 0 on error or returns the number of regions put into the regions array.
|
||||
*/
|
||||
size_t fdt_read_memory_regions(const void *blob,
|
||||
struct device_tree_region regions[],
|
||||
size_t regions_count)
|
||||
{
|
||||
u32 node, root, addrcp, sizecp;
|
||||
u32 nodes[FDT_MAX_MEMORY_NODES] = {0};
|
||||
size_t region_idx = 0;
|
||||
size_t node_count = 0;
|
||||
|
||||
if (!fdt_is_valid(blob))
|
||||
return 0;
|
||||
|
||||
node = fdt_find_node_by_path(blob, "/memory", &addrcp, &sizecp);
|
||||
if (node) {
|
||||
region_idx += fdt_read_reg_prop(blob, node, addrcp, sizecp,
|
||||
regions, regions_count);
|
||||
if (region_idx >= regions_count) {
|
||||
printk(BIOS_WARNING, "FDT: Too many memory regions\n");
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
root = fdt_find_node_by_path(blob, "/", &addrcp, &sizecp);
|
||||
node_count = fdt_find_subnodes_by_prefix(blob, root, "memory@",
|
||||
&addrcp, &sizecp, nodes,
|
||||
FDT_MAX_MEMORY_NODES);
|
||||
if (node_count >= FDT_MAX_MEMORY_NODES) {
|
||||
printk(BIOS_WARNING, "FDT: Too many memory nodes\n");
|
||||
/* Can still reading the regions for those we got */
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < MIN(node_count, FDT_MAX_MEMORY_NODES); i++) {
|
||||
region_idx += fdt_read_reg_prop(blob, nodes[i], addrcp, sizecp,
|
||||
®ions[region_idx],
|
||||
regions_count - region_idx);
|
||||
if (region_idx >= regions_count) {
|
||||
printk(BIOS_WARNING, "FDT: Too many memory regions\n");
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
for (size_t i = 0; i < MIN(region_idx, regions_count); i++) {
|
||||
printk(BIOS_DEBUG, "FDT: Memory region [%#llx - %#llx]\n",
|
||||
regions[i].addr, regions[i].addr + regions[i].size);
|
||||
}
|
||||
|
||||
return region_idx;
|
||||
}
|
||||
|
||||
/*
|
||||
* fdt_get_memory_top finds top of memory from a flat device-tree
|
||||
*
|
||||
* @params blob address of FDT
|
||||
*
|
||||
* Returns: Either 0 on error or returns the maximum memory address
|
||||
*/
|
||||
uint64_t fdt_get_memory_top(const void *blob)
|
||||
{
|
||||
struct device_tree_region regions[FDT_MAX_MEMORY_REGIONS] = {0};
|
||||
uint64_t top = 0;
|
||||
uint64_t total = 0;
|
||||
size_t count;
|
||||
|
||||
if (!fdt_is_valid(blob))
|
||||
return 0;
|
||||
|
||||
count = fdt_read_memory_regions(blob, regions, FDT_MAX_MEMORY_REGIONS);
|
||||
for (size_t i = 0; i < MIN(count, FDT_MAX_MEMORY_REGIONS); i++) {
|
||||
top = MAX(top, regions[i].addr + regions[i].size);
|
||||
total += regions[i].size;
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "FDT: Found %u MiB of RAM\n",
|
||||
(uint32_t)(total / MiB));
|
||||
|
||||
return top;
|
||||
}
|
||||
|
||||
/*
|
||||
* Functions to turn a flattened tree into an unflattened one.
|
||||
*/
|
||||
@@ -701,7 +608,7 @@ struct device_tree *fdt_unflatten(const void *blob)
|
||||
const struct fdt_header *header = (const struct fdt_header *)blob;
|
||||
tree->header = header;
|
||||
|
||||
if (!fdt_is_valid(blob))
|
||||
if (fdt_is_valid(blob))
|
||||
return NULL;
|
||||
|
||||
uint32_t struct_offset = be32toh(header->structure_offset);
|
||||
|
@@ -209,9 +209,7 @@ enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk)
|
||||
|
||||
dram_type = *(spd_cache + SC_SPD_OFFSET(i) + SPD_DRAM_TYPE);
|
||||
|
||||
if (dram_type == SPD_DRAM_DDR5)
|
||||
blk->len = CONFIG_DIMM_SPD_SIZE;
|
||||
else if (dram_type == SPD_DRAM_DDR4)
|
||||
if (dram_type == SPD_DRAM_DDR4)
|
||||
blk->len = SPD_PAGE_LEN_DDR4;
|
||||
else
|
||||
blk->len = SPD_PAGE_LEN;
|
||||
|
@@ -122,11 +122,6 @@ config BOARD_GOOGLE_OVIS4ES
|
||||
config BOARD_GOOGLE_REX0
|
||||
select BOARD_GOOGLE_MODEL_REX
|
||||
|
||||
config BOARD_GOOGLE_REX64
|
||||
select BOARD_GOOGLE_MODEL_REX
|
||||
select HAVE_X86_64_SUPPORT
|
||||
select USE_X86_64_SUPPORT
|
||||
|
||||
config BOARD_GOOGLE_REX_EC_ISH
|
||||
select BOARD_GOOGLE_MODEL_REX_EC_ISH
|
||||
|
||||
@@ -187,7 +182,6 @@ config MAINBOARD_FAMILY
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
default "Rex" if BOARD_GOOGLE_REX0
|
||||
default "Rex64" if BOARD_GOOGLE_REX64
|
||||
default "Rex_Ec_Ish" if BOARD_GOOGLE_REX_EC_ISH
|
||||
default "Rex4ES" if BOARD_GOOGLE_REX4ES
|
||||
default "Rex4ES_Ec_Ish" if BOARD_GOOGLE_REX4ES_EC_ISH
|
||||
|
@@ -32,9 +32,6 @@ config BOARD_GOOGLE_REX4ES
|
||||
config BOARD_GOOGLE_REX4ES_EC_ISH
|
||||
bool "-> Rex4ES EC ISH"
|
||||
|
||||
config BOARD_GOOGLE_REX64
|
||||
bool "-> Rex 64"
|
||||
|
||||
config BOARD_GOOGLE_SCREEBO
|
||||
bool "-> Screebo"
|
||||
|
||||
|
@@ -1,12 +1,16 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
config BOARD_RAZER_BLADE_STEALTH_KBL
|
||||
bool
|
||||
if BOARD_RAZER_BLADE_STEALTH_KBL
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select SYSTEM_TYPE_LAPTOP
|
||||
select BOARD_ROMSIZE_KB_8192
|
||||
select SUPERIO_ITE_IT8528E
|
||||
select SOC_INTEL_KABYLAKE
|
||||
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
|
||||
select MEMORY_MAPPED_TPM
|
||||
select MAINBOARD_HAS_TPM2
|
||||
select MAINBOARD_HAS_LIBGFXINIT
|
||||
select HAVE_SPD_IN_CBFS
|
||||
select DRIVERS_I2C_HID
|
||||
@@ -14,31 +18,6 @@ config BOARD_RAZER_BLADE_STEALTH_KBL
|
||||
select HAVE_ACPI_TABLES
|
||||
select DRIVERS_GENERIC_CBFS_SERIAL
|
||||
|
||||
config BOARD_RAZER_BLADE_H2U
|
||||
select BOARD_RAZER_BLADE_STEALTH_KBL
|
||||
select MEMORY_MAPPED_TPM
|
||||
select MAINBOARD_HAS_TPM2
|
||||
|
||||
config BOARD_RAZER_BLADE_H3Q
|
||||
select BOARD_RAZER_BLADE_STEALTH_KBL
|
||||
|
||||
if BOARD_RAZER_BLADE_STEALTH_KBL
|
||||
|
||||
config VARIANT_DIR
|
||||
default "h2u" if BOARD_RAZER_BLADE_H2U
|
||||
default "h3q" if BOARD_RAZER_BLADE_H3Q
|
||||
|
||||
config OVERRIDE_DEVICETREE
|
||||
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
|
||||
config MAINBOARD_FAMILY
|
||||
string
|
||||
default "BLADE_STEALTH"
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
default "H2U: RZ09-01962" if BOARD_RAZER_BLADE_H2U
|
||||
default "H3Q: RZ09-01963/RZ09-01964" if BOARD_RAZER_BLADE_H3Q
|
||||
|
||||
# For now no way to choose the correct the available RAM
|
||||
config BOARD_RAZER_BLADE_STEALTH_KBL_16GB
|
||||
bool "16GB RAM (4x MT52L1G32D4PG)"
|
||||
@@ -48,6 +27,13 @@ config VGA_BIOS_ID
|
||||
string
|
||||
default "8086,5916"
|
||||
|
||||
config MAINBOARD_FAMILY
|
||||
string
|
||||
default "BLADE_STEALTH"
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
default "H2U"
|
||||
|
||||
config MAINBOARD_VERSION
|
||||
string
|
||||
default "1.0"
|
||||
|
@@ -1,7 +1,4 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
config BOARD_RAZER_BLADE_H2U
|
||||
bool "Razer Blade Stealth KabyLake (2016, RZ09-01962, 12.5\")"
|
||||
|
||||
config BOARD_RAZER_BLADE_H3Q
|
||||
bool "Razer Blade Stealth KabyLake (Mid 2017, RZ09-01963/RZ09-10964, 13.3\")"
|
||||
config BOARD_RAZER_BLADE_STEALTH_KBL
|
||||
bool "Razer Blade Stealth KabyLake (2016)"
|
||||
|
@@ -3,8 +3,6 @@
|
||||
subdirs-y += spd
|
||||
|
||||
ramstage-y += ramstage.c
|
||||
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
|
||||
ramstage-y += hda_verb.c
|
||||
|
||||
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
|
||||
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
|
||||
|
@@ -1,5 +1,5 @@
|
||||
Vendor name: RAZER
|
||||
Board name: Blade Stealth KabyLake
|
||||
Board name: Blade Stealth KabyLake (H2U)
|
||||
Category: laptop
|
||||
ROM package: SOIC8
|
||||
ROM protocol: SPI
|
||||
|
@@ -126,6 +126,24 @@ chip soc/intel/skylake
|
||||
|
||||
register "PcieRpHotPlug[4]" = "1"
|
||||
|
||||
register "usb2_ports" = "{
|
||||
[0] = USB2_PORT_MID(OC1), /* Type-A Port (right) */
|
||||
[1] = USB2_PORT_MID(OC1), /* Type-A Port (left) */
|
||||
[2] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
[3] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
[4] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
[5] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
[6] = USB2_PORT_FLEX(OC2), /* Camera */
|
||||
[7] = USB2_PORT_FLEX(OC2), /* Keyboard */
|
||||
[8] = USB2_PORT_FLEX(OC2), /* Touchscreen */
|
||||
}"
|
||||
|
||||
register "usb3_ports" = "{
|
||||
[0] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (left) */
|
||||
[1] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (right) */
|
||||
[5] = USB3_PORT_DEFAULT(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
}"
|
||||
|
||||
# PL1 override 25W
|
||||
# PL2 override 44W
|
||||
register "power_limits_config" = "{
|
||||
@@ -173,6 +191,9 @@ chip soc/intel/skylake
|
||||
device ref pcie_rp5 on end
|
||||
device ref pcie_rp9 on end
|
||||
device ref lpc_espi on
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
chip superio/ite/it8528e
|
||||
device pnp 6e.1 off end
|
||||
device pnp 6e.2 off end
|
||||
|
@@ -20,7 +20,7 @@ const u32 cim_verb_data[] = {
|
||||
AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x03211020),
|
||||
|
||||
/* Intel, Kaby Lake HDMI */
|
||||
/* Intel, KabylakeHDMI */
|
||||
0x8086280b, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
@@ -1,7 +1,7 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include <variant/gpio.h>
|
||||
#include "gpio.h"
|
||||
|
||||
void mainboard_silicon_init_params(FSP_SIL_UPD *params)
|
||||
{
|
||||
|
@@ -4,6 +4,7 @@
|
||||
#define MAINBOARD_SPD_H
|
||||
|
||||
#include <gpio.h>
|
||||
#include "../gpio.h"
|
||||
|
||||
void mainboard_fill_dq_map_data(void *dq_map_ptr);
|
||||
void mainboard_fill_dqs_map_data(void *dqs_map_ptr);
|
||||
|
@@ -1,9 +0,0 @@
|
||||
Vendor name: RAZER
|
||||
Board name: Blade Stealth KabyLake (H2U: RZ09-01962)
|
||||
Board URL: https://mysupport.razer.com/app/answers/detail/a_id/3698/
|
||||
Category: laptop
|
||||
ROM package: SOIC8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
Release year: 2016
|
@@ -1,31 +0,0 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/skylake
|
||||
device domain 0 on
|
||||
device ref south_xhci on
|
||||
register "usb2_ports" = "{
|
||||
[0] = USB2_PORT_MID(OC1), /* Type-A Port (right) */
|
||||
[1] = USB2_PORT_MID(OC1), /* Type-A Port (left) */
|
||||
[2] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
[3] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
[4] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
[5] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
[6] = USB2_PORT_FLEX(OC2), /* Camera */
|
||||
[7] = USB2_PORT_FLEX(OC2), /* Keyboard */
|
||||
[8] = USB2_PORT_FLEX(OC2), /* Touchscreen */
|
||||
}"
|
||||
|
||||
register "usb3_ports" = "{
|
||||
[0] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (left) */
|
||||
[1] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (right) */
|
||||
[5] = USB3_PORT_DEFAULT(OC1), /* TODO Unknown. Maybe USBC? */
|
||||
}"
|
||||
end
|
||||
|
||||
device ref lpc_espi on
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
@@ -1,9 +0,0 @@
|
||||
Vendor name: RAZER
|
||||
Board name: Blade Stealth KabyLake (H3Q: RZ09-01963 / RZ09-01964)
|
||||
Board URL: https://mysupport.razer.com/app/answers/detail/a_id/3694/
|
||||
Category: laptop
|
||||
ROM package: SOIC8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
Release year: 2017
|
@@ -1,34 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC298 */
|
||||
0x10ec0298, /* Vendor ID */
|
||||
0x1a586753, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x1a586753),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x4075812d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x04211020),
|
||||
|
||||
/* Intel, Kaby Lake HDMI */
|
||||
0x8086280b, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x07, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
AZALIA_ARRAY_SIZES;
|
@@ -1,200 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef CFG_GPIO_H
|
||||
#define CFG_GPIO_H
|
||||
|
||||
#include <gpio.h>
|
||||
|
||||
/* Pad configuration was generated automatically using intelp2m utility */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
|
||||
/* ------- GPIO Community 0 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_A ------- */
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A11, 0, DEEP),
|
||||
PAD_NC(GPP_A12, NONE),
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A23, 0, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_B ------- */
|
||||
PAD_CFG_GPO(GPP_B0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B4, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B8, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B10, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP),
|
||||
PAD_CFG_GPO(GPP_B15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B17, 0, DEEP),
|
||||
PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
|
||||
|
||||
/* ------- GPIO Community 1 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_C ------- */
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI_APIC_LOW(GPP_C5, DN_20K, DEEP),
|
||||
/* GPP_C6 - RESERVED */
|
||||
/* GPP_C7 - RESERVED */
|
||||
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C15, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C23, 0, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_D ------- */
|
||||
PAD_CFG_GPO(GPP_D0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D23, 0, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_E ------- */
|
||||
PAD_CFG_GPO(GPP_E0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E1, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E4, 0, DEEP),
|
||||
PAD_CFG_GPI_SCI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT),
|
||||
PAD_CFG_GPO(GPP_E6, 0, DEEP),
|
||||
PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E9, 0, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_E10, 1, DN_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_E11, 1, DN_20K, DEEP),
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT),
|
||||
PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT),
|
||||
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E22, 0, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_E23, 0, DN_20K, PLTRST),
|
||||
|
||||
/* ------- GPIO Community 2 ------- */
|
||||
|
||||
/* -------- GPIO Group GPD -------- */
|
||||
PAD_CFG_NF(GPD0, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD2, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD7, 0, DEEP),
|
||||
PAD_NC(GPD8, NONE),
|
||||
PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
|
||||
|
||||
/* ------- GPIO Community 3 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_F ------- */
|
||||
PAD_CFG_GPO(GPP_F0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F7, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F12, 0, DEEP),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F23, 0, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_G ------- */
|
||||
PAD_CFG_GPO(GPP_G0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G7, 0, DEEP),
|
||||
};
|
||||
|
||||
#endif /* CFG_GPIO_H */
|
@@ -1,23 +0,0 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/skylake
|
||||
device domain 0 on
|
||||
device ref south_xhci on
|
||||
# NOTE: TYPE-C port is controlled by Intel Thunderbolt
|
||||
|
||||
register "usb2_ports" = "{
|
||||
[0] = USB2_PORT_MID(OC0), /* Type-A Port (right) */
|
||||
[1] = USB2_PORT_MID(OC0), /* Type-A Port (left) */
|
||||
[5] = USB2_PORT_SHORT(OC2), /* M.2 Slot (Bluetooth) */
|
||||
[6] = USB2_PORT_FLEX(OC3), /* Camera */
|
||||
[7] = USB2_PORT_FLEX(OC3), /* Keyboard */
|
||||
[8] = USB2_PORT_FLEX(OC_SKIP), /* Touchscreen */
|
||||
}"
|
||||
|
||||
register "usb3_ports" = "{
|
||||
[0] = USB3_PORT_DEFAULT(OC0), /* Type-A Port (left) */
|
||||
[1] = USB3_PORT_DEFAULT(OC0), /* Type-A Port (right) */
|
||||
}"
|
||||
end
|
||||
end
|
||||
end
|
@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select BOARD_ROMSIZE_KB_16384
|
||||
select DRIVERS_GENERIC_CBFS_SERIAL
|
||||
select DRIVERS_GENERIC_CBFS_UUID
|
||||
select DRIVERS_GFX_NVIDIA
|
||||
select DRIVERS_I2C_HID
|
||||
select DRIVERS_I2C_TAS5825M
|
||||
select EC_SYSTEM76_EC
|
||||
|
@@ -1,6 +1,6 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
|
||||
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
|
||||
|
||||
bootblock-y += bootblock.c
|
||||
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
|
||||
|
@@ -1,19 +1,11 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <variant/gpio.h>
|
||||
|
||||
#define EC_GPE_SCI 0x03 /* GPP_K3 */
|
||||
#define EC_GPE_SWI 0x06 /* GPP_K6 */
|
||||
#include <ec/system76/ec/acpi/ec.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
#include "sleep.asl"
|
||||
Scope (PCI0) {
|
||||
Device (PEGP) {
|
||||
Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
|
||||
#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_GPE) {
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
register "common_soc_config" = "{
|
||||
// Touchpad I2C bus
|
||||
@@ -58,12 +56,6 @@ chip soc/intel/cannonlake
|
||||
# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
|
||||
register "PcieClkSrcUsage[8]" = "0x40"
|
||||
register "PcieClkSrcClkReq[8]" = "8"
|
||||
chip drivers/gfx/nvidia
|
||||
device pci 00.0 on end # VGA controller
|
||||
device pci 00.1 on end # Audio device
|
||||
device pci 00.2 on end # USB xHCI Host controller
|
||||
device pci 00.3 on end # USB Type-C UCSI controller
|
||||
end
|
||||
end
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 04.0 on # SA Thermal device
|
||||
|
@@ -3,16 +3,7 @@
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#define DGPU_RST_N GPP_F8
|
||||
#define DGPU_PWR_EN GPP_F9
|
||||
#define DGPU_GC6 GPP_K11
|
||||
#define DGPU_SSID 0x50151558
|
||||
|
||||
#ifndef __ACPI__
|
||||
void variant_configure_early_gpios(void);
|
||||
void variant_configure_gpios(void);
|
||||
#endif
|
||||
|
||||
#endif
|
@@ -1,9 +1,7 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <drivers/gfx/nvidia/gpu.h>
|
||||
#include <soc/cnl_memcfg_init.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
static const struct cnl_mb_cfg memcfg = {
|
||||
.spd[0] = {
|
||||
@@ -22,17 +20,5 @@ static const struct cnl_mb_cfg memcfg = {
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
const struct nvidia_gpu_config config = {
|
||||
.power_gpio = DGPU_PWR_EN,
|
||||
.reset_gpio = DGPU_RST_N,
|
||||
.enable = true,
|
||||
};
|
||||
|
||||
// Enable dGPU power
|
||||
nvidia_set_power(&config);
|
||||
|
||||
// Set primary display to internal graphics
|
||||
memupd->FspmConfig.PrimaryDisplay = 0;
|
||||
|
||||
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
|
||||
}
|
||||
|
@@ -1,18 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#define DGPU_RST_N GPP_F22
|
||||
#define DGPU_PWR_EN GPP_F23
|
||||
#define DGPU_GC6 GPP_C12
|
||||
#define DGPU_SSID 0x65d11558
|
||||
|
||||
#ifndef __ACPI__
|
||||
void variant_configure_early_gpios(void);
|
||||
void variant_configure_gpios(void);
|
||||
#endif
|
||||
|
||||
#endif
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
# Serial I/O
|
||||
register "SerialIoDevMode" = "{
|
||||
|
@@ -1,18 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#define DGPU_RST_N GPP_F22
|
||||
#define DGPU_PWR_EN GPP_F23
|
||||
#define DGPU_GC6 GPP_C12
|
||||
#define DGPU_SSID 0x65e11558
|
||||
|
||||
#ifndef __ACPI__
|
||||
void variant_configure_early_gpios(void);
|
||||
void variant_configure_gpios(void);
|
||||
#endif
|
||||
|
||||
#endif
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
# Serial I/O
|
||||
register "SerialIoDevMode" = "{
|
||||
|
@@ -10,7 +10,6 @@ config BOARD_SYSTEM76_ADL_COMMON
|
||||
select DRIVERS_INTEL_PMC
|
||||
select DRIVERS_INTEL_USB4_RETIMER
|
||||
select EC_SYSTEM76_EC
|
||||
select EC_SYSTEM76_EC_LOCKDOWN
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select HAVE_CMOS_DEFAULT
|
||||
@@ -36,12 +35,10 @@ config BOARD_SYSTEM76_GALP6
|
||||
|
||||
config BOARD_SYSTEM76_GAZE17_3050
|
||||
select BOARD_SYSTEM76_ADL_COMMON
|
||||
select DRIVERS_GFX_NVIDIA
|
||||
select EC_SYSTEM76_EC_DGPU
|
||||
|
||||
config BOARD_SYSTEM76_GAZE17_3060_B
|
||||
select BOARD_SYSTEM76_ADL_COMMON
|
||||
select DRIVERS_GFX_NVIDIA
|
||||
select EC_SYSTEM76_EC_DGPU
|
||||
select MAINBOARD_USES_IFD_GBE_REGION
|
||||
|
||||
@@ -51,15 +48,11 @@ config BOARD_SYSTEM76_LEMP11
|
||||
|
||||
config BOARD_SYSTEM76_ORYP9
|
||||
select BOARD_SYSTEM76_ADL_COMMON
|
||||
select DRIVERS_GFX_NVIDIA
|
||||
select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
|
||||
select DRIVERS_I2C_TAS5825M
|
||||
select EC_SYSTEM76_EC_DGPU
|
||||
|
||||
config BOARD_SYSTEM76_ORYP10
|
||||
select BOARD_SYSTEM76_ADL_COMMON
|
||||
select DRIVERS_GFX_NVIDIA
|
||||
select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
|
||||
select EC_SYSTEM76_EC_DGPU
|
||||
|
||||
if BOARD_SYSTEM76_ADL_COMMON
|
||||
@@ -104,22 +97,12 @@ config MAINBOARD_VERSION
|
||||
default "oryp9" if BOARD_SYSTEM76_ORYP9
|
||||
default "oryp10" if BOARD_SYSTEM76_ORYP10
|
||||
|
||||
config CMOS_DEFAULT_FILE
|
||||
default "src/mainboard/\$(MAINBOARDDIR)/cmos-csme.default" if BOARD_SYSTEM76_DARP8
|
||||
default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
|
||||
|
||||
config CONSOLE_POST
|
||||
default y
|
||||
|
||||
config D3COLD_SUPPORT
|
||||
default n
|
||||
|
||||
config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
|
||||
default 45 if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
|
||||
|
||||
config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
|
||||
default 25 if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
|
||||
|
||||
config FMDFILE
|
||||
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
|
||||
|
||||
|
@@ -2,10 +2,6 @@
|
||||
|
||||
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
|
||||
|
||||
ifeq ($(CONFIG_DRIVERS_GFX_NVIDIA),y)
|
||||
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
|
||||
endif
|
||||
|
||||
bootblock-y += bootblock.c
|
||||
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
|
||||
|
||||
|
@@ -1,9 +1,5 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#if CONFIG(DRIVERS_GFX_NVIDIA)
|
||||
#include <variant/gpio.h>
|
||||
#endif
|
||||
|
||||
#define EC_GPE_SCI 0x6E
|
||||
#define EC_GPE_SWI 0x6B
|
||||
#include <ec/system76/ec/acpi/ec.asl>
|
||||
@@ -12,11 +8,5 @@ Scope (\_SB) {
|
||||
#include "sleep.asl"
|
||||
Scope (PCI0) {
|
||||
#include "backlight.asl"
|
||||
|
||||
#if CONFIG(DRIVERS_GFX_NVIDIA)
|
||||
Scope (PEG2) {
|
||||
#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
@@ -1,3 +0,0 @@
|
||||
boot_option=Fallback
|
||||
debug_level=Debug
|
||||
me_state=Enable
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "common_soc_config" = "{
|
||||
// Touchpad I2C bus
|
||||
|
@@ -1,8 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "s0ix_enable" = "1"
|
||||
|
||||
register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
|
||||
.tdp_pl1_override = 20,
|
||||
.tdp_pl2_override = 56,
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
|
||||
.tdp_pl1_override = 28,
|
||||
|
@@ -1,13 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#define DGPU_RST_N GPP_B2
|
||||
#define DGPU_PWR_EN GPP_A14
|
||||
#define DGPU_GC6 GPP_F13
|
||||
#define DGPU_SSID 0x866d1558
|
||||
|
||||
#endif
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
# FIVR configuration
|
||||
# Read EXT_RAIL_CONFIG to determine bitmaps
|
||||
@@ -40,10 +38,6 @@ chip soc/intel/alderlake
|
||||
.clk_req = 3,
|
||||
.flags = PCIE_RP_LTR,
|
||||
}"
|
||||
chip drivers/gfx/nvidia
|
||||
device pci 00.0 on end # VGA controller
|
||||
device pci 00.1 on end # Audio device
|
||||
end
|
||||
end
|
||||
device ref pcie4_0 on
|
||||
# PCIe PEG0 x4, Clock 0 (SSD2)
|
||||
|
@@ -1,9 +1,7 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <drivers/gfx/nvidia/gpu.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
@@ -19,14 +17,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
};
|
||||
const bool half_populated = false;
|
||||
|
||||
const struct nvidia_gpu_config config = {
|
||||
.power_gpio = DGPU_PWR_EN,
|
||||
.reset_gpio = DGPU_RST_N,
|
||||
.enable = true,
|
||||
};
|
||||
// Enable dGPU power
|
||||
nvidia_set_power(&config);
|
||||
|
||||
// Set primary display to internal graphics
|
||||
mupd->FspmConfig.PrimaryDisplay = 0;
|
||||
|
||||
|
@@ -1,13 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#define DGPU_RST_N GPP_B2
|
||||
#define DGPU_PWR_EN GPP_A14
|
||||
#define DGPU_GC6 GPP_F13
|
||||
#define DGPU_SSID 0x867c1558
|
||||
|
||||
#endif
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
# FIVR configuration
|
||||
# Read EXT_RAIL_CONFIG to determine bitmaps
|
||||
@@ -40,10 +38,6 @@ chip soc/intel/alderlake
|
||||
.clk_req = 3,
|
||||
.flags = PCIE_RP_LTR,
|
||||
}"
|
||||
chip drivers/gfx/nvidia
|
||||
device pci 00.0 on end # VGA controller
|
||||
device pci 00.1 on end # Audio device
|
||||
end
|
||||
end
|
||||
device ref igpu on
|
||||
# DDIA is eDP
|
||||
|
@@ -1,9 +1,7 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <drivers/gfx/nvidia/gpu.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
@@ -19,14 +17,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
};
|
||||
const bool half_populated = false;
|
||||
|
||||
const struct nvidia_gpu_config config = {
|
||||
.power_gpio = DGPU_PWR_EN,
|
||||
.reset_gpio = DGPU_RST_N,
|
||||
.enable = true,
|
||||
};
|
||||
// Enable dGPU power
|
||||
nvidia_set_power(&config);
|
||||
|
||||
// Set primary display to internal graphics
|
||||
mupd->FspmConfig.PrimaryDisplay = 0;
|
||||
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{
|
||||
.tdp_pl1_override = 15,
|
||||
|
@@ -1,13 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#define DGPU_RST_N GPP_B2
|
||||
#define DGPU_PWR_EN GPP_A14
|
||||
#define DGPU_GC6 GPP_A7
|
||||
#define DGPU_SSID 0x65f51558
|
||||
|
||||
#endif
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
|
||||
.tdp_pl1_override = 45,
|
||||
@@ -25,10 +23,6 @@ chip soc/intel/alderlake
|
||||
.clk_req = 3,
|
||||
.flags = PCIE_RP_LTR,
|
||||
}"
|
||||
chip drivers/gfx/nvidia
|
||||
device pci 00.0 on end # VGA controller
|
||||
device pci 00.1 on end # Audio device
|
||||
end
|
||||
end
|
||||
device ref igpu on
|
||||
register "ddi_portA_config" = "1"
|
||||
|
@@ -1,9 +1,7 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <drivers/gfx/nvidia/gpu.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
@@ -22,14 +20,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
};
|
||||
const bool half_populated = false;
|
||||
|
||||
const struct nvidia_gpu_config config = {
|
||||
.power_gpio = DGPU_PWR_EN,
|
||||
.reset_gpio = DGPU_RST_N,
|
||||
.enable = true,
|
||||
};
|
||||
// Enable dGPU power
|
||||
nvidia_set_power(&config);
|
||||
|
||||
// Set primary display to internal graphics
|
||||
mupd->FspmConfig.PrimaryDisplay = 0;
|
||||
|
||||
|
@@ -1,13 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#define DGPU_RST_N GPP_B2
|
||||
#define DGPU_PWR_EN GPP_A14
|
||||
#define DGPU_GC6 GPP_A7
|
||||
#define DGPU_SSID 0x65f51558
|
||||
|
||||
#endif
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
|
||||
.tdp_pl1_override = 45,
|
||||
@@ -25,10 +23,6 @@ chip soc/intel/alderlake
|
||||
.clk_req = 3,
|
||||
.flags = PCIE_RP_LTR,
|
||||
}"
|
||||
chip drivers/gfx/nvidia
|
||||
device pci 00.0 on end # VGA controller
|
||||
device pci 00.1 on end # Audio device
|
||||
end
|
||||
end
|
||||
device ref igpu on
|
||||
register "ddi_portA_config" = "1"
|
||||
|
@@ -1,9 +1,7 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <drivers/gfx/nvidia/gpu.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
@@ -19,14 +17,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
};
|
||||
const bool half_populated = false;
|
||||
|
||||
const struct nvidia_gpu_config config = {
|
||||
.power_gpio = DGPU_PWR_EN,
|
||||
.reset_gpio = DGPU_RST_N,
|
||||
.enable = true,
|
||||
};
|
||||
// Enable dGPU power
|
||||
nvidia_set_power(&config);
|
||||
|
||||
// Set primary display to internal graphics
|
||||
mupd->FspmConfig.PrimaryDisplay = 0;
|
||||
|
||||
|
@@ -7,9 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select BOARD_ROMSIZE_KB_16384
|
||||
select DRIVERS_GENERIC_CBFS_SERIAL
|
||||
select DRIVERS_GENERIC_CBFS_UUID
|
||||
select DRIVERS_GFX_NVIDIA
|
||||
select DRIVERS_I2C_HID
|
||||
select DRIVERS_I2C_TAS5825M
|
||||
select EC_SYSTEM76_EC
|
||||
select EC_SYSTEM76_EC_DGPU
|
||||
select HAVE_ACPI_RESUME
|
||||
|
@@ -10,4 +10,3 @@ romstage-y += romstage.c
|
||||
ramstage-y += ramstage.c
|
||||
ramstage-y += gpio.c
|
||||
ramstage-y += hda_verb.c
|
||||
ramstage-y += tas5825m.c
|
||||
|
@@ -1,5 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/cannonlake
|
||||
register "common_soc_config" = "{
|
||||
// Touchpad I2C bus
|
||||
@@ -61,12 +59,11 @@ chip soc/intel/cannonlake
|
||||
# PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU)
|
||||
register "PcieClkSrcUsage[7]" = "0x40"
|
||||
register "PcieClkSrcClkReq[7]" = "7"
|
||||
chip drivers/gfx/nvidia
|
||||
device pci 00.0 on end # VGA controller
|
||||
device pci 00.1 on end # Audio device
|
||||
device pci 00.2 on end # USB xHCI Host controller
|
||||
device pci 00.3 on end # USB Type-C UCSI controller
|
||||
end
|
||||
|
||||
device pci 00.0 on end # VGA controller
|
||||
device pci 00.1 on end # Audio device
|
||||
device pci 00.2 on end # USB xHCI Host controller
|
||||
device pci 00.3 on end # USB Type-C UCSI controller
|
||||
end
|
||||
# TODO: is this enough to disable iGPU?
|
||||
device pci 02.0 off end # Integrated Graphics Device
|
||||
@@ -222,16 +219,7 @@ chip soc/intel/cannonlake
|
||||
device pci 1f.3 on # Intel HDA
|
||||
register "PchHdaAudioLinkHda" = "1"
|
||||
end
|
||||
device pci 1f.4 on # SMBus
|
||||
chip drivers/i2c/tas5825m
|
||||
register "id" = "0"
|
||||
device i2c 4e on end # (8bit address: 0x9c)
|
||||
end
|
||||
chip drivers/i2c/tas5825m
|
||||
register "id" = "1"
|
||||
device i2c 4f on end # (8bit address: 0x9e)
|
||||
end
|
||||
end
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
|
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Reference in New Issue
Block a user