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Author SHA1 Message Date
Tim Crawford
d3ab11534d mb/system76/mtl: Add Darter Pro 10
The Darter Pro 10 (darp10) is an Intel Meteor Lake-H based board.

There are 2 variants in order to differentiate the 14" and 16" models,
as they have different keyboards and so have different EC firmware.

Change-Id: Iaef03a47cf108591ef823bfa779777c7c05c6337
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-06-03 14:53:54 -06:00
143 changed files with 152 additions and 6322 deletions

36
.gitmodules vendored
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@@ -1,70 +1,70 @@
[submodule "3rdparty/blobs"]
path = 3rdparty/blobs
url = https://review.coreboot.org/blobs.git
url = ../blobs.git
update = none
ignore = dirty
[submodule "util/nvidia-cbootimage"]
path = util/nvidia/cbootimage
url = https://review.coreboot.org/nvidia-cbootimage.git
url = ../nvidia-cbootimage.git
[submodule "vboot"]
path = 3rdparty/vboot
url = https://review.coreboot.org/vboot.git
url = ../vboot.git
branch = main
[submodule "arm-trusted-firmware"]
path = 3rdparty/arm-trusted-firmware
url = https://review.coreboot.org/arm-trusted-firmware.git
url = ../arm-trusted-firmware.git
[submodule "3rdparty/chromeec"]
path = 3rdparty/chromeec
url = https://review.coreboot.org/chrome-ec.git
url = ../chrome-ec.git
[submodule "libhwbase"]
path = 3rdparty/libhwbase
url = https://review.coreboot.org/libhwbase.git
url = ../libhwbase.git
[submodule "libgfxinit"]
path = 3rdparty/libgfxinit
url = https://review.coreboot.org/libgfxinit.git
url = ../libgfxinit.git
[submodule "3rdparty/fsp"]
path = 3rdparty/fsp
url = https://review.coreboot.org/fsp.git
url = ../fsp.git
update = none
ignore = dirty
[submodule "opensbi"]
path = 3rdparty/opensbi
url = https://review.coreboot.org/opensbi.git
url = ../opensbi.git
[submodule "intel-microcode"]
path = 3rdparty/intel-microcode
url = https://review.coreboot.org/intel-microcode.git
url = ../intel-microcode.git
update = none
ignore = dirty
branch = main
[submodule "3rdparty/ffs"]
path = 3rdparty/ffs
url = https://review.coreboot.org/ffs.git
url = ../ffs.git
[submodule "3rdparty/amd_blobs"]
path = 3rdparty/amd_blobs
url = https://review.coreboot.org/amd_blobs
url = ../amd_blobs
update = none
ignore = dirty
[submodule "3rdparty/cmocka"]
path = 3rdparty/cmocka
url = https://review.coreboot.org/cmocka.git
url = ../cmocka.git
update = none
branch = stable-1.1
[submodule "3rdparty/qc_blobs"]
path = 3rdparty/qc_blobs
url = https://review.coreboot.org/qc_blobs.git
url = ../qc_blobs.git
update = none
ignore = dirty
[submodule "3rdparty/intel-sec-tools"]
path = 3rdparty/intel-sec-tools
url = https://review.coreboot.org/9esec-security-tooling.git
url = ../9esec-security-tooling.git
[submodule "3rdparty/stm"]
path = 3rdparty/stm
url = https://review.coreboot.org/STM
url = ../STM
branch = stmpe
[submodule "util/goswid"]
path = util/goswid
url = https://review.coreboot.org/goswid.git
url = ../goswid
branch = trunk
[submodule "src/vendorcode/amd/opensil/genoa_poc/opensil"]
path = src/vendorcode/amd/opensil/genoa_poc/opensil
url = https://review.coreboot.org/opensil_genoa_poc.git
url = ../opensil_genoa_poc.git

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@@ -1,38 +0,0 @@
config DRIVERS_GFX_NVIDIA
bool
default n
help
Support for NVIDIA Optimus graphics
config DRIVERS_GFX_NVIDIA_BRIDGE
hex "PCI bridge for the GPU device"
default 0x01
depends on DRIVERS_GFX_NVIDIA
config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
depends on DRIVERS_GFX_NVIDIA
bool
default n
help
Support for NVIDIA Dynamic Boost
config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
int "Total processor power offset from default TGP in watts"
default 45
depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
help
This identifies the available power for the CPU or GPU boost
config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN
int "Minimum TGP offset from default TGP in watts"
default 0
depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
help
This is used to transfer power from the GPU to the CPU
config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
int "Maximum TGP offset from default TGP in watts"
default 0
depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
help
This is used to transfer power from the CPU to the GPU

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@@ -1,5 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c

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@@ -1,96 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* NVIDIA GC6 on CFL and CML CPU PCIe ports */
// Memory mapped PCI express config space
OperationRegion (PCIC, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + (CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15), 0x1000)
Field (PCIC, ByteAcc, NoLock, Preserve) {
PVID, 16,
PDID, 16,
Offset (0x248),
, 7,
L23E, 1, /* L23_Rdy Entry Request */
L23R, 1, /* L23_Rdy to Detect Transition */
Offset (0xC20),
, 4,
P0AP, 2, /* Additional power savings */
Offset (0xC38),
, 3,
P0RM, 1, /* Robust squelch mechanism */
}
// Enter L23
Method (DL23, 0, Serialized) {
Printf(" GPU PORT DL23 START")
L23E = 1
Sleep (16)
Local0 = 0
While (L23E) {
If ((Local0 > 4)) {
Break
}
Sleep (16)
Local0++
}
P0RM = 1
P0AP = 3
Printf(" GPU PORT DL23 FINISH")
}
// Exit L23
Method (L23D, 0, Serialized) {
Printf(" GPU PORT L23D START")
L23R = 1
Sleep (16)
Local0 = 0
While (L23R) {
If ((Local0 > 4)) {
Break
}
Sleep (16)
Local0++
}
P0RM = 0
P0AP = 0
Printf(" GPU PORT L23D FINISH")
}
// Main power resource
PowerResource (PWRR, 0, 0) {
Name (_STA, 1)
Method (_ON, 0, Serialized) {
Printf("GPU PORT PWRR._ON")
^^DEV0._ON()
_STA = 1
}
Method (_OFF, 0, Serialized) {
Printf("GPU PORT PWRR._OFF")
^^DEV0._OFF()
_STA = 0
}
}
// Power resources for entering D0
Name (_PR0, Package () { PWRR })
// Power resources for entering D3
Name (_PR3, Package () { PWRR })
#include "common/gpu.asl"

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@@ -1,30 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#define NV_ERROR_SUCCESS 0x0
#define NV_ERROR_UNSPECIFIED 0x80000001
#define NV_ERROR_UNSUPPORTED 0x80000002
#include "gps.asl"
#include "nvjt.asl"
Method (_DSM, 4, Serialized) {
Printf("GPU _DSM")
If (Arg0 == ToUUID (JT_DSM_GUID)) {
If (ToInteger(Arg1) >= JT_REVISION_ID_MIN) {
Return (NVJT(Arg2, Arg3))
} Else {
Printf(" Unsupported JT revision: %o", SFST(Arg1))
Return (NV_ERROR_UNSUPPORTED)
}
} ElseIf (Arg0 == ToUUID (GPS_DSM_GUID)) {
If (ToInteger(Arg1) == GPS_REVISION_ID) {
Return (GPS(Arg2, Arg3))
} Else {
Printf(" Unsupported GPS revision: %o", SFST(Arg1))
Return (NV_ERROR_UNSUPPORTED)
}
} Else {
Printf(" Unsupported GUID: %o", IDST(Arg0))
Return (NV_ERROR_UNSPECIFIED)
}
}

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@@ -1,66 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#define GPS_DSM_GUID "A3132D01-8CDA-49BA-A52E-BC9D46DF6B81"
#define GPS_REVISION_ID 0x00000200
#define GPS_FUNC_SUPPORT 0x00000000
#define GPS_FUNC_PSHARESTATUS 0x00000020
#define GPS_FUNC_PSHAREPARAMS 0x0000002A
Method(GPS, 2, Serialized) {
Printf(" GPU GPS")
Switch(ToInteger(Arg0)) {
Case(GPS_FUNC_SUPPORT) {
Printf(" Supported Functions")
Return(ITOB(
(1 << GPS_FUNC_SUPPORT) |
(1 << GPS_FUNC_PSHARESTATUS) |
(1 << GPS_FUNC_PSHAREPARAMS)
))
}
Case(GPS_FUNC_PSHARESTATUS) {
Printf(" Power Share Status")
Return(ITOB(0))
}
Case(GPS_FUNC_PSHAREPARAMS) {
Printf(" Power Share Parameters")
CreateField(Arg1, 0, 4, QTYP) // Query type
Name(GPSP, Buffer(36) { 0x00 })
CreateDWordField(GPSP, 0, RSTS) // Response status
CreateDWordField(GPSP, 4, VERS) // Version
// Set query type of response
RSTS = QTYP
// Set version of response
VERS = 0x00010000
Switch(ToInteger(QTYP)) {
Case(0) {
Printf(" Request Current Information")
// No required information
Return(GPSP)
}
Case(1) {
Printf(" Request Supported Fields")
// Support GPU temperature field
RSTS |= (1 << 8)
Return(GPSP)
}
Case(2) {
Printf(" Request Current Limits")
// No required limits
Return(GPSP)
}
Default {
Printf(" Unknown Query: %o", SFST(QTYP))
Return(NV_ERROR_UNSUPPORTED)
}
}
}
Default {
Printf(" Unsupported function: %o", SFST(Arg0))
Return(NV_ERROR_UNSUPPORTED)
}
}
}

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@@ -1,18 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Device (DEV0) {
Name(_ADR, 0x00000000)
#include "utility.asl"
#include "dsm.asl"
#include "power.asl"
}
#if CONFIG(DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST)
Scope (\_SB) {
Device(NPCF) {
#include "utility.asl"
#include "nvpcf.asl"
}
}
#endif

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@@ -1,152 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#define JT_DSM_GUID "CBECA351-067B-4924-9CBD-B46B00B86F34"
#define JT_REVISION_ID_MIN 0x00000100
#define JT_REVISION_ID_MAX 0x00000200
#define JT_FUNC_SUPPORT 0x00000000
#define JT_FUNC_CAPS 0x00000001
#define JT_FUNC_POWERCONTROL 0x00000003
//TODO: SMI traps and EGIN/XCLM
#define JT_GPC_GSS 0 // Get current GPU GCx sleep status
#define JT_GPC_EGNS 1 // Enter GC6 without self-refresh
#define JT_GPC_EGIS 2 // Enter GC6 with self-refresh
#define JT_GPC_XGXS 3 // Exit GC6 and stop self-refresh
#define JT_GPC_XGIS 4 // Exit GC6 for self-refresh update
#define JT_DFGC_NONE 0 // Handle request immediately
#define JT_DFGC_DEFER 1 // Defer GPC and GPCX
//TODO #define JT_DFGC_CLEAR 2 // Clear pending requests
// Deferred GC6 enter/exit until D3-cold (saved DFGC)
Name(DFEN, 0)
// Deferred GC6 enter control (saved GPC)
Name(DFCI, 0)
// Deferred GC6 exit control (saved GPCX)
Name(DFCO, 0)
Method (NVJT, 2, Serialized) {
Printf(" GPU NVJT")
Switch (ToInteger(Arg0)) {
Case (JT_FUNC_SUPPORT) {
Printf(" Supported Functions")
Return(ITOB(
(1 << JT_FUNC_SUPPORT) |
(1 << JT_FUNC_CAPS) |
(1 << JT_FUNC_POWERCONTROL)
))
}
Case (JT_FUNC_CAPS) {
Printf(" Capabilities")
Return(ITOB(
(1 << 0) | // G-SYNC NSVR power-saving features are enabled
(1 << 1) | // NVSR disabled
(2 << 3) | // Panel power and backlight are on the suspend rail
(0 << 5) | // self-refresh controller remains powered while panel is powered
(0 << 6) | // FB is not on the suspend rail but is powered on in GC6
(0 << 8) | // Combined power rail for all GPUs
(0 << 10) | // External SPI ROM
(1 << 11) | // No SMI handler for kernel panic exit while in GC6
(0 << 12) | // Supports notify on GC6 state done
(1 << 13) | // Support deferred GC6
(1 << 14) | // Support fine-grained root port control
(2 << 15) | // GC6 version is GC6-R
(0 << 17) | // GC6 exit ISR is not supported
(0 << 18) | // GC6 self wakeup not supported
(JT_REVISION_ID_MAX << 20) // Highest revision supported
))
}
Case (JT_FUNC_POWERCONTROL) {
Printf(" Power Control: %o", SFST(Arg1))
CreateField (Arg1, 0, 3, GPC) // GPU power control
CreateField (Arg1, 4, 1, PPC) // Panel power control
CreateField (Arg1, 14, 2, DFGC) // Defer GC6 enter/exit until D3 cold
CreateField (Arg1, 16, 3, GPCX) // Deferred GC6 exit control
// Save deferred GC6 request
If ((ToInteger(GPC) != 0) || (ToInteger(DFGC) != 0)) {
DFEN = DFGC
DFCI = GPC
DFCO = GPCX
}
// Buffer to cache current state
Name (JTBF, Buffer (4) { 0, 0, 0, 0 })
CreateField (JTBF, 0, 3, CGCS) // Current GC state
CreateField (JTBF, 3, 1, CGPS) // Current GPU power status
CreateField (JTBF, 7, 1, CPSS) // Current panel and SRC state (0 when on)
// If doing deferred GC6 request, return now
If (ToInteger(DFGC) != 0) {
CGCS = 1
CGPS = 1
Return (JTBF)
}
// Apply requested state
Switch (ToInteger(GPC)) {
Case (JT_GPC_GSS) {
Printf(" Get current GPU GCx sleep status")
//TODO: include transitions!
If (GTXS(DGPU_RST_N)) {
// GPU powered on
CGCS = 1
CGPS = 1
} ElseIf (GTXS(DGPU_PWR_EN)) {
// GPU powered off, GC6
CGCS = 3
CGPS = 0
} Else {
// GPU powered off, D3 cold
CGCS = 2
CGPS = 0
}
}
Case (JT_GPC_EGNS) {
Printf(" Enter GC6 without self-refresh")
GC6I()
CPSS = 1
}
Case (JT_GPC_EGIS) {
Printf(" Enter GC6 with self-refresh")
GC6I()
If (ToInteger(PPC) == 0) {
CPSS = 0
}
}
Case (JT_GPC_XGXS) {
Printf(" Exit GC6 and stop self-refresh")
GC6O()
CGCS = 1
CGPS = 1
If (ToInteger(PPC) != 0) {
CPSS = 0
}
}
Case (JT_GPC_XGIS) {
Printf(" Exit GC6 for self-refresh update")
GC6O()
CGCS = 1
CGPS = 1
If (ToInteger(PPC) != 0) {
CPSS = 0
}
}
Default {
Printf(" Unsupported GPU power control: %o", SFST(GPC))
}
}
Return (JTBF)
}
Default {
Printf(" Unsupported function: %o", SFST(Arg0))
Return (NV_ERROR_UNSUPPORTED)
}
}
}

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@@ -1,113 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#define NVPCF_DSM_GUID "36b49710-2483-11e7-9598-0800200c9a66"
#define NVPCF_REVISION_ID 0x00000200
#define NVPCF_ERROR_SUCCESS 0x0
#define NVPCF_ERROR_GENERIC 0x80000001
#define NVPCF_ERROR_UNSUPPORTED 0x80000002
#define NVPCF_FUNC_GET_SUPPORTED 0x00000000
#define NVPCF_FUNC_GET_STATIC_CONFIG_TABLES 0x00000001
#define NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS 0x00000002
Name(_HID, "NVDA0820")
Name(_UID, "NPCF")
Method(_DSM, 4, Serialized) {
Printf("NVPCF _DSM")
If (Arg0 == ToUUID(NVPCF_DSM_GUID)) {
If (ToInteger(Arg1) == NVPCF_REVISION_ID) {
Return(NPCF(Arg2, Arg3))
} Else {
Printf(" Unsupported NVPCF revision: %o", SFST(Arg1))
Return(NVPCF_ERROR_GENERIC)
}
} Else {
Printf(" Unsupported GUID: %o", IDST(Arg0))
Return(NVPCF_ERROR_GENERIC)
}
}
Method(NPCF, 2, Serialized) {
Printf(" NVPCF NPCF")
Switch(ToInteger(Arg0)) {
Case(NVPCF_FUNC_GET_SUPPORTED) {
Printf(" Supported Functions")
Return(ITOB(
(1 << NVPCF_FUNC_GET_SUPPORTED) |
(1 << NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) |
(1 << NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS)
))
}
Case(NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) {
Printf(" Get Static Config")
Return(Buffer(14) {
// Device table header
0x20, 0x03, 0x01,
// Intel + NVIDIA
0x00,
// Controller table header
0x23, 0x04, 0x05, 0x01,
// Dynamic boost controller
0x01,
// Supports DC
0x01,
// Reserved
0x00, 0x00, 0x00,
// Checksum
0xAD
})
}
Case(NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS) {
Printf(" Update Dynamic Boost")
CreateField(Arg1, 0x28, 2, ICMD) // Input command
Name(PCFP, Buffer(49) {
// Table version
0x23,
// Table header size
0x05,
// Size of common status in bytes
0x10,
// Size of controller entry in bytes
0x1C,
// Other fields filled in later
})
CreateByteField(PCFP, 0x04, CCNT) // Controller count
CreateWordField(PCFP, 0x19, ATPP) // AC TPP offset
CreateWordField(PCFP, 0x1D, AMXP) // AC maximum TGP offset
CreateWordField(PCFP, 0x21, AMNP) // AC minimum TGP offset
Switch(ToInteger(ICMD)) {
Case(0) {
Printf(" Get Controller Params")
// Number of controllers
CCNT = 1
// AC total processor power offset from default TGP in 1/8 watt units
ATPP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP << 3)
// AC maximum TGP offset from default TGP in 1/8 watt units
AMXP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX << 3)
// AC minimum TGP offset from default TGP in 1/8 watt units
AMNP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN << 3)
Printf("PCFP: %o", SFST(PCFP))
Return(PCFP)
}
Case(1) {
Printf(" Set Controller Status")
//TODO
Printf("PCFP: %o", SFST(PCFP))
Return(PCFP)
}
Default {
Printf(" Unknown Input Command: %o", SFST(ICMD))
Return(NV_ERROR_UNSUPPORTED)
}
}
}
Default {
Printf(" Unsupported function: %o", SFST(Arg0))
Return(NVPCF_ERROR_UNSUPPORTED)
}
}
}

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@@ -1,120 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
//TODO: evaluate sleeps
OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
Field (PCIC, DwordAcc, NoLock, Preserve) {
Offset (0x40),
SSID, 32, // Subsystem vendor and product ID
}
// Enter GC6
Method(GC6I, 0, Serialized) {
Printf(" GPU GC6I START")
// Enter L23
^^DL23()
Sleep(5)
// Put GPU into reset
Printf(" Put GPU into reset")
CTXS(DGPU_RST_N)
Sleep(5)
Printf(" GPU GC6I FINISH")
}
// Exit GC6
Method(GC6O, 0, Serialized) {
Printf(" GPU GC6O START")
// Bring GPU out of reset
Printf(" Bring GPU out of reset")
STXS(DGPU_RST_N)
Sleep(5)
// Exit L23
^^L23D()
Sleep(5)
Printf(" GPU GC6O FINISH")
}
Method (_ON, 0, Serialized) {
Printf(" GPU _ON START")
If (DFEN == JT_DFGC_DEFER) {
Switch (ToInteger(DFCO)) {
Case (JT_GPC_XGXS) {
Printf(" Exit GC6 and stop self-refresh")
GC6O()
}
Default {
Printf(" Unsupported DFCO: %o", SFST(DFCO))
}
}
DFEN = JT_DFGC_NONE
} Else {
Printf(" Standard RTD3 power on")
STXS(DGPU_PWR_EN)
Sleep(5)
GC6O()
}
Printf(" GPU _ON FINISH")
}
Method (_OFF, 0, Serialized) {
Printf(" GPU _OFF START")
If (DFEN == JT_DFGC_DEFER) {
Switch (ToInteger(DFCI)) {
Case (JT_GPC_EGNS) {
Printf(" Enter GC6 without self-refresh")
GC6I()
}
Case (JT_GPC_EGIS) {
Printf(" Enter GC6 with self-refresh")
GC6I()
}
Default {
Printf(" Unsupported DFCI: %o", SFST(DFCI))
}
}
DFEN = JT_DFGC_NONE
} Else {
Printf(" Standard RTD3 power off")
GC6I()
CTXS(DGPU_PWR_EN)
Sleep(5)
}
Printf(" GPU _OFF FINISH")
}
// Main power resource
PowerResource (PWRR, 0, 0) {
Name (_STA, 1)
Method (_ON, 0, Serialized) {
Printf("GPU PWRR._ON")
// Restore SSID
^^SSID = DGPU_SSID
Printf(" Restore SSID: %o", SFST(^^SSID))
_STA = 1
}
Method (_OFF, 0, Serialized) {
Printf("GPU PWRR._OFF")
_STA = 0
}
}
// Power resources for entering D0
Name (_PR0, Package () { PWRR })
// Power resources for entering D3
Name (_PR3, Package () { PWRR })

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@@ -1,63 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
// Convert a byte to a hex string, trimming extra parts
Method (BHEX, 1) {
Local0 = ToHexString(Arg0)
Return (Mid(Local0, SizeOf(Local0) - 2, 2))
}
// UUID to string
Method (IDST, 1) {
Local0 = ""
Fprintf(
Local0,
"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
BHEX(DerefOf(Arg0[3])),
BHEX(DerefOf(Arg0[2])),
BHEX(DerefOf(Arg0[1])),
BHEX(DerefOf(Arg0[0])),
BHEX(DerefOf(Arg0[5])),
BHEX(DerefOf(Arg0[4])),
BHEX(DerefOf(Arg0[7])),
BHEX(DerefOf(Arg0[6])),
BHEX(DerefOf(Arg0[8])),
BHEX(DerefOf(Arg0[9])),
BHEX(DerefOf(Arg0[10])),
BHEX(DerefOf(Arg0[11])),
BHEX(DerefOf(Arg0[12])),
BHEX(DerefOf(Arg0[13])),
BHEX(DerefOf(Arg0[14])),
BHEX(DerefOf(Arg0[15]))
)
Return (Local0)
}
// Safe hex conversion, checks type first
Method (SFST, 1) {
Local0 = ObjectType(Arg0)
If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
Return (ToHexString(Arg0))
} Else {
Return (Concatenate("Type: ", Arg0))
}
}
// Convert from 4-byte buffer to 32-bit integer
Method (BTOI, 1) {
Return(
DerefOf(Arg0[0]) |
(DerefOf(Arg0[1]) << 8) |
(DerefOf(Arg0[2]) << 16) |
(DerefOf(Arg0[3]) << 24)
)
}
// Convert from 32-bit integer to 4-byte buffer
Method (ITOB, 1) {
Local0 = Buffer(4) { 0, 0, 0, 0 }
Local0[0] = Arg0 & 0xFF
Local0[1] = (Arg0 >> 8) & 0xFF
Local0[2] = (Arg0 >> 16) & 0xFF
Local0[3] = (Arg0 >> 24) & 0xFF
Return (Local0)
}

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@@ -1,140 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* NVIDIA GC6 on (TGL and ADL) (CPU and PCH) PCIe ports */
// Port mapped PCI express config space
OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
Field (PCIC, AnyAcc, NoLock, Preserve) {
Offset(0x52), /* LSTS - Link Status Register */
, 13,
LASX, 1, /* 0, Link Active Status */
Offset(0x60), /* RSTS - Root Status Register */
, 16,
PSPX, 1, /* 16, PME Status */
Offset(0xD8), /* 0xD8, MPC - Miscellaneous Port Configuration Register */
, 30,
HPEX, 1, /* 30, Hot Plug SCI Enable */
PMEX, 1, /* 31, Power Management SCI Enable */
Offset (0xE0), /* 0xE0, SPR - Scratch Pad Register */
SCB0, 1, /* Scratch bit 0 */
Offset(0xE2), /* 0xE2, RPPGEN - Root Port Power Gating Enable */
, 2,
L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */
L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */
}
Field (PCIC, AnyAcc, NoLock, WriteAsZeros) {
Offset(0xDC), /* 0xDC, SMSCS - SMI/SCI Status Register */
, 30,
HPSX, 1, /* 30, Hot Plug SCI Status */
PMSX, 1 /* 31, Power Management SCI Status */
}
// Enter L23
Method (DL23, 0, Serialized) {
Printf(" GPU PORT DL23 START")
L23E = 1
Sleep (16)
Local0 = 0
While (L23E) {
If ((Local0 > 4)) {
Break
}
Sleep (16)
Local0++
}
SCB0 = 1
Printf(" GPU PORT DL23 FINISH")
}
// Exit L23
Method (L23D, 0, Serialized) {
Printf(" GPU PORT L23D START")
If ((SCB0 == 1)) {
L23R = 1
Local0 = 0
While (L23R) {
If ((Local0 > 4)) {
Break
}
Sleep (16)
Local0++
}
SCB0 = 0
Local0 = 0
While ((LASX == 0)) {
If ((Local0 > 8)) {
Break
}
Sleep (16)
Local0++
}
}
Printf(" GPU PORT L23D FINISH")
}
Method (HPME, 0, Serialized) {
Printf(" GPU PORT HPME START")
If (PMSX == 1) {
Printf(" Notify GPU driver of PME SCI")
Notify(DEV0, 0x2)
Printf(" Clear PME SCI")
PMSX = 1
Printf(" Consume PME notification")
PSPX = 1
}
Printf(" GPU PORT HPME FINISH")
}
// Main power resource
PowerResource (PWRR, 0, 0) {
Name (_STA, 1)
Method (_ON, 0, Serialized) {
Printf("GPU PORT PWRR._ON")
HPME();
If (PMEX == 1) {
Printf(" Disable power management SCI")
PMEX = 0
}
^^DEV0._ON()
_STA = 1
}
Method (_OFF, 0, Serialized) {
Printf("GPU PORT PWRR._OFF")
^^DEV0._OFF()
If (PMEX == 0) {
Printf(" Enable power management SCI")
PMEX = 1
HPME()
}
_STA = 0
}
}
// Power resources for entering D0
Name (_PR0, Package () { PWRR })
// Power resources for entering D3
Name (_PR3, Package () { PWRR })
#include "common/gpu.asl"

View File

@@ -1,10 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_
#define _DRIVERS_GFX_NVIDIA_CHIP_H_
struct drivers_gfx_nvidia_config {
/* TODO: Set GPIOs in devicetree? */
};
#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */

View File

@@ -1,19 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_
#define _DRIVERS_GFX_NVIDIA_GPU_H_
#include <stdbool.h>
struct nvidia_gpu_config {
/* GPIO for GPU_PWR_EN */
unsigned int power_gpio;
/* GPIO for GPU_RST# */
unsigned int reset_gpio;
/* Enable or disable GPU power */
bool enable;
};
void nvidia_set_power(const struct nvidia_gpu_config *config);
#endif /* _DRIVERS_NVIDIA_GPU_H_ */

View File

@@ -1,71 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include "chip.h"
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40
static void nvidia_read_resources(struct device *dev)
{
printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev));
pci_dev_read_resources(dev);
// Find all BARs on GPU, mark them above 4g if prefetchable
for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
struct resource *res = probe_resource(dev, bar);
if (res) {
if (res->flags & IORESOURCE_PREFETCH) {
printk(BIOS_INFO, " BAR at 0x%02x marked above 4g\n", bar);
res->flags |= IORESOURCE_ABOVE_4G;
} else {
printk(BIOS_DEBUG, " BAR at 0x%02x not prefetch\n", bar);
}
} else {
printk(BIOS_DEBUG, " BAR at 0x%02x not found\n", bar);
}
}
}
static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
{
pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations nvidia_device_ops_pci = {
.set_subsystem = nvidia_set_subsystem,
};
static struct device_operations nvidia_device_ops = {
.read_resources = nvidia_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = pci_rom_write_acpi_tables,
.acpi_fill_ssdt = pci_rom_ssdt,
#endif
.init = pci_dev_init,
.ops_pci = &nvidia_device_ops_pci,
};
static void nvidia_enable(struct device *dev)
{
if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
return;
if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_NVIDIA)
return;
dev->ops = &nvidia_device_ops;
}
struct chip_operations drivers_gfx_nvidia_ops = {
.name = "NVIDIA Optimus Graphics Device",
.enable_dev = nvidia_enable
};

View File

@@ -1,33 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <gpio.h>
#include "chip.h"
#include "gpu.h"
void nvidia_set_power(const struct nvidia_gpu_config *config)
{
if (!config->power_gpio || !config->reset_gpio) {
printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__);
return;
}
printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio);
printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio);
gpio_set(config->reset_gpio, 0);
mdelay(10);
if (config->enable) {
gpio_set(config->power_gpio, 1);
mdelay(25);
gpio_set(config->reset_gpio, 1);
} else {
gpio_set(config->power_gpio, 0);
}
mdelay(10);
}

View File

@@ -1,4 +0,0 @@
config DRIVERS_INTEL_DTBT
def_bool n
help
Support for discrete Thunderbolt controllers

View File

@@ -1,3 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
ramstage-$(CONFIG_DRIVERS_INTEL_DTBT) += dtbt.c

View File

@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _DRIVERS_INTEL_DTBT_CHIP_H_
#define _DRIVERS_INTEL_DTBT_CHIP_H_
struct drivers_intel_dtbt_config {};
#endif /* _DRIVERS_INTEL_DTBT_CHIP_H_ */

View File

@@ -1,199 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include "chip.h"
#include <acpi/acpigen.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
#include <timer.h>
#define PCIE2TBT 0x54C
#define PCIE2TBT_VALID BIT(0)
#define PCIE2TBT_GO2SX 2
#define PCIE2TBT_GO2SX_NO_WAKE 3
#define PCIE2TBT_SX_EXIT_TBT_CONNECTED 4
#define PCIE2TBT_OS_UP 6
#define PCIE2TBT_SET_SECURITY_LEVEL 8
#define PCIE2TBT_GET_SECURITY_LEVEL 9
#define PCIE2TBT_BOOT_ON 24
#define PCIE2TBT_USB_ON 25
#define PCIE2TBT_GET_ENUMERATION_METHOD 26
#define PCIE2TBT_SET_ENUMERATION_METHOD 27
#define PCIE2TBT_POWER_CYCLE 28
#define PCIE2TBT_SX_START 29
#define PCIE2TBT_ACL_BOOT 30
#define PCIE2TBT_CONNECT_TOPOLOGY 31
#define TBT2PCIE 0x548
#define TBT2PCIE_DONE BIT(0)
// Default timeout for mailbox commands unless otherwise specified.
#define TIMEOUT_MS 1000
// Default timeout for controller to ack GO2SX/GO2SX_NO_WAKE mailbox command.
#define GO2SX_TIMEOUT_MS 600
static void dtbt_cmd(struct device *dev, u32 command, u32 data, u32 timeout)
{
u32 reg = (data << 8) | (command << 1) | PCIE2TBT_VALID;
u32 status;
printk(BIOS_DEBUG, "dTBT send command %08x\n", command);
pci_write_config32(dev, PCIE2TBT, reg);
if (!wait_ms(timeout, (status = pci_read_config32(dev, TBT2PCIE)) & TBT2PCIE_DONE)) {
printk(BIOS_ERR, "dTBT command %08x send timeout %08x\n", command, status);
}
pci_write_config32(dev, PCIE2TBT, 0);
if (!wait_ms(timeout, !(pci_read_config32(dev, TBT2PCIE) & TBT2PCIE_DONE))) {
printk(BIOS_ERR, "dTBT command %08x clear timeout\n", command);
}
}
static void dtbt_write_dsd(void)
{
struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
acpi_device_add_hotplug_support_in_d3(dsd);
acpi_device_add_external_facing_port(dsd);
acpi_dp_write(dsd);
}
static void dtbt_write_opregion(const struct bus *bus)
{
uintptr_t mmconf_base = (uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS
+ (((uintptr_t)(bus->secondary)) << 20);
const struct opregion opregion = OPREGION("PXCS", SYSTEMMEMORY, mmconf_base, 0x1000);
const struct fieldlist fieldlist[] = {
FIELDLIST_OFFSET(TBT2PCIE),
FIELDLIST_NAMESTR("TB2P", 32),
FIELDLIST_OFFSET(PCIE2TBT),
FIELDLIST_NAMESTR("P2TB", 32),
};
acpigen_write_opregion(&opregion);
acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist),
FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE);
}
static void dtbt_fill_ssdt(const struct device *dev)
{
struct bus *bus;
struct device *parent;
const char *parent_scope;
const char *dev_name = acpi_device_name(dev);
bus = dev->upstream;
if (!bus) {
printk(BIOS_ERR, "dTBT bus invalid\n");
return;
}
parent = bus->dev;
if (!parent || parent->path.type != DEVICE_PATH_PCI) {
printk(BIOS_ERR, "dTBT parent invalid\n");
return;
}
parent_scope = acpi_device_path(parent);
if (!parent_scope) {
printk(BIOS_ERR, "dTBT parent scope not valid\n");
return;
}
/* Scope */
acpigen_write_scope(parent_scope);
dtbt_write_dsd();
/* Device */
acpigen_write_device(dev_name);
acpigen_write_name_integer("_ADR", 0);
dtbt_write_opregion(bus);
/* Method */
acpigen_write_method_serialized("PTS", 0);
acpigen_write_debug_string("dTBT prepare to sleep");
acpigen_write_store_int_to_namestr(PCIE2TBT_GO2SX_NO_WAKE << 1, "P2TB");
acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", PCIE2TBT_GO2SX_NO_WAKE << 1);
acpigen_write_debug_namestr("TB2P");
acpigen_write_store_int_to_namestr(0, "P2TB");
acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", 0);
acpigen_write_debug_namestr("TB2P");
acpigen_write_method_end();
acpigen_write_device_end();
acpigen_write_scope_end();
printk(BIOS_DEBUG, "dTBT fill SSDT\n");
printk(BIOS_DEBUG, " Dev %s\n", dev_path(dev));
//printk(BIOS_DEBUG, " Bus %s\n", bus_path(bus));
printk(BIOS_DEBUG, " Parent %s\n", dev_path(parent));
printk(BIOS_DEBUG, " Scope %s\n", parent_scope);
printk(BIOS_DEBUG, " Device %s\n", dev_name);
// \.TBTS Method
acpigen_write_scope("\\");
acpigen_write_method("TBTS", 0);
acpigen_emit_namestring(acpi_device_path_join(dev, "PTS"));
acpigen_write_method_end();
acpigen_write_scope_end();
}
static const char *dtbt_acpi_name(const struct device *dev)
{
return "DTBT";
}
static struct pci_operations dtbt_device_ops_pci = {
.set_subsystem = 0,
};
static struct device_operations dtbt_device_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.acpi_fill_ssdt = dtbt_fill_ssdt,
.acpi_name = dtbt_acpi_name,
.scan_bus = pciexp_scan_bridge,
.reset_bus = pci_bus_reset,
.ops_pci = &dtbt_device_ops_pci,
};
static void dtbt_enable(struct device *dev)
{
if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
return;
if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_INTEL)
return;
// TODO: check device ID
dev->ops = &dtbt_device_ops;
printk(BIOS_INFO, "dTBT controller found at %s\n", dev_path(dev));
// XXX: Recommendation is to set SL1 ("User Authorization")
printk(BIOS_DEBUG, "dTBT set security level SL0\n");
dtbt_cmd(dev, PCIE2TBT_SET_SECURITY_LEVEL, 0, TIMEOUT_MS);
// XXX: Must verify change or rollback all controllers
if (acpi_is_wakeup_s3()) {
printk(BIOS_DEBUG, "dTBT SX exit\n");
dtbt_cmd(dev, PCIE2TBT_SX_EXIT_TBT_CONNECTED, 0, TIMEOUT_MS);
// TODO: "wait for fast link bring-up" loop (timeout: 5s)
} else {
printk(BIOS_DEBUG, "dTBT boot on\n");
dtbt_cmd(dev, PCIE2TBT_BOOT_ON, 0, TIMEOUT_MS);
}
}
struct chip_operations drivers_intel_dtbt_ops = {
.name = "Intel Discrete Thunderbolt",
.enable_dev = dtbt_enable,
};

View File

@@ -15,11 +15,6 @@ config EC_SYSTEM76_EC_DGPU
bool
default n
config EC_SYSTEM76_EC_LOCKDOWN
depends on EC_SYSTEM76_EC
bool
default n
config EC_SYSTEM76_EC_OLED
depends on EC_SYSTEM76_EC
bool

View File

@@ -4,7 +4,6 @@ ifeq ($(CONFIG_EC_SYSTEM76_EC),y)
all-y += system76_ec.c
ramstage-y += smbios.c
ramstage-$(CONFIG_EC_SYSTEM76_EC_LOCKDOWN) += lockdown.c
smm-$(CONFIG_DEBUG_SMI) += system76_ec.c

View File

@@ -1,59 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include "system76_ec.h"
#include <bootstate.h>
#include <commonlib/region.h>
#include <fmap.h>
#include <spi_flash.h>
static int protect_region_by_name(const char *name)
{
int res;
struct region region;
res = fmap_locate_area(name, &region);
if (res < 0) {
printk(BIOS_ERR, "fmap_locate_area '%s' failed: %d\n", name, res);
return res;
}
res = spi_flash_ctrlr_protect_region(
boot_device_spi_flash(),
&region,
WRITE_PROTECT
);
if (res < 0) {
printk(BIOS_ERR, "spi_flash_ctrlr_protect_region '%s' failed: %d\n", name, res);
return res;
}
printk(BIOS_INFO, "protected '%s'\n", name);
return 0;
}
static void lock(void *unused)
{
uint8_t state = SYSTEM76_EC_SECURITY_STATE_UNLOCK;
if (!system76_ec_security_get(&state)) {
printk(BIOS_INFO, "failed to get security state, assuming unlocked\n");
state = SYSTEM76_EC_SECURITY_STATE_UNLOCK;
}
printk(BIOS_INFO, "security state: %d\n", state);
if (state != SYSTEM76_EC_SECURITY_STATE_UNLOCK) {
// Protect WP_RO region, which should contain FMAP and COREBOOT
protect_region_by_name("WP_RO");
// Protect RW_MRC_CACHE region, this must be done after it is written
protect_region_by_name("RW_MRC_CACHE");
//TODO: protect entire flash except when in SMM?
}
}
/*
* Keep in sync with mrc_cache.c
*/
#if CONFIG(MRC_WRITE_NV_LATE)
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, lock, NULL);
#else
BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, lock, NULL);
#endif

View File

@@ -26,9 +26,6 @@
#define CMD_PRINT_REG_LEN 3
#define CMD_PRINT_REG_DATA 4
// Get security state command
#define CMD_SECURITY_GET 20
static inline uint8_t system76_ec_read(uint8_t addr)
{
return inb(SYSTEM76_EC_BASE + (uint16_t)addr);
@@ -113,9 +110,3 @@ bool system76_ec_cmd(uint8_t cmd, const uint8_t *request_data,
return ret;
}
bool system76_ec_security_get(uint8_t *state)
{
*state = SYSTEM76_EC_SECURITY_STATE_LOCK;
return system76_ec_cmd(CMD_SECURITY_GET, NULL, 0, state, sizeof(*state));
}

View File

@@ -6,15 +6,6 @@
#include <stdbool.h>
#include <stdint.h>
// Default value, flashing is prevented, cannot be set with CMD_SECURITY_SET
#define SYSTEM76_EC_SECURITY_STATE_LOCK 0
// Flashing is allowed, cannot be set with CMD_SECURITY_SET
#define SYSTEM76_EC_SECURITY_STATE_UNLOCK 1
// Flashing will be prevented on the next reboot
#define SYSTEM76_EC_SECURITY_STATE_PREPARE_LOCK 2
// Flashing will be allowed on the next reboot
#define SYSTEM76_EC_SECURITY_STATE_PREPARE_UNLOCK 3
/*
* Send a command to the EC. request_data/request_size are the request payload,
* request_data can be NULL if request_size is 0. reply_data/reply_size are
@@ -23,6 +14,4 @@
bool system76_ec_cmd(uint8_t cmd, const uint8_t *request_data,
uint8_t request_size, uint8_t *reply_data, uint8_t reply_size);
bool system76_ec_security_get(uint8_t *state);
#endif

View File

@@ -36,18 +36,6 @@
#define DDR4_SPD_PART_OFF 329
#define DDR4_SPD_PART_LEN 20
#define DDR4_SPD_SN_OFF 325
#define MAX_SPD_PAGE_SIZE_SPD5 128
#define MAX_SPD_SIZE (SPD_PAGE_LEN * 4)
#define SPD_HUB_MEMREG(addr) ((u8)(0x80 | (addr)))
#define SPD5_MR11 0x0B
#define SPD5_MR0 0x00
#define SPD5_MEMREG_REG(addr) ((u8)((~0x80) & (addr)))
#define SPD5_MR0_SPD5_HUB_DEV 0x51
struct spd_offset_table {
u16 start; /* Offset 0 */
u16 end; /* Offset 2 */
};
struct spd_block {
u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */

View File

@@ -209,9 +209,7 @@ enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk)
dram_type = *(spd_cache + SC_SPD_OFFSET(i) + SPD_DRAM_TYPE);
if (dram_type == SPD_DRAM_DDR5)
blk->len = CONFIG_DIMM_SPD_SIZE;
else if (dram_type == SPD_DRAM_DDR4)
if (dram_type == SPD_DRAM_DDR4)
blk->len = SPD_PAGE_LEN_DDR4;
else
blk->len = SPD_PAGE_LEN;

View File

@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_16384
select DRIVERS_GENERIC_CBFS_SERIAL
select DRIVERS_GENERIC_CBFS_UUID
select DRIVERS_GFX_NVIDIA
select DRIVERS_I2C_HID
select DRIVERS_I2C_TAS5825M
select EC_SYSTEM76_EC

View File

@@ -1,6 +1,6 @@
## SPDX-License-Identifier: GPL-2.0-only
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
bootblock-y += bootblock.c
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

View File

@@ -1,19 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <variant/gpio.h>
#define EC_GPE_SCI 0x03 /* GPP_K3 */
#define EC_GPE_SWI 0x06 /* GPP_K6 */
#include <ec/system76/ec/acpi/ec.asl>
Scope (\_SB) {
#include "sleep.asl"
Scope (PCI0) {
Device (PEGP) {
Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
}
}
}
Scope (\_GPE) {

View File

@@ -58,12 +58,6 @@ chip soc/intel/cannonlake
# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
register "PcieClkSrcUsage[8]" = "0x40"
register "PcieClkSrcClkReq[8]" = "8"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
device pci 00.2 on end # USB xHCI Host controller
device pci 00.3 on end # USB Type-C UCSI controller
end
end
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on # SA Thermal device

View File

@@ -3,16 +3,7 @@
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_F8
#define DGPU_PWR_EN GPP_F9
#define DGPU_GC6 GPP_K11
#define DGPU_SSID 0x50151558
#ifndef __ACPI__
void variant_configure_early_gpios(void);
void variant_configure_gpios(void);
#endif
#endif

View File

@@ -1,9 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
static const struct cnl_mb_cfg memcfg = {
.spd[0] = {
@@ -22,17 +20,5 @@ static const struct cnl_mb_cfg memcfg = {
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
const struct nvidia_gpu_config config = {
.power_gpio = DGPU_PWR_EN,
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
memupd->FspmConfig.PrimaryDisplay = 0;
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
}

View File

@@ -1,18 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_F22
#define DGPU_PWR_EN GPP_F23
#define DGPU_GC6 GPP_C12
#define DGPU_SSID 0x65d11558
#ifndef __ACPI__
void variant_configure_early_gpios(void);
void variant_configure_gpios(void);
#endif
#endif

View File

@@ -1,18 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_F22
#define DGPU_PWR_EN GPP_F23
#define DGPU_GC6 GPP_C12
#define DGPU_SSID 0x65e11558
#ifndef __ACPI__
void variant_configure_early_gpios(void);
void variant_configure_gpios(void);
#endif
#endif

View File

@@ -10,7 +10,6 @@ config BOARD_SYSTEM76_ADL_COMMON
select DRIVERS_INTEL_PMC
select DRIVERS_INTEL_USB4_RETIMER
select EC_SYSTEM76_EC
select EC_SYSTEM76_EC_LOCKDOWN
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
@@ -36,12 +35,10 @@ config BOARD_SYSTEM76_GALP6
config BOARD_SYSTEM76_GAZE17_3050
select BOARD_SYSTEM76_ADL_COMMON
select DRIVERS_GFX_NVIDIA
select EC_SYSTEM76_EC_DGPU
config BOARD_SYSTEM76_GAZE17_3060_B
select BOARD_SYSTEM76_ADL_COMMON
select DRIVERS_GFX_NVIDIA
select EC_SYSTEM76_EC_DGPU
select MAINBOARD_USES_IFD_GBE_REGION
@@ -51,15 +48,11 @@ config BOARD_SYSTEM76_LEMP11
config BOARD_SYSTEM76_ORYP9
select BOARD_SYSTEM76_ADL_COMMON
select DRIVERS_GFX_NVIDIA
select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
select DRIVERS_I2C_TAS5825M
select EC_SYSTEM76_EC_DGPU
config BOARD_SYSTEM76_ORYP10
select BOARD_SYSTEM76_ADL_COMMON
select DRIVERS_GFX_NVIDIA
select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
select EC_SYSTEM76_EC_DGPU
if BOARD_SYSTEM76_ADL_COMMON
@@ -104,22 +97,12 @@ config MAINBOARD_VERSION
default "oryp9" if BOARD_SYSTEM76_ORYP9
default "oryp10" if BOARD_SYSTEM76_ORYP10
config CMOS_DEFAULT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/cmos-csme.default" if BOARD_SYSTEM76_DARP8
default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
config CONSOLE_POST
default y
config D3COLD_SUPPORT
default n
config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
default 45 if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
default 25 if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"

View File

@@ -2,10 +2,6 @@
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
ifeq ($(CONFIG_DRIVERS_GFX_NVIDIA),y)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
endif
bootblock-y += bootblock.c
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

View File

@@ -1,9 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#if CONFIG(DRIVERS_GFX_NVIDIA)
#include <variant/gpio.h>
#endif
#define EC_GPE_SCI 0x6E
#define EC_GPE_SWI 0x6B
#include <ec/system76/ec/acpi/ec.asl>
@@ -12,11 +8,5 @@ Scope (\_SB) {
#include "sleep.asl"
Scope (PCI0) {
#include "backlight.asl"
#if CONFIG(DRIVERS_GFX_NVIDIA)
Scope (PEG2) {
#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
}
#endif
}
}

View File

@@ -1,3 +0,0 @@
boot_option=Fallback
debug_level=Debug
me_state=Enable

View File

@@ -1,8 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
chip soc/intel/alderlake
register "s0ix_enable" = "1"
register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
.tdp_pl1_override = 20,
.tdp_pl2_override = 56,

View File

@@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_B2
#define DGPU_PWR_EN GPP_A14
#define DGPU_GC6 GPP_F13
#define DGPU_SSID 0x866d1558
#endif

View File

@@ -40,10 +40,6 @@ chip soc/intel/alderlake
.clk_req = 3,
.flags = PCIE_RP_LTR,
}"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
end
end
device ref pcie4_0 on
# PCIe PEG0 x4, Clock 0 (SSD2)

View File

@@ -1,9 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
@@ -19,14 +17,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
};
const bool half_populated = false;
const struct nvidia_gpu_config config = {
.power_gpio = DGPU_PWR_EN,
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;

View File

@@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_B2
#define DGPU_PWR_EN GPP_A14
#define DGPU_GC6 GPP_F13
#define DGPU_SSID 0x867c1558
#endif

View File

@@ -40,10 +40,6 @@ chip soc/intel/alderlake
.clk_req = 3,
.flags = PCIE_RP_LTR,
}"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
end
end
device ref igpu on
# DDIA is eDP

View File

@@ -1,9 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
@@ -19,14 +17,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
};
const bool half_populated = false;
const struct nvidia_gpu_config config = {
.power_gpio = DGPU_PWR_EN,
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;

View File

@@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_B2
#define DGPU_PWR_EN GPP_A14
#define DGPU_GC6 GPP_A7
#define DGPU_SSID 0x65f51558
#endif

View File

@@ -25,10 +25,6 @@ chip soc/intel/alderlake
.clk_req = 3,
.flags = PCIE_RP_LTR,
}"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
end
end
device ref igpu on
register "ddi_portA_config" = "1"

View File

@@ -1,9 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
@@ -22,14 +20,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
};
const bool half_populated = false;
const struct nvidia_gpu_config config = {
.power_gpio = DGPU_PWR_EN,
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;

View File

@@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_B2
#define DGPU_PWR_EN GPP_A14
#define DGPU_GC6 GPP_A7
#define DGPU_SSID 0x65f51558
#endif

View File

@@ -25,10 +25,6 @@ chip soc/intel/alderlake
.clk_req = 3,
.flags = PCIE_RP_LTR,
}"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
end
end
device ref igpu on
register "ddi_portA_config" = "1"

View File

@@ -1,9 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
@@ -19,14 +17,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
};
const bool half_populated = false;
const struct nvidia_gpu_config config = {
.power_gpio = DGPU_PWR_EN,
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;

View File

@@ -7,9 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_16384
select DRIVERS_GENERIC_CBFS_SERIAL
select DRIVERS_GENERIC_CBFS_UUID
select DRIVERS_GFX_NVIDIA
select DRIVERS_I2C_HID
select DRIVERS_I2C_TAS5825M
select EC_SYSTEM76_EC
select EC_SYSTEM76_EC_DGPU
select HAVE_ACPI_RESUME

View File

@@ -10,4 +10,3 @@ romstage-y += romstage.c
ramstage-y += ramstage.c
ramstage-y += gpio.c
ramstage-y += hda_verb.c
ramstage-y += tas5825m.c

View File

@@ -61,12 +61,11 @@ chip soc/intel/cannonlake
# PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU)
register "PcieClkSrcUsage[7]" = "0x40"
register "PcieClkSrcClkReq[7]" = "7"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
device pci 00.2 on end # USB xHCI Host controller
device pci 00.3 on end # USB Type-C UCSI controller
end
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
device pci 00.2 on end # USB xHCI Host controller
device pci 00.3 on end # USB Type-C UCSI controller
end
# TODO: is this enough to disable iGPU?
device pci 02.0 off end # Integrated Graphics Device
@@ -222,16 +221,7 @@ chip soc/intel/cannonlake
device pci 1f.3 on # Intel HDA
register "PchHdaAudioLinkHda" = "1"
end
device pci 1f.4 on # SMBus
chip drivers/i2c/tas5825m
register "id" = "0"
device i2c 4e on end # (8bit address: 0x9c)
end
chip drivers/i2c/tas5825m
register "id" = "1"
device i2c 4f on end # (8bit address: 0x9e)
end
end
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE
end

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

View File

@@ -1,15 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/i2c/tas5825m/tas5825m.h>
#include "tas5825m-normal.c"
#include "tas5825m-sub.c"
int tas5825m_setup(struct device *dev, int id)
{
if (id == 0)
return tas5825m_setup_normal(dev);
if (id == 1)
return tas5825m_setup_sub(dev);
return -1;
}

View File

@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_16384
select DRIVERS_GENERIC_CBFS_SERIAL
select DRIVERS_GENERIC_CBFS_UUID
select DRIVERS_GFX_NVIDIA
select DRIVERS_I2C_HID
select EC_SYSTEM76_EC
select EC_SYSTEM76_EC_DGPU

View File

@@ -1,6 +1,6 @@
## SPDX-License-Identifier: GPL-2.0-only
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
bootblock-y += bootblock.c
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

View File

@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <variant/gpio.h>
#define EC_GPE_SCI 0x03 /* GPP_K3 */
#define EC_GPE_SWI 0x06 /* GPP_K6 */
#include <ec/system76/ec/acpi/ec.asl>
@@ -10,10 +8,6 @@ Scope (\_SB) {
#include "sleep.asl"
Scope (PCI0) {
#include "backlight.asl"
Device (PEGP) {
Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
}
}
}

View File

@@ -57,12 +57,6 @@ chip soc/intel/cannonlake
# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
register "PcieClkSrcUsage[8]" = "0x40"
register "PcieClkSrcClkReq[8]" = "8"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
device pci 00.2 on end # USB xHCI Host controller
device pci 00.3 on end # USB Type-C UCSI controller
end
end
device pci 02.0 on # Integrated Graphics Device
register "gfx" = "GMA_DEFAULT_PANEL(0)"

View File

@@ -3,16 +3,7 @@
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_F8
#define DGPU_PWR_EN GPP_F9
#define DGPU_GC6 GPP_K11
#define DGPU_SSID 0x50e11558
#ifndef __ACPI__
void variant_configure_early_gpios(void);
void variant_configure_gpios(void);
#endif
#endif

View File

@@ -1,9 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
static const struct cnl_mb_cfg memcfg = {
.spd[0] = {
@@ -22,17 +20,5 @@ static const struct cnl_mb_cfg memcfg = {
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
const struct nvidia_gpu_config config = {
.power_gpio = DGPU_PWR_EN,
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
memupd->FspmConfig.PrimaryDisplay = 0;
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
}

View File

@@ -1,18 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_F22
#define DGPU_PWR_EN GPP_F23
#define DGPU_GC6 GPP_K21
#define DGPU_SSID 0x85501558
#ifndef __ACPI__
void variant_configure_early_gpios(void);
void variant_configure_gpios(void);
#endif
#endif

View File

@@ -8,7 +8,6 @@ config BOARD_SYSTEM76_MTL_COMMON
select DRIVERS_GENERIC_CBFS_UUID
select DRIVERS_I2C_HID
select EC_SYSTEM76_EC
select EC_SYSTEM76_EC_LOCKDOWN
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
@@ -38,20 +37,6 @@ config BOARD_SYSTEM76_DARP10_B
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
select SOC_INTEL_METEORLAKE_U_H
config BOARD_SYSTEM76_LEMP13
select BOARD_SYSTEM76_MTL_COMMON
select DRIVERS_I2C_TAS5825M
select HAVE_SPD_IN_CBFS
select SOC_INTEL_METEORLAKE_U_H
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config BOARD_SYSTEM76_LEMP13_B
select BOARD_SYSTEM76_MTL_COMMON
select DRIVERS_I2C_TAS5825M
select HAVE_SPD_IN_CBFS
select SOC_INTEL_METEORLAKE_U_H
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
if BOARD_SYSTEM76_MTL_COMMON
config MAINBOARD_DIR
@@ -59,7 +44,6 @@ config MAINBOARD_DIR
config VARIANT_DIR
default "darp10" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B
default "lemp13" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
@@ -67,18 +51,13 @@ config OVERRIDE_DEVICETREE
config MAINBOARD_PART_NUMBER
default "darp10" if BOARD_SYSTEM76_DARP10
default "darp10-b" if BOARD_SYSTEM76_DARP10_B
default "lemp13" if BOARD_SYSTEM76_LEMP13
default "lemp13-b" if BOARD_SYSTEM76_LEMP13_B
config MAINBOARD_SMBIOS_PRODUCT_NAME
default "Darter Pro" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B
default "Lemur Pro" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B
config MAINBOARD_VERSION
default "darp10" if BOARD_SYSTEM76_DARP10
default "darp10-b" if BOARD_SYSTEM76_DARP10_B
default "lemp13" if BOARD_SYSTEM76_LEMP13
default "lemp13-b" if BOARD_SYSTEM76_LEMP13_B
config CMOS_DEFAULT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"

View File

@@ -5,9 +5,3 @@ config BOARD_SYSTEM76_DARP10
config BOARD_SYSTEM76_DARP10_B
bool "darp10-b"
config BOARD_SYSTEM76_LEMP13
bool "lemp13"
config BOARD_SYSTEM76_LEMP13_B
bool "lemp13-b"

View File

@@ -12,5 +12,3 @@ ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
ramstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
SPD_SOURCES = samsung-M425R1GB4BB0-CQKOD

View File

@@ -28,7 +28,7 @@ chip soc/intel/meteorlake
[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
register "gfx" = "GMA_DEFAULT_PANEL(0)"
#register "gfx" = "GMA_DEFAULT_PANEL(0)"
end
device ref ioe_shared_sram on end
device ref pmc_shared_sram on end

View File

@@ -1,65 +0,0 @@
# Samsung M425R1GB4BB0-CQKOD
30 10 12 03 04 00 40 42 00 00 00 00 90 02 00 00
00 00 00 00 A0 01 F2 03 7A 0D 00 00 00 00 80 3E
80 3E 80 3E 00 7D 80 BB 30 75 27 01 A0 00 82 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 88 13 08 88 13 08 20 4E 20 10
27 10 1A 41 28 10 27 10 C4 09 04 4C 1D 0C 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
10 00 80 B3 80 21 80 B3 82 20 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 0F 01 02 81 00 22 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 09 D1
80 CE 00 00 00 00 00 00 00 4D 34 32 35 52 31 47
42 34 42 42 30 2D 43 51 4B 4F 44 20 20 20 20 20
20 20 20 20 20 20 20 00 80 CE 95 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

View File

@@ -1,12 +0,0 @@
FLASH 32M {
SI_DESC 16K
SI_ME 10128K
SI_BIOS@16M 16M {
RW_MRC_CACHE 64K
SMMSTORE(PRESERVE) 256K
WP_RO {
FMAP 4K
COREBOOT(CBFS)
}
}
}

View File

@@ -1,2 +0,0 @@
Board name: lemp13
Release year: 2024

View File

@@ -1,208 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0_EC
PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1_EC
PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC
PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC
PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC#
PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), // ESPI_CLK_EC
PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET#
PAD_NC(GPP_A07, NONE),
PAD_NC(GPP_A08, NONE),
PAD_NC(GPP_A09, NONE),
PAD_NC(GPP_A10, NONE),
PAD_CFG_GPO(GPP_A11, 0, PLTRST),
PAD_NC(GPP_A12, NONE),
PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST),
PAD_CFG_TERM_GPO(GPP_A14, 0, UP_20K, PLTRST),
PAD_CFG_TERM_GPO(GPP_A15, 0, UP_20K, PLTRST),
PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1),
PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
PAD_CFG_TERM_GPO(GPP_A18, 0, UP_20K, PLTRST),
PAD_CFG_TERM_GPO(GPP_A19, 0, UP_20K, DEEP),
PAD_CFG_TERM_GPO(GPP_A20, 0, NATIVE, DEEP),
PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1),
_PAD_CFG_STRUCT(GPP_B00, 0x40100100, 0x0000),
PAD_CFG_GPO(GPP_B01, 0, PLTRST),
PAD_CFG_GPO(GPP_B02, 0, PLTRST),
PAD_CFG_GPO(GPP_B03, 0, PLTRST),
PAD_CFG_GPO(GPP_B04, 0, PLTRST),
PAD_CFG_GPO(GPP_B05, 1, PLTRST),
PAD_CFG_GPO(GPP_B06, 0, DEEP),
PAD_CFG_GPO(GPP_B07, 1, DEEP),
PAD_CFG_GPO(GPP_B08, 1, DEEP),
PAD_CFG_GPI(GPP_B09, NONE, DEEP),
PAD_CFG_GPI(GPP_B10, NONE, DEEP),
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), // CPU_HDMI_HPD
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1),
PAD_CFG_GPO(GPP_B14, 0, PLTRST),
PAD_CFG_GPI(GPP_B15, NONE, DEEP),
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
PAD_CFG_GPO(GPP_B17, 1, PLTRST), // HDMI_EN
PAD_CFG_GPO(GPP_B18, 1, PLTRST),
PAD_CFG_GPO(GPP_B19, 1, PLTRST),
PAD_CFG_GPO(GPP_B20, 1, PLTRST),
PAD_CFG_GPO(GPP_B21, 0, PLTRST),
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
PAD_CFG_GPO(GPP_B23, 1, DEEP),
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK_DDR
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA_DDR
PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1), // GPP_C2_STRAP
PAD_CFG_NF(GPP_C03, UP_20K, DEEP, NF1), // SML0_CLK
PAD_CFG_NF(GPP_C04, UP_20K, DEEP, NF1), // SML0_DATA
PAD_CFG_NF(GPP_C05, UP_20K, DEEP, NF1), // GPP_C5_STRAP
PAD_CFG_NF(GPP_C06, UP_20K, DEEP, NF1), // TBT_I2C_SCL
PAD_CFG_NF(GPP_C07, UP_20K, DEEP, NF1), // TBT_I2C_SDA
PAD_CFG_NF(GPP_C08, NONE, DEEP, NF1), // GPP_C08_TEST
PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), // CARD_CLKREQ
PAD_CFG_GPO(GPP_C10, 0, PLTRST), // 5G_PCIE_CLKREQ
PAD_CFG_NF(GPP_C11, NONE, PWROK, NF1), // WLAN_CLKREQ
PAD_CFG_NF(GPP_C12, NONE, PWROK, NF1), // GPP_C13-TEST (typo from schematic)
PAD_CFG_GPO(GPP_C13, 1, DEEP),
PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), // GPP_C15
// GPP_C16 (TBTA_LSX0_TXD) configured by FSP
// GPP_C17 (TBTA_LSX0_RXD) configured by FSP
// GPP_C18 not connected
// GPP_C19 not connected
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF2), // HDMI_CTRLCLK
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF2), // HDMI_CTRLDATA
// GPP_C22 not connected
// GPP_C23 not connected
PAD_CFG_GPO(GPP_D00, 1, PLTRST),
PAD_CFG_GPO(GPP_D01, 1, PLTRST),
PAD_CFG_GPO(GPP_D02, 1, PLTRST),
PAD_NC(GPP_D03, NONE),
PAD_CFG_GPO(GPP_D04, 0, PLTRST),
PAD_CFG_GPO(GPP_D05, 1, PLTRST),
PAD_CFG_GPO(GPP_D06, 0, PLTRST),
PAD_CFG_GPO(GPP_D07, 0, PLTRST),
PAD_CFG_GPO(GPP_D08, 0, PLTRST),
PAD_CFG_GPO(GPP_D09, 0, PLTRST),
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
PAD_CFG_GPO(GPP_D14, 0, PLTRST),
PAD_CFG_GPO(GPP_D15, 0, PLTRST),
PAD_CFG_GPO(GPP_D16, 0, DEEP),
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
PAD_NC(GPP_D18, NONE), // GPP_D18-TEST
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // SSD2_CLKREQ
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // SSD1_CLKREQ
PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1),
PAD_CFG_GPO(GPP_E00, 0, PLTRST),
_PAD_CFG_STRUCT(GPP_E01, 0x40100100, 0x1000),
PAD_CFG_GPI(GPP_E02, NONE, DEEP),
PAD_NC(GPP_E03, NONE),
PAD_CFG_GPO(GPP_E04, 0, PLTRST),
PAD_CFG_GPO(GPP_E05, 0, PLTRST),
PAD_CFG_GPI(GPP_E06, NONE, DEEP),
PAD_CFG_GPO(GPP_E07, 0, PLTRST),
PAD_CFG_GPO(GPP_E08, 0, PLTRST),
PAD_CFG_GPI(GPP_E09, NONE, DEEP),
PAD_CFG_GPO(GPP_E10, 0, PLTRST),
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
_PAD_CFG_STRUCT(GPP_E12, 0x84002200, 0x0000),
_PAD_CFG_STRUCT(GPP_E13, 0x44002100, 0x0000),
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
PAD_CFG_GPO(GPP_E15, 0, PLTRST),
PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2),
PAD_CFG_GPO(GPP_E17, 0, PLTRST),
PAD_NC(GPP_E18, NONE),
PAD_NC(GPP_E19, NONE),
PAD_NC(GPP_E20, NONE),
PAD_NC(GPP_E21, NONE),
PAD_CFG_TERM_GPO(GPP_E22, 0, DN_20K, PLTRST),
PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3),
PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F07, DN_20K, DEEP, NF1),
PAD_CFG_NF(GPP_F08, DN_20K, DEEP, NF1),
PAD_CFG_GPI(GPP_F09, NONE, DEEP),
PAD_NC(GPP_F10, NONE),
PAD_CFG_GPO(GPP_F11, 0, PLTRST),
_PAD_CFG_STRUCT(GPP_F12, 0x44002300, 0x0000), // AMP_SMB_CLK
_PAD_CFG_STRUCT(GPP_F13, 0x44002300, 0x0000), // AMP_SMB_DATA
PAD_CFG_GPO(GPP_F14, 0, PLTRST),
PAD_CFG_GPO(GPP_F15, 0, PLTRST),
PAD_CFG_GPO(GPP_F16, 0, PLTRST),
PAD_CFG_GPO(GPP_F17, 0, PLTRST),
PAD_CFG_GPO(GPP_F18, 0, DEEP),
PAD_CFG_GPO(GPP_F19, 0, PLTRST),
PAD_CFG_GPO(GPP_F20, 0, PLTRST),
PAD_CFG_GPO(GPP_F21, 0, PLTRST),
PAD_CFG_GPO(GPP_F22, 0, PLTRST),
PAD_CFG_GPO(GPP_F23, 0, PLTRST),
PAD_CFG_GPO(GPP_H00, 0, PLTRST),
PAD_CFG_GPO(GPP_H01, 0, PLTRST),
PAD_CFG_GPO(GPP_H02, 1, PLTRST),
PAD_NC(GPP_H03, NONE),
PAD_NC(GPP_H04, NONE),
PAD_NC(GPP_H05, NONE),
PAD_NC(GPP_H06, NONE),
PAD_NC(GPP_H07, NONE),
PAD_NC(GPP_H08, NONE),
PAD_NC(GPP_H09, NONE),
PAD_CFG_GPO(GPP_H10, 0, PLTRST),
PAD_CFG_GPO(GPP_H11, 0, PLTRST),
PAD_NC(GPP_H12, NONE),
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
PAD_CFG_GPO(GPP_H14, 0, PLTRST),
PAD_CFG_GPO(GPP_H15, 0, PLTRST),
PAD_CFG_GPO(GPP_H16, 0, PLTRST),
PAD_CFG_GPO(GPP_H17, 0, PLTRST),
PAD_NC(GPP_H18, NONE),
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
PAD_CFG_GPO(GPP_S00, 0, PLTRST),
PAD_CFG_GPO(GPP_S01, 0, PLTRST),
PAD_CFG_GPO(GPP_S02, 0, PLTRST),
PAD_CFG_GPO(GPP_S03, 0, PLTRST),
PAD_CFG_GPO(GPP_S04, 0, PLTRST),
PAD_CFG_GPO(GPP_S05, 0, PLTRST),
PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V05, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_V06, NATIVE, DEEP, NF1),
PAD_CFG_GPI(GPP_V07, NATIVE, DEEP),
PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
PAD_NC(GPP_V12, NONE),
PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_V15, NONE, PLTRST, NF1),
PAD_CFG_GPO(GPP_V16, 0, PLTRST),
PAD_CFG_GPO(GPP_V17, 0, PLTRST),
PAD_NC(GPP_V18, NONE),
PAD_CFG_NF(GPP_V19, NONE, DEEP, NF1),
PAD_NC(GPP_V20, NONE),
PAD_NC(GPP_V21, NONE),
PAD_NC(GPP_V22, NONE),
PAD_NC(GPP_V23, NONE),
};
void mainboard_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

View File

@@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX
};
void mainboard_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}

View File

@@ -1,50 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek, ALC245 */
0x10ec0245, /* Vendor ID */
0x15582624, /* Subsystem ID */
34, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x15582624),
AZALIA_RESET(1),
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
AZALIA_PIN_CFG(0, 0x14, 0x411111f0),
AZALIA_PIN_CFG(0, 0x17, 0x90170110),
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1d, 0x40689b2d),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
AZALIA_PIN_CFG(0, 0x21, 0x04211020),
0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b,
0x0205004a, 0x02042010, 0x02050038, 0x02046909,
0x05c50000, 0x05c43d82, 0x05c50000, 0x05c43d82,
0x05350000, 0x0534201a, 0x05350000, 0x0534201a,
0x0535001d, 0x05340800, 0x0535001e, 0x05340800,
0x05350003, 0x05341ec4, 0x05350004, 0x05340000,
0x05450000, 0x05442000, 0x0545001d, 0x05440800,
0x0545001e, 0x05440800, 0x05450003, 0x05441ec4,
0x05450004, 0x05440000, 0x05350000, 0x0534a01a,
0x0205003c, 0x0204f175, 0x0205003c, 0x0204f135,
0x02050040, 0x02048800, 0x05a50001, 0x05a4001f,
0x02050010, 0x02040020, 0x02050010, 0x02040020,
0x0205006b, 0x0204a390, 0x0205006b, 0x0204a390,
0x0205006c, 0x02040c9e, 0x0205006d, 0x02040c00,
0x00170500, 0x00170500, 0x05a50004, 0x05a40113,
0x02050008, 0x02046a8c, 0x02050076, 0x0204f000,
0x0205000e, 0x020465c0, 0x02050033, 0x02048580,
0x02050069, 0x0204fda8, 0x02050068, 0x02040000,
0x02050003, 0x02040002, 0x02050069, 0x02040000,
0x02050068, 0x02040001, 0x0205002e, 0x0204290e,
0x02050010, 0x02040020, 0x02050010, 0x02040020,
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;

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@@ -1,122 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
chip soc/intel/meteorlake
#TODO: POWER LIMITS
#register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
# .tdp_pl1_override = 15,
# .tdp_pl2_override = 46,
#}"
device domain 0 on
subsystemid 0x1558 0x2624 inherit
device ref tbt_pcie_rp0 on end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
#TODO: TCP1 is used as USB Type-A
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
#TODO: TCP2 is used as HDMI
#TODO: TCP3 goes to redriver, then mux, then USB Type-C
register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""TBT Type-C""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device ref tcss_usb3_port0 on end
end
chip drivers/usb/acpi
register "desc" = ""USB Type-A""
register "type" = "UPC_TYPE_USB3_A"
device ref tcss_usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB Type-C""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device ref tcss_usb3_port3 on end
end
end
end
end
device ref tcss_dma0 on end
device ref xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* TODO: USB TYPEA port1 GEN2 */
[1] = USB2_PORT_MID(OC_SKIP), /* TODO: USB TYPEA port2 GEN1 */
[2] = USB2_PORT_TYPE_C(OC_SKIP), /* TODO: TBT TYPEC USB2.0 */
[4] = USB2_PORT_TYPE_C(OC_SKIP), /* TODO: TYPEC USB2.0 */
[6] = USB2_PORT_MID(OC_SKIP), /* Camera */
[9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* TODO: USB port1 GEN1 */
}"
end
device ref i2c0 on
# Touchpad I2C bus
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
chip drivers/i2c/hid
register "generic.hid" = ""ELAN0412""
register "generic.desc" = ""ELAN Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""FTCS1000""
register "generic.desc" = ""FocalTech Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 38 on end
end
end
device ref i2c5 on
# Smart Amplifier I2C bus
register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
chip drivers/i2c/tas5825m
register "id" = "0"
device i2c 4e on end # (8bit address: 0x9c)
end
end
device ref pcie_rp1 on
# PCH RP#1 x1, Clock 0 (CARD)
register "pcie_rp[PCH_RP(1)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp2 on
# PCH RP#2 x1, Clock 2 (WLAN)
register "pcie_rp[PCH_RP(2)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp10 on
# PCH RP#10 x4, Clock 7 (SSD2)
# This uses signals PCIE_13 through PCIE_16 in the schematics
# but is identified as root port 10 in firmware.
register "pcie_rp[PCH_RP(10)]" = "{
.clk_src = 7,
.clk_req = 7,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp11 on
# CPU RP#11 x4, Clock 8 (SSD1)
# This uses signals PCIE_17 through PCIE_20 in the schematics
# but is identified as root port 11 in firmware.
register "pcie_rp[PCIE_RP(11)]" = "{
.clk_src = 8,
.clk_req = 8,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
end
end

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@@ -1,19 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/ramstage.h>
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
// TODO: Pin Mux settings
// Enable TCP1 and TCP3 USB-A conversion
// BIT 0:3 is mapping to PCH XHCI USB2 port
// BIT 4:5 is reserved
// BIT 6 is orientational
// BIT 7 is enable
params->EnableTcssCovTypeA[1] = 0x81;
params->EnableTcssCovTypeA[3] = 0x85;
// Disable reporting CPU C10 state over eSPI (causes LED flicker).
params->PchEspiHostC10ReportEnable = 0;
}

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@@ -1,24 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/meminit.h>
#include <soc/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg board_cfg = {
.type = MEM_TYPE_DDR5,
.ect = true,
.LpDdrDqDqsReTraining = 1,
};
const struct mem_spd spd_info = {
.topo = MEM_TOPO_MIXED,
.cbfs_index = 0,
.smbus[1] = { .addr_dimm[0] = 0x52, },
};
const bool half_populated = false;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
}

File diff suppressed because it is too large Load Diff

View File

@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_16384
select DRIVERS_GENERIC_CBFS_SERIAL
select DRIVERS_GENERIC_CBFS_UUID
select DRIVERS_GFX_NVIDIA
select DRIVERS_I2C_HID
select DRIVERS_I2C_TAS5825M
select EC_SYSTEM76_EC

View File

@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#define EC_GPE_SCI 0x17 /* GPP_B23 */
#define EC_GPE_SWI 0x26 /* GPP_G6 */
#include <ec/system76/ec/acpi/ec.asl>
@@ -11,10 +9,6 @@ Scope (\_SB)
#include "sleep.asl"
Scope (PCI0) {
#include "backlight.asl"
Device (PEGP) {
Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
}
}
}

View File

@@ -65,12 +65,6 @@ chip soc/intel/cannonlake
# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
register "PcieClkSrcUsage[8]" = "0x40"
register "PcieClkSrcClkReq[8]" = "8"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
device pci 00.2 on end # USB xHCI Host controller
device pci 00.3 on end # USB Type-C UCSI controller
end
end
device pci 02.0 on # Integrated Graphics Device
register "gfx" = "GMA_DEFAULT_PANEL(0)"

View File

@@ -3,16 +3,7 @@
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_F22
#define DGPU_PWR_EN GPP_F23
#define DGPU_GC6 GPP_C12
#define DGPU_SSID 0x95e61558
#ifndef __ACPI__
void mainboard_configure_early_gpios(void);
void mainboard_configure_gpios(void);
#endif
#endif

View File

@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <mainboard/gpio.h>
#include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h>
@@ -22,18 +20,6 @@ static const struct cnl_mb_cfg memcfg = {
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
const struct nvidia_gpu_config config = {
.power_gpio = DGPU_PWR_EN,
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
memupd->FspmConfig.PrimaryDisplay = 0;
// Allow memory speeds higher than 2666 MT/s
memupd->FspmConfig.SaOcSupport = 1;

View File

@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_16384
select DRIVERS_GENERIC_CBFS_SERIAL
select DRIVERS_GENERIC_CBFS_UUID
select DRIVERS_GFX_NVIDIA
select DRIVERS_I2C_HID
select DRIVERS_I2C_TAS5825M
select EC_SYSTEM76_EC

View File

@@ -1,7 +1,6 @@
## SPDX-License-Identifier: GPL-2.0-only
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
bootblock-y += bootblock.c
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

View File

@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <variant/gpio.h>
#define EC_GPE_SCI 0x03 /* GPP_K3 */
#define EC_GPE_SWI 0x06 /* GPP_K6 */
#include <ec/system76/ec/acpi/ec.asl>
@@ -10,10 +8,6 @@ Scope (\_SB) {
#include "sleep.asl"
Scope (PCI0) {
#include "backlight.asl"
Device (PEGP) {
Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
}
}
}

View File

@@ -62,12 +62,6 @@ chip soc/intel/cannonlake
# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
register "PcieClkSrcUsage[8]" = "0x40"
register "PcieClkSrcClkReq[8]" = "8"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
device pci 00.2 on end # USB xHCI Host controller
device pci 00.3 on end # USB Type-C UCSI controller
end
end
device pci 02.0 on # Integrated Graphics Device
register "gfx" = "GMA_DEFAULT_PANEL(0)"

View File

@@ -3,16 +3,7 @@
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_F8
#define DGPU_PWR_EN GPP_F9
#define DGPU_GC6 GPP_K11
#define DGPU_SSID 0x65f11558
#ifndef __ACPI__
void variant_configure_early_gpios(void);
void variant_configure_gpios(void);
#endif
#endif

View File

@@ -1,9 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
#include <variant/romstage.h>
static const struct cnl_mb_cfg memcfg = {
@@ -23,18 +21,6 @@ static const struct cnl_mb_cfg memcfg = {
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
const struct nvidia_gpu_config config = {
.power_gpio = DGPU_PWR_EN,
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
memupd->FspmConfig.PrimaryDisplay = 0;
variant_configure_fspm(memupd);
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);

View File

@@ -1,18 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_F22
#define DGPU_PWR_EN GPP_F23
#define DGPU_GC6 GPP_K21
#define DGPU_SSID 0x50d31558
#ifndef __ACPI__
void variant_configure_early_gpios(void);
void variant_configure_gpios(void);
#endif
#endif

View File

@@ -1,18 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_F22
#define DGPU_PWR_EN GPP_F23
#define DGPU_GC6 GPP_K21
#define DGPU_SSID 0x65e51558
#ifndef __ACPI__
void variant_configure_early_gpios(void);
void variant_configure_gpios(void);
#endif
#endif

View File

@@ -8,7 +8,6 @@ config BOARD_SYSTEM76_RPL_COMMON
select DRIVERS_GENERIC_CBFS_UUID
select DRIVERS_I2C_HID
select EC_SYSTEM76_EC
select EC_SYSTEM76_EC_LOCKDOWN
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
@@ -28,9 +27,6 @@ config BOARD_SYSTEM76_RPL_COMMON
config BOARD_SYSTEM76_ADDW3
select BOARD_SYSTEM76_RPL_COMMON
select DRIVERS_GFX_NVIDIA
select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
select DRIVERS_INTEL_DTBT
select EC_SYSTEM76_EC_DGPU
select MAINBOARD_USES_IFD_GBE_REGION
select PCIEXP_HOTPLUG
@@ -38,17 +34,12 @@ config BOARD_SYSTEM76_ADDW3
config BOARD_SYSTEM76_ADDW4
select BOARD_SYSTEM76_RPL_COMMON
select DRIVERS_GFX_NVIDIA
select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
select EC_SYSTEM76_EC_DGPU
select PCIEXP_HOTPLUG
select SOC_INTEL_ALDERLAKE_PCH_S
config BOARD_SYSTEM76_BONW15
select BOARD_SYSTEM76_RPL_COMMON
select DRIVERS_GFX_NVIDIA
select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
select DRIVERS_INTEL_DTBT
select EC_SYSTEM76_EC_DGPU
select PCIEXP_HOTPLUG
select SOC_INTEL_ALDERLAKE_PCH_S
@@ -65,8 +56,6 @@ config BOARD_SYSTEM76_GALP7
config BOARD_SYSTEM76_GAZE18
select BOARD_SYSTEM76_RPL_COMMON
select DRIVERS_GFX_NVIDIA
select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
select EC_SYSTEM76_EC_DGPU
select SOC_INTEL_ALDERLAKE_PCH_P
@@ -78,27 +67,19 @@ config BOARD_SYSTEM76_LEMP12
config BOARD_SYSTEM76_ORYP11
select BOARD_SYSTEM76_RPL_COMMON
select DRIVERS_GFX_NVIDIA
select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
select EC_SYSTEM76_EC_DGPU
select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config BOARD_SYSTEM76_ORYP12
select BOARD_SYSTEM76_RPL_COMMON
select DRIVERS_GFX_NVIDIA
select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
select DRIVERS_I2C_TAS5825M
select DRIVERS_INTEL_DTBT
select EC_SYSTEM76_EC_DGPU
select PCIEXP_HOTPLUG
select SOC_INTEL_ALDERLAKE_PCH_S
config BOARD_SYSTEM76_SERW13
select BOARD_SYSTEM76_RPL_COMMON
select DRIVERS_GFX_NVIDIA
select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
select DRIVERS_INTEL_DTBT
select EC_SYSTEM76_EC_DGPU
select PCIEXP_HOTPLUG
select SOC_INTEL_ALDERLAKE_PCH_S
@@ -157,27 +138,12 @@ config MAINBOARD_VERSION
default "oryp12" if BOARD_SYSTEM76_ORYP12
default "serw13" if BOARD_SYSTEM76_SERW13
config CMOS_DEFAULT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/cmos-csme.default" if BOARD_SYSTEM76_DARP9
default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
config CONSOLE_POST
default y
config D3COLD_SUPPORT
default n
config DRIVERS_GFX_NVIDIA_BRIDGE
default 0x02 if BOARD_SYSTEM76_BONW15
config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
default 45 if BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12
default 55 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_SERW13
default 80 if BOARD_SYSTEM76_BONW15
config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
default 25 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12 || BOARD_SYSTEM76_SERW13
config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"

View File

@@ -2,10 +2,6 @@
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
ifeq ($(CONFIG_DRIVERS_GFX_NVIDIA),y)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
endif
bootblock-y += bootblock.c
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

View File

@@ -1,9 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#if CONFIG(DRIVERS_GFX_NVIDIA)
#include <variant/gpio.h>
#endif
#define EC_GPE_SCI 0x6E
#define EC_GPE_SWI 0x6B
#include <ec/system76/ec/acpi/ec.asl>
@@ -12,17 +8,5 @@ Scope (\_SB) {
#include "sleep.asl"
Scope (PCI0) {
#include "backlight.asl"
#if CONFIG(DRIVERS_GFX_NVIDIA)
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) || CONFIG(BOARD_SYSTEM76_BONW15)
Scope (PEG2) {
#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
}
#else
Scope (PEG1) {
#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
}
#endif
#endif // CONFIG(DRIVERS_GFX_NVIDIA)
}
}

View File

@@ -1,3 +0,0 @@
boot_option=Fallback
debug_level=Debug
me_state=Enable

View File

@@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_R16
#define DGPU_PWR_EN GPP_F9
#define DGPU_GC6 GPP_F8
#define DGPU_SSID 0xa6711558
#endif

View File

@@ -103,9 +103,6 @@ chip soc/intel/alderlake
.clk_req = 15,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR,
}"
chip drivers/intel/dtbt
device pci 00.0 on end
end
end
device ref pcie_rp25 on

View File

@@ -1,9 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
@@ -24,15 +22,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
};
const bool half_populated = false;
const struct nvidia_gpu_config config = {
.power_gpio = DGPU_PWR_EN,
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;

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