mb/system76/mtl: Add Darter Pro 10

The Darter Pro 10 (darp10) is an Intel Meteor Lake-H based board.

There are 2 variants in order to differentiate the 14" and 16" models,
as they have different keyboards and so have different EC firmware.

Change-Id: Iaef03a47cf108591ef823bfa779777c7c05c6337
Signed-off-by: Tim Crawford <tcrawford@system76.com>

Makefile.mk

@@ -501,8 +501,7 @@ CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
 CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie
 CFLAGS_common += -Wstring-compare
 ifeq ($(CONFIG_COMPILER_GCC),y)
-CFLAGS_common += -Wold-style-declaration -Wflex-array-member-not-at-end
-CFLAGS_common += -Wcalloc-transposed-args
+CFLAGS_common += -Wold-style-declaration
 # Don't add these GCC specific flags when running scan-build
 ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
 CFLAGS_common += -Wno-packed-not-aligned

src/arch/arm64/smbios.c

@@ -66,8 +66,8 @@ int smbios_write_type4(unsigned long *current, int handle)
 	smbios_processor_id(t->processor_id);
 	t->processor_manufacturer = smbios_processor_manufacturer(t->eos);
 	t->processor_version = smbios_processor_name(t->eos);
-	t->processor_family = 0xfe; /* Use processor_family2 field */
-	t->processor_family2 = 0x101; /* ARMv8 */
+	t->processor_family = SMBIOS_PROCESSOR_FAMILY_FROM_FAMILY2;
+	t->processor_family2 = SMBIOS_PROCESSOR_FAMILY2_ARMV8;
 	t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL;
 
 	smbios_cpu_get_core_counts(&t->core_count2, &t->thread_count2);

src/arch/x86/smbios.c

@@ -68,7 +68,7 @@ static int get_socket_type(void)
 
 unsigned int __weak smbios_processor_family(struct cpuid_result res)
 {
-	return (res.eax > 0) ? 0x0c : 0x6;
+	return (res.eax > 0) ? SMBIOS_PROCESSOR_FAMILY_PENTIUM_PRO : SMBIOS_PROCESSOR_FAMILY_INTEL486;
 }
 
 static size_t get_number_of_caches(size_t max_logical_cpus_sharing_cache)

src/ec/dasharo/ec/Kconfig

@@ -0,0 +1,21 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config EC_DASHARO_EC
+	bool
+	help
+	  Dasharo EC
+
+config EC_DASHARO_EC_BAT_THRESHOLDS
+	depends on EC_DASHARO_EC
+	bool
+	default y
+
+config EC_DASHARO_EC_DGPU
+	depends on EC_DASHARO_EC
+	bool
+	default n
+
+config EC_DASHARO_EC_OLED
+	depends on EC_DASHARO_EC
+	bool
+	default n

src/ec/dasharo/ec/Makefile.mk

@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-only
+ifeq ($(CONFIG_EC_DASHARO_EC),y)
+
+all-y += dasharo_ec.c
+
+ramstage-y += smbios.c
+
+smm-$(CONFIG_DEBUG_SMI) += dasharo_ec.c
+
+endif

src/ec/dasharo/ec/acpi/ac.asl

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (AC)
+{
+	Name (_HID, "ACPI0003" /* Power Source Device */)
+	Name (_PCL, Package (0x01)  // _PCL: Power Consumer List
+	{
+		_SB
+	})
+
+	Name (ACFG, 1)
+
+	Method (_PSR, 0, NotSerialized)  // _PSR: Power Source
+	{
+		Return (ACFG)
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}

src/ec/dasharo/ec/acpi/battery.asl

@@ -0,0 +1,248 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (BAT0)
+{
+	Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */)
+	Name (_UID, 0)
+	Name (_PCL, Package (0x01)  // _PCL: Power Consumer List
+	{
+		_SB
+	})
+	Name (BFCC, 0)
+	Method (_STA, 0, NotSerialized)
+	{
+		If (^^PCI0.LPCB.EC0.ECOK)
+		{
+			If (^^PCI0.LPCB.EC0.BAT0)
+			{
+				Return (0x1F)
+			}
+			Else
+			{
+				Return (0x0F)
+			}
+		}
+		Else
+		{
+			Return (0x0F)
+		}
+	}
+
+	Name (PBIF, Package (0x0D)
+	{
+		1, // 0 - Power Unit
+		0xFFFFFFFF, // 1 - Design Capacity
+		0xFFFFFFFF, // 2 - Last Full Charge Capacity
+		1, // 3 - Battery Technology
+		0xFFFFFFFF, // 4 - Design Voltage
+		0, // 5 - Design Capacity of Warning
+		0, // 6 - Design Capacity of Low
+		0x40, // 7 - Battery Capacity Granularity 1
+		0x40, // 8 - Battery Capacity Granularity 2
+		" ", // 9 - Model Number
+		" ", // 10 - Serial Number
+		" ", // 11 - Battery Type
+		" " // 12 - OEM Information
+	})
+	Method (IVBI, 0, NotSerialized)
+	{
+		PBIF [1] = 0xFFFFFFFF
+		PBIF [2] = 0xFFFFFFFF
+		PBIF [4] = 0xFFFFFFFF
+		PBIF [9] = " "
+		PBIF [10] = " "
+		PBIF [11] = " "
+		PBIF [12] = " "
+		BFCC = 0
+	}
+
+	Method (UPBI, 0, NotSerialized)
+	{
+		If (^^PCI0.LPCB.EC0.BAT0)
+		{
+			Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
+			PBIF [1] = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
+			PBIF [2] = Local0
+			BFCC = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
+			PBIF [4] = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
+			PBIF [5] = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
+			PBIF [6] = Local0
+			PBIF [9] = "BAT"
+			PBIF [10] = "0001"
+			PBIF [11] = "LION"
+			PBIF [12] = "Notebook"
+		}
+		Else
+		{
+			IVBI ()
+		}
+	}
+
+	Method (_BIF, 0, NotSerialized)  // _BIF: Battery Information
+	{
+		If (^^PCI0.LPCB.EC0.ECOK)
+		{
+			UPBI ()
+		}
+		Else
+		{
+			IVBI ()
+		}
+
+		Return (PBIF) /* \_SB_.BAT0.PBIF */
+	}
+
+	Name (PBIX, Package ()
+	{
+		0, // 0 - Revision
+		1, // 1 - Power Unit: mAh
+		0xFFFFFFFF, // 2 - Design Capacity
+		0xFFFFFFFF, // 3 - Last Full Charge Capacity
+		1, // 4 - Battery Technology: Rechargeable
+		0xFFFFFFFF, // 5 - Design Voltage
+		0, // 6 - Design Capacity of Warning
+		0, // 7 - Design Capacity of Low
+		0, // 8 - Cycle Count
+		98000, // 9 - Measurement Accuracy
+		0xFFFFFFFF, // 10 - Max Sampling Time
+		0xFFFFFFFF, // 11 - Min Sampling Time
+		0xFFFFFFFF, // 12 - Max Averaging Interval
+		0xFFFFFFFF, // 13 - Min Averaging Interval
+		0x40, // 14 - Battery Capacity Granularity 1
+		0x40, // 15 - Battery Capacity Granularity 2
+		" ", // 16 - Model Number
+		" ", // 17 - Serial Number
+		" ", // 18 - Battery Type
+		" " // 19 - OEM Information
+	})
+
+	Method (IVBX, 0, NotSerialized)
+	{
+		PBIX [2] = 0xFFFFFFFF
+		PBIX [3] = 0xFFFFFFFF
+		PBIX [5] = 0xFFFFFFFF
+		PBIX [16] = " "
+		PBIX [17] = " "
+		PBIX [18] = " "
+		PBIX [19] = " "
+		BFCC = 0
+	}
+
+	Method (UPBX, 0, NotSerialized)
+	{
+		If (^^PCI0.LPCB.EC0.BAT0)
+		{
+			Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
+			PBIX [2] = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
+			PBIX [3] = Local0
+			BFCC = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
+			PBIX [5] = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
+			PBIX [6] = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
+			PBIX [7] = Local0
+			LOCAL0 = ^^PCI0.LPCB.EC0.CYC0
+			PBIX [8] = LOCAL0
+			PBIX [16] = "BAT"
+			PBIX [17] = "0001"
+			PBIX [18] = "LION"
+			PBIX [19] = "Notebook"
+		}
+		Else
+		{
+			IVBX ()
+		}
+	}
+
+	// _BIX: Battery Information Extended
+	Method (_BIX, 0, NotSerialized)
+	{
+		If (^^PCI0.LPCB.EC0.ECOK)
+		{
+			UPBX ()
+		}
+		Else
+		{
+			IVBX ()
+		}
+		Return (PBIX) /* \_SB_.BAT0.PBIX */
+	}
+
+	Name (PBST, Package (0x04)
+	{
+		0, // 0 - Battery state
+		0xFFFFFFFF, // 1 - Battery present rate
+		0xFFFFFFFF, // 2 - Battery remaining capacity
+		0xFFFFFFFF // 3 - Battery present voltage
+	})
+	Method (IVBS, 0, NotSerialized)
+	{
+		PBST [0] = 0
+		PBST [1] = 0xFFFFFFFF
+		PBST [2] = 0xFFFFFFFF
+		PBST [3] = 0xFFFFFFFF
+	}
+
+	Method (UPBS, 0, NotSerialized)
+	{
+		If (^^PCI0.LPCB.EC0.BAT0)
+		{
+			Local0 = 0
+			Local1 = 0
+			If (^^AC.ACFG)
+			{
+				If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02))
+				{
+					Local0 |= 0x02
+					Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
+				}
+			}
+			Else
+			{
+				Local0 |= 1
+				Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
+			}
+
+			Local7 = (Local1 & 0x8000)
+			If ((Local7 == 0x8000))
+			{
+				Local1 ^= 0xFFFF
+			}
+
+			Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF)
+			Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF)
+			PBST [0] = Local0
+			PBST [1] = Local1
+			PBST [2] = Local2
+			PBST [3] = Local3
+			If ((BFCC != ^^PCI0.LPCB.EC0.BFC0))
+			{
+				Notify (BAT0, 0x81) // Information Change
+			}
+		}
+		Else
+		{
+			IVBS ()
+		}
+	}
+
+	Method (_BST, 0, NotSerialized)  // _BST: Battery Status
+	{
+		If (^^PCI0.LPCB.EC0.ECOK)
+		{
+			UPBS ()
+		}
+		Else
+		{
+			IVBS ()
+		}
+
+		Return (PBST) /* \_SB_.BAT0.PBST */
+	}
+}

src/ec/dasharo/ec/acpi/battery_thresholds.asl

@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Field (ERAM, ByteAcc, Lock, Preserve)
+{
+	Offset (0xBC),
+	BTL0,   8,      /* BAT0 charging start threshold */
+	BTH0,   8,      /* BAT0 charging end threshold */
+}
+
+/*
+ * Get battery charging threshold
+ *
+ * Arg0: 0: Start threshold
+ *       1: Stop threshold
+ */
+Method (GBCT, 1, NotSerialized)
+{
+	If (Arg0 == 0) {
+		Return (BTL0)
+	}
+
+	If (Arg0 == 1) {
+		Return (BTH0)
+	}
+
+	Return (0xFF)
+}
+
+/*
+ * Set battery charging threshold
+ *
+ * Arg0: 0: Start threshold
+ *       1: Stop threshold
+ * Arg1: Percentage
+ */
+Method (SBCT, 2, NotSerialized)
+{
+	If (Arg1 <= 100) {
+		If (Arg0 == 0) {
+			BTL0 = Arg1
+		}
+		If (Arg0 == 1) {
+			BTH0 = Arg1
+		}
+	}
+}

src/ec/dasharo/ec/acpi/buttons.asl

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (PWRB)
+{
+	Name (_HID, EisaId ("PNP0C0C"))
+	Name (_PRW, Package () { EC_GPE_SWI, 3 })
+}
+
+Device (SLPB)
+{
+	Name (_HID, EisaId ("PNP0C0E"))
+	Name (_PRW, Package () { EC_GPE_SWI, 3 })
+}

src/ec/dasharo/ec/acpi/ec.asl

@@ -0,0 +1,241 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB) {
+	#include "ac.asl"
+	#include "battery.asl"
+	#include "buttons.asl"
+	#include "hid.asl"
+	#include "lid.asl"
+	#include "s76.asl"
+}
+
+Device (\_SB.PCI0.LPCB.EC0)
+{
+	Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */)
+	Name (_GPE, EC_GPE_SCI)  // _GPE: General Purpose Events
+	Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+	{
+		IO (Decode16,
+			0x0062,             // Range Minimum
+			0x0062,             // Range Maximum
+			0x00,               // Alignment
+			0x01,               // Length
+			)
+		IO (Decode16,
+			0x0066,             // Range Minimum
+			0x0066,             // Range Maximum
+			0x00,               // Alignment
+			0x01,               // Length
+			)
+	})
+
+	#include "ec_ram.asl"
+
+	Name (ECOK, 0)
+	Method (_REG, 2, Serialized)  // _REG: Region Availability
+	{
+		Printf ("EC: _REG %o %o", ToHexString(Arg0), ToHexString(Arg1))
+		If ((Arg0 == 0x03) && (Arg1 == 1)) {
+			// Enable hardware touchpad lock, airplane mode, and keyboard backlight keys
+			ECOS = 1
+
+			// Enable software display brightness keys
+			WINF = 1
+
+			// Set current AC state
+			^^^^AC.ACFG = ADP
+			// Update battery information and status
+			^^^^BAT0.UPBI()
+			^^^^BAT0.UPBS()
+
+			// Notify of changes
+			Notify(^^^^AC, 0)
+			Notify(^^^^BAT0, 0)
+
+			PNOT ()
+
+			// EC is now available
+			ECOK = Arg1
+
+			// Reset Dasharo Device
+			^^^^S76D.RSET()
+		}
+	}
+
+	Name (S3OS, 0)
+	Method (PTS, 1, Serialized) {
+		Printf ("EC: PTS: %o", ToHexString(Arg0))
+		If (ECOK) {
+			// Save ECOS during sleep
+			S3OS = ECOS
+
+			// Clear wake cause
+			WFNO = 0
+		}
+	}
+
+	Method (WAK, 1, Serialized) {
+		Printf ("EC: WAK: %o", ToHexString(Arg0))
+		If (ECOK) {
+			// Restore ECOS after sleep
+			ECOS = S3OS
+
+			// Set current AC state
+			^^^^AC.ACFG = ADP
+
+			// Update battery information and status
+			^^^^BAT0.UPBI()
+			^^^^BAT0.UPBS()
+
+			// Notify of changes
+			Notify(^^^^AC, 0)
+			Notify(^^^^BAT0, 0)
+		}
+	}
+
+	Method (_Q0A, 0, NotSerialized) // Touchpad Toggle
+	{
+		Printf ("EC: Touchpad Toggle")
+	}
+
+	Method (_Q0B, 0, NotSerialized) // Screen Toggle
+	{
+		Printf ("EC: Screen Toggle")
+#if CONFIG(EC_DASHARO_EC_OLED)
+		Notify (^^^^S76D, 0x85)
+#endif // CONFIG(EC_DASHARO_EC_OLED)
+	}
+
+	Method (_Q0C, 0, NotSerialized)  // Mute
+	{
+		Printf ("EC: Mute")
+	}
+
+	Method (_Q0D, 0, NotSerialized) // Keyboard Backlight
+	{
+		Printf ("EC: Keyboard Backlight")
+	}
+
+	Method (_Q0E, 0, NotSerialized) // Volume Down
+	{
+		Printf ("EC: Volume Down")
+	}
+
+	Method (_Q0F, 0, NotSerialized) // Volume Up
+	{
+		Printf ("EC: Volume Up")
+	}
+
+	Method (_Q10, 0, NotSerialized) // Switch Video Mode
+	{
+		Printf ("EC: Switch Video Mode")
+	}
+
+	Method (_Q11, 0, NotSerialized) // Brightness Down
+	{
+		Printf ("EC: Brightness Down")
+		if (^^^^HIDD.HRDY) {
+			^^^^HIDD.HPEM (20)
+		}
+	}
+
+	Method (_Q12, 0, NotSerialized) // Brightness Up
+	{
+		Printf ("EC: Brightness Up")
+		if (^^^^HIDD.HRDY) {
+			^^^^HIDD.HPEM (19)
+		}
+	}
+
+	Method (_Q13, 0, NotSerialized) // Camera Toggle
+	{
+		Printf ("EC: Camera Toggle")
+	}
+
+	Method (_Q14, 0, NotSerialized) // Airplane Mode
+	{
+		Printf ("EC: Airplane Mode")
+		if (^^^^HIDD.HRDY) {
+			^^^^HIDD.HPEM (8)
+		}
+		// TODO: hardware airplane mode
+	}
+
+	Method (_Q15, 0, NotSerialized) // Suspend Button
+	{
+		Printf ("EC: Suspend Button")
+		Notify (SLPB, 0x80)
+	}
+
+	Method (_Q16, 0, NotSerialized) // AC Detect
+	{
+		Printf ("EC: AC Detect")
+		^^^^AC.ACFG = ADP
+		Notify (AC, 0x80) // Status Change
+		If (BAT0)
+		{
+			Notify (^^^^BAT0, 0x81) // Information Change
+			Notify (^^^^BAT0, 0x80) // Status Change
+		}
+	}
+
+	Method (_Q17, 0, NotSerialized)  // BAT0 Update
+	{
+		Printf ("EC: BAT0 Update (17)")
+		Notify (^^^^BAT0, 0x81) // Information Change
+	}
+
+	Method (_Q19, 0, NotSerialized)  // BAT0 Update
+	{
+		Printf ("EC: BAT0 Update (19)")
+		Notify (^^^^BAT0, 0x81) // Information Change
+	}
+
+	Method (_Q1B, 0, NotSerialized) // Lid Close
+	{
+		Printf ("EC: Lid Close")
+		Notify (LID0, 0x80)
+	}
+
+	Method (_Q1C, 0, NotSerialized) // Thermal Trip
+	{
+		Printf ("EC: Thermal Trip")
+		/* TODO
+		Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change
+		Notify (\_TZ.TZ0, 0x80) // Thermal Status Change
+		*/
+	}
+
+	Method (_Q1D, 0, NotSerialized) // Power Button
+	{
+		Printf ("EC: Power Button")
+		Notify (PWRB, 0x80)
+	}
+
+	Method (_Q50, 0, NotSerialized) // Other Events
+	{
+		Local0 = OEM4
+		If (Local0 == 0x8A) {
+			Printf ("EC: White Keyboard Backlight")
+			Notify (^^^^S76D, 0x80)
+		} ElseIf (Local0 == 0x9F) {
+			Printf ("EC: Color Keyboard Toggle")
+			Notify (^^^^S76D, 0x81)
+		} ElseIf (Local0 == 0x81) {
+			Printf ("EC: Color Keyboard Down")
+			Notify (^^^^S76D, 0x82)
+		} ElseIf (Local0 == 0x82) {
+			Printf ("EC: Color Keyboard Up")
+			Notify (^^^^S76D, 0x83)
+		} ElseIf (Local0 == 0x80) {
+			Printf ("EC: Color Keyboard Color Change")
+			Notify (^^^^S76D, 0x84)
+		} Else {
+			Printf ("EC: Other: %o", ToHexString(Local0))
+		}
+	}
+
+	#if CONFIG(EC_DASHARO_EC_BAT_THRESHOLDS)
+	#include "battery_thresholds.asl"
+	#endif
+}

src/ec/dasharo/ec/acpi/ec_ram.asl

@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+OperationRegion (ERAM, EmbeddedControl, 0, 0xFF)
+Field (ERAM, ByteAcc, Lock, Preserve)
+{
+	Offset (0x03),
+	LSTE, 1,	// Lid is open
+	, 1,
+	LWKE, 1,	// Lid wake
+	, 5,
+	Offset (0x07),
+	TMP1, 8,	// CPU temperature
+	Offset (0x10),
+	ADP, 1,		// AC adapter connected
+	, 1,
+	BAT0, 1,	// Battery connected
+	, 5,
+	WFNO, 8,	// Wake cause (not implemented)
+	Offset (0x16),
+	BDC0, 32,	// Battery design capacity
+	BFC0, 32,	// Battery full capacity
+	Offset (0x22),
+	BDV0, 32,	// Battery design voltage
+	BST0, 32,	// Battery status
+	BPR0, 32,	// Battery current
+	BRC0, 32,	// Battery remaining capacity
+	BPV0, 32,	// Battery voltage
+	Offset (0x3A),
+	BCW0, 32,
+	BCL0, 32,
+	CYC0, 16,	// Battery cycle count
+	Offset (0x68),
+	ECOS, 8,	// Detected OS, 0 = no ACPI, 1 = ACPI but no driver, 2 = ACPI with driver
+	Offset (0xC8),
+	OEM1, 8,
+	OEM2, 8,
+	OEM3, 16,
+	OEM4, 8,	// Extra SCI data
+	Offset (0xCD),
+	TMP2, 8,	// GPU temperature
+	DUT1, 8,	// Fan 1 duty
+	DUT2, 8,	// Fan 2 duty
+	RPM1, 16,	// Fan 1 RPM
+	RPM2, 16,	// Fan 2 RPM
+	Offset (0xD9),
+	AIRP, 8,	// Airplane mode LED
+	WINF, 8,	// Enable ACPI brightness controls
+	Offset (0xF8),
+	FCMD, 8,
+	FDAT, 8,
+	FBUF, 8,
+	FBF1, 8,
+	FBF2, 8,
+	FBF3, 8,
+}

src/ec/dasharo/ec/acpi/hid.asl

@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (HIDD)
+{
+	Name (_HID, "INT33D5")
+	Name (HBSY, 0)
+	Name (HIDX, 0)
+	Name (HRDY, 0)
+
+	Method (HDEM, 0, Serialized)
+	{
+		HBSY = 0
+		Return (HIDX)
+	}
+
+	Method (HDMM, 0, Serialized)
+	{
+		Return (0)
+	}
+
+	Method (HDSM, 1, Serialized)
+	{
+		HRDY = Arg0
+	}
+
+	Method (HPEM, 1, Serialized)
+	{
+		HBSY = 1
+		HIDX = Arg0
+
+		Notify (HIDD, 0xC0)
+		Local0 = 0
+		While ((Local0 < 0xFA) && HBSY)
+		{
+			Sleep (0x04)
+			Local0++
+		}
+
+		If (HBSY == 1)
+		{
+			HBSY = 0
+			HIDX = 0
+			Return (1)
+		}
+		Else
+		{
+			Return (0)
+		}
+	}
+}

src/ec/dasharo/ec/acpi/lid.asl

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (LID0)
+{
+	Name (_HID, EisaId ("PNP0C0D"))
+	Name (_PRW, Package () { EC_GPE_SWI, 3 })
+
+	Method (_LID, 0, NotSerialized) {
+		Printf ("LID: _LID")
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			Return (^^PCI0.LPCB.EC0.LSTE)
+		} Else {
+			Return (1)
+		}
+	}
+
+	Method (_PSW, 1, NotSerialized) {
+		Printf ("LID: _PSW: %o", ToHexString(Arg0))
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.LWKE = Arg0
+		}
+	}
+}

src/ec/dasharo/ec/acpi/s76.asl

@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Notifications:
+//   0x80 - hardware backlight toggle
+//   0x81 - backlight toggle
+//   0x82 - backlight down
+//   0x83 - backlight up
+//   0x84 - backlight color change
+//   0x85 - OLED screen toggle
+Device (S76D) {
+	Name (_HID, "17761776")
+	Name (_UID, 0)
+	// Hide the device so that Windows does not warn about a missing driver.
+	Name (_STA, 0xB)
+
+	Method (RSET, 0, Serialized) {
+		Printf ("S76D: RSET")
+		SAPL(0)
+		SKBB(0)
+		SKBC(0xFFFFFF)
+	}
+
+	Method (INIT, 0, Serialized) {
+		Printf ("S76D: INIT")
+		RSET()
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			// Set flags to use software control
+			^^PCI0.LPCB.EC0.ECOS = 2
+			Return (0)
+		} Else {
+			Return (1)
+		}
+	}
+
+	Method (FINI, 0, Serialized) {
+		Printf ("S76D: FINI")
+		RSET()
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			// Set flags to use hardware control
+			^^PCI0.LPCB.EC0.ECOS = 1
+			Return (0)
+		} Else {
+			Return (1)
+		}
+	}
+
+	// Get Airplane LED
+	Method (GAPL, 0, Serialized) {
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			If (^^PCI0.LPCB.EC0.AIRP & 0x40) {
+				Return (1)
+			}
+		}
+		Return (0)
+	}
+
+	// Set Airplane LED
+	Method (SAPL, 1, Serialized) {
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			If (Arg0) {
+				^^PCI0.LPCB.EC0.AIRP |= 0x40
+			} Else {
+				^^PCI0.LPCB.EC0.AIRP &= 0xBF
+			}
+		}
+	}
+
+	// Get Keyboard Backlight Kind
+	// 0 - No backlight
+	// 1 - White backlight
+	// 2 - RGB backlight
+	Method (GKBK, 0, Serialized) {
+		Local0 = 0
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = 2
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+			Local0 = ^^PCI0.LPCB.EC0.FBUF
+		}
+		Return (Local0)
+	}
+
+	// Get Keyboard Brightness
+	Method (GKBB, 0, Serialized) {
+		Local0 = 0
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = 1
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+			Local0 = ^^PCI0.LPCB.EC0.FBUF
+		}
+		Return (Local0)
+	}
+
+	// Set Keyboard Brightness
+	Method (SKBB, 1, Serialized) {
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = 0
+			^^PCI0.LPCB.EC0.FBUF = Arg0
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+		}
+	}
+
+	// Get Keyboard Color
+	Method (GKBC, 0, Serialized) {
+		Local0 = 0
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = 4
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+			Local0 = ^^PCI0.LPCB.EC0.FBUF
+			Local0 |= (^^PCI0.LPCB.EC0.FBF1) << 16
+			Local0 |= (^^PCI0.LPCB.EC0.FBF2) << 8
+		}
+		Return (Local0)
+	}
+
+	// Set Keyboard Color
+	Method (SKBC, 1, Serialized) {
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = 3
+			^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF)
+			^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF)
+			^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF)
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+		}
+	}
+
+	// Fan names
+	Method (NFAN, 0, Serialized) {
+		Return (Package() {
+			"CPU fan",
+#if CONFIG(EC_DASHARO_EC_DGPU)
+			"GPU fan",
+#endif
+		})
+	}
+
+	// Get fan duty cycle and RPM as a single value
+	Method (GFAN, 1, Serialized) {
+		Local0 = 0
+		Local1 = 0
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			If (Arg0 == 0) {
+				Local0 = ^^PCI0.LPCB.EC0.DUT1
+				Local1 = ^^PCI0.LPCB.EC0.RPM1
+			} ElseIf (Arg0 == 1) {
+				Local0 = ^^PCI0.LPCB.EC0.DUT2
+				Local1 = ^^PCI0.LPCB.EC0.RPM2
+			}
+		}
+		If (Local1 != 0) {
+			// 60 * (EC frequency / 120) / 2
+			Local1 = 2156250 / Local1
+		}
+		Return ((Local1 << 8) | Local0)
+	}
+
+	// Temperature names
+	Method (NTMP, 0, Serialized) {
+		Return (Package() {
+			"CPU temp",
+#if CONFIG(EC_DASHARO_EC_DGPU)
+			"GPU temp",
+#endif
+		})
+	}
+
+	// Get temperature
+	Method (GTMP, 1, Serialized) {
+		Local0 = 0;
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			If (Arg0 == 0) {
+				Local0 = ^^PCI0.LPCB.EC0.TMP1
+			} ElseIf (Arg0 == 1) {
+				Local0 = ^^PCI0.LPCB.EC0.TMP2
+			}
+		}
+		Return (Local0)
+	}
+}

src/ec/dasharo/ec/dasharo_ec.c

@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "dasharo_ec.h"
+#include <arch/io.h>
+#include <console/dasharo_ec.h>
+#include <console/console.h>
+#include <timer.h>
+
+// This is the command region for Dasharo EC firmware. It must be
+// enabled for LPC in the mainboard.
+#define DASHARO_EC_BASE 0x0E00
+#define DASHARO_EC_SIZE 256
+
+#define REG_CMD 0
+#define REG_RESULT 1
+#define REG_DATA 2	// Start of command data
+
+// When command register is 0, command is complete
+#define CMD_FINISHED 0
+
+#define RESULT_OK 0
+
+// Print command. Registers are unique for each command
+#define CMD_PRINT 4
+#define CMD_PRINT_REG_FLAGS 2
+#define CMD_PRINT_REG_LEN 3
+#define CMD_PRINT_REG_DATA 4
+
+static inline uint8_t dasharo_ec_read(uint8_t addr)
+{
+	return inb(DASHARO_EC_BASE + (uint16_t)addr);
+}
+
+static inline void dasharo_ec_write(uint8_t addr, uint8_t data)
+{
+	outb(data, DASHARO_EC_BASE + (uint16_t)addr);
+}
+
+void dasharo_ec_init(void)
+{
+	// Clear entire command region
+	for (int i = 0; i < DASHARO_EC_SIZE; i++)
+		dasharo_ec_write((uint8_t)i, 0);
+}
+
+void dasharo_ec_flush(void)
+{
+	dasharo_ec_write(REG_CMD, CMD_PRINT);
+
+	// Wait for command completion, for up to 10 milliseconds, with a
+	// test period of 1 microsecond
+	wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED);
+
+	dasharo_ec_write(CMD_PRINT_REG_LEN, 0);
+}
+
+void dasharo_ec_print(uint8_t byte)
+{
+	uint8_t len = dasharo_ec_read(CMD_PRINT_REG_LEN);
+	dasharo_ec_write(CMD_PRINT_REG_DATA + len, byte);
+	dasharo_ec_write(CMD_PRINT_REG_LEN, len + 1);
+
+	// If we hit the end of the buffer, or were given a newline, flush
+	if (byte == '\n' || len >= (DASHARO_EC_SIZE - CMD_PRINT_REG_DATA))
+		dasharo_ec_flush();
+}
+
+bool dasharo_ec_cmd(uint8_t cmd, const uint8_t *request_data,
+	uint8_t request_size, uint8_t *reply_data, uint8_t reply_size)
+{
+	if (request_size > DASHARO_EC_SIZE - REG_DATA ||
+		reply_size > DASHARO_EC_SIZE - REG_DATA) {
+		printk(BIOS_ERR, "EC command %d too long - request size %u, reply size %u\n",
+			cmd, request_size, reply_size);
+		return false;
+	}
+
+	/* If any data were buffered by dasharo_ec_print(), flush it first */
+	uint8_t buffered_len = dasharo_ec_read(CMD_PRINT_REG_LEN);
+	if (buffered_len > 0)
+		dasharo_ec_flush();
+
+	/* Write the data */
+	uint8_t i;
+	for (i = 0; i < request_size; ++i)
+		dasharo_ec_write(REG_DATA + i, request_data[i]);
+
+	/* Write the command */
+	dasharo_ec_write(REG_CMD, cmd);
+
+	/* Wait for the command to complete */
+	bool ret = true;
+	int elapsed = wait_ms(1000, dasharo_ec_read(REG_CMD) == CMD_FINISHED);
+	if (elapsed == 0) {
+		/* Timed out: fail the command, don't attempt to read a reply. */
+		printk(BIOS_WARNING, "EC command %d timed out - request size %d, reply size %d\n",
+			cmd, request_size, reply_size);
+		ret = false;
+	} else {
+		/* Read the reply */
+		for (i = 0; i < reply_size; ++i)
+			reply_data[i] = dasharo_ec_read(REG_DATA+i);
+		/* Check the reply status */
+		ret = (dasharo_ec_read(REG_RESULT) == RESULT_OK);
+	}
+
+	/* Reset the flags and length so we can buffer console prints again */
+	dasharo_ec_write(CMD_PRINT_REG_FLAGS, 0);
+	dasharo_ec_write(CMD_PRINT_REG_LEN, 0);
+
+	return ret;
+}

src/ec/dasharo/ec/dasharo_ec.h

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DASHARO_EC_H
+#define DASHARO_EC_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/*
+ * Send a command to the EC.  request_data/request_size are the request payload,
+ * request_data can be NULL if request_size is 0.  reply_data/reply_size are
+ * the reply payload, reply_data can be NULL if reply_size is 0.
+ */
+bool dasharo_ec_cmd(uint8_t cmd, const uint8_t *request_data,
+	uint8_t request_size, uint8_t *reply_data, uint8_t reply_size);
+
+#endif

src/ec/dasharo/ec/smbios.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <smbios.h>
+
+smbios_wakeup_type smbios_system_wakeup_type(void)
+{
+	// TODO: Read wake source from EC.
+	return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
+}

src/include/device_tree.h

@@ -129,6 +129,12 @@ u32 fdt_find_node_by_alias(const void *blob, const char *alias_name,
  */
 int fdt_next_node_name(const void *blob, uint32_t node_offset, const char **name);
 
+ /* Read memory regions from a flat device-tree. */
+size_t fdt_read_memory_regions(const void *blob, struct device_tree_region regions[],
+			       size_t regions_count);
+ /* Find top of memory from a flat device-tree. */
+uint64_t fdt_get_memory_top(const void *blob);
+
 /* Read a flattened device tree into a hierarchical structure which refers to
    the contents of the flattened tree in place. Modifying the flat tree
    invalidates the unflattened one. */

src/include/smbios.h

@@ -584,7 +584,13 @@ enum smbios_processor_upgrade_field {
 /* defines for processor family */
 #define SMBIOS_PROCESSOR_FAMILY_OTHER			0x01
 #define SMBIOS_PROCESSOR_FAMILY_UNKNOWN			0x02
+#define SMBIOS_PROCESSOR_FAMILY_INTEL486		0x06
+#define SMBIOS_PROCESSOR_FAMILY_PENTIUM_PRO		0x0c
 #define SMBIOS_PROCESSOR_FAMILY_XEON			0xb3
+#define SMBIOS_PROCESSOR_FAMILY_FROM_FAMILY2		0xfe
+
+/* defines for processor family 2 */
+#define SMBIOS_PROCESSOR_FAMILY2_ARMV8			0x101
 
 /* defines for processor characteristics */
 #define PROCESSOR_64BIT_CAPABLE				(1 << 2)

src/lib/Makefile.mk

@@ -160,10 +160,12 @@ ramstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
 ramstage-$(CONFIG_GENERIC_UDELAY) += timer.c
 ramstage-y += b64_decode.c
 ramstage-$(CONFIG_ACPI_NHLT) += nhlt.c
-ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c
 ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit.c
 ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c
 
+romstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c
+ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c
+
 romstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c
 ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c
 

src/lib/device_tree.c

@@ -12,9 +12,12 @@
 #include <string.h>
 #include <stddef.h>
 #include <stdlib.h>
+#include <limits.h>
 
 #define FDT_PATH_MAX_DEPTH 10 // should be a good enough upper bound
 #define FDT_PATH_MAX_LEN 128 // should be a good enough upper bound
+#define FDT_MAX_MEMORY_NODES 4 // should be a good enough upper bound
+#define FDT_MAX_MEMORY_REGIONS 16 // should be a good enough upper bound
 
 /*
  * Functions for picking apart flattened trees.
@@ -503,6 +506,96 @@ void fdt_print_node(const void *blob, uint32_t offset)
 	print_flat_node(blob, offset, 0);
 }
 
+/*
+ * fdt_read_memory_regions finds memory ranges from a flat device-tree
+ *
+ * @params blob	          address of FDT
+ * @params regions        all regions that are read inside the reg property of
+ *                        memory nodes are saved inside this array
+ * @params regions_count  maximum number of entries that can be saved inside
+ *                        the regions array.
+ *
+ * Returns: Either 0 on error or returns the number of regions put into the regions array.
+ */
+size_t fdt_read_memory_regions(const void *blob,
+			       struct device_tree_region regions[],
+			       size_t regions_count)
+{
+	u32 node, root, addrcp, sizecp;
+	u32 nodes[FDT_MAX_MEMORY_NODES] = {0};
+	size_t region_idx = 0;
+	size_t node_count = 0;
+
+	if (!fdt_is_valid(blob))
+		return 0;
+
+	node = fdt_find_node_by_path(blob, "/memory",  &addrcp, &sizecp);
+	if (node) {
+		region_idx += fdt_read_reg_prop(blob, node, addrcp, sizecp,
+						regions, regions_count);
+		if (region_idx >= regions_count) {
+			printk(BIOS_WARNING, "FDT: Too many memory regions\n");
+			goto out;
+		}
+	}
+
+	root = fdt_find_node_by_path(blob, "/",  &addrcp, &sizecp);
+	node_count = fdt_find_subnodes_by_prefix(blob, root, "memory@",
+						 &addrcp, &sizecp, nodes,
+						 FDT_MAX_MEMORY_NODES);
+	if (node_count >= FDT_MAX_MEMORY_NODES) {
+		printk(BIOS_WARNING, "FDT: Too many memory nodes\n");
+		/* Can still reading the regions for those we got */
+	}
+
+	for (size_t i = 0; i < MIN(node_count, FDT_MAX_MEMORY_NODES); i++) {
+		region_idx += fdt_read_reg_prop(blob, nodes[i], addrcp, sizecp,
+						&regions[region_idx],
+						regions_count - region_idx);
+		if (region_idx >= regions_count) {
+			printk(BIOS_WARNING, "FDT: Too many memory regions\n");
+			goto out;
+		}
+	}
+
+out:
+	for (size_t i = 0; i < MIN(region_idx, regions_count); i++) {
+		printk(BIOS_DEBUG, "FDT: Memory region [%#llx - %#llx]\n",
+		       regions[i].addr, regions[i].addr + regions[i].size);
+	}
+
+	return region_idx;
+}
+
+/*
+ * fdt_get_memory_top finds top of memory from a flat device-tree
+ *
+ * @params blob	          address of FDT
+ *
+ * Returns: Either 0 on error or returns the maximum memory address
+ */
+uint64_t fdt_get_memory_top(const void *blob)
+{
+	struct device_tree_region regions[FDT_MAX_MEMORY_REGIONS] = {0};
+	uint64_t top = 0;
+	uint64_t total = 0;
+	size_t count;
+
+	if (!fdt_is_valid(blob))
+		return 0;
+
+	count = fdt_read_memory_regions(blob, regions, FDT_MAX_MEMORY_REGIONS);
+	for (size_t i = 0; i < MIN(count, FDT_MAX_MEMORY_REGIONS); i++) {
+		top = MAX(top, regions[i].addr + regions[i].size);
+		total += regions[i].size;
+	}
+
+	printk(BIOS_DEBUG, "FDT: Found %u MiB of RAM\n",
+	       (uint32_t)(total / MiB));
+
+	return top;
+}
+
 /*
  * Functions to turn a flattened tree into an unflattened one.
  */
@@ -608,7 +701,7 @@ struct device_tree *fdt_unflatten(const void *blob)
 	const struct fdt_header *header = (const struct fdt_header *)blob;
 	tree->header = header;
 
-	if (fdt_is_valid(blob))
+	if (!fdt_is_valid(blob))
 		return NULL;
 
 	uint32_t struct_offset = be32toh(header->structure_offset);

src/mainboard/google/rex/Kconfig

@@ -122,6 +122,11 @@ config BOARD_GOOGLE_OVIS4ES
 config BOARD_GOOGLE_REX0
 	select BOARD_GOOGLE_MODEL_REX
 
+config BOARD_GOOGLE_REX64
+	select BOARD_GOOGLE_MODEL_REX
+	select HAVE_X86_64_SUPPORT
+	select USE_X86_64_SUPPORT
+
 config BOARD_GOOGLE_REX_EC_ISH
 	select BOARD_GOOGLE_MODEL_REX_EC_ISH
 
@@ -182,6 +187,7 @@ config MAINBOARD_FAMILY
 
 config MAINBOARD_PART_NUMBER
 	default "Rex" if BOARD_GOOGLE_REX0
+	default "Rex64" if BOARD_GOOGLE_REX64
 	default "Rex_Ec_Ish" if BOARD_GOOGLE_REX_EC_ISH
 	default "Rex4ES" if BOARD_GOOGLE_REX4ES
 	default "Rex4ES_Ec_Ish" if BOARD_GOOGLE_REX4ES_EC_ISH

src/mainboard/google/rex/Kconfig.name

@@ -32,6 +32,9 @@ config BOARD_GOOGLE_REX4ES
 config BOARD_GOOGLE_REX4ES_EC_ISH
 	bool "-> Rex4ES EC ISH"
 
+config BOARD_GOOGLE_REX64
+	bool "-> Rex 64"
+
 config BOARD_GOOGLE_SCREEBO
 	bool "->  Screebo"
 

src/mainboard/razer/blade_stealth_kbl/Kconfig

@@ -1,16 +1,12 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-if BOARD_RAZER_BLADE_STEALTH_KBL
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
+config BOARD_RAZER_BLADE_STEALTH_KBL
+	bool
 	select SYSTEM_TYPE_LAPTOP
 	select BOARD_ROMSIZE_KB_8192
 	select SUPERIO_ITE_IT8528E
 	select SOC_INTEL_KABYLAKE
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select MEMORY_MAPPED_TPM
-	select MAINBOARD_HAS_TPM2
 	select MAINBOARD_HAS_LIBGFXINIT
 	select HAVE_SPD_IN_CBFS
 	select DRIVERS_I2C_HID
@@ -18,6 +14,31 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_TABLES
 	select DRIVERS_GENERIC_CBFS_SERIAL
 
+config BOARD_RAZER_BLADE_H2U
+	select BOARD_RAZER_BLADE_STEALTH_KBL
+	select MEMORY_MAPPED_TPM
+	select MAINBOARD_HAS_TPM2
+
+config BOARD_RAZER_BLADE_H3Q
+	select BOARD_RAZER_BLADE_STEALTH_KBL
+
+if BOARD_RAZER_BLADE_STEALTH_KBL
+
+config VARIANT_DIR
+	default "h2u" if BOARD_RAZER_BLADE_H2U
+	default "h3q" if BOARD_RAZER_BLADE_H3Q
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config MAINBOARD_FAMILY
+	string
+	default "BLADE_STEALTH"
+
+config MAINBOARD_PART_NUMBER
+	default "H2U: RZ09-01962" if BOARD_RAZER_BLADE_H2U
+	default "H3Q: RZ09-01963/RZ09-01964" if BOARD_RAZER_BLADE_H3Q
+
 # For now no way to choose the correct the available RAM
 config BOARD_RAZER_BLADE_STEALTH_KBL_16GB
 	bool "16GB RAM (4x MT52L1G32D4PG)"
@@ -27,13 +48,6 @@ config VGA_BIOS_ID
 	string
 	default "8086,5916"
 
-config MAINBOARD_FAMILY
-	string
-	default "BLADE_STEALTH"
-
-config MAINBOARD_PART_NUMBER
-	default "H2U"
-
 config MAINBOARD_VERSION
 	string
 	default "1.0"

src/mainboard/razer/blade_stealth_kbl/Kconfig.name

@@ -1,4 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-config BOARD_RAZER_BLADE_STEALTH_KBL
-	bool "Razer Blade Stealth KabyLake (2016)"
+config BOARD_RAZER_BLADE_H2U
+	bool "Razer Blade Stealth KabyLake (2016, RZ09-01962, 12.5\")"
+
+config BOARD_RAZER_BLADE_H3Q
+	bool "Razer Blade Stealth KabyLake (Mid 2017, RZ09-01963/RZ09-10964, 13.3\")"

src/mainboard/razer/blade_stealth_kbl/Makefile.mk

@@ -3,6 +3,8 @@
 subdirs-y += spd
 
 ramstage-y += ramstage.c
-ramstage-y += hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

src/mainboard/razer/blade_stealth_kbl/board_info.txt

@@ -1,5 +1,5 @@
 Vendor name: RAZER
-Board name: Blade Stealth KabyLake (H2U)
+Board name: Blade Stealth KabyLake
 Category: laptop
 ROM package: SOIC8
 ROM protocol: SPI

src/mainboard/razer/blade_stealth_kbl/devicetree.cb

@@ -126,24 +126,6 @@ chip soc/intel/skylake
 
 	register "PcieRpHotPlug[4]" = "1"
 
-	register "usb2_ports" = "{
-		[0] = USB2_PORT_MID(OC1),	/* Type-A Port (right) */
-		[1] = USB2_PORT_MID(OC1),	/* Type-A Port (left) */
-		[2] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
-		[3] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
-		[4] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
-		[5] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
-		[6] = USB2_PORT_FLEX(OC2),	/* Camera */
-		[7] = USB2_PORT_FLEX(OC2),	/* Keyboard */
-		[8] = USB2_PORT_FLEX(OC2),	/* Touchscreen */
-	}"
-
-	register "usb3_ports" = "{
-		[0] = USB3_PORT_DEFAULT(OC1),	/* Type-A Port (left) */
-		[1] = USB3_PORT_DEFAULT(OC1),	/* Type-A Port (right) */
-		[5] = USB3_PORT_DEFAULT(OC1),	/* TODO Unknown. Maybe USBC? */
-	}"
-
 	# PL1 override 25W
 	# PL2 override 44W
 	register "power_limits_config" = "{
@@ -191,9 +173,6 @@ chip soc/intel/skylake
 		device ref pcie_rp5	on  end
 		device ref pcie_rp9	on  end
 		device ref lpc_espi	on
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
 			chip superio/ite/it8528e
 				device pnp 6e.1 off end
 				device pnp 6e.2 off end

src/mainboard/razer/blade_stealth_kbl/ramstage.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <soc/ramstage.h>
-#include "gpio.h"
+#include <variant/gpio.h>
 
 void mainboard_silicon_init_params(FSP_SIL_UPD *params)
 {

src/mainboard/razer/blade_stealth_kbl/spd/spd.h

@@ -4,7 +4,6 @@
 #define MAINBOARD_SPD_H
 
 #include <gpio.h>
-#include "../gpio.h"
 
 void mainboard_fill_dq_map_data(void *dq_map_ptr);
 void mainboard_fill_dqs_map_data(void *dqs_map_ptr);

src/mainboard/razer/blade_stealth_kbl/variants/h2u/board_info.txt

@@ -0,0 +1,9 @@
+Vendor name: RAZER
+Board name: Blade Stealth KabyLake (H2U: RZ09-01962)
+Board URL: https://mysupport.razer.com/app/answers/detail/a_id/3698/
+Category: laptop
+ROM package: SOIC8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2016

src/mainboard/razer/blade_stealth_kbl/variants/h2u/hda_verb.c

@@ -20,7 +20,7 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
 	AZALIA_PIN_CFG(0, 0x21, 0x03211020),
 
-	/* Intel, KabylakeHDMI */
+	/* Intel, Kaby Lake HDMI */
 	0x8086280b, /* Vendor ID */
 	0x80860101, /* Subsystem ID */
 	4, /* Number of entries */

src/mainboard/razer/blade_stealth_kbl/variants/h2u/overridetree.cb

@@ -0,0 +1,31 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC1),	/* Type-A Port (right) */
+				[1] = USB2_PORT_MID(OC1),	/* Type-A Port (left) */
+				[2] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
+				[3] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
+				[4] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
+				[5] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
+				[6] = USB2_PORT_FLEX(OC2),	/* Camera */
+				[7] = USB2_PORT_FLEX(OC2),	/* Keyboard */
+				[8] = USB2_PORT_FLEX(OC2),	/* Touchscreen */
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC1),	/* Type-A Port (left) */
+				[1] = USB3_PORT_DEFAULT(OC1),	/* Type-A Port (right) */
+				[5] = USB3_PORT_DEFAULT(OC1),	/* TODO Unknown. Maybe USBC? */
+			}"
+		end
+
+		device ref lpc_espi on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+	end
+end

src/mainboard/razer/blade_stealth_kbl/variants/h3q/board_info.txt

@@ -0,0 +1,9 @@
+Vendor name: RAZER
+Board name: Blade Stealth KabyLake (H3Q: RZ09-01963 / RZ09-01964)
+Board URL: https://mysupport.razer.com/app/answers/detail/a_id/3694/
+Category: laptop
+ROM package: SOIC8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2017

src/mainboard/razer/blade_stealth_kbl/variants/h3q/hda_verb.c

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC298 */
+	0x10ec0298, /* Vendor ID */
+	0x1a586753, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x1a586753),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4075812d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+
+	/* Intel, Kaby Lake HDMI */
+	0x8086280b, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+AZALIA_ARRAY_SIZES;

src/mainboard/razer/blade_stealth_kbl/variants/h3q/include/variant/gpio.h

@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CFG_GPIO_H
+#define CFG_GPIO_H
+
+#include <gpio.h>
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+	PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+	PAD_CFG_GPO(GPP_A11, 0, DEEP),
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_A14, 0, DEEP),
+	PAD_CFG_GPO(GPP_A15, 0, DEEP),
+	PAD_CFG_GPO(GPP_A16, 0, DEEP),
+	PAD_CFG_GPO(GPP_A17, 0, DEEP),
+	PAD_CFG_GPO(GPP_A18, 0, DEEP),
+	PAD_CFG_GPO(GPP_A19, 0, DEEP),
+	PAD_CFG_GPO(GPP_A20, 0, DEEP),
+	PAD_CFG_GPO(GPP_A21, 0, DEEP),
+	PAD_CFG_GPO(GPP_A22, 0, DEEP),
+	PAD_CFG_GPO(GPP_A23, 0, DEEP),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_GPO(GPP_B0, 0, DEEP),
+	PAD_CFG_GPO(GPP_B1, 0, DEEP),
+	PAD_CFG_GPO(GPP_B2, 0, DEEP),
+	PAD_CFG_GPO(GPP_B3, 0, DEEP),
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_B8, 0, DEEP),
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_B10, 0, DEEP),
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP),
+	PAD_CFG_GPO(GPP_B15, 0, DEEP),
+	PAD_CFG_GPO(GPP_B16, 0, DEEP),
+	PAD_CFG_GPO(GPP_B17, 0, DEEP),
+	PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),
+	PAD_NC(GPP_B19, NONE),
+	PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1),
+	PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),
+	PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+	PAD_CFG_GPI_APIC_LOW(GPP_C5, DN_20K, DEEP),
+	/* GPP_C6 - RESERVED */
+	/* GPP_C7 - RESERVED */
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C10, 0, DEEP),
+	PAD_CFG_GPO(GPP_C11, 0, DEEP),
+	PAD_CFG_GPO(GPP_C12, 0, DEEP),
+	PAD_CFG_GPO(GPP_C13, 0, DEEP),
+	PAD_CFG_GPO(GPP_C14, 0, DEEP),
+	PAD_CFG_GPO(GPP_C15, 0, DEEP),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C22, 0, DEEP),
+	PAD_CFG_GPO(GPP_C23, 0, DEEP),
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D0, 0, DEEP),
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
+	PAD_CFG_GPO(GPP_D3, 0, DEEP),
+	PAD_CFG_GPO(GPP_D4, 0, DEEP),
+	PAD_CFG_GPO(GPP_D5, 0, DEEP),
+	PAD_CFG_GPO(GPP_D6, 0, DEEP),
+	PAD_CFG_GPO(GPP_D7, 0, DEEP),
+	PAD_CFG_GPO(GPP_D8, 0, DEEP),
+	PAD_CFG_GPO(GPP_D9, 0, DEEP),
+	PAD_CFG_GPO(GPP_D10, 0, DEEP),
+	PAD_CFG_GPO(GPP_D11, 0, DEEP),
+	PAD_CFG_GPO(GPP_D12, 0, DEEP),
+	PAD_CFG_GPO(GPP_D13, 0, DEEP),
+	PAD_CFG_GPO(GPP_D14, 0, DEEP),
+	PAD_CFG_GPO(GPP_D15, 0, DEEP),
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),
+	PAD_CFG_GPO(GPP_D17, 0, DEEP),
+	PAD_CFG_GPO(GPP_D18, 0, DEEP),
+	PAD_CFG_GPO(GPP_D19, 0, DEEP),
+	PAD_CFG_GPO(GPP_D20, 0, DEEP),
+	PAD_CFG_GPO(GPP_D21, 0, DEEP),
+	PAD_CFG_GPO(GPP_D22, 0, DEEP),
+	PAD_CFG_GPO(GPP_D23, 0, DEEP),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),
+	PAD_CFG_GPO(GPP_E1, 0, DEEP),
+	PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E3, 0, DEEP),
+	PAD_CFG_GPO(GPP_E4, 0, DEEP),
+	PAD_CFG_GPI_SCI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	PAD_CFG_GPO(GPP_E6, 0, DEEP),
+	PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI),
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E9, 0, DEEP),
+	PAD_CFG_TERM_GPO(GPP_E10, 1, DN_20K, DEEP),
+	PAD_CFG_TERM_GPO(GPP_E11, 1, DN_20K, DEEP),
+	PAD_NC(GPP_E12, NONE),
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT),
+	PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT),
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E22, 0, DEEP),
+	PAD_CFG_TERM_GPO(GPP_E23, 0, DN_20K, PLTRST),
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* -------- GPIO Group GPD -------- */
+	PAD_CFG_NF(GPD0, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD1, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD2, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD7, 0, DEEP),
+	PAD_NC(GPD8, NONE),
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_GPO(GPP_F0, 0, DEEP),
+	PAD_CFG_GPO(GPP_F1, 0, DEEP),
+	PAD_CFG_GPO(GPP_F2, 0, DEEP),
+	PAD_CFG_GPO(GPP_F3, 0, DEEP),
+	PAD_CFG_GPO(GPP_F4, 0, DEEP),
+	PAD_CFG_GPO(GPP_F5, 0, DEEP),
+	PAD_CFG_GPO(GPP_F6, 0, DEEP),
+	PAD_CFG_GPO(GPP_F7, 0, DEEP),
+	PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+	PAD_CFG_GPO(GPP_F11, 0, DEEP),
+	PAD_CFG_GPO(GPP_F12, 0, DEEP),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_F17, 0, DEEP),
+	PAD_CFG_GPO(GPP_F18, 0, DEEP),
+	PAD_CFG_GPO(GPP_F19, 0, DEEP),
+	PAD_CFG_GPO(GPP_F20, 0, DEEP),
+	PAD_CFG_GPO(GPP_F21, 0, DEEP),
+	PAD_CFG_GPO(GPP_F22, 0, DEEP),
+	PAD_CFG_GPO(GPP_F23, 0, DEEP),
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_CFG_GPO(GPP_G0, 0, DEEP),
+	PAD_CFG_GPO(GPP_G1, 0, DEEP),
+	PAD_CFG_GPO(GPP_G2, 0, DEEP),
+	PAD_CFG_GPO(GPP_G3, 0, DEEP),
+	PAD_CFG_GPO(GPP_G4, 0, DEEP),
+	PAD_CFG_GPO(GPP_G5, 0, DEEP),
+	PAD_CFG_GPO(GPP_G6, 0, DEEP),
+	PAD_CFG_GPO(GPP_G7, 0, DEEP),
+};
+
+#endif /* CFG_GPIO_H */

src/mainboard/razer/blade_stealth_kbl/variants/h3q/overridetree.cb

@@ -0,0 +1,23 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+	device domain 0 on
+		device ref south_xhci on
+			# NOTE: TYPE-C port is controlled by Intel Thunderbolt
+
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC0),	/* Type-A Port (right) */
+				[1] = USB2_PORT_MID(OC0),	/* Type-A Port (left) */
+				[5] = USB2_PORT_SHORT(OC2),	/* M.2 Slot (Bluetooth) */
+				[6] = USB2_PORT_FLEX(OC3),	/* Camera */
+				[7] = USB2_PORT_FLEX(OC3),	/* Keyboard */
+				[8] = USB2_PORT_FLEX(OC_SKIP),	/* Touchscreen */
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),	/* Type-A Port (left) */
+				[1] = USB3_PORT_DEFAULT(OC0),	/* Type-A Port (right) */
+			}"
+		end
+	end
+end

src/mainboard/system76/addw1/devicetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/cannonlake
 	register "common_soc_config" = "{
 		// Touchpad I2C bus

src/mainboard/system76/addw1/variants/addw1/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/cannonlake
 	# Serial I/O
 	register "SerialIoDevMode" = "{

src/mainboard/system76/addw1/variants/addw2/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/cannonlake
 	# Serial I/O
 	register "SerialIoDevMode" = "{

src/mainboard/system76/adl/devicetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/alderlake
 	register "common_soc_config" = "{
 		// Touchpad I2C bus

src/mainboard/system76/adl/variants/darp8/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/alderlake
 	register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
 		.tdp_pl1_override = 20,

src/mainboard/system76/adl/variants/galp6/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/alderlake
 	register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
 		.tdp_pl1_override = 28,

src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/alderlake
 	# FIVR configuration
 	#   Read EXT_RAIL_CONFIG to determine bitmaps

src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/alderlake
 	# FIVR configuration
 	#   Read EXT_RAIL_CONFIG to determine bitmaps

src/mainboard/system76/adl/variants/lemp11/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/alderlake
 	register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{
 		.tdp_pl1_override = 15,

src/mainboard/system76/adl/variants/oryp10/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/alderlake
 	register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
 		.tdp_pl1_override = 45,

src/mainboard/system76/adl/variants/oryp9/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/alderlake
 	register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
 		.tdp_pl1_override = 45,

src/mainboard/system76/bonw14/devicetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/cannonlake
 	register "common_soc_config" = "{
 		// Touchpad I2C bus

src/mainboard/system76/cml-u/devicetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/cannonlake
 	register "common_soc_config" = "{
 		/* Touchpad */

src/mainboard/system76/cml-u/variants/darp6/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/cannonlake
 	device domain 0 on
 		subsystemid 0x1558 0x1404 inherit

src/mainboard/system76/cml-u/variants/galp4/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/cannonlake
 	device domain 0 on
 		subsystemid 0x1558 0x1403 inherit

src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/cannonlake
 	device domain 0 on
 		subsystemid 0x1558 0x1401 inherit

src/mainboard/system76/gaze15/devicetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/cannonlake
 	register "common_soc_config" = "{
 		// Touchpad I2C bus

src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/cannonlake
 	# Serial I/O
 	register "SerialIoDevMode" = "{

src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/cannonlake
 	# Serial I/O
 	register "SerialIoDevMode" = "{

src/mainboard/system76/kbl-u/devicetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/skylake
 	# Send an extra VR mailbox command for the PS4 exit issue
 	register "SendVrMbxCmd" = "2"

src/mainboard/system76/kbl-u/variants/galp2/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/skylake
 	device domain 0 on
 		subsystemid 0x1558 0x1303 inherit

src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/skylake
 	device domain 0 on
 		subsystemid 0x1558 0x1413 inherit

src/mainboard/system76/kbl-u/variants/galp3/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/skylake
 	device domain 0 on
 		subsystemid 0x1558 0x1313 inherit

src/mainboard/system76/mtl/Kconfig

@@ -0,0 +1,96 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_SYSTEM76_MTL_COMMON
+	def_bool n
+	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_GENERIC_BAYHUB_LV2
+	select DRIVERS_GENERIC_CBFS_SERIAL
+	select DRIVERS_GENERIC_CBFS_UUID
+	select DRIVERS_I2C_HID
+	select EC_SYSTEM76_EC
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_SUPPORT_RESIZABLE_BARS
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_CRASHLOG
+	select SOC_INTEL_METEORLAKE
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+
+config BOARD_SYSTEM76_DARP10
+	select BOARD_SYSTEM76_MTL_COMMON
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SOC_INTEL_METEORLAKE_U_H
+
+config BOARD_SYSTEM76_DARP10_B
+	select BOARD_SYSTEM76_MTL_COMMON
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SOC_INTEL_METEORLAKE_U_H
+
+if BOARD_SYSTEM76_MTL_COMMON
+
+config MAINBOARD_DIR
+	default "system76/mtl"
+
+config VARIANT_DIR
+	default "darp10" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config MAINBOARD_PART_NUMBER
+	default "darp10" if BOARD_SYSTEM76_DARP10
+	default "darp10-b" if BOARD_SYSTEM76_DARP10_B
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Darter Pro" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B
+
+config MAINBOARD_VERSION
+	default "darp10" if BOARD_SYSTEM76_DARP10
+	default "darp10-b" if BOARD_SYSTEM76_DARP10_B
+
+config CMOS_DEFAULT_FILE
+	default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
+
+config CONSOLE_POST
+	default y
+
+config D3COLD_SUPPORT
+	default n
+
+config DIMM_SPD_SIZE
+	default 1024
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
+
+config ONBOARD_VGA_IS_PRIMARY
+	default y
+
+config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS
+	default 36
+
+config POST_DEVICE
+	default n
+
+config TPM_MEASURED_BOOT
+	default y
+
+config UART_FOR_CONSOLE
+	default 0
+
+# PM Timer Disabled, saves power
+config USE_PM_ACPI_TIMER
+	default n
+
+endif

src/mainboard/system76/mtl/Kconfig.name

@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_SYSTEM76_DARP10
+	bool "darp10"
+
+config BOARD_SYSTEM76_DARP10_B
+	bool "darp10-b"

src/mainboard/system76/mtl/Makefile.mk

@@ -0,0 +1,14 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
+bootblock-y += bootblock.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
+
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
+
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
+ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c

src/mainboard/system76/mtl/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		100, /* default AC */
+		100, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/mtl/acpi/mainboard.asl

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SCI 0x6E
+#define EC_GPE_SWI 0x6B
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
+}

src/mainboard/system76/mtl/acpi/sleep.asl

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+External(\TBTS, MethodObj)
+
+Method(MPTS, 1, Serialized) {
+	If (CondRefOf(\TBTS)) {
+		\TBTS()
+	}
+}

src/mainboard/system76/mtl/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: System76
+Category: laptop
+ROM package: WSON-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/mtl/bootblock.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <mainboard/gpio.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	mainboard_configure_early_gpios();
+}

src/mainboard/system76/mtl/cmos.default

@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+boot_option=Fallback
+debug_level=Debug
+me_state=Disable

src/mainboard/system76/mtl/cmos.layout

@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+entries
+
+0	384	r	0	reserved_memory
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# RTC_CLK_ALTCENTURY
+400	8	r	0	century
+
+412	4	e	6	debug_level
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+
+# CMOS_VSTART_ramtop
+800	80	r	0	ramtop
+
+984	16	h	0	check_sum
+
+enumerations
+
+2	0	Enable
+2	1	Disable
+
+4	0	Fallback
+4	1	Normal
+
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+
+checksums
+
+checksum 408 799 984

src/mainboard/system76/mtl/devicetree.cb

@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/meteorlake
+	register "common_soc_config" = "{
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+	# Thermal
+	register "tcc_offset" = "8"
+
+	device cpu_cluster 0 on end
+
+	device domain 0 on
+		device ref system_agent on end
+		device ref igpu on
+			# DDIA is eDP, TCP2 is HDMI
+			register "ddi_port_A_config" = "1"
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A] = DDI_ENABLE_HPD,
+				[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			}"
+
+			#register "gfx" = "GMA_DEFAULT_PANEL(0)"
+		end
+		device ref ioe_shared_sram on end
+		device ref pmc_shared_sram on end
+		device ref cnvi_wifi on
+			register "cnvi_bt_core" = "true"
+			register "cnvi_bt_audio_offload" = "true"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c1 on
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+		end
+
+		device ref heci1 on end
+		device ref soc_espi on
+			register "gen1_dec" = "0x00040069" # EC PM channel
+			register "gen2_dec" = "0x00fc0e01" # AP/EC command
+			register "gen3_dec" = "0x00fc0f01" # AP/EC debug
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device ref p2sb on end
+		device ref hda on
+			register "pch_hda_audio_link_hda_enable" = "1"
+			register "pch_hda_sdi_enable[0]" = "1"
+			register "pch_hda_idisp_codec_enable" = "1"
+			register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+			register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+		end
+		device ref smbus on end
+		device ref fast_spi on end
+	end
+end

src/mainboard/system76/mtl/dsdt.asl

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+//TODO: HACK FOR MISSING MISCCFG_GPIO_PM_CONFIG_BITS
+#include <soc/gpio.h>
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/meteorlake/acpi/southbridge.asl>
+		#include <soc/intel/meteorlake/acpi/tcss.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/system76/mtl/include/mainboard/gpio.h

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_configure_early_gpios(void);
+void mainboard_configure_gpios(void);
+
+#endif

src/mainboard/system76/mtl/ramstage.c

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/ramstage.h>
+
+static void mainboard_init(void *chip_info)
+{
+	mainboard_configure_gpios();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};

src/mainboard/system76/mtl/variants/darp10/board.fmd

@@ -0,0 +1,13 @@
+FLASH 32M {
+	SI_DESC 16K
+	SI_GBE 8K
+	SI_ME 10640K
+	SI_BIOS@16M 16M {
+		RW_MRC_CACHE 64K
+		SMMSTORE(PRESERVE) 256K
+		WP_RO {
+			FMAP 4K
+			COREBOOT(CBFS)
+		}
+	}
+}

src/mainboard/system76/mtl/variants/darp10/board_info.txt

@@ -0,0 +1,2 @@
+Board name: darp10
+Release year: 2024

src/mainboard/system76/mtl/variants/darp10/gpio.c

@@ -0,0 +1,216 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET_N
+	// GPP_A07 missing
+	// GPP_A08 missing
+	// GPP_A09 missing
+	// GPP_A10 missing
+	PAD_CFG_GPO(GPP_A11, 0, DEEP), // ADDS_CODE
+	PAD_CFG_GPI(GPP_A12, NONE, DEEP), // WLAN_WAKEUP#
+	PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), // M2_SSD2_RST#
+	PAD_NC(GPP_A14, NONE),
+	PAD_NC(GPP_A15, NONE), // CPU_SWI# (test point)
+	PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+	PAD_NC(GPP_A17, NONE), // TP_ATTN#_A17
+	PAD_NC(GPP_A18, NONE),
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), // PMC_I2C_INT
+
+	PAD_CFG_GPI_INT(GPP_B00, NONE, PLTRST, LEVEL), // TP_ATTN#_B00
+	PAD_NC(GPP_B01, NONE),
+	PAD_NC(GPP_B02, NONE),
+	PAD_NC(GPP_B03, NONE),
+	PAD_CFG_GPO(GPP_B04, 0, DEEP), // NO REBOOT strap
+	PAD_CFG_GPO(GPP_B05, 0, DEEP), // CPU_KBCRST# (test point)
+	PAD_CFG_GPO(GPP_B06, 0, DEEP), // ROM_I2C_EN
+	PAD_NC(GPP_B07, NONE),
+	PAD_NC(GPP_B08, NONE),
+	PAD_NC(GPP_B09, NONE),
+	PAD_NC(GPP_B10, NONE),
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), // HDMI_HPD
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLTRST#
+	PAD_CFG_GPI(GPP_B14, NONE, DEEP), // Top swap override strap
+	PAD_CFG_GPI(GPP_B15, NONE, DEEP), // GPP_B15_USB2_OC0_N
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_GPO(GPP_B18, 1, DEEP), // PCH_BT_EN
+	PAD_CFG_GPO(GPP_B19, 1, DEEP), // WIFI_RF_EN
+	PAD_NC(GPP_B20, NONE),
+	PAD_CFG_GPO(GPP_B21, 0, PLTRST), // TCP_RETIMER_FORCE_PWR
+	PAD_NC(GPP_B22, NONE),
+	PAD_NC(GPP_B23, NONE),
+
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1), // TLS confidentiality strap
+	PAD_CFG_NF(GPP_C03, UP_20K, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_C04, UP_20K, DEEP, NF1), // SML0_DATA
+	PAD_CFG_NF(GPP_C05, UP_20K, DEEP, NF1), // eSPI disabled strap
+	PAD_CFG_NF(GPP_C06, UP_20K, DEEP, NF1), // PMC_I2C_SCL
+	PAD_CFG_NF(GPP_C07, UP_20K, DEEP, NF1), // PMC_I2C_SDA
+	PAD_NC(GPP_C08, NONE),
+	PAD_NC(GPP_C09, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_CFG_NF(GPP_C11, NONE, PWROK, NF1), // CPU_LAN_CLKREQ#
+	PAD_CFG_NF(GPP_C12, NONE, PWROK, NF1), // CPU_CARD_CLKREQ#
+	PAD_NC(GPP_C13, NONE),
+	// GPP_C14 missing
+	PAD_CFG_GPO(GPP_C15, 0, DEEP), // GPP_C15_STRAP
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // TBT_LSX0_TXD
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // TBT_LSX0_RXD
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF2), // HDMI_CTRLCLK
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF2), // HDMI_CTRLDATA
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+
+	PAD_CFG_GPO(GPP_D00, 1, DEEP), // SB_BLON
+	PAD_CFG_GPO(GPP_D01, 1, DEEP), // SSD2_PWR_EN
+	PAD_CFG_GPO(GPP_D02, 1, DEEP), // M2_SSD1_RST#
+	PAD_NC(GPP_D03, NONE),
+	PAD_NC(GPP_D04, NONE),
+	PAD_CFG_GPO(GPP_D05, 1, DEEP), // SSD1_PWR_EN
+	PAD_NC(GPP_D06, NONE),
+	PAD_NC(GPP_D07, NONE),
+	PAD_NC(GPP_D08, NONE),
+	PAD_NC(GPP_D09, NONE),
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE
+	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), // HDA_SDI0
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_CFG_GPO(GPP_D16, 0, DEEP), // GPIO_SPK_MUTE
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), // HDA_RST#
+	PAD_NC(GPP_D18, NONE),
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // CPU_SSD1_CLKREQ#
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // CPU_SSD2_CLKREQ#
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), // CPU_WLAN_CLKREQ#
+	PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1),
+
+	PAD_NC(GPP_E00, NONE),
+	_PAD_CFG_STRUCT(GPP_E01, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_CFG_GPI(GPP_E02, NONE, DEEP), // BOARD_ID4
+	PAD_CFG_GPI(GPP_E03, NONE, DEEP), // CNVI_WAKE#
+	PAD_NC(GPP_E04, NONE),
+	PAD_NC(GPP_E05, NONE),
+	PAD_CFG_GPO(GPP_E06, 0, DEEP), // JTAG ODT disable strap
+	PAD_NC(GPP_E07, NONE),
+	PAD_NC(GPP_E08, NONE),
+	PAD_CFG_GPI(GPP_E09, NONE, DEEP), // GPP_E9_USB2_OC0_N
+	PAD_NC(GPP_E10, NONE),
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID6
+	PAD_NC(GPP_E12, NONE),
+	PAD_NC(GPP_E13, NONE),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
+	PAD_NC(GPP_E15, NONE),
+	PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), // VRALERT#
+	PAD_CFG_GPO(GPP_E17, 0, DEEP), // BOARD_ID5
+	// GPP_E18 missing
+	// GPP_E19 missing
+	// GPP_E20 missing
+	// GPP_E21 missing
+	PAD_CFG_GPO(GPP_E22, 0, DEEP), // DNX_FORCE_RELOAD
+
+	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), // CNVI_RST#
+	PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), // CNVI_CLKREQ
+	PAD_CFG_GPO(GPP_F06, 0, DEEP), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F07, NONE),
+	PAD_NC(GPP_F08, NONE),
+	PAD_CFG_GPI(GPP_F09, NONE, DEEP), // TPM_DET
+	PAD_NC(GPP_F10, NONE),
+	PAD_CFG_GPO(GPP_F11, 0, DEEP), // BOARD_ID3
+	PAD_NC(GPP_F12, NONE), // I2C_SCL_CODEC
+	PAD_NC(GPP_F13, NONE), // I2C_SDA_CODEC
+	PAD_CFG_GPO(GPP_F14, 0, DEEP), // BOARD_ID1
+	PAD_CFG_GPO(GPP_F15, 0, DEEP), // BOARD_ID2
+	PAD_NC(GPP_F16, NONE),
+	PAD_NC(GPP_F17, NONE),
+	PAD_CFG_GPO(GPP_F18, 0, DEEP), // CPU_CCD_WP#
+	PAD_NC(GPP_F19, NONE),
+	PAD_CFG_GPO(GPP_F20, 0, DEEP), // SVID support strap
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	PAD_CFG_GPO(GPP_H00, 0, DEEP), // eSPI flash sharing mode strap
+	PAD_CFG_GPO(GPP_H01, 0, DEEP), // SPI flash descriptor recovery strap
+	PAD_NC(GPP_H02, NONE),
+	// GPP_H03 missing
+	PAD_CFG_GPO(GPP_H04, 0, DEEP), // CNVI_MFUART2_RXD
+	PAD_CFG_GPO(GPP_H05, 0, DEEP), // CNVI_MFUART2_TXD
+	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), // I2C3_SDA (Pantone)
+	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), // I2C3_SCL (Pantone)
+	// GPP_H08 (UART0_RXD) configured in bootblock
+	// GPP_H09 (UART0_TXD) configured in bootblock
+	PAD_CFG_GPO(GPP_H10, 0, DEEP),
+	PAD_CFG_GPO(GPP_H11, 0, DEEP),
+	PAD_CFG_GPO(GPP_H12, 0, DEEP),
+	PAD_NC(GPP_H13, NONE),
+	PAD_NC(GPP_H14, NONE),
+	PAD_NC(GPP_H15, NONE),
+	PAD_NC(GPP_H16, NONE),
+	PAD_NC(GPP_H17, NONE),
+	// GPP_H18 missing
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // I2C_SDA_TP
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // I2C_SCL_TP
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), // PCH_I2C_SDA
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), // PCH_I2C_SCL
+
+	PAD_NC(GPP_S00, NONE),
+	PAD_NC(GPP_S01, NONE),
+	PAD_NC(GPP_S02, NONE), // DMIC_CLK_A1
+	PAD_NC(GPP_S03, NONE), // DMIC_DATA_A1
+	PAD_NC(GPP_S04, NONE),
+	PAD_NC(GPP_S05, NONE),
+	PAD_NC(GPP_S06, NONE),
+	PAD_NC(GPP_S07, NONE),
+
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), // AC_PRESENT
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), // LAN_WAKEUP#
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPP_V05, UP_20K, DEEP, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPP_V06, NATIVE, DEEP, NF1), // SLP_A#
+	// GPP_V07 missing
+	PAD_CFG_NF(GPP_V08, UP_20K, DEEP, NF1), // SUS_CLK
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), // SLP_WLAN#
+	PAD_NC(GPP_V10, NONE),
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), // LANPHYPC
+	PAD_CFG_GPO(GPP_V12, 0, DEEP), // SLP_LAN#
+	// GPP_V13 missing
+	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), // PCIE_WAKE#
+	// GPP_V15 missing
+	// GPP_V16 missing
+	// GPP_V17 missing
+	// GPP_V18 missing
+	// GPP_V19 missing
+	// GPP_V20 missing
+	// GPP_V21 missing
+	PAD_NC(GPP_V22, NONE),
+	PAD_NC(GPP_V23, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/mtl/variants/darp10/gpio_early.c

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/system76/mtl/variants/darp10/hda_verb.c

@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC245 */
+	0x10ec0245, /* Vendor ID */
+	0x1558a763, /* Subsystem ID */
+	40, /* Number of entries */
+	//AZALIA_SUBVENDOR(0, 0x1558a763),
+	AZALIA_SUBVENDOR(0, 0x1558a743),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40789b2d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+
+	0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b,
+	0x0205004a, 0x02042010, 0x02050038, 0x02047909,
+	0x05c50000, 0x05c43d82, 0x05c50000, 0x05c43d82,
+	0x05350000, 0x0534201a, 0x05350000, 0x0534201a,
+	0x0535001d, 0x05340800, 0x0535001e, 0x05340800,
+	0x05350003, 0x05341ec4, 0x05350004, 0x05340000,
+	0x05450000, 0x05442000, 0x0545001d, 0x05440800,
+	0x0545001e, 0x05440800, 0x05450003, 0x05441ec4,
+	0x05450004, 0x05440000, 0x05350000, 0x0534a01a,
+	0x0205003c, 0x0204f175, 0x0205003c, 0x0204f135,
+	0x02050040, 0x02048800, 0x05a50001, 0x05a4001f,
+	0x02050010, 0x02040020, 0x02050010, 0x02040020,
+	0x0205006b, 0x0204a390, 0x0205006b, 0x0204a390,
+	0x0205006c, 0x02040c9e, 0x0205006d, 0x02040c00,
+	0x00170500, 0x00170500, 0x05a50004, 0x05a40113,
+	0x02050008, 0x02046a8c, 0x02050076, 0x0204f000,
+	0x0205000e, 0x020465c0, 0x02050033, 0x02048580,
+	0x02050069, 0x0204fda8, 0x02050068, 0x02040000,
+	0x02050003, 0x02040002, 0x02050069, 0x02040000,
+	0x02050068, 0x02040001, 0x0205002e, 0x0204290e,
+	0x02236100, 0x02235100, 0x00920011, 0x00970610,
+	0x00936000, 0x00935000, 0x0205000d, 0x0204a020,
+	0x00220011, 0x00270610, 0x0023a046, 0x00239046,
+	0x0173b000, 0x01770740, 0x05a50001, 0x05a4001f,
+	0x05c5000f, 0x05c40003, 0x02050036, 0x020437d7,
+	0x0143b000, 0x01470740, 0x02050010, 0x02040020,
+	0x01470c02, 0x01470c02,
+
+	// XXX: Duplicate last 2 u32s to keep in 4-dword blocks
+	0x01470c02, 0x01470c02,
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/mtl/variants/darp10/overridetree.cb

@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/meteorlake
+	device domain 0 on
+		subsystemid 0x1558 0xa743 inherit
+
+		device ref tbt_pcie_rp0 on end
+		device ref tcss_xhci on end
+		device ref tcss_dma0 on end
+		device ref xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC_SKIP),	/* J_AUD1 / AJ_USB3_1 */
+				[1] = USB2_PORT_MID(OC_SKIP),	/* J_TYPEC1 */
+				[2] = USB2_PORT_MID(OC_SKIP),	/* J_USB3_1 */
+				[5] = USB2_PORT_MID(OC_SKIP),	/* TBT */
+				[6] = USB2_PORT_MID(OC_SKIP),	/* Camera */
+				[9] = USB2_PORT_MID(OC_SKIP),	/* Bluetooth */
+			}"
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC_SKIP),	/* J_AUD1 / AJ_USB3_1 */
+				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* J_USB3_1 */
+			}"
+		end
+		device ref i2c0 on
+			# Touchpad I2C bus
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+		device ref pcie_rp5 on
+			# GLAN
+			register "pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,
+			}"
+			register "pcie_clk_config_flag[2]" = "PCIE_CLK_FREE_RUNNING"
+			device pci 00.0 on end
+		end
+		device ref pcie_rp6 on
+			# Card Reader
+			register "pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp8 on
+			# WLAN
+			register "pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp10 on
+			# SSD2
+			# XXX: Schematics show RP[13:16] used
+			register "pcie_rp[PCH_RP(10)]" = "{
+				.clk_src = 8,
+				.clk_req = 8,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp11 on
+			# SSD1
+			# XXX: Schematics show RP[17:20] used
+			register "pcie_rp[PCH_RP(11)]" = "{
+				.clk_src = 7,
+				.clk_req = 7,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref hda on
+			subsystemid 0x1558 0xa763
+		end
+		device ref gbe on end
+	end
+end

src/mainboard/system76/mtl/variants/darp10/ramstage.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// XXX: Enabling C10 reporting causes system to constantly enter and
+	// exit opportunistic suspend when idle.
+	params->PchEspiHostC10ReportEnable = 0;
+}

src/mainboard/system76/mtl/variants/darp10/romstage.c

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR5,
+		.ect = true,
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = { .addr_dimm[0] = 0x50, },
+			[1] = { .addr_dimm[0] = 0x52, },
+		},
+	};
+	const bool half_populated = false;
+
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}

src/mainboard/system76/oryp5/devicetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/cannonlake
 	register "common_soc_config" = "{
 		// Touchpad I2C bus

src/mainboard/system76/oryp6/devicetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/cannonlake
 	register "common_soc_config" = "{
 		// Touchpad I2C bus

src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/cannonlake
 	device domain 0 on
 		subsystemid 0x1558 0x50d3 inherit

src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/cannonlake
 	device domain 0 on
 		subsystemid 0x1558 0x65e5 inherit

src/mainboard/system76/rpl/Kconfig.name

@@ -4,7 +4,7 @@ config BOARD_SYSTEM76_ADDW3
 	bool "addw3"
 
 config BOARD_SYSTEM76_ADDW4
-	bool "addw3"
+	bool "addw4"
 
 config BOARD_SYSTEM76_BONW15
 	bool "bonw15"

src/mainboard/system76/rpl/Makefile.mk

@@ -10,5 +10,6 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c
 ramstage-y += ramstage.c
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
 ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
 
 SPD_SOURCES = samsung-M425R1GB4BB0-CQKOD

src/mainboard/system76/rpl/devicetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/alderlake
 	register "common_soc_config" = "{
 		// Touchpad I2C bus

src/mainboard/system76/rpl/variants/addw3/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/alderlake
 	# Support 5600 MT/s memory
 	register "max_dram_speed_mts" = "5600"

src/mainboard/system76/rpl/variants/bonw15/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/alderlake
 	# Support 5600 MT/s memory
 	register "max_dram_speed_mts" = "5600"

src/mainboard/system76/rpl/variants/darp9/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/alderlake
 	register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{
 		.tdp_pl1_override = 20,

src/mainboard/system76/rpl/variants/galp7/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/alderlake
 	register "power_limits_config[RPL_P_682_642_482_45W_CORE]" = "{
 		.tdp_pl1_override = 45,

src/mainboard/system76/rpl/variants/gaze18/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/alderlake
 	device domain 0 on
 		subsystemid 0x1558 0x5630 inherit

src/mainboard/system76/rpl/variants/lemp12/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/alderlake
 	register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
 		.tdp_pl1_override = 15,

src/mainboard/system76/rpl/variants/oryp11/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/alderlake
 	device domain 0 on
 		subsystemid 0x1558 0x66a2 inherit

src/mainboard/system76/rpl/variants/serw13/overridetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/alderlake
 	# Support 5600 MT/s memory
 	register "max_dram_speed_mts" = "5600"

src/mainboard/system76/tgl-h/devicetree.cb

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
 chip soc/intel/tigerlake
 	register "common_soc_config" = "{
 		// Touchpad I2C bus