soc/intel/mtl: Hook up GMA ACPI brightness controls

Add function needed to generate ACPI backlight control SSDT, along with
Kconfig values for accessing the registers.

Change-Id: Ied08e5e9fe4913bd60474ed7dcf88b945172558d
Signed-off-by: Jeremy Soller <jeremy@sysetm76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>

src/soc/intel/common/block/cse/cse.c

@@ -11,7 +11,6 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <intelblocks/cse.h>
-#include <intelblocks/fast_spi.h>
 #include <intelblocks/me.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/post_codes.h>
@@ -1311,17 +1310,10 @@ static void cse_set_state(struct device *dev)
 
 	size_t enable_reply_size;
 
-	int send;
-	int result;
-
 	/* Function Start */
 
-	if (fast_spi_flash_descriptor_override()) {
-		printk(BIOS_WARNING, "HECI: not setting ME state because "
-			"flash descriptor override is enabled\n");
-		return;
-	}
-
+	int send;
+	int result;
 	/*
 	 * Check if the CMOS value "me_state" exists, if it doesn't, then
 	 * don't do anything.

src/soc/intel/common/block/cse/cse_eop.c

@@ -4,7 +4,6 @@
 #include <bootstate.h>
 #include <console/console.h>
 #include <intelblocks/cse.h>
-#include <intelblocks/fast_spi.h>
 #include <intelblocks/pmc_ipc.h>
 #include <security/vboot/vboot_common.h>
 #include <soc/intel/common/reset.h>
@@ -244,11 +243,6 @@ static void do_send_end_of_post(bool wait_for_completion)
 		return;
 	}
 
-	if (fast_spi_flash_descriptor_override()) {
-		printk(BIOS_WARNING, "CSE: not sending EOP because flash descriptor override is enabled\n");
-		return;
-	}
-
 	if (!eop_sent) {
 		set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE);
 		timestamp_add_now(TS_ME_END_OF_POST_START);

src/soc/intel/common/block/fast_spi/fast_spi.c

@@ -483,15 +483,6 @@ void fast_spi_clear_outstanding_status(void)
 	write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS);
 }
 
-/* Check if flash descriptor override is asserted */
-bool fast_spi_flash_descriptor_override(void)
-{
-	void *spibar = fast_spi_get_bar();
-	uint32_t hsfsts = read32(spibar + SPIBAR_HSFSTS_CTL);
-	printk(BIOS_DEBUG, "HSFSTS: 0x%X\n", hsfsts);
-	return !(hsfsts & SPIBAR_HSFSTS_FDOPSS);
-}
-
 
 /* As there is no official ACPI ID for this controller use the generic PNP ID for now. */
 static const char *fast_spi_acpi_hid(const struct device *dev)

src/soc/intel/common/block/include/intelblocks/fast_spi.h

@@ -111,7 +111,5 @@ void fast_spi_set_bde(void);
  * Set FAST_SPIBAR Vendor Component Lock bit.
  */
 void fast_spi_set_vcl(void);
-/* Check if flash descriptor override is asserted */
-bool fast_spi_flash_descriptor_override(void);
 
 #endif	/* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */

src/soc/intel/meteorlake/Kconfig

@@ -402,6 +402,18 @@ config BUILDING_WITH_DEBUG_FSP
 	help
 	  Set this option if debug build of FSP is used.
 
+config INTEL_GMA_BCLV_OFFSET
+	default 0xc8258
+
+config INTEL_GMA_BCLV_WIDTH
+	default 32
+
+config INTEL_GMA_BCLM_OFFSET
+	default 0xc8254
+
+config INTEL_GMA_BCLM_WIDTH
+	default 32
+
 config DROP_CPU_FEATURE_PROGRAM_IN_FSP
 	bool
 	default y if MP_SERVICES_PPI_V2_NOOP || CHROMEOS

src/soc/intel/meteorlake/Makefile.mk

@@ -37,6 +37,7 @@ ramstage-y += elog.c
 ramstage-y += espi.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
+ramstage-y += graphics.c
 ramstage-y += lockdown.c
 ramstage-y += p2sb.c
 ramstage-y += pcie_rp.c

src/soc/intel/meteorlake/chip.h

@@ -4,6 +4,7 @@
 #define _SOC_CHIP_H_
 
 #include <drivers/i2c/designware/dw_i2c.h>
+#include <drivers/intel/gma/gma.h>
 #include <device/pci_ids.h>
 #include <gpio.h>
 #include <intelblocks/cfg.h>
@@ -527,6 +528,9 @@ struct soc_intel_meteorlake_config {
 	 * as per `enum slew_rate` data type.
 	 */
 	uint8_t slow_slew_rate_config[NUM_VR_DOMAINS];
+
+	/* i915 struct for GMA backlight control */
+	struct i915_gpu_controller_info gfx;
 };
 
 typedef struct soc_intel_meteorlake_config config_t;

src/soc/intel/meteorlake/graphics.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <intelblocks/graphics.h>
+#include <soc/ramstage.h>
+
+const struct i915_gpu_controller_info *
+intel_igd_get_controller_info(const struct device *const dev)
+{
+	const struct soc_intel_meteorlake_config *const chip = dev->chip_info;
+	return &chip->gfx;
+}