intel/block/pcie/rtd3: Also implement _PR3

Change-Id: Id7f4373989dffe8c3bc68a034f59a94d2160dd15
Signed-off-by: Jeremy Soller <jeremy@system76.com>

src/mainboard/google/brya/variants/nova/overridetree.cb

@@ -6,8 +6,6 @@ chip soc/intel/alderlake
 	register "sagv" = "SaGv_Enabled"
 
 	register "usb2_ports[1]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 1
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A3
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A2
 	register "usb2_ports[4]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 4
 	register "usb2_ports[5]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 5
 	register "usb2_ports[6]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 6

src/soc/intel/common/block/crashlog/crashlog.c

@@ -112,7 +112,7 @@ int cpu_cl_poll_mailbox_ready(u32 cl_mailbox_addr)
 	u16 stall_cnt = 0;
 
 	do {
-		cl_mailbox_interface.data = read32((u32 *)(uintptr_t)cl_mailbox_addr);
+		cl_mailbox_interface.data = read32((u32 *)cl_mailbox_addr);
 		udelay(CPU_CRASHLOG_WAIT_STALL);
 		stall_cnt++;
 	} while ((cl_mailbox_interface.fields.busy == 1)
@@ -140,7 +140,7 @@ int cpu_cl_mailbox_cmd(u8 cmd, u8 param)
 	cl_mailbox_intf.fields.param = param;
 	cl_mailbox_intf.fields.busy = 1;
 
-	write32((u32 *)(uintptr_t)(cl_base_addr + cl_get_cpu_mb_int_addr()),
+	write32((u32 *)(cl_base_addr + cl_get_cpu_mb_int_addr()),
 		cl_mailbox_intf.data);
 
 	cpu_cl_poll_mailbox_ready(cl_base_addr + cl_get_cpu_mb_int_addr());
@@ -167,7 +167,7 @@ int pmc_cl_gen_descriptor_table(u32 desc_table_addr,
 				pmc_crashlog_desc_table_t *descriptor_table)
 {
 	int total_data_size = 0;
-	descriptor_table->numb_regions = read32((u32 *)(uintptr_t)desc_table_addr);
+	descriptor_table->numb_regions = read32((u32 *)desc_table_addr);
 	printk(BIOS_DEBUG, "CL PMC desc table: numb of regions is 0x%x at addr 0x%x\n",
 	       descriptor_table->numb_regions, desc_table_addr);
 	for (int i = 0; i < descriptor_table->numb_regions; i++) {
@@ -178,7 +178,7 @@ int pmc_cl_gen_descriptor_table(u32 desc_table_addr,
 			break;
 		}
 		desc_table_addr += 4;
-		descriptor_table->regions[i].data = read32((u32 *)(uintptr_t)(desc_table_addr));
+		descriptor_table->regions[i].data = read32((u32 *)(desc_table_addr));
 		total_data_size += descriptor_table->regions[i].bits.size * sizeof(u32);
 		printk(BIOS_DEBUG, "CL PMC desc table: region 0x%x has size 0x%x at offset 0x%x\n",
 			i, descriptor_table->regions[i].bits.size,
@@ -295,7 +295,7 @@ bool cl_copy_data_from_sram(u32 src_bar,
 
 	u32 src_addr = src_bar + offset;
 
-	u32 data =  read32((u32 *)(uintptr_t)src_addr);
+	u32 data =  read32((u32 *)src_addr);
 
 	/* First 32bits of the record must not be 0xdeadbeef */
 	if (data == INVALID_CRASHLOG_RECORD) {
@@ -320,7 +320,7 @@ bool cl_copy_data_from_sram(u32 src_bar,
 	u32 copied = 0;
 	while (copied < size) {
 		/* DW by DW copy: byte access to PMC SRAM not allowed */
-		*dest_addr = read32((u32 *)(uintptr_t)src_addr);
+		*dest_addr = read32((u32 *)src_addr);
 		dest_addr++;
 		src_addr += 4;
 		copied++;

src/soc/intel/common/block/cse/cse.c

@@ -11,7 +11,6 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <intelblocks/cse.h>
-#include <intelblocks/fast_spi.h>
 #include <intelblocks/me.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/post_codes.h>
@@ -1311,17 +1310,10 @@ static void cse_set_state(struct device *dev)
 
 	size_t enable_reply_size;
 
-	int send;
-	int result;
-
 	/* Function Start */
 
-	if (fast_spi_flash_descriptor_override()) {
-		printk(BIOS_WARNING, "HECI: not setting ME state because "
-			"flash descriptor override is enabled\n");
-		return;
-	}
-
+	int send;
+	int result;
 	/*
 	 * Check if the CMOS value "me_state" exists, if it doesn't, then
 	 * don't do anything.

src/soc/intel/common/block/cse/cse_eop.c

@@ -4,7 +4,6 @@
 #include <bootstate.h>
 #include <console/console.h>
 #include <intelblocks/cse.h>
-#include <intelblocks/fast_spi.h>
 #include <intelblocks/pmc_ipc.h>
 #include <security/vboot/vboot_common.h>
 #include <soc/intel/common/reset.h>
@@ -244,11 +243,6 @@ static void do_send_end_of_post(bool wait_for_completion)
 		return;
 	}
 
-	if (fast_spi_flash_descriptor_override()) {
-		printk(BIOS_WARNING, "CSE: not sending EOP because flash descriptor override is enabled\n");
-		return;
-	}
-
 	if (!eop_sent) {
 		set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE);
 		timestamp_add_now(TS_ME_END_OF_POST_START);

src/soc/intel/common/block/fast_spi/fast_spi.c

@@ -483,15 +483,6 @@ void fast_spi_clear_outstanding_status(void)
 	write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS);
 }
 
-/* Check if flash descriptor override is asserted */
-bool fast_spi_flash_descriptor_override(void)
-{
-	void *spibar = fast_spi_get_bar();
-	uint32_t hsfsts = read32(spibar + SPIBAR_HSFSTS_CTL);
-	printk(BIOS_DEBUG, "HSFSTS: 0x%X\n", hsfsts);
-	return !(hsfsts & SPIBAR_HSFSTS_FDOPSS);
-}
-
 
 /* As there is no official ACPI ID for this controller use the generic PNP ID for now. */
 static const char *fast_spi_acpi_hid(const struct device *dev)

src/soc/intel/common/block/include/intelblocks/fast_spi.h

@@ -111,7 +111,5 @@ void fast_spi_set_bde(void);
  * Set FAST_SPIBAR Vendor Component Lock bit.
  */
 void fast_spi_set_vcl(void);
-/* Check if flash descriptor override is asserted */
-bool fast_spi_flash_descriptor_override(void);
 
 #endif	/* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */

src/soc/intel/common/block/pcie/rtd3/rtd3.c

@@ -384,7 +384,7 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev)
 	static bool mutex_created = false;
 
 	const struct soc_intel_common_block_pcie_rtd3_config *config = config_of(dev);
-	static const char *const power_res_states[] = {"_PR0"};
+	static const char *const power_res_states[] = {"_PR0", "_PR3"};
 	const struct device *parent = dev->upstream->dev;
 	const char *scope = acpi_device_path(parent);
 	const struct opregion opregion = OPREGION("PXCS", PCI_CONFIG, 0, 0xff);

src/soc/intel/meteorlake/crashlog.c

@@ -34,7 +34,7 @@ static u32 disc_tab_addr;
 
 static u64 get_disc_tab_header(void)
 {
-	return read64((void *)(uintptr_t)disc_tab_addr);
+	return read64((void *)disc_tab_addr);
 }
 
 /* Get the SRAM BAR. */
@@ -338,7 +338,7 @@ static bool cpu_cl_gen_discovery_table(void)
 
 	disc_tab_addr = bar_addr + get_disc_table_offset();
 
-	u32 dw0 = read32((u32 *)(uintptr_t)disc_tab_addr);
+	u32 dw0 = read32((u32 *)disc_tab_addr);
 	if (!is_crashlog_data_valid(dw0))
 		return false;
 
@@ -351,7 +351,7 @@ static bool cpu_cl_gen_discovery_table(void)
 	for (int i = 0; i < cpu_cl_disc_tab.header.fields.count; i++) {
 		cur_offset = 8 + 24 * i;
 
-		dw0 = read32((u32 *)(uintptr_t)disc_tab_addr + cur_offset);
+		dw0 = read32((u32 *)disc_tab_addr + cur_offset);
 		if (!is_crashlog_data_valid(dw0))
 			continue;
 
@@ -361,7 +361,7 @@ static bool cpu_cl_gen_discovery_table(void)
 			break;
 		}
 
-		cpu_cl_disc_tab.buffers[i].data = read64((void *)(uintptr_t)(disc_tab_addr + cur_offset));
+		cpu_cl_disc_tab.buffers[i].data = read64((void *)(disc_tab_addr + cur_offset));
 		printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size: "
 			"0x%x offset: 0x%x\n", i,  cpu_cl_disc_tab.buffers[i].fields.size,
 			cpu_cl_disc_tab.buffers[i].fields.offset);
@@ -450,7 +450,7 @@ void cpu_cl_rearm(void)
 	cl_punit_control_interface_t punit_ctrl_intfc;
 	memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
 	punit_ctrl_intfc.fields.set_re_arm = 1;
-	write32((u32 *)(uintptr_t)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
+	write32((u32 *)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
 
 	if (!wait_and_check(CRASHLOG_RE_ARM_STATUS_MASK))
 		printk(BIOS_ERR, "CPU crashlog re_arm not asserted\n");
@@ -480,7 +480,7 @@ void cpu_cl_cleanup(void)
 	cl_punit_control_interface_t punit_ctrl_intfc;
 	memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
 	punit_ctrl_intfc.fields.set_storage_off = 1;
-	write32((u32 *)(uintptr_t)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
+	write32((u32 *)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
 
 	if (!wait_and_check(CRASHLOG_PUNIT_STORAGE_OFF_MASK))
 		printk(BIOS_ERR, "CPU crashlog storage_off not asserted\n");