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Author SHA1 Message Date
Jeremy Soller
bc20dc48e0 intel/block/pcie/rtd3: Also implement _PR3
Change-Id: Id7f4373989dffe8c3bc68a034f59a94d2160dd15
Signed-off-by: Jeremy Soller <jeremy@system76.com>
2024-05-31 10:19:27 -06:00
3 changed files with 1 additions and 11 deletions

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@@ -6,8 +6,6 @@ chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2 Port 5
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6

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@@ -73,14 +73,6 @@ static tpm_result_t tpm_setup_s3_helper(void)
default:
printk(BIOS_ERR, "TPM: Resume failed (%#x).\n", rc);
if (CONFIG(TPM2)) {
/*
* TODO: Record EV_SEPARATOR event to indicate to host
* that an error has occurred.
*/
printk(BIOS_WARNING, "TPM: Performing restart\n");
rc = tlcl_startup();
}
break;
}

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@@ -384,7 +384,7 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev)
static bool mutex_created = false;
const struct soc_intel_common_block_pcie_rtd3_config *config = config_of(dev);
static const char *const power_res_states[] = {"_PR0"};
static const char *const power_res_states[] = {"_PR0", "_PR3"};
const struct device *parent = dev->upstream->dev;
const char *scope = acpi_device_path(parent);
const struct opregion opregion = OPREGION("PXCS", PCI_CONFIG, 0, 0xff);