soc/intel/mtl: Set HDA subsystem ID during FSP-M

Intel introduced a new UPD specifically for setting the HDA subsystem ID
in FSP-M. Using SiSsidTablePtr in FSP-S no longer works as it will be
locked with a default value of 0 by that point.

Tested on Clevo V560TU with MTL FSP 4122.12 (0D.00.A8.20).

TEST=PCI config space for HDA device has subsystem ID set.

Change-Id: I5e668747d99b955b0a3946524c5918d328b8e1d3
Signed-off-by: Tim Crawford <tcrawford@system76.com>

src/security/tpm/tspi/tspi.c

@@ -73,14 +73,6 @@ static tpm_result_t tpm_setup_s3_helper(void)
 
 	default:
 		printk(BIOS_ERR, "TPM: Resume failed (%#x).\n", rc);
-		if (CONFIG(TPM2)) {
-			/*
-			 * TODO: Record EV_SEPARATOR event to indicate to host
-			 * that an error has occurred.
-			 */
-			printk(BIOS_WARNING, "TPM: Performing restart\n");
-			rc = tlcl_startup();
-		}
 		break;
 	}
 

src/soc/intel/common/block/crashlog/crashlog.c

@@ -112,7 +112,7 @@ int cpu_cl_poll_mailbox_ready(u32 cl_mailbox_addr)
 	u16 stall_cnt = 0;
 
 	do {
-		cl_mailbox_interface.data = read32((u32 *)cl_mailbox_addr);
+		cl_mailbox_interface.data = read32((u32 *)(uintptr_t)cl_mailbox_addr);
 		udelay(CPU_CRASHLOG_WAIT_STALL);
 		stall_cnt++;
 	} while ((cl_mailbox_interface.fields.busy == 1)
@@ -140,7 +140,7 @@ int cpu_cl_mailbox_cmd(u8 cmd, u8 param)
 	cl_mailbox_intf.fields.param = param;
 	cl_mailbox_intf.fields.busy = 1;
 
-	write32((u32 *)(cl_base_addr + cl_get_cpu_mb_int_addr()),
+	write32((u32 *)(uintptr_t)(cl_base_addr + cl_get_cpu_mb_int_addr()),
 		cl_mailbox_intf.data);
 
 	cpu_cl_poll_mailbox_ready(cl_base_addr + cl_get_cpu_mb_int_addr());
@@ -167,7 +167,7 @@ int pmc_cl_gen_descriptor_table(u32 desc_table_addr,
 				pmc_crashlog_desc_table_t *descriptor_table)
 {
 	int total_data_size = 0;
-	descriptor_table->numb_regions = read32((u32 *)desc_table_addr);
+	descriptor_table->numb_regions = read32((u32 *)(uintptr_t)desc_table_addr);
 	printk(BIOS_DEBUG, "CL PMC desc table: numb of regions is 0x%x at addr 0x%x\n",
 	       descriptor_table->numb_regions, desc_table_addr);
 	for (int i = 0; i < descriptor_table->numb_regions; i++) {
@@ -178,7 +178,7 @@ int pmc_cl_gen_descriptor_table(u32 desc_table_addr,
 			break;
 		}
 		desc_table_addr += 4;
-		descriptor_table->regions[i].data = read32((u32 *)(desc_table_addr));
+		descriptor_table->regions[i].data = read32((u32 *)(uintptr_t)(desc_table_addr));
 		total_data_size += descriptor_table->regions[i].bits.size * sizeof(u32);
 		printk(BIOS_DEBUG, "CL PMC desc table: region 0x%x has size 0x%x at offset 0x%x\n",
 			i, descriptor_table->regions[i].bits.size,
@@ -295,7 +295,7 @@ bool cl_copy_data_from_sram(u32 src_bar,
 
 	u32 src_addr = src_bar + offset;
 
-	u32 data =  read32((u32 *)src_addr);
+	u32 data =  read32((u32 *)(uintptr_t)src_addr);
 
 	/* First 32bits of the record must not be 0xdeadbeef */
 	if (data == INVALID_CRASHLOG_RECORD) {
@@ -320,7 +320,7 @@ bool cl_copy_data_from_sram(u32 src_bar,
 	u32 copied = 0;
 	while (copied < size) {
 		/* DW by DW copy: byte access to PMC SRAM not allowed */
-		*dest_addr = read32((u32 *)src_addr);
+		*dest_addr = read32((u32 *)(uintptr_t)src_addr);
 		dest_addr++;
 		src_addr += 4;
 		copied++;

src/soc/intel/meteorlake/crashlog.c

@@ -34,7 +34,7 @@ static u32 disc_tab_addr;
 
 static u64 get_disc_tab_header(void)
 {
-	return read64((void *)disc_tab_addr);
+	return read64((void *)(uintptr_t)disc_tab_addr);
 }
 
 /* Get the SRAM BAR. */
@@ -338,7 +338,7 @@ static bool cpu_cl_gen_discovery_table(void)
 
 	disc_tab_addr = bar_addr + get_disc_table_offset();
 
-	u32 dw0 = read32((u32 *)disc_tab_addr);
+	u32 dw0 = read32((u32 *)(uintptr_t)disc_tab_addr);
 	if (!is_crashlog_data_valid(dw0))
 		return false;
 
@@ -351,7 +351,7 @@ static bool cpu_cl_gen_discovery_table(void)
 	for (int i = 0; i < cpu_cl_disc_tab.header.fields.count; i++) {
 		cur_offset = 8 + 24 * i;
 
-		dw0 = read32((u32 *)disc_tab_addr + cur_offset);
+		dw0 = read32((u32 *)(uintptr_t)disc_tab_addr + cur_offset);
 		if (!is_crashlog_data_valid(dw0))
 			continue;
 
@@ -361,7 +361,7 @@ static bool cpu_cl_gen_discovery_table(void)
 			break;
 		}
 
-		cpu_cl_disc_tab.buffers[i].data = read64((void *)(disc_tab_addr + cur_offset));
+		cpu_cl_disc_tab.buffers[i].data = read64((void *)(uintptr_t)(disc_tab_addr + cur_offset));
 		printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size: "
 			"0x%x offset: 0x%x\n", i,  cpu_cl_disc_tab.buffers[i].fields.size,
 			cpu_cl_disc_tab.buffers[i].fields.offset);
@@ -450,7 +450,7 @@ void cpu_cl_rearm(void)
 	cl_punit_control_interface_t punit_ctrl_intfc;
 	memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
 	punit_ctrl_intfc.fields.set_re_arm = 1;
-	write32((u32 *)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
+	write32((u32 *)(uintptr_t)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
 
 	if (!wait_and_check(CRASHLOG_RE_ARM_STATUS_MASK))
 		printk(BIOS_ERR, "CPU crashlog re_arm not asserted\n");
@@ -480,7 +480,7 @@ void cpu_cl_cleanup(void)
 	cl_punit_control_interface_t punit_ctrl_intfc;
 	memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
 	punit_ctrl_intfc.fields.set_storage_off = 1;
-	write32((u32 *)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
+	write32((u32 *)(uintptr_t)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
 
 	if (!wait_and_check(CRASHLOG_PUNIT_STORAGE_OFF_MASK))
 		printk(BIOS_ERR, "CPU crashlog storage_off not asserted\n");

src/soc/intel/meteorlake/romstage/fsp_params.c

@@ -282,6 +282,8 @@ static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg,
 static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,
 		const struct soc_intel_meteorlake_config *config)
 {
+	const struct device *dev;
+
 	/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
 	m_cfg->PchHdaEnable = is_devfn_enabled(PCI_DEVFN_HDA);
 	m_cfg->PchHdaDspEnable = config->pch_hda_dsp_enable;
@@ -302,6 +304,13 @@ static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,
 	memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
 	memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable));
 	memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
+
+	dev = pcidev_path_on_root(PCI_DEVFN_HDA);
+	if (dev) {
+		uint16_t svid = CONFIG_SUBSYSTEM_VENDOR_ID ? : (dev->subsystem_vendor ? : 0x8086);
+		uint16_t ssid = CONFIG_SUBSYSTEM_DEVICE_ID ? : (dev->subsystem_device ? : 0x7e28);
+		m_cfg->PchHdaSubSystemIds = (ssid << 16) | svid;
+	}
 }
 
 static void fill_fspm_cnvi_params(FSP_M_CONFIG *m_cfg,