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881 Commits

Author SHA1 Message Date
d3ab11534d mb/system76/mtl: Add Darter Pro 10
The Darter Pro 10 (darp10) is an Intel Meteor Lake-H based board.

There are 2 variants in order to differentiate the 14" and 16" models,
as they have different keyboards and so have different EC firmware.

Change-Id: Iaef03a47cf108591ef823bfa779777c7c05c6337
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-06-03 14:53:54 -06:00
178a5054b3 tree: Use calloc(n, sizeof(struct)) insteadof calloc(sizeof(struct), n)
Change-Id: I5e67e370d4eb8fe28227843bbca34db06ad84b26
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82786
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-03 19:02:31 +00:00
ea7a83ee88 Revert "Makefile: Warn if flexible array members are not at the end"
This reverts commit f4acef92.

Reason for revert: '-Wflex-array-member-not-at-end' is new command
option came with GCC-14. older versions will not support it.

Change-Id: I179d0bc0db3e863645ae4c87e1534c5c20025dfb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82758
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-03 17:27:24 +00:00
ba39cd59db mb/razer/blade_stealth_kbl: Add H3Q variant
The Razer Blade Stealth Kaby Lake has 2 variants. One is the H2U
variant, as originally committed, with the SKU number RZ09-01962, also
known as the 2016 model, and the H3Q model with SKU numbers RZ09-01963
and RZ09-01964, known as the Mid 2017 model. This commit adds support
for the H3Q model. With respect to coreboot, there are few known
differences:

1. Only the H2U has TPM.
2. The USB ports are different.
3. The screen size (and therefore VBIOS Table) is different.
4. The hda_verb is very slightly different.
5. The gpio is different.

Change-Id: I493a651e52c2eb938daa67a05e9caaa784020fa4
Signed-off-by: Reagan Bohan <xbjfk.github@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-03 16:57:09 +00:00
657cef204a soc/intel/meteorlake: Enable USB2 port reset message on Type-C ports
Apply commit c6b65c1a81 ("soc/intel/alderlake: Enable USB2 port reset
message on Type-C ports") to Meteor Lake.

This change is added to address the issue of USB3 ports downgrading to
high speed during low power modes and not returning back to super speed.

The patch enables port reset event on USB2 ports. This event is
is passed to USB3 upstream ports to upgrade back to super speed (USB3)
after a downgrade during low power state.

Change-Id: Iac702a8d8edd2b3b7e03abcac020be7e45335821
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82730
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-03 16:55:47 +00:00
740cf98f0f util/cbfstool: Fix linux_trampoline.c generation
linux_trampoline.c generation is broken with latest crossgcc-i386
toolchain. Fix the issue to enable the building.

../cbfstool/linux_trampoline.S: Assembler messages:
../cbfstool/linux_trampoline.S💯 Error: no instruction mnemonic
	suffix given and no register operands; can't size
	instruction
<builtin>: recipe for target '../cbfstool/linux_trampoline.o'
	failed

TEST=Build and boot on intel/archercity CRB

cd util/cbfstool/
rm linux_trampoline.c
make linux_trampoline.c

Change-Id: I7faca296f946bb4e9fd510661357925e5dcf9a6b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82704
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-03 16:54:02 +00:00
ed55218c5e mb/system76/rpl: Fix addw4 Kconfig name
Change-Id: I1ed280c1e62e0f094fd40d2165892240f76de390
Fixes: 29f1b79127 ("mb/system76/rpl: Add Adder WS 4 as a variant")
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-03 16:47:40 +00:00
cfcd0851a2 mb/system76/rpl: Hook up TAS5825M init
Ensure per-board smart amp init is configured. Fixes speaker output on
oryp12.

Change-Id: I40ff1889dd144bf83ef85979a55535493aa7abdd
Fixes: 8b9716e226 ("mb/system76/rpl: Add Oryx Pro 12 as a variant")
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-06-03 16:47:26 +00:00
8093b77c34 mb/system76: Add SPDX ID to devicetree files
Change-Id: I55f2730f7277a3c699b86ded5864e9690d92d518
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82700
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-03 16:46:51 +00:00
3a26aec8bd soc/intel/meteorlake: Hook up PchHdaAudioLinkHdaEnable to devicetree
The comment that the PchHdaAudioLink UPDs only configure GPIOs is
incorrect. Setting this to 1 is needed to enable HDA audio link.

Same exact situation as with Alder Lake in CL 71715.

Change-Id: Iecbe106ae18b5a8b53c04a5335a4e4c4ae27c7a0
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
2024-06-03 16:46:00 +00:00
a79af4c7fd ec/dasharo/ec: Add initial copy of ec/system76/ec
Initial commit is a copy of ec/system76/ec from tag v24.02.1 (commit
0a280ff7) with string changes. Dasharo-specific features will be added
in subsequent commits, similar to how Librem EC support was added in
changes 52390 and 52391.

Change-Id: Ic7c3d9413488026548514963eb78accc28e41e06
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-03 16:45:20 +00:00
377157c7fb device_tree: Add function to get top of memory from a FDT blob
coreboot needs to figure out top of memory to place CBMEM data. On some
non-x86 QEMU virtual machines, this is achieved by probing the RAM space
to find where the VM starts discarding data since it's not backed by
actual RAM. This behaviour seems to have changed on the QEMU side since
then, VMs using the "virt" model have started raising exceptions/errors
instead of silently discarding data (likely [1] for example) which has
previously broken coreboot on these emulation boards.

The qemu-aarch64 and qemu-riscv mainboards are intended for the "virt"
models and had this issue, which were mostly fixed by using exception
handlers in the RAM detection process [2][3]. But on 32-bit RISC-V we
fail to initialize CBMEM if we have 2048 MiB or more of RAM, and on
64-bit RISC-V we had to limit probing to 16383 MiB because it can run
into MMIO regions otherwise.

The qemu-armv7 mainboard code is intended for the "vexpress-a9" model VM
which doesn't appear to suffer from this issue. Still, the issue can be
observed on the ARMv7 "virt" model via a port based on qemu-aarch64.

QEMU docs for ARM and RISC-V "virt" models [4][5] recommend reading the
device tree blob it provides for device information (incl. RAM size).
Implement functions that parse the device tree blob to find described
memory regions and calculate the top of memory in order to use it in
mainboard code as an alternative to probing RAM space. ARM64 code
initializes CBMEM in romstage where malloc isn't available, so take care
to do parsing without unflattening the blob and make the code available
in romstage as well.

[1] https://lore.kernel.org/qemu-devel/1504626814-23124-1-git-send-email-peter.maydell@linaro.org/T/#u
[2] https://review.coreboot.org/c/coreboot/+/34774
[3] https://review.coreboot.org/c/coreboot/+/36486
[4] https://qemu-project.gitlab.io/qemu/system/arm/virt.html
[5] https://qemu-project.gitlab.io/qemu/system/riscv/virt.html

Change-Id: I8bef09bc1bc4e324ebeaa37f78d67d3aa315f52c
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80322
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-06-03 15:38:55 +00:00
eed791e851 Revert "tree: Use Wcalloc-transposed-args command option"
This reverts commit b3db3abd63.

Reason for revert: `Wcalloc-transposed-args` is new command option came with GCC-14. older versions will not support it.

Change-Id: I74ef8de1f7d38e1e0519c3b41e79fd9b11d8e16f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82759
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-03 14:58:01 +00:00
6466354ee9 lib/device_tree.c: Fix wrong check for FDT validity
Obviously one should return NULL if a FDT is not valid an not the other
way around.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I77c0e187b841e60965daac17025110181bdd32bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-03 11:17:30 +00:00
f38c940754 tree: Add some SMBIOS_PROCESSOR_FAMILY macros
Change-Id: Ibe551a4c83f416ba30326077aa165818cf79c1fd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82648
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-01 06:40:14 +00:00
87a6600264 mainboard/google/rex: Enable Rex64 build configuration
- Add Rex64 board to Kconfig menu
- Enable building for Rex64 with x86_64 support

Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82625
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-31 22:11:55 +00:00
c097c4788b soc/intel: Fix pointer size mismatch errors in crashlog
The crashlog code in intel/common/block and meteorlake soc
was casting integer addresses directly to pointer types,
which caused compilation errors in x86_64 bit builds.

This commit fixes the issue by using uintptr_t for casting
integer addresses to pointer types before dereferencing.

BUG=b:329034258
TEST=Successfully build Meteor Lake (rex) in both x86_32 and
x86_64 modes.

Change-Id: I2d0814a8b767270ec140341bfb51d0782469545d
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82481
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-31 20:36:45 +00:00
1f97d801ce mb/google/brya/var/nova: Update USB ports setting
Update used USB port[2][3](type-a) setting for nova.

BUG=b:328711879
TEST=emerge-constitution coreboot chromeos-bootimage

Change-Id: I63cf97b23627feac05743f2a6e514a33fcaf7dff
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82703
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2024-05-31 16:18:12 +00:00
eaaa630e7d soc/intel/xeon_sp: Add _OSC ASL generation utils for IIO domains
For multi-SKU/SoC supports, IIO domain layouts are returned from FSP
HOBs. Add _OSC ASL generation utils so that static IIO domain layout
definition file per SKU/SoC are not needed any more.

The _OSC generation codes is a thin AML generation layer which
further invokes \_SB.POSC which is defined in ASL. The ASL handler
is able to handle boot-time generated info as parameters while keeps
good readability for the ease of maintenance. In this case, firmware
granted capabilities are calculated in boot time and passed to ASL
handler as parameters.

TEST=Build and boot on intel/archercity CRB

Change-Id: Ibd3bfa2428725fe593754436d5ed75a3a11b4cdc
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2024-05-31 13:18:11 +00:00
cf4c6fd225 vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard
This commit removes config guard around FSPM_ARCH_UPD from the
FspApi.h header file. This change is done to ensure
that this header file can be used with both x86_32 and x86_64
architectures and also with different FSP specification versions.

The following modifications are made:
- Removes PLATFORM_USES_FSP2_X86_32 config guard around
  FSPM_ARCH_UPD, this was added to isolate the structure from
  x64 build. This is not really required since the x64 build uses
  FSP2.4 structures.

BUG=b:343428206
TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex)

Change-Id: Idc849de73723036323f81dfd055730f6669cd52e
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82425
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-31 10:46:13 +00:00
3303b3684b mb/google/trulo: Support OCP fault on A0/1 ports
The devicetree entry and gpio.c updated as per the schematics of Trulo
to map the OC fault signals from A0/A1 USB ports.

BUG=b:335858378
TEST= Able to build google/trulo

Change-Id: Ic17debc5eecebca8c000c43a660e1b52d2932f2a
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82637
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-05-31 09:13:17 +00:00
11fad8fc86 soc/intel/meteorlake: Exclude deprecated upd from FSP2.4 builds
EnableMultiPhaseSiliconInit upd is deprecated and has been
removed starting with v2.4 of FSP specification. Multi-phase
silicon initialization is mandatory for all FSP implementations
compliant to v2.4.

The following modifications are made:
- In fsp_params.c and silicon_init.c EnableMultiPhaseSiliconInit
  update is guarded so that it will get included only if FSP2.4
  is not selected.

BUG=b:329034258
TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex)

Change-Id: Icdbf3bacc0a05975fc941b264fd400d74f506fce
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-31 08:22:01 +00:00
415932097a soc/intel/meteorlake: Tailor FSP Version Selection for Architecture
* Conditionally select FSP 2.4 when x86_64 support is available
  (HAVE_X86_64_SUPPORT).
* Default to FSP 2.3 otherwise.
* Adjust default FSP header path to align with architecture.

BUG=b:242829490
TEST=Able to build google/rex in both 32-bit and 64-bit mode.

Change-Id: Ib77a34c6bf7bca3485a197f109d1550ac3d51cc0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-31 06:13:48 +00:00
09b9a80677 soc/intel/meteorlake: Enable eSOL without 64-bit support
This change allows eSOL to be enabled on production Meteor Lake silicon
even when 64-bit support is not present. eSOL support is still TBD for
64-bit FSP hence, skip adding this support for 64-bit build.

TEST=Able to build and boot google/rex64 w/o eSOL.

Change-Id: I16762e5b74ae0aaa3c28730479a1fd9defc4d93c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82716
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-31 06:13:43 +00:00
9761b87fae tree: Remove duplicated <soc/gpio.h>
<gpio.h> is supposed to chain-include <soc/gpio.h>.

Change-Id: Ib25581bd2c8dd38cdd0396561ce5f9a782365f14
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82691
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-30 14:40:32 +00:00
e527e954be vc/intel/fsp/mtl: Add x86_64 FSP V3471.91 headers
This commit introduces new header files of V3471.91 for the x86_64
architecture in the fsp2_0/meteorlake directory. FSP2.4 brings FSP
64-bits support and the soc Kconfig file has been updated to select
this new header path when FSP2.4 is in use.

BUG=b:329034258
TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex)

Change-Id: Ib41b57e794311db729ac65a968f562aa127e86c3
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-05-30 13:22:10 +00:00
acd0e1a5b8 vc/intel/fsp/mtl: Organize FSP headers into x86_32 directory
This commit moves FSP V3471.91 header files for Meteor Lake
into a new x86_32 directory to better organize the files based
on the architecture. The Kconfig file has been modified accordingly
to reflect the new paths of the relocated headers.

BUG=b:329034258
TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex)

Change-Id: Id30186a8b1b5a9082f498e18a3378f5e9907b668
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82424
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-30 13:21:58 +00:00
3725fce22b soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility
This commit updates the type definitions for FSP parameters in the
Meteor Lake platform to ensure compatibility with the FSP2.4
specification, that supports 64-bit builds for the first time and
this  also ensures that parameter types works for both 32-bit
and 64-bit builds.

- In fsp_params.c, FSPS_ARCH_UPD macro is changed to
  FSPS_ARCHx_UPD which supports FSP2.4 and older specifications.
  Special handling is added for FspEventHandler assignment to handle
  as the variable type is different in both cases.

- In meminit.c, the type for SPD pointers is changed from uint32_t
  to efi_uintn_t to support both 32-bit and 64-bit builds.

BUG=b:329034258
TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex)

Change-Id: Ide220f60184135a6488f4472f69a471e2b383e2a
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82177
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-30 13:21:46 +00:00
8c3cf9eace mb/siemens/mc_ehl5: Remove DDI settings from devicetree
Since this mainboard no longer uses the FSP GOP driver, the DDI port
settings are no longer necessary. The GOP driver was used in the initial
phase of development where we used Tianocore as payload for some test
cases. Finally, this mainboard uses a self-made Linux payload, which
does the graphic initialization.

BUG=none
TEST=Boot into Linux and check if graphic works correctly

Change-Id: Ie9e135fbc2627546d6ef95d7d5ff3e9a9222b5d2
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82663
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-30 13:02:55 +00:00
29f1b79127 mb/system76/rpl: Add Adder WS 4 as a variant
The Adder WS 4 (addw4) is a Raptor Lake-HX board.

Tested with a custom edk2 UefiPayloadPkg.

Working:

- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots (with Crucial CT8G48C40S5)
- M.2 NVMe SSDs
- All USB ports
- MicroSD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Backlight controls on Linux 6.8
- DisplayPort output over USB-C
- Internal microphone
- Internal speakers
- Combined headset + mic 3.5mm audio
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.8.0
- TPM 2.0 device

Not working:

- Discrete/Hybrid graphics
- Detection of devices in TBT slot on boot

Change-Id: I4a6819cbcf64f68237008adebdd7eb196336514c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82595
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29 21:50:32 +00:00
8b9716e226 mb/system76/rpl: Add Oryx Pro 12 as a variant
The Oryx Pro 12 (oryp12) is a Raptor Lake-HX board.

Tested with a custom edk2 UefiPayloadPkg.

Working:

- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots (with Crucial CT8G48C40S5)
- M.2 NVMe SSDs
- MicroSD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Backlight controls on Linux 6.8
- Internal microphone
- Internal speakers
- Combined headset + mic 3.5mm audio
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.8.0
- TPM 2.0 device

Not working:

- Discrete/Hybrid graphics
- Thunderbolt

Change-Id: I11cf2dbd1512ebae44e0109bdb78e6eafa027444
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-29 20:57:44 +00:00
3a4e1392df mb/system76/rpl: darp9: Add SSD RTD3 configs
Some drives block the CPU from reaching C10 during S0ix suspend without
the RTD3 configs.

Fixes suspend with the following drives:

- Kingston KC3000 (SKC3000D/4096G)
- Kingston HyperX (SHPM2280P2H/240G)
- Solidigm P44 Pro (SSDPFKKW010X7)

The following drives continue to work:

- Samsung 970 Evo (MZVLB250HAHQ)
- WD Black SN770 (WDS250G3X0E)
- WD Green SN350 (WDS240G2G0C-00AJM0)
- WD Blue SN570 (WDS100T3B0C)

Change-Id: Ia369727d0f1aa5ff546cfb5700a63063730e8248
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Tested-by: Levi Portenier <levi@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-05-29 20:09:07 +00:00
ac44327bc2 mb/intel/mtlrvp: Enable EC MKBP device
MKBP device is required for passing events from input sources to AP.
Input sources include buttons (power, volume); switches (lid, tablet
mode) and sysrq.

BUG=b:342227155
TEST=Able to build coreboot for mtlrvp platform and switch tablet
     mode.

Change-Id: I630421c83784bb4492486d72290b9e8cdada1d47
Signed-off-by: Jay Patel <jay2.patel@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82612
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2024-05-29 19:49:37 +00:00
0306cc2bbd payloads/iPXE: Hook up TRUST_CMD switch
Change-Id: Ia4f5d4140eeb8625c5ee41e38f048658db28a199
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79684
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29 19:22:57 +00:00
fda9d75d90 cpu/x86/pae/pgtbl.c: extract reusable code from memset_pae()
Code dealing with PAE can be used outside of memset_pae(). This change
extracts creation of identity mapped pagetables to init_pae_pagetables()
and mapping of single 2 MiB map to pae_map_2M_page(). Both functions are
exported in include/cpu/x86/pae.h to allow use outside of pgtbl.c.

MEMSET_PAE_* macros were renamed to PAE_* since they no longer apply
only to memset_pae().

Change-Id: I8aa80eb246ff0e77e1f51d71933d3d00ab75aaeb
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82249
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29 13:04:30 +00:00
b1bd442ca9 mb/google/nissa/var/sundance: Add WWAN power off sequence
Sundance support FM101 WWAN, use wwan_power.asl to handle the
power off sequence

BUG=b:343139385
TEST=Build and boot on sundance

Change-Id: I82085172db370ab5a6c0f77afe6042c53b89e43e
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-29 12:37:59 +00:00
6d21f5c845 mb/google/nissa/var/pujjoga: Update touchscreen IC settings
Modify the Goodix touchscreen from new vendor and remove 3 unused
touchscreens. According to the information provided by the key-part
team.

BUG=b:340689681
TEST=Build and check Goodix touchscreen can work.

Change-Id: I1e6349e80431aadf27cd72b8439b01f95348071d
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82427
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-29 12:37:36 +00:00
2f2ceef27b mb/google/nissa/var/sundance: Update eMMC DLL settings
Currently Samsung eMMC (KLMBG2JETD-B041) can't power on to OS nomally.
According to Intel provides eMMC DLL delay patch that tuning on each
Sundance different eMMC system to modify some system can't boot to OS problem.

BUG=b:342057438
TEST=Build and check each SKU eMMC can work.

Change-Id: I29d4305bbe5f91d822d947cae942b654e80a8a57
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82602
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-29 12:37:11 +00:00
08375b5082 tree: Remove unused <string.h>
Change-Id: I9ed1a82fcd3fc29124ddc406592bd45dc84d4628
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-29 10:34:08 +00:00
bdd03c20d5 tree: Use <stdio.h> for snprintf
<stdio.h> header is used for input/output operations (such as printf,
scanf, fopen, etc.). Although some input/output functions can manipulate
strings, they do not need to directly include <string.h> because they
are declared independently.

Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29 10:33:54 +00:00
93ca6b676c libpayload: Include libpayload-config.h in lib target
- Added `$(obj)/libpayload-config.h` as a dependency for the `lib`
  target.
- This ensures the config header is up-to-date before building the
  library.

TEST=Able to build google/rex.

Change-Id: If26336f6261aadf611fa5338c4300873156cc3da
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-29 09:18:26 +00:00
eec556be2d util/nvidia: Use c11 dialect
Change-Id: I75909ce85eed549d9094ba6f62d93656621d9f0d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82679
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29 08:19:15 +00:00
fbca398293 util/superiotool: Use c11 dialect
Change-Id: Ic03d9ac883a92d52467d563f048446871b928712
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-29 08:19:09 +00:00
b3db3abd63 tree: Use Wcalloc-transposed-args command option
GCC-14 documentation says "The first argument to calloc is documented to
be number of elements in array, while the second argument is size of
each element, so calloc(n, sizeof (int)) is preferred over
calloc(sizeof(int), n)."

Change-Id: I77b6f4d2eda487b087ba5665b588999633c33e8d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82658
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29 08:19:02 +00:00
877fafab57 tree: Remove unused <stddef.h>
Change-Id: I7d7ad562eeff7247b7377b6570d489faee0aeda0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82669
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-29 02:51:20 +00:00
5d1494adda mb/system76/tgl: Update VBTs to version 250
Commit 4c7e97b26a ("Update fsp submodule to upstream master branch")
included an update to the VBT from 240 to 250, breaking parsing of
existing VBTs.

After that commit, the VBT was parsed as (from gaze16-3060-b):

    [DEBUG]  PCI: 00:02.0 init
    [INFO ]  GMA: Found VBT in CBFS
    [INFO ]  GMA: Found valid VBT in CBFS
    [INFO ]  framebuffer_info: bytes_per_line: 4096, bits_per_pixel: 32
    [INFO ]                     x_res x y_res: 1024 x 768, size: 3145728 at 0xd0000000
    [DEBUG]  PCI: 00:02.0 init finished in 6 msecs

When the expected output is:

    [DEBUG]  PCI: 00:00:02.0 init
    [INFO ]  GMA: Found VBT in CBFS
    [INFO ]  GMA: Found valid VBT in CBFS
    [INFO ]  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
    [INFO ]                     x_res x y_res: 1920 x 1080, size: 8294400 at 0xd0000000
    [DEBUG]  PCI: 00:00:02.0 init finished in 6 msecs

Generate blobs for the new version using Intel Display Configuration
Tool (DisCon) v3.3, based on the existing 237 and 240 VBTs.

(For our edk2 payload, the UEFI GOP driver was updated to 17.0.1077.)

Tested on all affected systems:

- darp7
- galp5
- gaze16-3050
- gaze16-3060
- gaze16-3060-b
- lemp10
- oryp8

Tested:

- Boot splash displays on screen again
- Firmware setup menu is rendered, at correct resolution

Change-Id: I918356d9f660b985ee4408ef77544fbd071ab35f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Tested-by: Daniel Sutton <daniel@system76.com>
Tested-by: Jacob Kauffmann <jacob@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-28 20:01:10 +00:00
5a8c11e2aa mb/google/brox: Add romstage early graphics
Select MAINBOARD_USE_EARLY_LIBGFXINIT for brox to enable SOL image.
This patch enables Sign of Life image during MRC training.

BUG=b:335369811
TEST=Able to boot to ChromeOS with SOL image.

CPU log:
[SPEW ]  bootmode is set to: 0 (boot with full config)
[0.384818] DP PHY mode status not complete
[0.388911] DP PHY mode status not complete
[0.393197] DP PHY mode status not complete
[0.397484] DP PHY mode status not complete
[0.401771] DP PHY mode status not complete
[0.406057] DP PHY mode status not complete
[0.410345] DP PHY mode status not complete
[0.414632] DP PHY mode status not complete
[0.418916] DP PHY mode status not complete
[0.423203] DP PHY mode status not complete
[0.427491] DP PHY mode status not complete
[0.431777] DP PHY mode status not complete
[INFO ]  Informing user on-display of memory training.
[DEBUG]  FMAP: area COREBOOT found @ 1877000 (7901184 bytes)
[WARN ]  CBFS: 'preram_locales' not found.
[ERROR]  ux_locales_get_text: preram_locales not found.
[DEBUG]  FMAP: area RW_ELOG found @ f20000 (16384 bytes)
[INFO ]  ELOG: NV offset 0xf20000 size 0x4000

elogtool list:
0 | 2024-05-10 02:26:07-0700 | Log area cleared | 4088
1 | 2024-05-10 02:26:07-0700 | Early Sign of Life | MRC Early SOL Screen Shown
2 | 2024-05-10 02:26:51-0700 | Memory Cache Update | Normal | Success
3 | 2024-05-10 02:27:09-0700 | System boot | 4
4 | 2024-05-10 02:27:09-0700 | Firmware Splash Screen | Enabled
5 | 2024-05-10 02:27:11-0700 | System Reset
6 | 2024-05-10 02:27:11-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown
7 | 2024-05-10 02:27:18-0700 | ACPI Enter | S5
8 | 2024-05-10 02:27:36-0700 | System boot | 5
9 | 2024-05-10 02:27:36-0700 | Firmware Splash Screen | Enabled
10 | 2024-05-10 02:27:37-0700 | System Reset
11 | 2024-05-10 02:27:37-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown


Change-Id: I1d4795825960bc58f8f7ef494b01aa975f3bc346
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
2024-05-28 19:14:23 +00:00
b72f5949cc tree: Add smbios_processor_type
Change-Id: I46f799ad255993ac42dab11b5c1d2608daa52b42
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82645
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-28 13:27:15 +00:00
23e3ea889f mb/google/trulo: Add initial devicetree.cb
This patch adds initial PCI device entries into the baseboard
devicetree.cb.

TEST=Able to build google/trulo.

Change-Id: I6ec25b98379cf7c8cbdb5be94d9f3ea43878620c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-28 13:17:27 +00:00
e75148cd13 mb/google/trulo: Mark unused USB ports as empty
This patch marks unused USB ports (USB2.0/TCSS) empty to avoid
prompting wrong dmesg as below.

   ```
  usb usb2-port3: Cannot enable. Maybe the USB cable is bad?
   ```
Trulo variants to override the USB ports as per the target
board design.

TEST=Able to build google/trulo.

Change-Id: I6240e66ed3d1a7198c1a526fdca2483910157235
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-28 13:17:08 +00:00
fab5482a1f mb/google/trulo: Program EC ranges (host cmd and memory map)
This patch adds chip config entries for EC host cmd and memory map
ranges.

TEST=Able to build Google/Trulo.

Change-Id: Id4b0f3bba934c8da56b6d7ca8579b46b6cccac28
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-28 13:16:36 +00:00
70de5bf9fd soc/intel/xeon_sp: Add PD_TYPE_CLUSTER
Add a new proximity type to represent the sub-NUMA cluster (SNC).

This patch adds necessary Xeon-SP common code level support for
SNC support. When SNC on, each SNC cluster will have a proximity
domain. DIMMs and CPU cores are attached to SNC proximity domains
instead of the processor proximity domains.

With SNC, there are 3 types of proximity domains,
PD_TYPE_PROCESSOR, PD_TYPE_GENERIC_INITIATOR and PD_TYPE_CLUSTER.
proximity domain type checks in Xeon-SP codes are updated to
correctly handle the adding of the new type.

This patch doesn't actually enable SNC. To fully enable SNC, SoC
codes need to override soc_get_cluster_count(), soc_set_cpu_node_
id() and memory_to_pd(), and call soc_set_cpu_node_id() in its
per-CPU init routine.

Change-Id: I32558983780f302ff4893901540a90baebf47add
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Ziang Wang <ziang.wang@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-28 09:47:35 +00:00
bd33b6ab9f include/device: Fix IO resource handling covering 0xFFFF
IO resource creation utils taking 'from' and 'to' as parameters
use uint16_t for them, where 'to' equals the resource limit plus
1. When a resource is with a limit of 0xFFFF, the value of 'to'
will be clipped to 0x0000 by uint16_t. Fix this problem by use
uint32_t and checks the effective range to make sure it no larger
than UINT16_MAX + 1.

TEST=Build and boot on intel/archercity CRB
TEST=Build on intel/avenuecity CRB

Change-Id: Ie83045683094d6330c1676809f83acf30175cc90
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82192
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-05-28 09:46:08 +00:00
6c708d8a46 soc/intel/xeon_sp: Add domain resource window creation utils
It might be benefical to have utils for domain resource window
creation so that the correct IORESOURCE flags used could be
guaranteed.

TEST=Build and boot on intel/archercity CRB
TEST=Build on intel/avenuecity CRB

Change-Id: I1e90512a48ab002a1c1d5031585ddadaac63673e
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-05-28 09:45:35 +00:00
94bfdd1282 tree: Remove unused <stdarg.h>
<stdarg.h> header is used to define macros for handling variable
argument lists in functions like printf. It does not depend on the string
or memory manipulation functions provided by <string.h>.
So let follow conventions and include only the necessary headers in each
header file.

Change-Id: I07ffc65b7feefb8ec4ab8dd268113f9ed8d24685
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82664
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-28 03:22:34 +00:00
0554fc10c0 spd_bin.h: Use same macro for DDR3 and LPDDR3
DDR3 and LPDDR3 share the same PART_NUM and PART_LEN.
So use the same macro.
This is to prepare SPD de-duplication in following patch.

Change-Id: Iea824a847b5072b1cbaa38dc38deae1d484d5b16
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-28 03:21:37 +00:00
1361beefb5 soc/mediatek/mt8188: Decrease OP-TEE image size from 80 MB to 70 MB
The secure buffer shrank from 42 MB to 32 MB, decreasing the total
OP-TEE image size from 80 MB to 70 MB.

BUG=b:246837563
TEST=emerge-geralt coreboot
     build coreboot and verify SVP works well

Change-Id: I6729e65f83ef994fe59b5bd4ed098e6d3a847695
Signed-off-by: Gavin Liu <gavin.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-05-28 01:35:24 +00:00
dfad318095 acpi/acpi_apic;arch/x86/acpi: better document ACPI_NO_PCAT_8259 case
Both acpi_create_madt_sci_override and acpi_sci_int have special
handling for the ACPI_NO_PCAT_8259 case, but those cases weren't exactly
obvious, so add a comment with the reason for that.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6dcf59d5ab9226c61e9c4af95a73a07771b71d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82643
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-27 14:49:22 +00:00
a0d453fa4d mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)
AOOSTAR R1 is a Chinese NAS based on Intel N100 (Alder Lake N), with
two 3.5" HDD slots, an M.2 NVMe 2280 SSD slot and a single DDR4-3200
SODIMM slot up to 32GB. It also comes with 2x 2.5Gb Intel NICs,
Intel AX200 WiFi + BT and USB-C Alt-DP Power Delivery.

Working:
- DDR4 RAM (tested with Crucial 16GB 3200MHz CL22)
- Automatic FAN control (IT8613E Super I/O)
- M.2 NVME slot
- 2x SATA ports (Issue on 3.5" HDD, see below)
- USB 2.0 ports
- USB 3.0 ports
- USB-C port with Alt-DP and PD
- HDMI / DisplayPort ports
- 2x 2.5Gb NICs
- WiFi + BT
- MicroSD card reader
- ASPM (Unavailable on stock)
- Linux (Arch Linux, kernel 6.8.7-arch1-1) UEFI booting with EDK2
- Windows 10 UEFI booting with EDK2

Broken:
- Power button (OFF->ON broken, ON->OFF works)
- 3.5" SATA HDDs (Detected only after reboot)

Untested:
- Internal audio
- S3

My motivation for doing this port is enabling ASPM, as it makes a
great difference on idle power consumption (from 8.4W to 5W measured
from the wall).

The last remaining annoyance of this port is the power button not
working. I spent a few hours double checking the Super I/O registers but
then I gave up. A workaround for this is to use the "ON after power
loss" feature and reconnect the power cord to turn on the board.
It's not a big problem for a NAS that will stay ON 24/7.
Any hint on the power button or 3.5" HDD issue is welcome.

VBT extracted from vendor UEFI firmware version 1AXFE 0.01 x64
(Build date and time 11/29/2023 10:57:44)
Compiled with FSP GOP video initialization, using IFD descriptor
and ME blob extracted from vendor UEFI firmware (see above).

The board can be flashed externally using a 1.8V adapter, I used a
CH341a modded for 3.3V I/O. Internal flashing works, as flash is
not read/write protected.

Patchset 5: Re-enabled dptf, added default options to Kconfig.
Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works
Patchset 8: Fixed microSD card reader
Patchset 13: Change Super I/O Fan configuration to reduce fan noise

Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5
Signed-off-by: Federico Amedeo Izzo <federico@izzo.pro>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82010
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-27 14:07:14 +00:00
61f826bdf1 mb/google/ovis/var/deku: Set PsysPL2 value to 178W
Adjust setting as recommended by power team.
Add ramstage.c in Makefile.inc to set psys_pl2_watts in
variant_devtree_update().

Also copy CPU power limit values from ovis baseboard.

BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST=FSP debug emerge-ovis coreboot intelfsp
     check overrides setting
     [INFO] CPU PsysPL2 = 178 Watts
     [INFO] Overriding PsysPL2 (178)
     [INFO] Overriding power limits PL1 (mW) (19000,28000) PL2 (mW)
     (64000, 64000) PL4 (W) (120)

Change-Id: I9ce3a8f843a87e81d404778aaf250b876b6801eb
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-27 12:53:20 +00:00
e5b86c7d5a mb/google/ovis/var/deku: Increase TDP PL1 value from 28 W to 33 W
Adjust settings as recommended by thermal team.

Set PL1 max value tdp_pl1_override from 28W to 33W.

PL2, PL4 remain the same as CPU default.

BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
     built bootleg and verified test result by thermal team

Change-Id: Iad0bca913496dda666ba9bcfe5f6fce1a6396692
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82615
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-27 12:52:42 +00:00
02b29e2f59 mb/google/ovis/var/deku: Set TCC_offset to 5
Adjust settings as recommended by thermal team.

Set tcc_offset value to 5 in devicetree.

BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
     built bootleg and verified test result by thermal team

Change-Id: I30f54ae6017c54c91ff9b432bba0ebd5bfc65ab9
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82614
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-27 12:52:32 +00:00
86028de8d4 mb/google/rex/var/deku: Update DPTF parameters
Adjust settings as recommended by thermal team.

Update DPTF parameters based on b:308704811#comment4.

BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
     built bootleg and verified test result by thermal team

Change-Id: I710682771bd0679ae4b44dd43be68f60e8984b2e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-27 12:52:19 +00:00
5ba17d5ccb security/memory_clear: fix wrong size of reserved memory range
The code used to reserve MEMSET_PAE_PGTL_SIZE (20 KiB) for page used
for clearing the memory above 4 GiB that was assumed to be 2 MiB page.
memset_pae() checks only the alignment and not the size of this region,
so no error was reported by it.

In most cases this reserved memory in 2-4 MiB range, and because this
range isn't usually used by coreboot (architectural stuff is located in
lower 1 MiB, coreboot tables and ramstage are close to TOLUM and payload
isn't yet loaded when the broken code is executed), it never caused any
problems.

Change MEMSET_PAE_PGTL_SIZE to MEMSET_PAE_VMEM_SIZE and fix wrong macro
definition to reserve properly sized region.

Change-Id: I0df15b0d1767196fe70be14d94428ccdf8dbd5d3
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-05-27 12:43:50 +00:00
ca88b5f0ac acpi/acpi_apic: use generic MADT IRQ override function for SCI override
Call acpi_create_madt_irqoverride from acpi_create_madt_sci_override
with the correct parameters instead or re-implementing the same
functionality.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7e6ee0eed837c2d46da62092b7cc5669dc177d8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82644
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-05-27 12:40:14 +00:00
96a193afa6 lint-stable-003-whitespace: Exclude DTB files
This excludes Devicetree blob files from the list of files to check for
superfluous whitespaces. A DTB file has recently been added in commit
33079b8174 ("lib/device_tree: Add some FDT helper functions").

Change-Id: Ic25ee5361163446370c530cccefa3bf085895d15
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82638
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-27 08:02:26 +00:00
f4acef9233 Makefile: Warn if flexible array members are not at the end
Change-Id: Ib704f7659d3b431ce7eebb4432c5b1a4272de3d2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77147
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-26 11:40:47 +00:00
afa39105d8 libpayload: Add x86_64 (64-bit) support
This patch introduces x86_64 (64-bit) support to the payload, building
upon the existing x86 (32-bit) architecture. Files necessary for 64-bit
compilation are now guarded by the `CONFIG_LP_ARCH_X86_64` Kconfig
option.

BUG=b:242829490
TEST=Able to verify all valid combinations between coreboot and
payload with this patch.

Payload Entry Point Behavior with below code.

+----------------+--------------------+----------------------------+
| LP_ARCH_X86_64 | Payload Entry Mode | Description                |
+----------------+--------------------+----------------------------+
| No             | 32-bit             | Direct protected mode init |
+----------------+--------------------+----------------------------+
| Yes            | 32-bit             | Protected to long mode     |
+----------------+--------------------+----------------------------+
| Yes            | 64-bit             | Long mode initialization   |
+----------------+--------------------+----------------------------+

Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81968
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-26 01:26:31 +00:00
4244527d8c acpi: add and use defines for LAPIC feature flags
Both the processor local APIC structure and the processor local x2APIC
structure use the same flag bit definitions. ACPI spec 6.4 was used as a
reference.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8101c2ea874c8b12b130dbe9a0a7e0f0d94adffa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-05-25 14:45:43 +00:00
824d9303f2 acpi: introduce and use ACPI_MADT_PCAT_COMPAT define
The multiple APIC flags table from the ACPI specification version 6.4
was used as a reference.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I36f67ca21465bc8753bb36896ee05669de6de333
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82640
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-25 14:42:57 +00:00
69bc2cc7de arch/arm64: Implement initial set of SMBIOS tables
Implement the two architectural tables: processor and cache.

Note that SoC/board code should override core-thread count
and, for spec-compliance, create CBMEM_ID_MEMINFO.

Change-Id: Iedae0f26f168bd6d3af866e35d9d39ddb01abc15
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-05-25 06:58:23 +00:00
f27b22ab4e arch/arm64: Support calling a trusted monitor
Implement support for generating an SMC to call a trusted monitor. Some
functions are provided to read the SoC ID from the monitor, if
supported.

Change-Id: I158db0b971aba722b3995d52162146aa406d1644
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78284
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-25 06:55:31 +00:00
c2ed5eaa12 soc/intel/xeon_sp: Move get_cxl_mode out of soc/util.h
get_cxl_mode() is the interface for CXL mode config check used by
SoC codes. It could be implemented by mechanisms outside of the
SoC codes, e.g. board codes or OCP VPD driver.

Move the interface declaration out of soc/util.h to a dedicated
header, a.k.a., soc/config.h, so that the implementation codes do
not need to include soc/util.h where there are lots of irrelevant
definitions. Future SoC config check interfaces could be added
to soc/config.h as well.

The default weak implementation is moved out of util.c to
config.c as well.

TEST=Build and boot on intel/archercity CRB

Change-Id: Ia0302b0d3fd93c49e1d6f64e8159f59d50f33e20
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82293
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-24 13:28:25 +00:00
8ed95c3d2b device/pci_rom: handle non-remapped VGA_BIOS_ID
While the SoC-level defaults for VGA_BIOS_ID are the expected correctly
remapped PCI VID/PID of the GPU which matches the PCI VID/DID inside the
VBIOS file, some mainboards override the VGA_BIOS_ID setting to the
non-remapped PCI ID. This resulted in coreboot not finding the VBIOS
file after commit 42f0396a10 ("device/pci_rom: rework PCI ID remapping
in pci_rom_probe"). The proper solution would be to not override this
SoC-level config in neither the mainboard code nor some external config
file. This however requires adding/using some mechanism to tell SeaBIOS
which VBIOS image to use for the GPU device. Once this is implemented,
the SoC default for VGA_BIOS_ID shouldn't be overridden any more and
this patch can be reverted again.

This sort-of reverts parts of commit 42f0396a10 ("device/pci_rom:
rework PCI ID remapping in pci_rom_probe"), but it still tries to find
the VBIOS image with the expected remapped PCI ID and only adds trying
the non-remapped PCI ID as a fallback when the file with the remapped
PCI ID doesn't exist and prints a notice in that case. Before the patch
referenced above, using the correct remapped PCI VID/DID resulted in a
warning about the CBFS file with the non-remapped name not being found,
but first checking the remapped version solves that problem.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7cd8e2036250f4ca2239b04cd070bbf0778b13aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-24 13:16:27 +00:00
ebfb285085 AUTHORS: Remove whitespaces at end of line
Change-Id: I8445ac2e1bfca6cbf9d4d544318eec666948a8c4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-05-24 11:06:45 +00:00
29c5e0012d AUTHORS: Update with 24.05 release info
This adds the Authors from the 24.02 tag to the 24.05 tag.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Icb53c62c9a122ccdf2548cc2eebc8b0316a844ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82617
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-24 11:02:50 +00:00
58a398e89d Update 24.05 release notes with final statistics
The pre-release notes never capture everything, so we need to do an
update to finalize them after the release is tagged.

This captures on additional SoC added right before the release and
updates the statistics.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id3efcd15597e4fee0bdbca76e474974ae32d3263
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82613
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-24 11:02:20 +00:00
36e2b97e4c libpayload: Inject head.S into libc, remove separate class
Integrate head.S directly into libc and remove all instances of head.o.

* Drop 'separate class' entry for head.S.
* Drop special treament for head.o inside lpgcc.
* Change the .text in `x86/head.S` to `.section .text._entry`.
* Drop arch/mock/head.c, initially added as a dummy file.

Change-Id: I156d781908fcc38d455bbf9f2c29e5ab95c7775a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-05-24 08:10:56 +00:00
814ae3b055 libpayload: x86: Move Multiboot header to include file
This moves the multiboot header into its own include file, simplifying
head.S and making it easier to include/exclude the multiboot header
based on config options.

BUG=b:242829490
TEST=Able to build and boot google/rex.

Change-Id: I59a22dfe36044b4dd64a5b028a134be7a7d02a48
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82533
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-24 08:10:51 +00:00
4050ef091a mb/google/trulo: Refactor gpio pad configuration
This patch tries to simplify the baseboard/variant GPIO programming
for Google/Trulo. The idea is to let each variant maintain
its own complete GPIO PAD configuration table instead of having a
back-and-forth call between baseboard and variants.

With this patch coreboot performing GPIO programming is now much
simpler where the common code block calls into respective variants
and gets the gpio table prior to the pad configuration.

BUG=b:334826281 ([TWL] Decouple GPIO from baseboard to variant)
TEST=Able to build google/orisa.

Change-Id: I4ab88ac094a45c608cd894feb5eeec24b867527a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-24 05:50:05 +00:00
2889787522 mb/google/nissa: Fix potential null pointer dereference
* Introduce a null check before calling `gpio_padbased_override`
  in `variant_configure_pads`.
* This prevents potential errors in cases where the
`variant_gpio_override_table` function returns a null pointer,
indicating that there are no override pads to configure.

BUG=b:334826281
TEST=Able to avoid hang incase there is no GPIO override.

Change-Id: I733210a08091b37eda6e6b0d6924aafd5e7e6280
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82628
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-24 05:49:55 +00:00
bfc92cb944 device: drop unnecessary CHECK_REV_IN_OPROM_NAME option
The CHECK_REV_IN_OPROM_NAME Kconfig option was introduced to solve the
problem of the PCI VID/DID combination of the Picasso iGPU not being
sufficient information to know which VGA BIOS file to run, so a new
function that additionally checks the PCI revision of that device was
introduced. Later it turned out that there might be a case where even
that isn't sufficient, so the soc_is_raven2() function is used in the
remap function to always use the correct VBIOS file.

Picasso is the only SoC that selected the CHECK_REV_IN_OPROM_NAME
Kconfig option, so all other SoCs are unaffected by this change.

Now that we use the VBIOS images with only the PCI VID and DID in the
CBFS file name for Picasso, SeaBIOS will find the VBIOS with the same ID
as the iGPU in CBFS and we don't need the workaround to add a third
VBIOS image via VGA_BIOS_DGPU_* that has the name that SeaBIOS expects.
This will result in SeaBIOS now running the VBIOS that has the same PCI
VID/DID as the hardware which will be the wrong one in the RV2 silicon
showing the PCO silicon PCI VID/DID, but that was also the case with the
VGA_BIOS_DGPU_* workaround where the board's Kconfig just selected one
of the two possible images during build time and hoped that it was the
correct one for that actual hardware. The only board where this patch
might cause a regression compared to the old behavior is the AMD Cereme
reference board with Pollock APU, but I'm not even sure if any coreboot
developer still has one of those boards, so I'm willing to accept that.

To properly solve the problem with SeaBIOS using the correct VBIOS file
in all cases, we'd need to generate that info during coreboot runtime
and somehow pass it to SeaBIOS, but that's out of scope for this patch.

TEST=On Mandolin with PCO silicon, the display output in both SeaBIOS
and Ubuntu still works. Booting Windows 10 via the pre-built EDK2
payload that I'm using also resulted in the display output working.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6de533c536044698d85404427719b8f534870fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82598
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23 21:54:26 +00:00
47eed41dcb soc/intel/xeon_sp/gnr/soc_iio: Remove unused <string.h>
Change-Id: I8d4500edaa0739921831a3b04131046599c35a87
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-05-23 20:18:03 +00:00
e3fbd2a958 mb/google/brox/var/brox: Remove mux references from typec port
The Type-C kernel driver no longer programs the AP mux, as of
https://review.coreboot.org/c/coreboot/+/82077. So remove device
references to the TCSS Mux control device from the Type-C port driver.

This eliminates the following kernel error which was observed as a
result of the kernel trying to program muxes it no longer has control
over:

[    4.618600] cros-ec-typec GOOG0014:00: Failed to get mux info for port: 0, err = -95
[    4.618608] cros-ec-typec GOOG0014:00: Configure muxes failed, err = -95

BUG=b:341331428
TEST=Run system reboot; configure mux kernel errors no longer seen.

Change-Id: I93e498b12b109c0e649a23a4a49868976a9ee06b
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82599
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23 18:29:15 +00:00
fe8323b7b6 mb/amd/birman/display_card_type.h: add missing include
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5208ceeec17051e7849263a4caa0838efd59c044
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-05-23 16:33:32 +00:00
4520555656 mb/amd/birman/display_card_type.h: add missing include guards
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaf4478814e672fb8cfae5ffc4fa89c475f5bb0b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82607
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23 16:33:20 +00:00
53523dc2a4 soc/amd/phoenix/chip_opensil.h: add missing include guards
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iba17d44772333ed59e3fdde1443a1862bae8e32f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82606
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-05-23 16:33:02 +00:00
3a5ed9b45a mb/google/brya: Add romstage early graphics for nissa
1) Add all changes needed for early graphics
2) select MAINBOARD_USE_EARLY_LIBGFXINIT for nissa

The InnoLux (N156HCN-EBA C7) panel is used for the device tree.

BUG=b:296433986
TEST=On-screen text message seen during MRC training on Craask

Logs:
[NOTE ]  MRC: no data in 'RW_MRC_CACHE'
[SPEW ]  bootmode is set to: 0
[0.171409] DP PHY mode status not complete
[0.175509] DP PHY mode status not complete
[0.179799] DP PHY mode status not complete
[0.184087] DP PHY mode status not complete
[0.188376] DP PHY mode status not complete
[0.192665] DP PHY mode status not complete
[0.196954] DP PHY mode status not complete
[0.201243] DP PHY mode status not complete
[0.205532] DP PHY mode status not complete
[0.209821] DP PHY mode status not complete
[0.214110] DP PHY mode status not complete
[0.218397] DP PHY mode status not complete
[INFO ]  Informing user on-display of memory training.

Change-Id: I33cfc5d1f8c25c344e598befd21c50a78a65275a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78932
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23 13:52:47 +00:00
c8b379bb79 mb/cwwk: Add CWWK CW-ADL-4L-V1.0 board
This board is the CWWK variant based upon Alder Lake with 4 2.5 GbE
ports, similar boards are available in other port configurations. As a
low cost, relatively high performance board with 4 NICs, it is well
suited for networking or 'homelab' tasks.

CPU: Intel N100 or N350
Memory: DDR5-4800 SODIMM (max 16 GB)
NIC: 4x Intel I226-V 2.5 GbE
Expansion:
- M.2 2230 E key
- M.2 2280 M key
- USB 2.0 header
- Fan header
External ports:
- DC power
- 4x Ethernet
- Display Port
- HDMI
- 4x USB 2.0
- Micro SD

Working:
- Boots Debian 12 with SeaBIOS and EDK II payloads
- Serial port
- External USB ports
- DisplayPort / HDMI
- 4x Intel I226 2.5 GbE NICs
- M.2 ports
- Micro SD slot
- ACPI S3

Not working / not tested:
- Fan (ITE IT8613E)
- Audio
- S0ix
- Internal USB ports

VBT extracted from vendor UEFI firmware version ADLN 0.01 x64
(04/04/2023 11:42:38).

Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be
Signed-off-by: Brandon Weeks <me@brandonweeks.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-23 12:36:46 +00:00
57e36a3320 cpu/intel/model_206ax: Program Ivy Bridge defaults for MSR_PKGC_IRTL
Ivy Bridge has lower latencies than Sandy Bridge has. Update MSRs
MSR_PKGC_IRTL with values from BWG.

Test: Lenovo X220 still boots.

Change-Id: Ib307e3b191ba68e016cc348f82e2dccf1dc9ae16
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78609
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-05-23 12:33:17 +00:00
93791db23e soc/intel/xeon_sp: Dump proximity domain info per types
Some proximity domain info are type specifics, e.g. base/size/dev
are effective for PD_TYPE_GENERIC_INITIATOR, but not for
PD_TYPE_PROCESSOR. Dump info per their type.

TEST=Build and boot on intel/archercity

Change-Id: I7e722a0577bba954efba3e91cc152c758c001d68
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-05-23 09:28:05 +00:00
0f87730a94 soc/intel/xeon_sp: Move proximity domain setting up
Move proximity domain setting up to ahead of attach_iio_stacks()
so that proximity domain info could be ready before
attach_iio_stacks()/create_xeonsp_domains().

For example in SPR, is_iio_cxl_stack_res() refers to proximity
domain info, and it will be called in create_xeonsp_domains().

TEST=Build and boot on intel/archercity

No significant boot log difference except for proximity domain
dump info display are moved ahead (with correct contents).

Change-Id: I594f0ec0c23e3b62c3bdd917ebf6e45be6e4069e
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82267
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23 09:27:59 +00:00
a839eb116b mb/google/nissa/var/orisa: Generate RAM ID for Micron MT62F512M32D2DR-031 WT:B
Add Micron part MT62F512M32D2DR-031 WT:B only for Orisa.

DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B       0 (0000)

BUG=b:337178014
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I559ed817250c40795e6c613794d4f65c636f5fc5
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82586
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23 03:01:02 +00:00
f85f1d7a4f Revert "mb/google/rex/var/deku: Configure GPIO"
This reverts commit 7088257b1a.

Reason for revert:  Intel suggest is NC only.
No need to change anything that isn't broken.

Change-Id: I976a85b35c69b03f1bc0ccd2bc7df923e47be815
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82572
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22 20:58:44 +00:00
fa27d2dc2a mb/prodrive/hermes: Tidy up hda_verb.c
Use the `AZALIA_PIN_CFG_NC(0)` macro instead of `0x411111f0` and tidy up
some comments (align them and be consistent with capitalisation).

Tested with BUILD_TIMELESS=1, prodrive/hermes remains identical.

Change-Id: I1ff1197b1309fc0e5b978d6d36867a3f1a68c67c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-05-22 16:55:41 +00:00
9251ddc27d mb/amd/birman/devicetree_phoenix_opensil: add USB PHY config
Now that we also have the devicetree registers for the USB PHY config
in the openSIL case, add the USB PHY config setting from the Phoenix
with FSP devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a0acbf1b9d705dbf09f4480eb35e71e587ddd44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-22 15:46:16 +00:00
d4938ba37b soc/amd/phoenix/chip.h: add USB PHY configuration for openSIL
Add the USB PHY configuration structs for the openSIL case, so that
those can be configured in the devicetree like in the FSP case.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ied25e90859c4b1bc9b876bed3f3c46358ca36d32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82584
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22 15:46:05 +00:00
af42198729 mb/amd/birman/update_devicetree_phoenix_opensil: update DDI1 config
Use the now common get_ddi1_type function to update the connector type
of the DDI1 port to match the display output extension card plugged into
the reference board.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7c51eab0d32e0a1708da415f690689a8ec38dcd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82583
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22 15:45:55 +00:00
84f8b8eb60 mb/amd/birman: factor out get_ddi1_type
Both port descriptor files used in the FSP case contain an identical
get_ddi1_type implementation, so factor it out into a separate file.
This will also allow using the same function in the openSIL case in a
following patch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6f5b75b9bdbdc67901d157079785c8fa2915bf0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82582
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22 15:45:44 +00:00
be1f05a24f mb/amd/birman/devicetree_phoenix_opensil: add static DDI configuration
Add a static DDI port configuration to the devicetree used in the
Phoenix with openSIL case. The configuration is taken from the
birman_ddi_descriptors array in port_descriptor_phoenix.c.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b85b04114591f3e9da183019c98ca2cb08e59da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82581
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22 15:45:26 +00:00
27cb75a075 soc/amd/phoenix/chip.h: add DDI configuration for openSIL
In the FSP case, the DDI descriptors aren't part of the devicetree and
are instead retrieved in romstage by calling the mainboard's
mainboard_get_dxio_ddi_descriptors function which allows updating the
descriptors during romstage where the devicetree is static. In the
openSIL case, the DDI configuration is first needed in ramstage, so we
can put this info into the devicetree and update it if needed in
ramstage.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3de12ff6af42e38751a3016efa313613677fa87a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82580
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-22 15:45:17 +00:00
abcbd5b998 mb/amd/birman/devicetree_phoenix_opensil: remove unexpected '<'
Remove the unexpected '<' char at the end of the comment about the PSPP
policy config.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id821351ce3a7a2b7844d8e7478fa3de3227a7da9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82579
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-05-22 15:45:08 +00:00
59d1796d66 soc/amd/phoenix/chipset_*.cb: remove TODO
Remove the TODO to update the chipset devicetree for Phoenix, since this
has already been done.

When re-checking the chipset devicetree, I found conflicting information
about the existence of the PCI bridge to an external PCIe port on bus 0
device 1 function 5, but after looking into this, I'm reasonably certain
that it either doesn't exist or at least wouldn't be usable, so I won't
add that one to the chipset devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8f0e1540ed45408e86186253d3982a7ba0065ac6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-05-22 15:45:01 +00:00
f2ac23fb13 mb/intel/archercity_crb: Fix build for specific configurations
Guard OCP functions calls to allow builds without OCP drivers.

Change-Id: Ie9a82387366a8bb3387bcba3ec7a4c7f0100f78c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-22 15:03:43 +00:00
1f199f283d mb/intel/mtlrvp: Include fw_config.c file
Update Makefile to include fw_config file for mtlrvp board.

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Id41cd8b015a796f7a959ceccf85106a48d15ae35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82559
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22 13:04:26 +00:00
6211c3f865 Revert "mb/google/brox: Update verb table to fix headset detection"
This reverts commit f867c9c547.

The new verb table breaks external mic detection on brox.
Revert and use old verb tables instead.

BUG=b:330433089
BRANCH=main
TEST=Verified headset on Brox
When connected to audiojack in power_save state of legacy hda driver,
headset is detected and audio is resumed.

Change-Id: I0d8c092de6166b2c62f5ecc3deaf4960128e6106
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82273
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22 13:03:35 +00:00
6a3ff9ce68 mb/google/brya/var/nova: Add SOLDERDOWN support
Nova will use SOLDERDOWN. Add memory.c to override baseboard.
Update dram id table for correct platform parameter.

BUG=b:328711879

Change-Id: I6fbce991ef5ab9f0e6216ad1a5af73fcc1996a2a
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82474
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-21 13:46:17 +00:00
7dcb3d9c72 mb/google/brox/var/greenbayupoc: Update verb table from ALC256 to ALC236
On GreenbayPOC, HDA Codec used is ALC236, different with Brox (ALC256)
Update to Realtek provided verb table for ALC236 audio codec.

BUG=b:336967284
TEST=Verified headset and audio workable on DUT with "rec" and
"aplay" command.

Change-Id: I9fbe57a0acab20387754f6b6cb5705e34c1c149b
Signed-off-by: Wu Garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82413
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-21 13:45:49 +00:00
33079b8174 lib/device_tree: Add some FDT helper functions
This adds some helper functions for FDT, since more and more mainboards
seem to need FDT nowadays. For example our QEMU boards need it in order
to know how much RAM is available. Also all RISC-V boards in our tree
need FDT.

This also adds some tests in order to test said functions.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I2fb1d93c5b3e1cb2f7d9584db52bbce3767b63d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81081
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-21 13:44:47 +00:00
25c737d403 tests/lib: Factor out file related functions
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I5c22913b35848c5ea32d6805ea081abefd3380bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82237
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-05-21 13:44:39 +00:00
62a6188da5 soc/intel/meteorlake: Add PsysPL2 configuration
psys_pl2_watts is configured in SoC node of devicetree.
Value represents Watts.

BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot

Change-Id: I9c4d62b93fc751db9e0ea04e475acb8861a844f8
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-21 13:37:09 +00:00
0da12e0f2a mb/google/brya/var/bujia: Add devicetree based on schematics
Add devicetree settings per the schematic.
Differences to gladios:
1. remove SD reader
2. remove EMMC setting
3. modify USB port distribution

FRONT
-------------------------------------------------------
|                                        A3   A1      |
|               C0                       A2   A0      |
-------------------------------------------------------

BACK
-------------------------------------------------------
|                    ---------------                  |
|                    |    TX25A    |                  |
-------------------------------------------------------

BUG=b:327549688
TEST= USE="-project_all project_bujia" emerge-brask coreboot

Change-Id: Ia010e99c21e8d6088f6bb873f79dc19cadc9e455
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81447
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-05-21 13:36:33 +00:00
b4949d3de5 crossgcc: Update LLVM from 18.1.5 to 18.1.6
Change-Id: Ie087f43e6f60df7b97d7d7b402d3540c3a0a2461
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-20 20:33:20 +00:00
c3086b12a4 util/docker: Change Debian suite from Sid to stable
Debian sid is too unstable at this point, and frequently ends up having
issues that cause the coreboot-sdk docker image to fail to build. Using
stable also better reflects what users will typically be running.

Also remove the parameters to quiet the apt-get install command so that
if something does break, we can see what happened more easily.

Fixes bug 536

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I41b6464b024df89c114db2cdb9367c0526eb0297
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82411
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-20 19:30:33 +00:00
455538d3ae 3rdparty/libgfxinit: Update submodule pointer
Update the submodule pointer to current main. This brings in 5 commits:

* e096913 connector_info: Fix HDMI/DVI default bytes per color setting
* 87469f2 gma config: Add new device IDs for Raptor Lake
* 4be2e75 gma: Update transcoder setup for TGL
* 4b991bf gfxtest: Drop unnecessary with of ancestor
* 17cfc92 tgl plls: Disable warnings about unused variable

Change-Id: Ic40edc773ba11ab9a0f9e92057bd687d10b95069
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82554
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-20 13:24:36 +00:00
78a26aca8b mb/prodrive/hermes/hda_verb.c: Refactor port B Vref cfg
Refactor the `get_port_b_vref_cfg()` function to only return the
variable bits of the value. The NID itself is not connected, and
the `misc` field in the verb conveys the Vref value.

Change-Id: I5108f5339c5b002403a4e5339da6d52046c8bcbe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82395
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-20 12:58:07 +00:00
f2d260d988 Libpayload: Rename arch variable _ARCH to _ARCHDIR for consistency
This commit renames the variable _ARCH to _ARCHDIR in the libpayload
build script (lpgcc) to align with the naming convention of other
variables used in this file.

This change improves code readability and maintainability.

Change-Id: Iea4af68e49ab1cd7ec8156a14f8215244e9c0622
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82479
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-18 18:27:53 +00:00
67a96902d5 mb/google/dedede/var/kracko: Disable un-used C1 port by daughterboard
Probe C1 port in devicetree and disable un-used C1/A1 port by FW_CONFG.

BUG=b:339534479
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
flash and check boot log on DUT.

Change-Id: I944ff6f2fa712e7579ed1c9879f75835adc3ac4c
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-05-17 17:48:59 +00:00
917bdbffd3 mb/google/brask/var/nova: Remove unused retimer
Remove unused setting for retimer.

BUG=b:328711879
Change-Id: I48d8680d43a07aa3408dfbf5b25b568c2b51b343
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82475
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-17 13:17:37 +00:00
557aad1df9 cr50: Replace "cr50" to "GSC" in debug messages
The cr50.c file currently prints "cr50" in debug messages no
matter the system is using Cr50 or Ti50. This can be confusing
for developers.

This patch replaces "cr50" with "GSC" in debug messages. Using
"GSC" makes the messages more clear and easier to search via
`grep`.

BUG=none
TEST=Build and test on karis

Change-Id: I21f66cf8b608ca4e4dc82d7a55a851ec996c8bb3
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82420
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2024-05-17 12:50:28 +00:00
43a54184b0 mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City
Beechnut City CRB is the 2 socket reference board for 6th Gen Xeon-SP
SP SoCs (Granite Rapids SP and Sierra Forest SP).

This patch initially sets the code set up as a compilation target with
GNR N-1 FSP, and with basic feature supports (Integrated IO Controller
(IIO) configuration, BMC, UART, HPET).

TEST=Build on intel/beechnutcity CRB

Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-16 21:05:28 +00:00
921ddba69e mb/intel/avenuecity_crb: Add GNR/SRF-AP 2S server board Avenue City
Avenue City CRB is the 2 socket reference board for 6th Gen Xeon-SP
AP SoCs (Granite Rapids AP and Sierra Forest AP).

This patch initially sets the code set up as a compilation target
with GNR N-1 FSP, and with basic feature supports (Integrated IO
Controller (IIO) configuration, BMC, UART, HPET).

TEST=Build on intel/avenuecity CRB

Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Co-authored-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-16 20:55:05 +00:00
6258093575 soc/intel/xeon_sp/gnr: Add IIO config utils
Add IIO configuration utils shared in GNR boards to handle the
complex IIO configuration settings.

Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Co-authored-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-16 20:52:20 +00:00
cc82f74605 chromeec/ec_acpi: Convert TK_DICTATE to ps2_action_key
When support for the dictation key was added in commit f2782b8328
(acpigen_ps2_keybd: Add support for dictation key), I had failed to
include this portion of the change in that commit. The top row key of
`TK_DICTATE` needs to be converted to the ps2_action_key.  This commit
simply adds that mapping so that it can be translated.

BUG=b:333101631
TEST=Flash DUT that emits a scancode for a dictation key, verify that it
is mapped to KEY_DICTATE in the Linux kernel using `evtest`.

Change-Id: I1be8c0a96931cca36e6bbbfa0be7d36c4cd93768
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82274
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-16 17:08:56 +00:00
e189043aec mb/amd/birman/update_devicetree_phoenix_opensil: use common header file
Instead of including stub/mpio/chip.h, include chip/mpio/chip.h that
will include the correct implementation to be able to use the same file
with both the openSIL stub and the actual openSIL implementation glue
code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaae26a0dfe0ba96842e72582c06f1b0b3f29871c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82472
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-16 15:47:15 +00:00
c61b35b696 mb/google/rex: Remove redundant VPU enablement code
This patch removes VPU enablement code that is no longer needed because
the VPU is already enabled by default in the baseboard devicetree.

BUG=b:332488817
TEST=Able to see VPU PCI device in lspci list after booting
google/screebo to OS

Change-Id: I94de92e970be1548068ed4e19309a95129f041ff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82423
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-16 13:03:31 +00:00
a0426b6d93 mb/google/rex: Enable VPU device for Rex/Ovis baseboard
This patch enables the Versatile Processing Unit (VPU) by default for
Rex/Ovis baseboard. VPU is a dedicated AI engine that is included in
the 14th generation "Meteor Lake" Core processors.

The VPU is designed to efficiently run AI models directly on the
system on chip (SoC). There is no power regression observed while
keeping the VPU default enabled to run AI models natively hence, this
patch enables the VPU by default.

BUG=b:332488817
TEST=Able to see VPU PCI device in lspci (0:11:0) list after booting
google/screebo to OS.

Change-Id: I8b3521c8ec613b002f971eaf9d346927fe8cd656
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-16 13:03:24 +00:00
1b2fe88a04 include/device/pci_ids.h: Update TWL device IDs
Set lowercase hex format for IGD DIDs.

BUG=b:326901448
TEST=Build tivviks and verify the IGD IDs.

Change-Id: I1299512d1c48eba854fea2ec394cef40d44a87d7
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82414
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-16 11:29:40 +00:00
3d4128299f mb/google/rex/var/baseboard/ovis: Support CPU power limits per variant
There is no direct way to override CPU default power_limits for
different SKUs.

This CL add structure variant_get_soc_power_limit_config() for
variants to define and configure the values of soc_power_limits_config
for current CPU SKU.

Variants can override these values i.e. pl1, pl2, psyspl2
in variant_devtree_update().

BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST=FSP debug emerge-ovis coreboot intelfsp
     check overrides setting

Change-Id: Ib60fa4e3fc502d0aeb0c94ad46ba5a55b4dd027c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82199
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-16 11:28:58 +00:00
ff79993e95 mb/google/brask/var/bujia: Update gpio table
Based on latest schematic to update the gpio table.

BUG=b:327549688
TEST= USE="-project_all project_bujia" emerge-brask coreboot

Change-Id: I3d01e3b9eaef72d9e143f5163ee49d8c8f455b5f
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82412
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-16 11:28:00 +00:00
a8fdafa427 cpu/x86/pae/pgtbl.c: remove dead paging_identity_map_addr()
This function had roughly the same use (except PAT) as part of
memset_pae(), however the latter is able to make use of PAE and map
physical memory located above 4 GB. Remove paging_identity_map_addr()
to avoid semi-duplicated code.

The function has been unused since CB:26745.

Change-Id: I7a4ebd84a6f5d222c3b2c6c6e3d26d6464cf01b8
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82248
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-15 16:53:50 +00:00
07913736e0 Doc/releases: List toolchain updates in coreboot-24.08-relnotes
Report upgraded version for ACPICA, CMake, nasm, LLVM and GCC.

Change-Id: I93a9ae4a2f4c3403a6e8c9a8b7aca74b996e7db8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82410
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-15 16:51:31 +00:00
744e389800 payload/external/edk2: Explicitly define the build arch as X64
Upstream commit 11ad164bce (UefiPayloadPkg: Make UPL build script arch
agnostic, 2024-02-22) changes the build script's behavior to not assume
the arch. Without defining BUILD_ARCH, the build script will not
function properly and results in the payload failing to build.

Both UefiPayload and Universal Payload can only be built in X64.

Change-Id: Icd942d0c15a99231d09f9cbdc5eb48333b6aa6e5
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-05-15 16:49:26 +00:00
ab42a64d99 Add 24.08 release notes template
In preparation for the upcoming release, add the template for the
24.05 release and update index.md.

Change-Id: I733f541a2d6e556c82aff1656fe7f79ae3673ba7
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82400
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-05-15 15:16:52 +00:00
b43accd233 mb/amd/birman: add function to update MPIO config in devicetree
Phoenix 2 has less PCIe lanes than Phoenix, so some of the lane end
numbers need to be adjusted to take that into account. When the Kconfig
options WLAN01 or WWAN01 are set, either the WLAN or the WWAN card uses
both PICe lanes that are available for those two devices, so the MPIO
descriptor information the devicetree needs to be updated accordingly
and the bridge to the PCIe port that doesn't have any lane left needs to
be disabled. Two other PCIe devices will be disabled when the
corresponding Kconfig options ENABLE_EVAL_CARD and DISABLE_DT_M2 have
the value that results in the device being disabled via some GPIO driven
by the EC. Since the code is specific to the openSIL case, only include
it in the build in the CONFIG_BOARD_AMD_BIRMAN_PHOENIX_OPENSIL case.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I23c14cc03980ea1e39f7e5aec551b975c237e487
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-05-15 15:01:55 +00:00
d7158c8149 mb/amd/birman/devicetree_phoenix_opensil: add stub MPIO chips
Add the stub MPIO chips that contain the PCIe engine configuration for
the external PCIe interfaces to the devicetree. Birman's
port_descriptors_phoenix.c was used as a reference. The static
configuration in the devicetree assumes that the default WLAN0_WWAN0 is
selected; for the other cases we'll still need to fix up things
accordingly in the mutable devicetree. The WLAN01 and WWAN01 cases still
need to be handled in a follow-up patch. Since openSIL currently doesn't
use the info from the gpio_group struct element, but deasserts both PCIe
reset pins GPIO 26 and 27, the gpio_group isn't specified in the chip
configuration in the devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icabe60322d46c1195284dd77ec39f9d143e3d2cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-15 15:01:05 +00:00
7728ed3ea2 mb/google/brya: Create orisa variant
Create the orisa variant of the nissa reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)

BUG=b:337178014
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_ORISA

Change-Id: I0cd8d763ffd8864b455a7f8909e95f6aee8bb23e
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-15 12:08:23 +00:00
acdd8dd14d util/crossgcc: Update GCC from 13.2 to 14.1.0
Change-Id: Idf5912d1fcdfabab7fe006b7e0cd4ebd25c07d09
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81683
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-05-15 01:53:34 +00:00
e885aa5a05 util/crossgcc: Update LLVM from 17.0.6 to 18.1.5
Change-Id: I03a44e0c23a925396f614f282882405dc886ba58
Signed-off-by: Lennart Eichhorn <lennarteichhorn@googlemail.com>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-05-15 01:53:22 +00:00
0090039bbd crossgcc: upgrade nasm from 2.16.01 to 2.16.03
Remove the patch since it was picked from master before and thus it's
included in the new release.

Change-Id: I70408b189b974f8abaadc66f0c809a1dbe10504b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81900
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-15 01:53:10 +00:00
41fdb882f1 util/crossgcc: Update ACPICA from 20230628 to 20240321
Change-Id: I41f56ba58af51b1ec1d7554fb35a49ccf9e778f6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-05-14 23:35:39 +00:00
6b4036ee9e util/crossgcc: Update CMake from 3.28.3 to 3.29.3
Change-Id: Iaf2d4f579d987fbfd4187ae41c1be5cec55e0e8e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-14 23:34:36 +00:00
5a0207e56a Documentation: Finalize 24.05 release notes
These are the final release notes for the 24.05 release before the tree
is marked with a tag, completing the release. We will update the notes
with final numbers and anything else after the release is tagged.

The 24.05 release will be announced a week later, barring any issues
that require an updated release tag.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I00be0127351f8641116b4bc523c266628b084e69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82407
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-14 22:13:50 +00:00
a5487ba17a soc/intel/xeon_sp: Add Granite Rapids initial codes
coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single
IO-APIC Xeon-SP platform. The same set of codes is also used
for SRF (Sierra Forest) SoC.

This patch initially sets the code set up as a build target with
Granite Rapids N-1 FSP (src/vc/intel/fsp/fsp2_0/graniterapids).

1. All register definitions are forked from SPR (Sapphire Rapids)
and EBG (Emmitsburg PCH)'s codes are reused.

2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip
common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later.

Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Co-authored-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-14 20:49:04 +00:00
ed366c07bb Documentation/vboot: Update vboot supported boards list
Auto-generated by util/vboot_list/vboot_list.sh.

Change-Id: I5e1a7046b03687d15e8ceae2074ec25aa72a6f28
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82399
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-14 20:33:35 +00:00
5a86707417 soc/intel/common: Add RPL tracehub support
Add PCI ID for RPL tracehub and update the PCI ID in the
pci_device_ids[] in tracehub.c.

Reference:
Raptor Lake External Design Specification Volume 1 (640555)

BUG=None
TEST=Verified on brox

Change-Id: I5d5c6c8ff44bcb5a7bbbd3e27a1577c169ecd6a9
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-05-14 19:48:55 +00:00
f1e4067a90 util/autoport: Remove incorrect comment
Yes, the DSDT revision is the OEM revision. But most certainly not that
of the board being ported. Because no one seems to care about the value
(newer boards inexplicably use lower values even though this represents
a date in 0xYYYYMMDD format), simply drop the incorrect comment. Should
save a bit of effort when reviewing mainboard ports: no longer will one
have to ask authors to drop the comment.

Change-Id: I9c425573e4fcb0f670a780e7821e815eadc8a2aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-05-14 19:48:31 +00:00
ff0f6dcba3 util/autoport/.gitignore: Ignore logs folder
The README suggests using `logs` as the folder name where autoport puts
the generated logs. Thus, add this folder to .gitignore for the sake of
convenience. Yes, people can use other folder names, but `logs` is most
commonly used.

Change-Id: I37906b43ba3e132de616184e4a5082ce00f4b230
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82398
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-05-14 19:48:17 +00:00
2e532b19d5 soc/intel/common: Add Panther Lake DIDs
Reference:
Panther Lake External Design Specification Volume 0.51 (815002)

BUG=b:329787286
TEST=verified on Panther Lake Simics Platform.

Change-Id: I941d6e1c8a697234b8e64a2523e60587897d7f7a
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81848
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14 13:12:00 +00:00
1057865a89 soc/intel: Add Panther Lake PCIE device IDs
Add Panther Lake specific CPU and PCIE device IDs

Reference:
Panther Lake External Design Specification Volume 0.51 (815002)

BUG=b:329787286
TEST=verified on Panther Lake Simics Platform.

Change-Id: I82f47b6077e28a01f34c59b7e7697323b3d5f990
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81849
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14 13:11:04 +00:00
47e7240ffc soc/intel/common: Add Lunar Lake IAA and TBTRP3 device IDs
Reference:
Lunar Lake External Design Specification Volume 1 (734362)

BUG=b:329787286
TEST=verified on Lunar Lake RVP board (lnlrvp).

Change-Id: I92b65c946682387cbb841d558c6f0a7cb0fcd4ac
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81850
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14 13:10:34 +00:00
e3b1a9d7a1 mb/google/nissa/var/glassway: Set VccIn Aux Imon IccMax to 25 A
Iccmax of VccIn_Aux is 25A with MBVR design.

BUG=b:330117043
BRANCH=firmware-nissa-15217.B
TEST=Local build successfully and boot to OOBE normally.

Change-Id: I105dc9df53c624fd7fc697408a1097e023a3cd68
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81445
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14 13:10:10 +00:00
e7e717b3a6 mb/google/nissa/var/quandiso: Add stop pin for G2 touchscreen
Add stop pin control for G2 touchscreen refer to
G7500_Datasheet_Ver.1.2.

BUG=b:335803573
TEST=build and verified touchscreen works normally

Change-Id: I4f085c67c0cdb8b9ca3ff03993fda69cca6319ef
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82254
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14 13:09:43 +00:00
d2f810ed9f mb/google/brox/var/greenbayupoc: Add vbt from brox
Copy the data.vbt from brox to greenbayupoc

BUG=b:326413034
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT

Change-Id: I1e8101519ab2ecbb4654c20485fbe83c90656e4d
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82108
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14 13:09:29 +00:00
bb616ca483 mb/google/brox/var/greenbayupoc: Update devicetree and gpio settings
Based on latest schematics GREENBAY_0412.SCH update the gpio and
devicetree settings.

BUG=b:326413034
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT

Cq-Depend:chrome-internal:7218819
Change-Id: I59f25b8abb7dd8a2dff7ff567b231bddc9db8455
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-14 13:08:30 +00:00
d05611d264 arch/x86: Remove unused protected_mode_jump API
This patch removes all instances of the `protected_mode_jump` API and
its associated header file.

The API is no longer used by any code within the tree.

BUG=b:332759882
TEST=Built and booted 64-bit coreboot with 32-bit payload successfully.

Change-Id: I3eb31b09c92512338ccc540f60289960bd6bf439
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82372
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14 13:08:04 +00:00
06b25c26a1 x86: Switch to protected_mode_call_1arg for correct argument passing
The payload execution process has been updated to utilize
protected_mode_call_1arg in order to guarantee proper handling of
function parameters.

The previous use of protected_mode_jump with a "jmp" instruction did
not allow for proper stack setup for argument passing, as the calling
convention was not aligned with the System V ABI calling convention.

This patch ensures that calling into the libpayload entry point using
protected mode is now aligned with the System V ABI calling convention.

This resolves an issue where retrieving the "pointer to coreboot tables"
from within the libpayload entry point was failing due to incorrect
argument passing.

BUG=b:332759882
TEST=Built and booted 64-bit coreboot with 32-bit payload successfully.

Change-Id: Ibd522544ad1e9deed6a11015b0c0e95265bda8eb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82294
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-05-14 13:07:28 +00:00
94d50bbe2a mb/google/nissa/var/sundance: Update HID offset to 0x01 for Focal touchpad
Currently the Focal touchpad does not work. Based on the Focal touchpad vendor, upadet the HID descriptor address from 0x20 to 0x01.

BUG=b:339756281
TEST=Build and check Focal touchpad can work.

Change-Id: I383ad907e6a23c34ab1bd0f6594a87564e21181d
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-14 13:06:12 +00:00
958d29fd83 mb/google/dedede/var/pirika: Add SPD IDs for two new memory parts
Support Memory of Micron MT53E512M32D1NP-046 WT:B and Hynix
H54G46CYRBX267 in mem_parts_used list, and generate SPD ID for these
parts.

DRAM Part Name                 ID to assign
MT53E512M32D1NP-046 WT:B       0 (0000)
H54G46CYRBX267                 0 (0000)

BUG=b:337173071
BRANCH=firmware-dedede-13606.B
TEST=Run command "go run \
     ./util/spd_tools/src/part_id_gen/part_id_gen.go \
     JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \
     src/mainboard/google/dedede/variants/pirika/memory/\
     mem_parts_used.txt"

Change-Id: I9b1a2a622d0ca1298671b1da58beacc1b4244769
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82094
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-14 13:05:49 +00:00
fbc4f699bc doc/release/24.05: Add git submodule updates
Change-Id: I136905d60de14749cfa325b24de3df204f0135ec
Signed-off-by: Lennart Eichhorn <lennart@zebre.us>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82116
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13 20:18:52 +00:00
8869414105 mb/asus/p8z77-m: Support AC97 front audio panel
Add a nvram option for front audio panel type.

If it is set to AC97, reprogram front line out and microphone
pins to match vendor firmware under same configuration.

TEST=On asus/p8z77-m housed in an AOpen H340D case with an AC97
front audio panel, front panel line out port is now available as
headphone port in Fedora 39 with this patch applied and option
set correctly. And it works. Without the patch (or with this option
set to HD Audio), front audio ports are completely inoperable.

Change-Id: I39ccf066d87c5744a697599861719182768e0728
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-05-13 17:18:22 +00:00
ca3764ab18 nb/intel/haswell: Use <device/dram/ddr3.h>
Change-Id: I353ceb7ab5ec0c82f5e717c856ad7934fcbd03b6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82355
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13 17:12:45 +00:00
200075ba2d mb/google/rambi: Use <device/dram/ddr3.h>
Change-Id: I3aa669042908b92d7b270df077a352e197071780
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82354
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13 17:12:30 +00:00
c2837e70b9 soc/intel/xeon_sp: Use <spd.h>
Change-Id: Ib86df42c74474ab6d0bd389073c36ca0761748af
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-05-13 17:12:19 +00:00
27becf5da6 mb/intel/{harcuvar,kunimitsu}: Use <spd.h> and <dram/ddr{3,4}.h>
Change-Id: I2d73f7815e83e8bf0c6d0a402d32bc99c32c7d90
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82243
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13 17:11:35 +00:00
7809eb8db6 mb/google/{eve,glados}: Use <spd.h> and <dram/ddr3.h>
Change-Id: I48b833a3727d4b7d7c50371dbe8f090983d80e36
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-13 17:10:25 +00:00
a8a4a39adc util/inteltool: Fix Emmitsburg GPIO Group J pad names
Pad names now matching soc/intel/xeon_sp/ebg/soc_gpio.c.

Test: Generated pad names for ASRock Rack SPC741D8 now compile.

Change-Id: Ied53b654f905add86a05bce8c2e366dea9ccf4d3
Signed-off-by: Fabian Meyer <fabian.meyer@student.kit.edu>
Co-authored-by: Yussuf Khalil <yussuf.khalil@kit.edu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82205
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13 15:09:45 +00:00
6fe35343b1 soc/amd/common/block/psp: Comment unused symbol
This adds a comment for unused AMD_FWM_POSITION_20000_DEFAULT.

Change-Id: Id8369f488893e7e5b2e7e7126d1b53199ed1aa77
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-05-13 14:30:54 +00:00
de7492e942 mb/google/brya/var/riven: Copy VBT data file from nivviks
Add data.vbt file for riven recovery image. Select INTEL_GMA_HAVE_VBT
for riven as it has a VBT file now.
The VBT file is copied from the nivviks reference board.

BUG=b:337169542
TEST=build pass

Change-Id: I499c1b3e61581483a1640375270f7707ebe8deeb
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82269
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13 12:32:17 +00:00
33192a3752 cpu/x86/pae/pgtbl.c: remove dead map_2M_page()
This function isn't used anywhere. It probably wouldn't work with
current coreboot anyway, as it identity mapped lower 2GB of RAM, while
ramstage is run from CBMEM, which is usually just below top of memory.

It was last used in K8 code that is long gone.

Change-Id: I97e2830f381181d7f21ab5f6d4c544066c15b08c
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
2024-05-13 12:31:32 +00:00
7e7e569db4 mb/google/brox: Disable c1 state auto-demotion
Disable c1 state auto-demotion support for brox

BUG=None
BRANCH=None
TEST=Boot brox and verify in fsp debug logs

Change-Id: I18d40cd721d46fce4702cf1a943583cd41c03cf4
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82104
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13 12:30:40 +00:00
254a4b9072 soc/intel/lunarlake: Support stepping A0_2
Details:
- Add support for new Lunar Lake MCH ID 0x6410
- Add new CPU id 0xb06d1

Reference:
Lunar Lake External Design Specification Volume 1 (734362)

TEST=Build, boot the system and verfiy MCH-ID prints in bootblock stage.
	Below prints verified on Lunar Lake RVP board (lnlrvp).
	[DEBUG]  MCH: device id 6410 (rev 02) is LunarLake M

Change-Id: I976d7f269485633d835d204afa224736d71baaa8
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81847
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-12 18:57:39 +00:00
7f2020b712 soc/intel/common: Add Lunar Lake CNVI device IDs
Without this patch, ACPI SSDT does not supports and lists CNVW.

With this patch, verified "CNVW" in ACPI SSDT listing.

Scope (\_SB.PCI0)
    {
        Device (CNVW)
        {
            Name (_ADR, 0x0000000000140003)  // _ADR: Address
            Method (_STA, 0, NotSerialized)  // _STA: Status
            {
                Return (0x0F)
            }
        }
    }

Reference:
Lunar Lake External Design Specification Volume 1 (734362)

BUG=b:329787286
TEST=verified on Lunar Lake RVP board (lnlrvp).

Change-Id: I5a0a3fbc9f43a6a573e33fcf3901055e10faaed1
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81846
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12 18:57:05 +00:00
83fd2d8a28 mb/google/rex/var/deku: Correct FVM Itrip for GT VR domain
Previous CL misspelling VR domain to IA not GT which cause
FVM Itrip(GT) not set correctly.

This CL corrects it to VR_DOMIAN_GT and confirm FVM Itrip(GT)
has set to 54.

BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST= FSP debug emerge-ovis coreboot intel-mtlfsp
      check overrides setting
      IccLimit[1] = 216 ( 1/4 A)

Change-Id: I99df053869aa11b7c82aa0b7f7ec0acf73467a76
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-12 18:55:47 +00:00
0fc69141e5 vc/amd/opensil: introduce common mpio/chip.h header file
The chip drivers in the devicetree use the path where the corresponding
chip.h file resides both to include this chip.h file in the static.c
generated by util/sconfig from the devicetree and also for the names of
the chip config and chip ops struct. To be able to build a SoC using
either the MPIO chip driver from the openSIL stub or from the actual
openSIL glue code without needing different devicetree files for the
different cases, introduce a common MPIO chip.h file that then includes
the correct MPIO header file. The chip config and ops structures also
need to be renamed to take this change into account.

Thanks to Matt for pointing out how to make the path to the actual MPIO
chip.h file configurable via a Kconfig setting. This allows overriding
this path from site-local without the need to have any reference to
site-local in the upstream code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iead97d1727569ec0d23a2b9c4fd96daff4bebcf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82262
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12 18:54:50 +00:00
444edcba5d vc/amd/opensil/*/mpio/chip.h: add missing include guards
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idef3b661b1cf3008373e61e0760a7dd3b9e9fede
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82261
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12 18:53:48 +00:00
7898594b7c util/intelp2m: add Meteor Lake support
Enables parsing Meteor Lake inteltool output into gpio.h pad macros.

Change-Id: Iaebd51d587507e68c6f263b92dc61cb6c0411bf8
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81916
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2024-05-12 18:53:31 +00:00
c42e28f077 mb/protectli/vault_cml: use combo v1/v2 FSP
Also switch configs to use combo v1/v2 FSP
The reason for this change is to simplify configuration - instead of
multiple targets for VP4630 and VP4650 or VP4670, it's now possible to
have one target covering all VP46x0.

Change-Id: I1a6f6e873e4ec35b9777dc17c0495151348d1d88
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81963
Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-12 18:52:41 +00:00
1a395728df mb/google/brox/var/greenbayupoc: Configure board for SODIMM use
Configure SODIMM settings for greenbayupoc. The SODIMM settings are
copied from mainboard/google/brya/variants/baseboard/brask/memory.c.

BUG=b:336955026, b:332230842
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot to OS
using Hynix HMAG56EXNSA051N 4G and Micron MTA8AFT1G64HZ-3G2R1 8G SODIMM.

Change-Id: I1552cadfa81c48fe561947ded078bcca2e6bc6ad
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82085
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-12 18:51:46 +00:00
a56baa1d50 mb/google/brya/var/riven: Generate SPD ID for supported parts
Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.

1. MT62F1G32D4DR-031 WT:B (Mircon)
2. MT62F512M32D2DR-031 WT:B (Mircon)
3. H9JCNNNBK3MLYR-N6E (Hynix)
4. K3LKLKL0EM-MGCN (Samsung)
5. K3LKBKB0BM-MGCP (Samsung)
6. H9JCNNNCP3MLYR-N6E (Hynix)

BUG=b:337169542
TEST=build pass

Change-Id: I0ff3b1e14fb8bb87d8fc9cbe0e177a5bcedef08c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82255
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-05-12 18:50:39 +00:00
eacc1c7ea9 util/inteltool: add Meteor Lake support
Based on:
Intel Core Ultra Processor External Design Specification
Meteor Lake SOC IO Registers
Meteor Lake-U/H/U Type4 and Arrow Lake-U/H GPIO Implementation Summary

Change-Id: I7473119fa97c57cd2a1303f08f964abd0ca96270
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2024-05-12 18:50:10 +00:00
6d5cc39a78 LinuxBoot/Makefile: initramfs not build for bzImage
initramfs is not build when bzImage is selected

Add build/initramfs dependency to build/bzImage

BUG = N/A
TEST = Built and boot facebook monolith

Change-Id: I002202a0340347e78ce22024761d997605bd3f72
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77606
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-11 18:28:30 +00:00
cf5fc2312a include/efi: Override EFIAPI macro for x86_64
This commit overrides the EFIAPI macro definition when using FSP on
x86_64 to ensure the correct calling convention is used.

On i386, there is no side-effect since the C calling convention used
by coreboot and FSP are the same. However, on x86_64, FSP/UEFI uses
the Microsoft x64 calling convention while coreboot uses the System
V AMD64 ABI.

This change resolves this incompatibility by setting EFIAPI to
attribute((ms_abi)) on x86_64 when using FSP.

TEST=Able to build google/rex0 in 32-bit and 64-bit mode.

Change-Id: Ifae910be66d550af04cce5136d186a7e9dd085b3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82266
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-11 08:28:17 +00:00
f5be5e4999 driver/intel/fsp2_0: Update soc_binding.h for coreboot compatibility
Included <efi/efi_datatype.h> to address coreboot style header
definitions rather using EDK2 header <Base.h>.

TEST=Able to build google/rex0.

Change-Id: I66559872c8d137d1baef5860fb98cad2a5214368
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82265
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-11 08:28:11 +00:00
3a3804f458 drivers/mipi: Update init code for IVO_T109NW41 panel
1. VCOM OTP burning, initial code Settings can be deleted, B6h
2. Fine-tune VGH, VGL, VGHO, VGLO voltage, B1h PA6
3. Boot CLK performance change: add E9h, C7h, E9h
4. Extend TFT life: D5h PA25~PA32,D3h PA1~PA5;
5. Gamma optimization: E0h
6. Improve picture quality, add EQ: D2h to CLK
7. Press mura to improve and modify B1h PA4 and PA5

BUG=b:320892589
TEST=boot ciri with IVO_T109NW41 panel and see firmware screen

Change-Id: I13421660faba9ef8e33a51c5ab28aeb1388aff40
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82240
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2024-05-10 09:25:59 +00:00
94c6cd1480 include/spd.h: Add SPD_MEMORY_TYPE_LPDDR3_INTEL into spd_memory_type
Change-Id: I694af163fb530be49561e74e74d9c08e04986a44
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82223
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-09 11:24:40 +00:00
365cd34813 include/spd.h: Add new spd_memory_type values
This adds LPDDR4X, DDR5,LPDDR5, DDR5_NVDIMM_P and LPDDR5X, according
to revision of JESD400-5A.01, January 2023.

Change-Id: I15802da03dc748c0e7f6b035fed25371afe3eed4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82217
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-09 11:24:31 +00:00
3d807d262f arch/arm64/Makefile.mk: Switch linker to GNU GCC
TF-A migrates the default choice of linker to GCC in order to enable
LTO. Change BL31_LDFLAGS from `--emit-relocs` to '-Wl,--emit-relocs', so
that GCC is able to pass `--emit-relocs` to the linker.

[1]: https://review.trustedfirmware.org/c/26703

BUG=b:338420310
TEST=emerge-geralt coreboot
TEST=./util/abuild/abuild -t google/geralt -b geralt -a
TEST=./util/abuild/abuild -t google/oak -b elm -a

Change-Id: I65b96aaa052138592a0f57230e1140a1bb2f07ac
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82189
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-09 08:34:05 +00:00
904c09bb9c Update arm-trusted-firmware submodule to upstream master
Updating from commit id 17bef2248:
2024-02-05 23:33:50 +0100 - (Merge "feat(fvp): delegate FFH RAS handling to SP" into integration)

to commit id 48f1bc9f5:
2024-05-02 10:13:54 +0200 - (Merge "feat(zynqmp): remove unused pm_get_proc_by_node()" into integration)

This brings in 535 new commits.

Change-Id: I562dd4d1e1ddc187341ae5856d47eeedfca85619
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-05-09 08:33:52 +00:00
817c58c2ae mb/google/brox: Sending End of Post (EOP) asynchronously
Currently EOP message is sent to CSE late in the boot flow. Instead send
it asynchronously to save ~10 ms in boot time.

BUG=b:337330958
TEST=Build Brox BIOS Image and boot to OS.

Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-09 08:33:24 +00:00
7e3cabec51 arch/arm64/Makefile.mk: Unset toolchain vars for BL31
This change is for upcoming arm-trusted uprev commit.

TF-A refactors the toolchain detection in [1][2]. After that `AR`,
`CC`, `LD` and other toolchain variables have precedence over
`CROSS_COMPILE`.

Since ChromeOS build system also sets those toolchain variables when
building coreboot, it results that TF-A uses CrOS GCC instead of
coreboot SDK. It needs to unset those variables in order to make
`CROSS_COMPILE` effective.

TF-A upstream changes the default linker from BFD to GCC in [3].
Therefore, temporarily overriding LD as $(LD_arm64} to fix the below
build error.

aarch64-elf-gcc: error: unrecognized command-line option '--emit-relocs'

In addition, TF-A wrapped LD with single quotes to solve Windows path
issue[4]. On MT8173 platform, `--fix-cortex-a53-843419` is appended to
$(LD_arm64} for ERRATA_A53_843419. It results in the below build error.

/bin/sh: 1: --fix-cortex-a53-843419: not found

Since `--fix-cortex-a53-843419` is never passed to TF-A, simply extract
the LD command from $(LD_arm64) by $(word 1, $(LD_arm64)).

[1]: https://review.trustedfirmware.org/c/24921
[2]: https://review.trustedfirmware.org/c/25333
[3]: https://review.trustedfirmware.org/c/26703
[4]: https://review.trustedfirmware.org/c/26737

BUG=b:338420310
TEST=emerge-geralt coreboot
TEST=./util/abuild/abuild -t google/geralt -b geralt -a -x
TEST=./util/abuild/abuild -t google/oak -b elm -a -x
TEST=./util/abuild/abuild -t google/cherry -x -a

Change-Id: Ieac9f96e81e574b87e20cd2df335c36abcb8bb5c
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-09 08:32:49 +00:00
a29d06a952 soc/mediatek/mt8188: devapc: set devapc permission for MFG
In order to support SVP Feature, EMI-MPU has to give MFG permissions
to allow MFG to access secure buffer by secure read and write.
Currently MFG is in domain 0, which include many other masters.

Move MFG to domain 6.
Set MFG remap, so that MFG can switch to protect mode by MFG register.
Change MFG permission from NO_PROTECTION to SEC_RW_ONLY for domain 0,
so that only AP in secure mode can access MFG_S_S-2 and MFG_S_S-5.

BUG=b:313855815
TEST=emerge-geralt coreboot

Change-Id: Ic6fb7d85bf9d4d92946a045a274b274abc440e1d
Signed-off-by: Fei Yan <fei.yan@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-09 08:18:07 +00:00
50b8880cd4 mb/google/brox: Fix the pad reset config for WLAN Wake interrupt
Update the pad reset config for WLAN Interrupt from PLTRST to DEEP
so that it can still act as a wake source during S3 suspend.

BUG=b:336398012
TEST=Build Brox BIOS image and boot to OS. Suspend to S0ix & S3 and
wakeup successfully using Wake on WLAN.
268 | 2024-05-07 13:56:44-0700 | S0ix Enter
269 | 2024-05-07 13:57:07-0700 | S0ix Exit
270 | 2024-05-07 13:57:07-0700 | Wake Source | GPE # | 3
271 | 2024-05-07 13:59:01-0700 | ACPI Enter | S3
273 | 2024-05-07 13:59:26-0700 | Wake Source | PME - WIFI | 0
274 | 2024-05-07 13:59:26-0700 | ACPI Wake | S3
275 | 2024-05-07 13:59:26-0700 | Wake Source | GPE # | 3

Change-Id: Ie0d6e6c8fefdd081e252ea99d6e3c559a5330b0e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82234
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-08 22:20:07 +00:00
986deb3e35 mb/google/brox/var/brox: increase PsysPmax from 21.5W to 208W
According to Brox HW design, the PsysPmax is supposed to be 208W.
This patch changes PsysPmax setting from 21.5W to 208W.

Change-Id: I43f4b00a54dc0dfe6bd690492f9ef92698c9b903
Signed-off-by: Lawrence Chang <lawrence.chang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
2024-05-08 22:19:48 +00:00
5470ae77fd util/chromeos/crosfirmware: ensure $BOARD is lowercase
If $BOARD is not all lowercase, then certain subfunctions of the
script will fail due to case-sensitive comparisons therein. To avoid
this, since all matched strings are fully lowercase, set $BOARD
to lowercase.

TEST: './crosfirmware.sh {akemi/Akemi/AKEMI}' all succeed.

Change-Id: I8ecb613a8d9384e2cccaff5183470e2e9956d0a2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-08 20:30:12 +00:00
e25c6ac11d soc/intel/xeon_sp/spr: Refine return value checks
mp_init_with_smm returns cb_err type, where 0 means success and
negative values represent error (see cb_err.h).

However, failure checks in form of "ret < 0" is not
straightforward. Use "ret != CB_SUCCESS" instead.

Change-Id: I7e57f2da0361f3109051e9a35b1cce81d559b261
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-08 14:55:24 +00:00
f5105313cf mb/asrock/z97_extreme6: Add new mainboard
That's an ATX mainboard with a LGA1150 socket and four DDR3 DIMM slots.
Porting was done using autoport and then doing a bunch of manual edits.

This board has two socketed DIP-8 SPI flash chips and a physical switch
to choose which one should the system boot from. As long as one of them
contains a bootable firmware image, it is possible to reflash the other
chip using the internal programmer by flipping the switch after booting
to OS. Even if one somehow manages to flash unbootable firmware to both
chips, they are socketed: one can carefully remove them from the socket
and reflash them externally, which is a relatively safe procedure (when
compared to in-circuit flashing, especially if the board isn't designed
to safely be flashed in-circuit). In short, the board is hard to brick.

Haswell MRC.bin cannot be used because it lacks support for the Z97 PCH
found on this mainboard. Broadwell MRC.bin only works with Haswell CPUs
so far, as raminit fails on Broadwell CPUs for an unknown reason. Maybe
it's something about RcvEn, but it's unlikely it can easily be fixed.

Working:
 - All four DIMM slots
 - Broadwell MRC.bin for raminit purposes
 - Serial port to emit spam
 - POST code display
 - S3 suspend/resume
 - All rear USB 3.0 ports
 - Internal USB 2.0 port
 - Audio output (green jack)
 - Integrated graphics (libgfxinit)
 - HDMI
 - VBT
 - Intel GbE (I218-V PHY and PCH MAC)
 - Realtek RTL8111E GbE
 - At least one SATA port
 - M2_1 slot (Gen3 x4, bifurcated from CPU)
 - Flashing internally with flashrom
 - SeaBIOS (current version) to boot Arch Linux
 - NCT6791D Super I/O software-based fan control
   tested using `sensors` and `pwmconfig`, all 6
   fan tachometers and 5 PWM outputs work fine.

Untested for now (i.e. should work, will eventually test):
 - DVI-I, DisplayPort
 - EHCI debug
 - Front USB 2.0 and 3.0 ports
 - The other audio jacks (as well as SPDIF)
 - The other PCIe and M.2 ports
 - Non-Linux OSes
 - PS/2 combo port (can only test with a keyboard)

Untestable (i.e. cannot test due to unavailable hardware):
 - Thunderbolt AIC (Add-In Card) support

Not working:
 - Broadwell CPUs, they require more magic to work (working on it).
 - Booting from ASM1062 SATA ports with SeaBIOS. Other payloads were
   not tested. It seems that the problem is with the controllers.
 - Super I/O automatic fan control: not yet implemented in coreboot.
   To control fans, use software fan control methods in the meantime.
 - Acer B247Y board driving a FHD panel of a Samsung S24E650 monitor,
   connected to the board's HDMI output says "Unsupported resolution"
   after libgfxinit configured the iGPU outputs in linear framebuffer
   mode. HDMI output works fine after Linux's i915 driver takes over.
   Not sure if it's specific to the monitor: the HDMI cable is beaten
   up, and it is hard to replace (need to relocate the logic board so
   that the ports are accessible).

Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-05-08 11:56:35 +00:00
b816b186f0 commonlib/timestamp_serialized: Define VB_AUXFW_SYNC_DONE timestamp
Define a new timestamp to identify the completion of Auxiliary Firmware
Sync. Without that, it gets accounted into a different timestamp ID in a
misleading way.

BUG=None
TEST=Build Brox BIOS image and boot to OS. Confirm the timestamp is
recorded in cbmem.

Change-Id: Icd01c68a5848e2aed7bbdcc794987bc780e78dab
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2024-05-08 11:54:54 +00:00
837060d4fc mb/samsung/lumpy: Fix smbus subsystem ID
The smbus subsystem ID was inadvertently reversed when added in commit
eb2897b113 ("mb/samsung/lumpy: override SMBus subsystem ID"), so
correct it.

TEST=build/boot Win10 on lumpy, verify touchpad driver functional.

Change-Id: I7520041ea113dff8f2abebfc71a1de6d0f9fc91f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-08 11:53:54 +00:00
4533b0ee5c mb/google/parrot: Fix smbus subsystem ID
The smbus subsystem ID was inadvertently reversed when added in commit
6974bcd28e ("mb/google/parrot: override SMBus subsystem ID"), so
correct it.

TEST=build/boot Win10 on parrot, verify touchpad driver functional.

Change-Id: I93d4812e24a6fc7419887e364974fcfae2465ea3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-08 11:53:36 +00:00
49de3e7027 mb/google/butterfly: Fix smbus subsystem ID
The smbus subsystem ID was inadvertently reversed when added in commit
a6076cfcfd ("mb/google/butterfly: override SMBus subsystem ID"), so
correct it.

TEST=build/boot Win10 on butterfly, verify touchpad driver functional.

Change-Id: If4a0eae06bbe4dcba893a42797e371bbf9f899b9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82225
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-08 11:53:27 +00:00
66f0cdbc86 mb/google/corsola: Add new board variant Squirtle
Add a new Kingler follower 'Squirtle'.

BRANCH=corsola
BUG=b:333826091
TEST=emerge-corsola coreboot

Change-Id: I393738fc470ffc907f125647a46bf81c243708d7
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-07 14:14:26 +00:00
e3003f65bc MAINTAINERS: Drop references to inexistent folders
It makes little sense to keep these around. Boards maintained on a
branch should use that branch's MAINTAINERS file instead, I'd say.

Change-Id: I670df889ffce82ee4ee4e2b91fe70f18adfcfdfa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-05-07 12:56:24 +00:00
6b2dd3e4d4 MAINTAINERS: Add self (Angel) to Prodrive Hermes board
I am the one who takes care of most coreboot things for this board.

Change-Id: I1f587822d60d2f69f34f272685cad50149faf79b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-05-07 12:56:07 +00:00
bc4a105031 MAINTAINERS: Update Prodrive boards' maintenance status
Both boards are most certainly `Supported`, and have been for a long
time. I have no idea why they were labelled as `Maintained` instead.

Change-Id: I02a5979f094b507e9f7d758daf47eeb95064cf0d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82221
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07 12:55:50 +00:00
81cdbc3e0f MAINTAINERS: Fix typo in Xeon-SP area name
`Sacalable` ---> `Scalable`

Change-Id: Iea6d3558269c41e87e2be936a82c22a2da666b47
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82219
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07 12:55:30 +00:00
fe18b4ba92 mb/adlink: Remove leftover directory
These boards are clones of LiPPERT boards, which are no longer in this
branch (they were AMD AGESA boards). So, drop the ADLINK placeholders.

Change-Id: Idfd77daf4a5b3d1e120ed22f9a48fa1bf884de9e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-05-07 12:55:21 +00:00
b9d489e01d soc/intel/meteorlake: Determine TBT controllers exist by VID/DID
The original code uses TRE0-TRE3 register to determine whether or not
the TBT controller exists. However, there is a remap in fsp could confuse
the TRPx._STA.
Ex:
    Disable TBT controller 0 on b:0 d:7 f:0
    Enable TBT controller 1 on b:0 d:7 f:1
The FSP will do the remap and after the remap:
    TBT controller 1 is on b:0 d:7 f:0
    TBT controller 0 is on b:0 d:7 f:1

This is becuase func 0 must exist per pci spec.
However, the TRE0-TRE3 will not be remapped so that the ACPI
TRPx._STA method could be confused.
In such scenario, TRP0._STA will return 0x0, TRP1._STA will return
0xf which is wrong because TBT controller 1 is now at b:0 d:7 f:0

TEST=tested on rex and _TRPx._STA returns correctly. TBT function OK

Change-Id: I54f2ea99cd1ec73dd0b71a6ba738aa927b0ae80f
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-07 12:51:25 +00:00
8c927c4dbf soc/intel/mtl: Fixed TBT PCIe devtree remapping
The TBT PCIe devicetree settings are not remapped properly when
TBT PCIe port 0 is disabled.
This code refer SHA:58bc5d937 to remap the PCIe devtree settings
properly in case of TBT PCIe port0 is disabled,

TEST=Tested on screebo and found "Remapping PCIe Root Port #2 msg"
     showed up in coreboot log

Change-Id: I7c7549ddf8ccdd67d7af7c69f51a84614cff9a03
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81841
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07 12:50:37 +00:00
8bcd8210ea dram/ddr3: Use the same naming convention as DDR4
Change-Id: Ifaff19c0117b5247d3321605ccc2e97bf8226ca8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82216
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07 10:53:31 +00:00
0f45e17f56 dram/ddr5: Use the same naming convention as DDR{2,3,4}
Change-Id: I2cc38926b56315d4a828311917ff58051b34b777
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07 10:53:18 +00:00
239347a909 spd.h: Move enum ddr4_module_type to ddr4.h
Move specific enum ddr4_module_type to <device/dram/ddr4.h>.

Change-Id: Ia538d2c73affa6560fa1533a40c02b3677588f5a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07 10:52:58 +00:00
78ba7a7865 device/dram/ddr{3,4}: Rename spd_raw_data for specific DDR
Rename different spd_raw_data[] for DDR3 and DDR4.
This is to solve the conflict when we include both "ddr3.h" and ddr4.h"
for example here: src/device/dram/spd.c.
Otherwise, it won't compile as DDR3 and DDR4 have different
spd_raw_data[] size.

Change-Id: I46597fe82790410fbb53d60e04b7fdffb7b0094a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07 10:52:44 +00:00
0f3316bc71 device/device_util: Add and use is_pci_bridge()
TEST=Build and boot on intel/archercity CRB

Change-Id: Ied4921f7dc7e144e580d05d4f2262777aa59d895
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81566
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07 10:20:11 +00:00
775c0e6de2 soc/intel/xeon_sp/spr: Print return codes for mp_init_with_smm
TEST=Build and boot on intel/archercity CRB

Change-Id: Iee2234a3055fe8a94ecbfc820e9ff9e981f8dff2
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07 09:26:58 +00:00
111bf46f7b soc/intel/xeon_sp/spr: Remove duplicated warning
When microcode is not found, intel_microcode_find() will output warning
and skip the update. Remove the duplicated warning in CPU codes.

TEST=Build and boot on intel/archercity CRB

Change-Id: I0264edc01e90186a7b77d57f9c147d3b73747437
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07 09:26:20 +00:00
13a3c3a144 soc/intel/xeon_sp/spr: Add comments for get_thread_count
Add comments to clarify the usage of logical core count instead of
physical core count.

TEST=Build and boot on intel/archercity CRB

Change-Id: I2bc94391f060cec9de91183021da03bc5c7438c0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82097
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07 09:26:05 +00:00
f063604c33 soc/intel/xeon_sp/spr: Remove unused file includes in cpu.c
TEST=Build and boot on intel/archercity CRB

Change-Id: I17b42331fa9b5f59d1fb1d66b9155c57e258357b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82191
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07 08:56:23 +00:00
305ee06933 spd.h: Move enum ddr5_module_type to ddr5.h
Move specific enum ddr5_module_type to <device/dram/ddr5.h>.

Change-Id: Ie38d1e99fa46c278e60ced2d3eef29ca823d4b1d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-05-07 08:47:55 +00:00
9580e7fba8 soc/intel/xeon_sp: Add fill_pd_distances
Update a simple algorithm to cover some basic case for proximity
domain distance handling. In the same time, the local variable
usage of fill_pds() is optimized.

TEST=Build and boot on intel/archercity CRB

ACPI SRAT, SLIT and DMAR (Remapping Hardware Static Affinity) are
generated correctly for 2S system.

Change-Id: I2b666dc2a140d1bb1fdff9bc7b835d5cf5b4bbc5
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Ziang Wang <ziang.wang@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81442
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06 17:34:07 +00:00
49e5d3dc26 mb/google/brya/var/bujia: Add VBT data file
Add data.vbt files for bujia supported by brask recovery images.
Select INTEL_GMA_HAVE_VBT for bujia which currently have a VBT file.

changes:
1. "integrated DisplayPort with HDMI/DVI compatible"
  -> "Integrated HDMI/DVI".
2. turn the AUX off.

BUG=b:327549688
TEST=build/boot various brya variants

Change-Id: Id56461708250eaedd288ddbf788d686153df0b96
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81553
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06 11:28:25 +00:00
3e77f77bee mb/google/brox:Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
Brox uses PDC<->PMC direct connection for USBC mux configuration. Select
SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION to enable it. This
patch also adds additional dependency on ENABLE_TCSS_USB_DETECTION to be
selected only when PDC<->PMC direct connection and CHROMEOS is not used.

BUG=b:332383540
TEST=USB3 plugged during G3, is detected after system boots from G3.

Cq-Depend: chromium:5484387
Cq-Depend: chrome-internal:7106592
Change-Id: I0f62943f87d8fb6eb494c0aca3ef08c33cd05ffd
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-05-06 11:23:05 +00:00
653ba223df common/block/tcss: Add config for PDC<->PMC mux configuration
Introduce a new Kconfig to enable PD controller to PMC mux
configuration. Selecting this config enables direct communication from
PDC to PMC. TCSS_HAS_USBC_OPS enables USB-C operations via the EC. When
SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION is selected, disable
TCSS_HAS_USBC_OPS to avoid sending PMC commands from AP/EC.

BUG=b:332383540
TEST=USB3 plugged during G3, is detected after system boots from G3.

Cq-Depend: chromium:5484387
Cq-Depend: chrome-internal:7106592
Change-Id: Ieeb503393418cdad43384be39ac49c93ba91e4db
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82077
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06 11:22:42 +00:00
4fa8354216 mb/google/brya: Correct _PLD values
For Mithrax and Felwinter, port C1 is on the left side and port C2 is on
the right side. Correct the values accordingly.

The board schematics was mirrored, so had to obtain an actual machine and physically check the correct ports.

BUG=b:321051330
TEST=emerge-${BOARD} coreboot then check ACPI table on DUT

Change-Id: I977c3b4081987592a1d46529eb848a07a6c4cb47
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81363
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Emilie Roberts <hadrosaur@google.com>
2024-05-06 11:22:02 +00:00
9207621d23 mb/google/brya: Fix mux_conn index used by ec/google/chromeec
Within ec_acpi.c, USB-C ports are iterated to be matched with
corresponding mux. The iteration happens from 0 to the number of USB-C
ports. Given iteration index i, the port with PLD group_token of (i+1)
is matched with mux_conn[i].

Mithrax and Felwinter devicetree matches conn1 to mux_conn[1] and conn2
to mux_conn[0]. However, conn1 is for usbX_port2 which has group_token
of 1 and conn2 is for usbX_port3 which has group_token of 2. Thus,
follow the convention to add conn1 to mux_conn[0] and conn2 to
mux_conn[1].

Otherwise, the kernel subsystem linking between Type C connector and USB
mux will be swapped.

BUG=b:329657774 b:121287022 b:321051330 b:204230406
TEST=emerge-${BOARD} coreboot then check ACPI table on DUT.
TEST=Manually check that usb-role-switches are mapped to the correct
    port.
  Attach USB 3 A to C cable from development machine to left port of
    DUT.
  Attach nothing to right-hand port.
  usbpd lines are workaround for devices without firmware patch to
    connect superspeed lines.
  ectool usbpd 0 none
  ectool usbpd 0 usb
  ectool usbpd 1 none
  ectool usbpd 1 usb
  echo host > /sys/class/typec/port0/usb-role-switch/role (should
    succeed)
  echo host > /sys/class/typec/port1/usb-role-switch/role (should fail
    as no cable attached)

Change-Id: I349682a6fe3fe4848e4e86d9c446530a31b35875
Signed-off-by: Won Chung <wonchung@google.com>, Emilie Roberts <hadrosaur@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81354
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Emilie Roberts <hadrosaur@google.com>
2024-05-06 11:21:45 +00:00
ce04bf8c7f drivers/intel/pmc_mux/conn: Copy ACPI _PLD property from USB port to mux
Copy ACPI _PLD values from USB ports to corresponding USB muxes so that
the kernel can create symlinks between Type C connectors and
corresponding USB muxes. This symlink will be used to let userspace be
able to modify the USB role without knowing ACPI topology for the
device.

BUG=b:121287022 b:329657774
TEST=emerge-${BOARD} coreboot then check ACPI table on DUT

Change-Id: If27042cc995ef188f8a3e31444e994318ff98803
Signed-off-by: Won Chung <wonchung@google.com>
Tested-by: Emilie Roberts <hadrosaur@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81089
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Emilie Roberts <hadrosaur@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06 11:21:18 +00:00
7b2b57b0b8 soc/intel/xeon_sp/acpi: Refactor Xeon-SP ASL file location
soc/intel/xeon_sp/acpi/*.asl are actually used only by SKX and CPX
platforms and not forward compatible to later SoC generations.
Move them to soc/intel/xeon_sp/acpi/gen1/ for clean maintenance.

TEST=Build and boot on intel/archercity CRB

Change-Id: Ib060b123ab0fd761f00d9a0573e9b73d600ea9ef
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82033
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06 10:48:46 +00:00
71814b0e5b acpi: Remove acpigen_write_OSC_pci_domain
For PCI domains, static _OSC will be used for better readability
and maintenance.

This reverts commit f4a12e1d39.

TEST=Build and boot on intel/archercity CRB

Change-Id: I2e2b2f0533a3940caf2806ec1ed048c30e4ba801
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82032
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06 10:48:06 +00:00
63f975b68f util/util_readme: Update post_util.md for MyST Parser
This file is appended to Documentation/util.md by the util_readme.sh
script, and contains toctree entries for utilities with more in-depth
documentation than the description automatically pulled from the
description.md files throughout the util directory. As of commit
35599f9a66 (Docs: Replace Recommonmark with MyST Parser), the syntax
for creating a toctree has changed, so update this post_util.md
accordingly.

Change-Id: Ia7ae3c513781e53512763578fd97db7e2f75e65c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-05-06 10:41:50 +00:00
6cd9f1a24c mb/system76: Exclude ramtop from CMOS checksum
Use the default position for ramtop and exclude it from the checksum.
Fixes invalid checksum after caching ramtop causing things like
disabling CSME to not work.

Fixes: 10d2af04e7 ("mb/system76: Add space for ramtop in CMOS layout")
Change-Id: If30df1e6f2735cf767856e42dfede3d17fe494eb
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81641
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06 10:41:16 +00:00
4050448944 mb/google/nissa/var/sundance: Use default eMMC DLL setting
Configure eMMC DLL tuning values for Sundance board Samsung sku.

BUG=b:337741162
TEST=Use the value to boot on Sundance successfully.

Change-Id: I5f1e03c06c9f8567e757fed999730dff2551f1e0
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82173
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06 10:40:34 +00:00
cdc061d81d mb/google/sarien: Make use of chipset dt reference names
Replace the PCI numbers with the reference names from the chipset
devicetree. Also, remove their comments since they are superfluous now.

Change-Id: I49f5fda5628b2ebc76cd8db20c8f7fe85c676c7a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-05-06 10:40:05 +00:00
cc452db5b0 mb/google/sarien: Remove dt entries equal to chipset dt
Clean up the devicetree by removing entries which are equal to the
chipset devicetree. The P2SB device is enabled but it's hidden by the
FSP. So just remove that as well since the chipset devicetree configures
it correctly.

Change-Id: I38f46949d36359826317252e8d3434ad1b24382d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82156
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06 10:39:52 +00:00
052b92dd49 mb/google/drallion: Make use of chipset dt reference names
Replace the PCI numbers with the reference names from the chipset
devicetree. Also, remove their comments since they are superfluous now.

Change-Id: Ib873854954e44b3ea370c2574da5db9792a446e9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82155
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06 10:39:33 +00:00
aa37528107 mb/google/drallion: Remove dt entries equal to chipset dt
Clean up the devicetree by removing entries which are equal to the
chipset devicetree. The P2SB device is enabled but it's hidden by the
FSP. So just remove that as well since the chipset devicetree configures
it correctly.

Change-Id: I6186d295427bcd4a3b696f4df59d94a148ced011
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-05-06 10:39:15 +00:00
3cc3a501cf mb/google/brya/var/pujjoga: Add GPIO table
Fill GPIO table for pujjoga.

BUG=b:336469694
TEST=emerge-nissa coreboot

Change-Id: I3f633cf99f56d5f855015de805e16c1205c9bc99
Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82044
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-06 10:36:56 +00:00
a053bca6ad mb/google/brya/var/xol: Override TDP PL1 value
Update TDP PL1 value for the DTT optimization. The new value 18W is from
internal thermal/performance team.
- tdp_pl1_override: 15 -> 18 (W)

BUG=b:336684032
BRANCH=brya
TEST=built and verified MSR PL1 value.
     Intel doc #614179 introduces how to check current PL values.

[Original MSR PL1/PL2/PL4 register values for xol]
cd /sys/class/powercap/intel-rapl/intel-rapl\:0/
grep . *power_limit*
  constraint_0_power_limit_uw:15000000 <= MSR PL1 (15W)
  constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W)
  constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W)

After this patch:
  constraint_0_power_limit_uw:18000000
  constraint_1_power_limit_uw:55000000
  constraint_2_power_limit_uw:114000000

Change-Id: I28c4f099e0169e8389f63083c03023dd8338589f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82151
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06 10:36:31 +00:00
7f0a7f65e6 mb/google/brya/var/xol: Tune I2C5 timing parameters
Update I2C5 timing parameter values to meet I2C bus spec.
- fall_time_ns: 400 -> 200

BUG=None
BRANCH=brya
TEST=built and measure I2C5 timing parameters

Before:
tLOW : 1.88 us (spec >= 1.30)
tHIGH: 0.57 us (spec >= 0.60)
fSCL : 399.80 KHz

After:
tLOW : 1.60 us (spec >= 1.30)
tHIGH: 0.97 us (spec >= 0.60)
fSCL : 392.1 KHz

Change-Id: I386b2765410fd10b8cd711f54478fb52428de5a3
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-06 10:36:18 +00:00
d145a840bf mb/google/nissa: Create a riven variant
Create the riven variant of nissa reference board by copying the
template files to a new directory named for the variant.

The riven variant is a twinlake platform.

BUG=b:337169542
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_RIVEN

Change-Id: I1be2346d87c891cc0e5fbda094e1f6e0dd60df1b
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82132
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06 10:36:04 +00:00
5c06922621 mb/google/corsola: Sort Kconfig board selection in alphabet order
Change-Id: Iefe61d3ad51d355806716483248df5b1083b69bc
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82149
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06 10:35:09 +00:00
674ee501e8 drivers/intel/mipi_camera: Add CSI2 Data Stream Interface GUID
Required in SSDB for Windows drivers. Tested on google/brya (kano)
and verified Intel Webcam shows up to Windows as a camera source

Change-Id: Id6089f6bd841333882e28de9307fe5e48e368d02
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82068
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06 10:34:37 +00:00
0b26bcd51a mb/google/nissa/var/pujjoga: Generate SPD IDs
Add pujjoga supported memory parts in mem_parts_used.txt, generate
SPD id for this part.

1. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT
2. Hynix H9JCNNNBK3MLYR-N6E, H58G56BK7BX068
3. Micron  MT62F1G32D2DS-026 WT:B

BUG=b:337990338
TEST=Use part_id_gen to generate related settings

Change-Id: I39d44fd278474a7375ad1d2d904d14b9463ba86d
Signed-off-by: roger2.wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82135
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-06 10:33:53 +00:00
bc00a2b2f6 mb/google/nissa/variant/pujjoga: Update devicetree settings
Based on schematic of 500E_GEN4S_ADL_N_MB_0418, generate overridetree.cb
settings for Pujjoga.

BUG=b:337611700
TEST=FW_NAME= pujjoga emerge-nissa coreboot chromeos-bootimage

Change-Id: I279f94044a22f25100a44b1abe2ef5fb6d0dd835
Signed-off-by: roger2.wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82109
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-06 10:33:36 +00:00
aaf8bdc675 soc/amd/phoenix/include/platform_descriptor: remove TODO
There's nothing in this header file that needs to be updated for the
Phoenix SoC, so remove the 'Update for Phoenix' TODO.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9d7b5e8d8d6c8c22c2fae8e89d073481d21d8bdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82150
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06 10:32:24 +00:00
e4b2f3a6a2 mb/lenovo/*: Set VR12 PSI to fix crash
When in Package C3 or deeper the PSI settings are used to switch the
CPU VR into a low power state. It was found that the voltage regulator
on the Sandy-Bridge series has non-default PSI settings, compared to
Lenovo's Ivy-Bridge series. Apply the same PSI value for PSI2 and PSI3
as the vendor BIOS does to fix a hang when the package is idle.

Since neither the vendor BIOS is open-source, nor datasheet exists for
the used VR it's unclear why those PSI values must be used and how
they influence the regulator.

The X220 already has the correct PSI values configured and is now stable
for more than 24h in Package C7 state.

TEST: Not tested on the affected boards, only checked vendor firmware.

Change-Id: Idf8c3719f19f7bcdab30c543215c8abd2669cfd2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-06 10:25:11 +00:00
2de0e87622 block/fast_spi: Use read32p/write32p for SPI RW
The current fast_spi code uses memcpy for rw. The SPI flash read/write
has 4 byte limit, due to which the current 64 bit memcpy doesn't work.
Hence update rw ops to use read32p/write32p.

BUG=b:242829490
TEST=Verified MRC cache working on MTL 64-bit, future 64 bit platforms
and RPL(brox/skolas) 32-bit platforms.

Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-06 09:47:56 +00:00
7da138dd10 mb/google/rex/var/deku: Update psys_pmax_watt value to 180W
Adjust setting is from power team.
Change from 172W to 180W

BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST= FSP debug emerge-ovis coreboot intel-mtlfsp
      check overrides setting

Change-Id: Icc8b12adc9fb9f680b05131c8d41212865223ca9
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-06 05:41:32 +00:00
031c1e0f9c mb/google/rex/var/deku: Update FVM itrip for VR domain
Adjust setting is from power team.
Itrip(GT) FVM 54
Itrip(SA) FVM 27

BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST= FSP debug emerge-ovis coreboot intel-mtlfsp
      check overrides setting

Change-Id: I6d6cf7cecaac650a7b1784833b4afb8dffb3db2c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82176
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06 05:32:50 +00:00
2913399768 payloads/U-Boot: Upgrade from U-Boot v2023.07 to v2024.4
U-Boot v2024.04 was released on Tue 02 April 2024

Change-Id: I21fe81e9e01f2f21f9a4581fa8fdbf661fe270bd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82007
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-04 21:03:55 +00:00
bb937c8775 libpayload: Save EAX and EBX only for multiboot payloads
When CONFIG_LP_MULTIBOOT is enabled, save the values of EAX and EBX
passed from the bootloader. This information can be useful for
multiboot payloads feature alone.

Change-Id: I98c2cd00206ee48eb0fc67edd9533032bcf3e5eb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82040
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-05-04 16:51:44 +00:00
e3eeba6aae docker/coreboot-sdk: Replace 'pkg-config' with 'pkgconf'
Replace transitional 'pkg-config' package with 'pkgconf'.

Change-Id: I9ee895cb2ca3186c4aefbdab1fd71778bf981009
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82167
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-04 14:54:22 +00:00
5ee749015d soc/intel/xeon_sp/spr: Drop unused symbol
SOC_INTEL_PCIE_64BIT_ALLOC is not used.

Change-Id: I1ef52104ef1d883330b800215cb4d0475092d8fe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-03 21:40:40 +00:00
6daeda89cd drivers/wifi/generic: Fix a typo on symbol
WIFI_MTCL_CBFS_FILEPATH is now used.

Change-Id: Icdd0332ae9c56a54596a775c0a9aa7b9f8d6738c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-03 21:40:24 +00:00
7f7a6e8f7a mb/google/brya/var/xol: Update board type to BOARD_TYPE_ULT_ULX
Correct .UserBd field to BOARD_TYPE_ULT_ULX from BOARD_TYPE_MOBILE. This
is from Intel's guidance for MRC to map the memory speed to proper POR
number.

BUG=b:332980211
BRANCH=brya
TEST=Built and compare the results of command 'dmidecode -t 17'
[Before]
  (Same values in all of memory device handle)
  Speed: 6400 MT/s
  Configured Memory Speed: 6400 MT/s
[After]
  (Same values in all of memory device handle)
  Speed: 5200 MT/s
  Configured Memory Speed: 5200 MT/s

Change-Id: Id16bcbc2d0cb4c2cf3008cf2ef1027ed98e93afb
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-03 17:40:22 +00:00
3c7bbde4fd drivers/intel/fsp2_0: Release bmp_logo during OS_PAYLOAD_LOAD stage
bmp_load_logo() loads the custom logo.bmp file into CBMEM. This cbmem
buffer is released after FSP-S init is complete. In certain platforms,
the logo file is displayed during PCI enumeration.  This means the logo
buffer is used after it is released. Fix this issue by releasing the
logo buffer when the coreboot has finished loading payload. During S3
scenario CBMEM is locked, bmp logo is not loaded and hence the release
is a no-op.

BUG=b:337144954
TEST=Build Skyrim BIOS Image and boot to OS. Ensure that the chromeOS
boot logo is seen without any corruption.

Change-Id: Id27cf02de04055075e7c1cb0ae531dee8524f828
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82121
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-03 17:03:37 +00:00
0c66e9ddf0 soc/intel/xeon_sp: Remove unused xeonsp_acpi_create_madt_lapics
TEST=Build and boot on intel/archercity CRB

Change-Id: I06e5ff635c37253b1c8f151b62f696ff7e5e22ef
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82110
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-03 11:15:56 +00:00
e282422c68 mb/google/corsola: Initialize USB port 0
The default MT8186 platform is to initialize USB3 port 1.
Use option bit 27 in fw_config to enable initialization of USB2 port 0
to support devices mounted on it.

BUG=b:335124437
TEST=boot to OS from USB-A
     boot to OS from SD Card
BRANCH=corsola

Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82089
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-03 08:35:11 +00:00
b566ce4aea mb/raptor-cs/talos-2: add basic mainboard structure
Change-Id: I0c4f74c7b27c8bb5599d68305adf369ddc6fcc70
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-02 23:15:01 +00:00
5fe9aa6ba9 soc/ibm/power9/*: add file structure for SOC
Boot device is stubbed to be able to build boards without errors.

Change-Id: Ie74b1e34f9aebe151d0fdb0e95c003510fd864c3
Signed-off-by: Igor Bagnucki <bagnucki02@gmail.com>
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-02 23:14:22 +00:00
1043080900 soc/intel/xeon_sp: Use fixed BDF for IBL
Integrated Boot Logic (IBL) codes doesn't support bootloader
controlled Primary-to-Sideband Bridge (P2SB) hidden and unhidden.
Hence, dynamically read IBL HPET/IOAPIC Bus:Device.Function (BDF)
by bootloader is not supported, because when P2SB is hidden the
register access is denied.

TEST=Build and boot on intel/archercity CRB
TEST=Build on intel/avenuecity CRB
TEST=Build on intel/beechnutcity CRB

Change-Id: I3975cb00e215c4984c63bb8510e8aef7d4cc85a4
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81321
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02 17:44:05 +00:00
45a670d223 soc/intel/xeon_sp: Move VPD based settings to mainboard codes
Configuration variable implementation (VPD, et al) is regarded to
be mainboard specific and should not be bounded to SoC codes.

This patch moves the VPD based settings (FSP log level, et al)
from SoC codes to mainboard codes.

TEST=Build and boot on intel/archercity CRB with no significant log
differences

Change-Id: Iefea72eec6e52f8d1ae2d10e1edbabdebf4dff91
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82090
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-02 17:43:51 +00:00
a0aff6e159 soc/intel/xeon_sp: Add get_cxl_mode
Configuration variable implementation (VPD, et al) is regarded to
be mainboard specific and should not be bounded to SoC codes.

Add get_cxl_mode so that SoC codes do not need to get this
configuration from VPD any more.

TEST=Build and boot on intel/archercity CRB with no significant log
differences

Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-02 17:43:42 +00:00
b25fa1cf9e soc/intel/mtlrvp: use different names for mtlrvp variants
This patch sets different names for different mtlrvp
variants so they can be matched properly at runtime against
unique frids (i.e. firmware read-only identifiers).

BRANCH=firmware-rex-15709.B
TEST=Verified boot functionality on intel/mtlrvp

Change-Id: I5292a0ffcd7524c55cd7aef37c2f59432b2af06a
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-02 17:22:14 +00:00
37f0735d0c soc/intel/xeon_sp: Clean up device enablement configuration
Clean up by using is_devfn_enabled().

Change-Id: I9ea3d8b1b18e84a75a81a7e926d2c638766bb493
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82120
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02 16:07:56 +00:00
fbf260a0d5 soc/intel/cannonlake: Clean up device enablement configuration
Clean up by using is_devfn_enabled().

Change-Id: I9a4984a096e72025e161bf117b70a7c59f2bb094
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82118
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02 16:07:49 +00:00
5ed9fe9497 soc/intel/xeon_sp: Add device to proximity domain map utils
In NUMA architecture, all devices (cpu, memory and PCI device)
belong to specific proximity domain. Add utils to map device
instance to their proximity domain.

Proximity domain ID is the index assigned at the creation of
proximity domains. There is no hard relationship between proximity
domain ID and the device identities (e.g. socket ID). Hence we
need the map utils to explicitly link them.

For now the Sub-NUMA config isn't taken into account.

TEST=Build and boot on intel/archercity CRB

Change-Id: Icd14a98823491ccfc38473e44a26dddfbbcaa7c0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Ziang Wang <ziang.wang@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81440
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02 14:31:51 +00:00
1c39bccf72 soc/intel/xeon_sp: Make NUMA support by default
TEST=Build and boot on intel/archercity CRB

Change-Id: I84f07c16e24e441a885144df8c805f1310acae29
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Ziang Wang <ziang.wang@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81439
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02 14:31:21 +00:00
98077dc359 Doc/tutorial/part2.md: Format URL as link
One URL in this document did not show up as a link. Fix it.

Change-Id: I22bf2014e71e6a127a7981cc90a028e48c25da49
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82160
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02 13:14:38 +00:00
c64bfdf23c soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE
Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total
SPD size of 512 bytes. Set this as the default and remove the setting
from mainboard Kconfigs.

Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82115
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-30 08:28:29 +00:00
916124cdba drivers/intel/fsp2_0: Default to 64-bits for FSP 2.4
Sets`PLATFORM_USES_FSP2_X86_32' to `n' by default if FSP 2.4 is
enabled as 64-bits FSP should be norm moving forward.

BUG=b:329034258
TEST=verified on Lunar Lake RVP board (lnlrvp)

Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec98
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80323
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-04-30 04:47:38 +00:00
7e1c8e2159 drivers/intel/fsp2_0: Add dedicated caller function for ap procedure calls
Add FSP 2 Multi Processor Platform Initialization module a function
indirection to ensure that efi_ap_procedure functions are called with
the appropriate C calling convention.

BUG=b:329034258
TEST=Verified both x86_32 and x86_64 builds on Meteor Lake board (Rex)

Change-Id: I64e65b2941207375d5e27c84aa26061e7e72a7f6
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81663
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-30 04:47:17 +00:00
f09fcd6fef drivers/intel/fsp2_0: Remove x64-specific assertion from fsp_header
Same fsp_header struture is being used for x64 and x32 modes
and hence dropping the x64 assertion.

BUG=b:329034258
TEST=Verified on Meteor Lake board (Rex)

Change-Id: I6013af342670e6377a3fe7641d7d9b52c9b6f57c
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81662
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-30 04:46:59 +00:00
a63ce30c93 drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned
- Stack alignment:

  1. FSP functions must be called with the stack 16-bytes aligned
     in x86_64 mode.This is already setup properly with the default
     value of the `mpreferred-stack-boundary' compiler option (4).

  2. The FSP heap buffer supplied by coreboot through the `StackBase'
     UPD must be 16-bytes aligned. This alignment is consistent for
     both x86_64 and x86_32 modes to simplify the implementation.

BUG=b:329034258
TEST=Verified on Meteor Lake board (Rex)

Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81661
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2024-04-30 04:46:46 +00:00
9493c2ece2 mb/google/brya/var/xol: Add EC_IN_RW_OD config into early_gpio_table
Add GPP_F18 configuration in early_gpio_table.
Without this, DUT cannot get the proper state of this signal on early
phase. It allowed DUT to attempt to enter into dev mode when EC is in RW
currently, it causes the failure of autotest/firmware_DevMode.

BUG=b:337365524
TEST=built and run autotest firmware_DevMode

Change-Id: I2179bb10b431547bc35f332c74915a63495b779d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82099
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
2024-04-30 03:39:04 +00:00
c7db3d0f08 mb/google/brox: Add 20K pulldown to GPP_D14
GPP_D14 is floating when ISH is not being used and wasting power. Add
pulldown to prevent this from happening.

BUG=b:336654954
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
     make sure OS boots up
     HW team validated that power usage is 20 mW lower

Change-Id: I4e19e98fa31022ece66a47402a2a4461b430ef70
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-04-30 03:12:04 +00:00
1fa0fcbd7b soc/intel/cmn/graphics: Make DDI-A 4 lanes configurable
As described in Intel document 336464 (8th gen S series datasheet volume
1), the CPU's 4 eDP lanes can be bifurcated, so that DDI-A (eDP) ends up
with 2 lanes, and DDI-E (DP, typically used for VGA) has the remaining 2
lanes. This lets mainboards provide a VGA output without sacrificing one
of the main 4-lane DDIs. Newer platforms seem to be lacking this.

However, the way this is structured in coreboot does not allow boards to
choose whether bifurcation should be enabled. Most boards in the tree do
not use DDI-E (it doesn't exist on mobile platforms), but there are some
boards (e.g. hp/280_g2) that use DDI-E and a DP-to-VGA converter chip to
provide a VGA output.

Replace `SOC_INTEL_CONFIGURE_DDI_A_4_LANES` with two new Kconfig options
to allow boards to decide. Use `SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION` to
specify whether a platform supports DDI-A bifurcation at all (do nothing
otherwise, maintaining the original code's behaviour). If bifurcation is
supported, the `SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION` is used to clear
or set the `DDI_A_4_LANES` bit in the `DDI_BUF_CTL_A` register.

Change-Id: I516538db77509209d371f3f49c920476e06b052f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82113
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-29 21:59:40 +00:00
0b90b0fb05 mb/hp/280_g2: Fix comment in gma-mainboard.ads
The DVI connector on this board is DVI-D (digital only), not DVI-I.

Change-Id: I74c1257efb67cfdff2ae04a42c163dd320c850a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82112
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-29 21:25:35 +00:00
5df42abbff mb/google/brox: Fix the pad reset config for Touchpad interrupt
Update the pad reset config for Touchpad Interrupt from PLTRST to DEEP
so that it can still act as a wake source during S3 suspend.

BUG=b:336398012
TEST=Build Brox BIOS image and boot to OS. Suspend to S3 and wakeup
using Trackpad.
246 | 2024-04-25 16:55:18-0700 | ACPI Enter | S3
247 | 2024-04-25 16:55:34-0700 | ACPI Wake | S3
248 | 2024-04-25 16:55:34-0700 | Wake Source | GPE # | 67
249 | 2024-04-25 17:00:38-0700 | ACPI Enter | S3
250 | 2024-04-25 17:00:47-0700 | ACPI Wake | S3
251 | 2024-04-25 17:00:47-0700 | Wake Source | GPE # | 67
Also suspend to S0ix and wakeup using Trackpad.

Change-Id: If1a275e42c6c7ad743eedc9cd3320776008bfd62
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2024-04-29 20:35:11 +00:00
7a6bb883c4 include/device/pci_ids.h, soc/intel/mtl: add new MTL-P iGPU DID
Found in a Clevo V560TU with Intel Core Ultra 155H

Change-Id: I0f10808fd0e2d9c122743615fbce656c6d2447cc
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82071
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-29 20:34:48 +00:00
78439118c8 soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSP
In a server platform many silicon specific register lock operations
are by default in FSP space. CHIPSET_LOCKDOWN_FSP provides an option
to make sure the codes could be used out-of-box to build products.

Change-Id: I8efcc1f27446be8e35f51e2568c4af6f8165486b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82081
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-29 15:40:07 +00:00
b84d55b582 MAINTAINERS: Add Granite Rapids FSP to Xeon-SP
Change-Id: I5170a69d798d0e8198b89f6932a80e6051228ac2
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82082
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-29 15:02:43 +00:00
52b3b8bc0f mb/google/brya/xol: Add Fn key scancode
The Fn key on Xol emits a scancode of 94 (0x5e).

BUG=b:327656989
TEST=Flash xol, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.

Change-Id: I34ed93d9666504bfd4d439e166911e49f58e5ff5
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82069
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-29 15:02:19 +00:00
05ee5c21b4 acpi: Fix return value in acpi_device_write_dsd_gpio()
Fix ++ as suffix and * precedence. After modification, the gpio index
can be obtained correctly.
The error was introduced in the commit making it public:
commit 01344bce

BUG=None
TEST= Can get the correct index test on nissa.

Change-Id: I7a3eb89633aaebebc8bd98ac6126c578fda23839
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82088
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-28 18:27:40 +00:00
fce08d7883 util/docker/coreboot-sdk: Remove libcurl4 from the package list
When installing the packages, apt-get returns an error about holding
broken packages. It occurs the diffutils depends on libcurl4t64
which breaks the libcurl4.

As a solution, remove the libcurl4 from the list, and let the package
manager resolve the dependencies.

TEST=Build coreboot-sdk

Change-Id: Iabc4f74619d4462317d8adb4068e50135d89d80e
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-04-26 23:00:19 +00:00
c96201acb1 mb/framework: Push initial port of azalea (Framework 13 AMD 7040)
This is a minimal framework that allows the build to compile.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ief4b5c75471a2ef5bedaaee9b4737510c2826b6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-04-26 22:01:31 +00:00
acfdf0d43c soc/amd/genoa_poc/chip.h: remove empty newline before '}'
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7f18f2d754f24bfcc9cbf95a98fa6fe40aaf3b02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-04-26 20:14:10 +00:00
3742308875 drivers/pc80/tpm: Disable device if TPM not present
If the TPM is not detected in the system it may	mean it	is inactive
due to enabled ME with active PTT. In such case, the chipset will route
the TPM	traffic to PTT CRB TPM on Intel systems.

If TPM is not probed, disable the PC80 TPM device driver, so that
coreboot will not generate improper SSDT ACPI table.

Change-Id: I05972ad74a36abaafa2f17a16f09710550a3a3f3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
2024-04-26 11:55:38 +00:00
fb2c09d516 drivers/crb: Disable device if CRB TPM not present
If CRB TPM is not detected in the system it may mean it is inactive
due to disabled or neutered ME. In such case, the chipset will route
the TPM traffic to LPC/SPI on Intel systems.

If CRB TPM is not probed, disable the CRB TPM device driver, so that
coreboot will not generate improper SMBIOS/SSDT ACPI tables.

Change-Id: Ie0928536d9042b1f680d585e1ca9ad2cadf0c8ef
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
2024-04-26 11:54:45 +00:00
7c587f2d59 mb/google/rex: remove duplicate config for karis
Remove duplicate config entry CHROMEOS_WIFI_SAR as it is
used at the baseboard.

BUG=None
TEST=emerge-rex coreboot

Change-Id: Iabf0e490103c2097f3f033036839b77b5a0bb1b3
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81226
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-26 11:53:41 +00:00
8b9063c6b8 arch/arm/armv7/exception.c: fix warnings of macros and functions
Use better alignment attribute macro and add missing identifier names
for function definition arguments.

Change-Id: I1c5c33fc9210f068ff88c8d981f1a1c739890c9c
Signed-off-by: Integral <integral@member.fsf.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82050
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-26 11:52:36 +00:00
90e835db2d vc/google/chromeos: Move RAMOOPS region creation to BS_DEV_INIT_CHIPS
RAMOOPS memory region was being overwritten by coreboot bmp_load_logo()
function. The CBMEM_ID_FSP_LOGO region created during bmp_load_logo()
was overlapping with RAMOOPS space created earlier. This resulted in
memory corruption of RAMOOPS buffer.

To prevent this, the RAMOOPS region allocation is moved to
BS_DEV_INIT_CHIPS phase from earlier BS_WRITE_TABLES phase of boot.

BUG=b:332910298
TEST=build and boot coreboot image on google/rex HW. Check RAMOOPS
CBMEM region creation using cbmem -l command

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ibae06362cd80eacb16f6cf0eed8c9aa1fbfb2535
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82042
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-04-25 20:56:25 +00:00
559ad55a94 util/ifdtool: Add support for checking GPR0 status
This patch adds support for the new command-line option `-c` to
the ifdtool, which is able to check GPR0 (Global Protected Range)
status.

This patch also add helper function get_enabled_gprd() to get enabled
GPR0 settings. It used in enable_gpr0() and is_gpr0_protected().

Developers can use ifdtool with '-c' option to check whether GPR0 is
set to enabled or disabled in the binary file.

BUG=none
TEST=(1) > ifdtool -p mtl -E image-unlocked.bin -O image-lock.bin
         ...
         Value at GPRD offset (64) is 0x83220004
         --------- GPR0 Protected Range --------------
         Start address = 0x00004000
         End address = 0x00322fff
         ...
         GPR0 protection is now enabled

     (2) > ifdtool -p mtl -c image-unlocked.bin
         GPR0 status: Disabled

         Value at GPRD offset (64) is 0x00000000
         --------- GPR0 Protected Range --------------
         Start address = 0x00000000
         End address = 0x00000fff

     (3) > ifdtool -p mtl -c image-lock.bin
         GPR0 status: Enabled

         Value at GPRD offset (64) is 0x83220004
         --------- GPR0 Protected Range --------------
         Start address = 0x00004000
         End address = 0x00322fff

Change-Id: I6b3af973be784200b965a68e5f6b7737cba03ed7
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2024-04-25 15:37:37 +00:00
8d37942483 mb/google/brox/var/lotso: Add fw_config field for storage
Add STORAGE_UNKNOWN, STORAGE_UFS, STORAGE_NVME for storage fw_config
field to prevent depthcharge build break.

BUG=b:333494257
TEST=emerge-brox coreboot depthcharge sys-boot/chromeos-bootimage

Change-Id: Idb62e3f37e1480979ae529692455beb533434520
Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82056
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-25 14:53:24 +00:00
348d3b6327 mb/google/nissa/var/glassway: Enable Wi-Fi sar table for Intel module
1.Enable CHROMEOS_WIFI_SAR flag to load a SAR table for Intel module.

2.Describe the FW_CONFIG probe for the settings on glassway.
- WIFI_SAR_0 for Intel Wi-Fi module AX211

BUG=336051631
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I9e43081c93ef17291c5d55cf262a0f4d1497447b
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81781
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-25 14:53:08 +00:00
506c4edab5 mb/google/brya/var/nova: Add initial configurations
Upload initial configuration for nova based on proto schematics.

Memory:
SAMSUNG 2G*4 K4U6E3S4AB-MGCL
HYNIX 2G*4 H9HCNNNBKMMLXR-NEE

BUG=b:328711879
TEST=FW_NAME=nova emerge-constitution coreboot chromeos-bootimage

Change-Id: Ic9ff3ed2fb3a7f0f100385d0a0444d38fcff5c51
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2024-04-25 14:52:22 +00:00
25465f91f3 mb/google/nissa/var/yaviks: Add stop pin for G2 touchscreen
Add stop pin control for G2 touchscreen

BUG=b:335803573
TEST=build and verified Touchscreen work normally

Change-Id: I7e0bbc7722cdda6bcca0485009fcf8510b1f55e2
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81971
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-25 14:51:20 +00:00
3979dd6df0 drivers/crb: Check for PTT before attempting to initialize CRB TPM
We can assume that platforms, which select HAVE_INTEL_PTT, will not
have any other CRB TPM than PTT. Check whether PTT is available before
forcefully initializing the TPM and selecting the CRB interface in the
TPM configuration registers.

Change-Id: If0ec6217b0e321b7d7a9410b70defde3c3195fc3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80453
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-04-25 10:12:39 +00:00
11afdb3afc mb/google/corsola/var/wugtrio: Add STA_ER88577 MIPI panel
Add STA_ER88577 MIPI panel for Wugtrio.
Datasheet: 2081101BH8028073-50E_Pre Spec_240424.pdf

BUG=b:331870701
TEST=emerge-staryu coreboot chromeos-bootimage
BRANCH=corsola

Change-Id: I279d431d80ca0770540d88e213d4aeafe77038ce
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82055
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-25 03:52:14 +00:00
6fb4381332 drivers/mipi: Add support for STA_ER88576 panel
Add STA panel STA_ER88577 serializable data to CBFS.
Datasheet: 2081101BH8028073-50E_Pre Spec_240424.pdf
About the init code, we communicated with the vendor through the
datasheet to confirm the writing method of each register value.

BUG=b:331870701
TEST=build and check the CBFS includes the panel
BRANCH=None

Change-Id: I210b23b67fbc102c9926171f1c78f6824820e4b7
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82054
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-25 03:52:05 +00:00
63d8fde896 soc/amd/common/amd_pci_util.h: assign 0 to PIN_A in pcie_swizzle_pin
Explicitly assign a value of 0 to the first value of the
pcie_swizzle_pin enum. This won't change the behavior, but clarifies
that the actual values of the enum elements matter.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I21850e21f859f2079f804d4344a1a11856b27d90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-04-24 21:25:57 +00:00
2ec63b54d8 soc/amd/common/amd_pci_util.h: rename bridge irq in pci_routing_info
Rename the 'irq' element of the pci_routing_info struct to 'bridge_irq'
to better describe what it's doing. This struct element contains the
number of the northbridge IOAPIC IRQ input the bridge IRQ is connected
to signal power management or error reporting IRQs. Right now, coreboot
doesn't put this information into the ACPI bytecode.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6410be673d15d6f9b5eb4c80b51fb705fec5b155
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-04-24 21:25:49 +00:00
6ad7513e03 arch/arm64: Extend cache helper functions
This patch extends the cpu_get_cache_info function, so that
additional information like size of cache lines can be retrieved.

Patch was tested against the qemu-sbsa mainboard.

Change-Id: If6fe731dc67ffeaff9344d2bd2627f45185c27de
Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79106
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-24 18:21:07 +00:00
75dd806499 mb/dell/optiplex_9020: Implement late HWM initialization
There are 4 different chassis types specified by vendor firmware, each
with a slightly different HWM configuration.

The chassis type to use is determined at runtime by reading a set of
4 PCH GPIOs: 70, 38, 17, and 1.

Additionally vendor firmware also provides an option to run the fans at
full speed. This is substituted with a coreboot nvram option in this
implementation.

This was tested to make fan control work on my OptiPlex 7020 SFF.

NOTE: This is superficially similar to the OptiPlex 9010's SCH5545
however the OptiPlex 9020's SCH5555 does not use externally
programmed EC firmware.

Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81529
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-24 17:42:40 +00:00
51e472d568 mb/google/nissa/var/anraggar: Add cbj_sleeve to control mic jack
Add a new GPIO port cbj-sleeve for kernel driver to call. At the same
time, a new rt5645 driver is added to replace the generic driver to
parse gpio. After entering the system, it is pulled high by the kernel
to enable the MIC function.

BUG=None
TEST=MIC function is normal

Change-Id: I093be6a3e357aae389fcbe8291a9701c40b62e15
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81774
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-24 06:18:31 +00:00
28b0156369 drivers/i2c/rt5645: Add RT5645 amp driver
RT5663 is very old and it was used the hard code like RT53 or 10EC5663,
which is the different series from RT5645/5650, it may caused some
ambiguity. Because I2C generic driver dose not support dsd gpio
setting, we declared the new rt5645 series driver for expansion.

Add RT5645 AMP support. The kernel driver of 5650 is written
in rt5645.c. Add acpi name cbj-sleeve-gpios for power gate GPIO.
ALC5650 DataSheet Rev 0.93

Realtek upstream link:
https://lore.kernel.org/all/20240404035747.118064-1-derek.fang@realtek.com/

Hide the device because of Microsoft Windows.

BUG=None
TEST=verified in anraggar and probe device rt5650 succeed
```
\_SB.PCI0.I2C3.RT58: Realtek RT5650
```

Change-Id: I602fcc4dd8576043943f6e20884edc4703350320
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81773
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-24 06:13:27 +00:00
3f431844c6 drivers/intel/fsp2_0: Support FSP 2.4 64-bits
FSP 2.4 brings FSP 64-bits support which requires some adjustments in
coreboot:

  FSP/UEFI uses the Microsoft x64 calling convention. Appropriate
  attribute has to be set to all functions calling or called by
  the FSP.

BUG=b:329034258
TEST=verified on Lunar Lake RVP board (lnlrvp)

Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec99
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2024-04-23 21:16:13 +00:00
859df7160a soc/intel/alderlake: Add Twinlake graphics device IDs
Add the graphics device IDs for Twinlake platform based on
Platform External Design Specification.

Document ID: 645548

BUG=b:326901448
TEST=Build tivviks and verify the IGD IDs.

Change-Id: Ide008d5c5302bd589784bc917a2610c42a0fdee4
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82038
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-23 21:09:52 +00:00
282b48e2f0 mb/google/rex/var/deku: Update USB _PLD values
Fix custom_pld for USB2-C2 and USB3-C3 with same PLD group.
Update USB2-A4 PLD group token.

USB2/USB3 Type-C Port C2
"ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(3, 1))"
USB2/USB3 Type-C Port C3
"ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"

BUG=b:320203629
BRANCH=firmware-rex-15709.B
TEST= emerge-ovis coreboot

Change-Id: Ieecf0f7dda671a421e4e4a4adbf83240fadd018d
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-23 13:04:50 +00:00
7088257b1a mb/google/rex/var/deku: Configure GPIO
Set unused pin to NC internal PU 20K

BUG=b:325674908
BRANCH=firmware-rex-15709.B
TEST= emerge-ovis coreboot

Change-Id: I78eddaa41c14721eeb6ff33a4cb15382853e430b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-04-23 13:04:32 +00:00
3a988ccebf soc/amd/phoenix/acpi: call acpi_add_opensil_tables in openSIL case
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifdfdbf193bd96a6dda72a2f23d51925fd369aa01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-04-22 18:37:07 +00:00
d7427c6dc8 vc/amd/opensil/stub/ramstage: add acpi_add_opensil_tables stub
In the non-stub openSIL coreboot glue code, this can be used to add the
ALIB SSDT.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3ccd2e81211417ad4ac94f208572e0fa4e1cf97c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82012
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-22 18:36:56 +00:00
62535b66e6 cpu/intel/model_206ax: Allow to configure VR settings
Allow to set board specific CPU voltage regulator settings.

The VR12 compatible voltage regulator for the CPU can be configured
by two MSRs. Currently a default value is applied, which mimics the
Intel reference code and is what the BWG suggest. However most board
vendors fill in the actual VR parameters to support OC or ULV board
variants.

When the mainboard design is too different from the Intel reference
design, not updating the VR settings might result in:
- unstable system behaviour
- limited turbo performance
- excessive battery drain
- no over-clocking capability

This patch adds support to set the board specific current limit for
Icc and Igfx.
It also allows to adjust PSI1, PSI2 and PSI3, which are powerstates
used by the VR, that consume less energy when the system is idle.

Test on Lenovo X220 with full CPU load after 1 minute, compared to
previous code with default settings:
- Limiting PP0 max current below Iccmax results in less CPU performance.
  RAPL readings show that less power is drawn over time.
- Limiting PP0 max current to Iccmax results in equal CPU performance.
  RAPL readings show that the same power is drawn over time.
- Setting the PP0 max current to a value >> Iccmax results in equal CPU
  performance. RAPL readings show that the same power is drawn over
  time.
- Updating the MSR at runtime has no effect.

Change-Id: I59edab47fc4fbe0240e1dd7d25647f7549b4def2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-22 15:31:15 +00:00
2d89c78217 drivers/intel/fsp2_0: Introduce fsp print helper macros
This patch introduces fsp print helper macros to print
`efi_return_status_t' with the appropriate format. These macros
are now used for fsp debug prints with return status

efi_return_status_t is defined as UINT64 or UNIT32 based on the
selected architecture

BUG=b:329034258
TEST=Verified on Meteor Lake board (Rex)

Change-Id: If6342c4d40c76b702351070e424797c21138a4a9
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81630
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-22 14:52:15 +00:00
b55000b2d5 acpigen_ps2_keybd: Add assistant key to linux,keymap
If the ChromiumOS EC indicates that the device has an assistant key,
we should also add it to the generated linux,keymap binding.  This
commit simply does so by examining the keyboard capabilities reported by
the EC.

BUG=b:333088656
TEST=With a device that has an assistant key, flash AP FW and verify
that the key is mapped to `KEY_ASSISTANT` in the Linux kernel using
`evtest`.

Change-Id: I217220e89bce88e3045a4fc3b124954696276442
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81996
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2024-04-22 14:05:42 +00:00
101685de0c device_util: Handle domain device in dev_get_domain
When the input device pointer pointing to a domain device,
dev_get_domain returns the input device itself.

TEST=Build and boot on intel/archercity CRB

Change-Id: I3a278a8f573de95406ee256fba17767def4ad75d
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-22 13:26:02 +00:00
48097a17f1 ec/google/chromeec: Do not fill TypeC ACPI device when UCSI is enabled
Do not fill the ACPI table entry associated with the cros_ec_typec
driver once we switch to the UCSI kernel driver. Skip the ACPI entry if
EC implements the UCSI_PPM feature, and the CBI flag to enable UCSI is
set.

BUG=b:333078787
TEST=emerge-brox coreboot chromeos-bootimage

Cq-Depend: chromium:5416841
Change-Id: I67dff6445aa7ba3ba48a04d1df3541f880d09d0a
Signed-off-by: Pavan Holla <pholla@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-04-22 13:21:01 +00:00
835ed7a7ab mb/google/nissa/var/craaskov: modify 6W and 15W DPTF parameters
The DPTF parameters were defined by the thermal team.
Based on thermal table in 330817690#comment33.
Set 6w "tcc_offset" to "15" by fw_config.

BUG=b:330817690, b:290705146
BRUNCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I19100d960919dc3087fd067c24659de467eea276
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81997
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-04-22 13:19:14 +00:00
41ba11229a arch/arm64: Add EL1/EL2/EL3 support for arm64
Currently, arch/arm64 requires coreboot to run on EL3 due
to EL3 register access. This might be an issue when, for example,
one boots into TF-A first and drops into EL2 for coreboot afterwards.

This patch aims at making arch/arm64 more versatile by removing the
current EL3 constraint and allowing arm64 coreboot to run on EL1,
EL2 and EL3.

The strategy here, is to add a Kconfig option (ARM64_CURRENT_EL) which
lets us specify coreboot's EL upon entry. Based on that, we access the
appropriate ELx registers. So, for example, when running coreboot on
EL1, we would not access vbar_el3 or vbar_el2 but instead vbar_el1.
This way, we don't generate faults when accessing higher-EL registers.

Currently only tested on the qemu-aarch64 target. Exceptions were
tested by enabling FATAL_ASSERTS.

Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74798
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-04-22 07:35:36 +00:00
93cbbbfc7f security/tpm/tspi/crtm.c: Fix space required before open brace error
Fix checkpatch error.

Change-Id: I890fcfa4ad7b7abe032248b435271514e8e264f3
Signed-off-by: Naveen R. Iyer <iyernaveenr@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82001
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-21 03:39:12 +00:00
8b53aa6eee util/lint: Add lint rule to watch for Makefile.inc
This should keep new makefiles from being named Makefile.inc.

Change-Id: I4a47998e1c997b82b8a15319eae96cdc0de64e77
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81857
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-04-20 21:08:36 +00:00
63ca402088 payloads/edk2: Add Kconfig to use LAPIC timer
Core 2 platforms have issues with HPET. Enable support to use the LAPIC
driver so those machines actually boot and don't hang.

The LAPIC is actually closer to the CPU than the HPET (on the PCH),
which reduces access latency, leading to higher resolution of the timer.

Tested on a Lenovo X200 with a Core 2 Duo.

Change-Id: I33144d6c1c120e7faa47b99e8262b0997c45c9b9
Signed-off-by: Jean Lucas <jean@4ray.co>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82000
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-20 18:38:55 +00:00
8d6625a595 ec/google/chromeec: Update ec_cmd_api.h and ec_commands.h
Generated using update_ec_headers.sh [EC-DIR].

The original include/ec_commands.h version in the EC repo is:
  b3b35d6433 PPM: Rename ucsi_disabled to ucsi_enabled
The original include/ec_cmd_api.h version in the EC repo is:
  562316a71e include: Add fingerprint host commands to ec_cmd_api.h

BUG=b:333078787
TEST=cros build-packages --board brox \
     chromeos-bootimage depthcharge coreboot
TEST=cros build-packages --board brya \
     chromeos-bootimage depthcharge coreboot
BRANCH=none

Change-Id: I94b509cd6ad8f24bfc3b44ef02633d06320f1e22
Signed-off-by: Pavan Holla <pholla@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81965
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2024-04-19 20:21:12 +00:00
552a179810 mb/google/brox/variants/lotso: add missing hda_verb.h
Commit 00b40090ae ("mb/google/brox: Move hda verb to variant dir")
introduces a variant-specific file for the HDA verb tables, which
commit 1bf0c3f189 ("mb/google/brox: Create lotso variant") was missing
which caused the build to fail when both patches were submitted. To fix
the tree, add this file to the newly created lotso variant.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8a85115a204d9d9447a58da71eb65b1de963023d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82014
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-19 19:04:26 +00:00
1bf0c3f189 mb/google/brox: Create lotso variant
Create the lotso variant of the brox reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:333494257
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_LOTSO

Change-Id: I5939127f9e6abe5b792c0627d9d67e739b27083b
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-04-19 17:23:18 +00:00
fef07f2c3a acpigen_ps2_keybd: Add Fn key to linux,keymap
Some devices may generate scancodes for the Fn key if they have one.
If they do, we should add them to the linux,keymap binding.

BUG=b:333096023
TEST=Flash DUT that emits a scancode for the Fn key, verify that it is
mapped to KEY_FN in the Linux kernel using `evtest` when pressing the Fn
key.

Change-Id: Ie4daa64bc6b619392276d0b5f16e2d195d5bd68c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2024-04-19 17:22:48 +00:00
00b40090ae mb/google/brox: Move hda verb to variant dir
Others variant boards might use diff HDA Codec, so move hda verb
to brox variant dir.

BUG=b:314702466
BRANCH=None
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage

Device list:
cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name
ALC256
cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name
Realtek

Headphone detection:
evtest 8
Event: time 1713404716.656768, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1
Event: time 1713404716.656768, -------------- SYN_REPORT ------------
Event: time 1713404722.802661, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 0
Event: time 1713404722.802661, -------------- SYN_REPORT ------------

Change-Id: Id987c248c37dc8bdc63be7a2513fa8997b5ddc33
Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81945
Reviewed-by: Poornima Tom <poornima.tom@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-19 15:34:21 +00:00
2ffacde135 mb/asus/p8z77-m: Squelch PNP error about 2e.b irq 70
[ERROR]  PNP: 002e.b 70 irq size: 0x0000000001 not assigned in devicetree

Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: I2231afd67031c963045b6e7930d239368c723aa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75142
Reviewed-by: Keith Hui <buurin@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-19 14:18:06 +00:00
0c47989176 mb/asus/p8z77-m: Disable deep sleep
One can argue whether or not this is desirable, but disabling this means
you cannot use power from the USB ports when the board shuts down, which
is better controlled from an option, but at the very least disabled so
as to replicate default vendor firmware behaviour.

Disable deep sleep like it is disabled on all other variants.

Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: I660f2efebf197df055ee7b9c349e4c2b64bda6cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75139
Reviewed-by: Keith Hui <buurin@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-19 14:17:24 +00:00
f62b0c332b mb/asus/p8z77-m: Enable Port 80 UART
Copied this bit from asus/p8z77-m_pro, without it a GRUB2 payload will
get stuck in an endless loop showing

Unknown key 0xff detected

whenever there is an USB device (such as a keyboard) connected.
In this mode GRUB2 is so busy showing this message repeatedly that no
other keypress ever gets handled, and thus no other remedy is possible
than a reset via mb pins and unplugging the USB device.

Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: Iebd433e2762a69241257e1b4f859319536a8d8f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75138
Reviewed-by: Keith Hui <buurin@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-19 14:17:01 +00:00
8068f941a9 mb/google/brox/var/greenbayupoc: Add fw_config field for storage
Add STORAGE_UNKNOWN, STORAGE_UFS, STORAGE_NVME for storage fw_config
field to prevent depthcharge build break.

BUG=b:333325006
TEST=emerge-brox coreboot depthcharge with no errors

Change-Id: I0e220787d6ac73ec8fa2469ed958981d0801920e
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
2024-04-19 14:15:06 +00:00
01344bce1a acpi: Make acpi_device_write_dsd_gpio() public
Make sure it can be used for other driver.
At present, i2c_generic_write_gpio() is not suitable for being called
by other drivers, so delete it, add acpi_device_write_dsd_gpio() to
replace it, and make it public.

BUG=None
TEST= Build BIOS FW pass and it can be use for other driver.

Change-Id: Ifb2e60690711b39743afd455c6776c5ace863378
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-04-19 14:13:41 +00:00
f8a46950cc soc/amd/glinda: Add support for A0 and B0 steppings
Update the A0 and B0 stepping IDs in CPU table per
the PPR document 57254 Rev 1.56 and 1.69

Change-Id: I0072f25f981ac7d5df2522594c8788bfabcbf24c
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-19 14:12:36 +00:00
70108382de libpayload: Fix inl() return type mismatch
Change `inl()` return type from `unsigned long` to `unsigned int` to
match the function definition and ensure consistency across platforms.

BUG=b:242829490
TEST=Compiled successfully in 32-bit and 64-bit modes.

Change-Id: I681935665c8de9ee472ab72fe1ac2f5dcc0f2534
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-04-19 08:29:12 +00:00
271ee0745e device/device_util: Rename dev_get_pci_domain
In coreboot, domain indicates hardware units that provide/group
resource windows, For Xeon-SP, domains are PCIe compatible and
further function in many aspects, e.g. PCIe, CXL, IOAT, UBOX.

Rename dev_get_pci_domain to dev_get_domain to align with coreboot
concept and distinguish from Xeon-SP concept.

TEST=Build and boot on intel/archercity CRB

Change-Id: I51b18b30fb41038869ea1384b01091da31a895b9
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-18 11:38:02 +00:00
e56a41b33f device/device_util: Use const qualifier
Allows to use the function in more places that expect the
struct device to be readonly.

TEST=Build and boot on intel/archercity CRB

Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81275
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-18 11:25:32 +00:00
72b8d2fbc7 mb/dell/optiplex_9020: Add support for TPM1.2 device
These machines come with a TPM1.2 device by default. It is somewhat
obsolete these days, but there is no harm in enabling it.

Change-Id: Iec05321862aed58695c256b00494e5953219786d
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81827
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-18 11:08:43 +00:00
e8090dd179 mb/asus/p8z77-m: Disable WDT1
WDT1 is currently enabled but gives these errors:

[ERROR] ERROR: Resource didn't fit!!!
               PNP: 002e.8 60 * size: 0x8 limit: fff io
[ERROR] PNP: 002e.8 60 io size: 0x0000000008 not assigned in devicetree

Therefore, just disable it, like it is disabled on all other variants.

Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: Ie33c219eae60f55d272b261480283a02c2d502e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75144
Reviewed-by: Keith Hui <buurin@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-18 11:06:43 +00:00
0cb5e8415b sb/intel/bd82x6x/pch.asl: Remove GPIO configuration access
Allowing access to change GPIO configuration from ACPI is asking
for trouble. Kill it while nobody cares (yet).

Access to mainpulate and blink GPIOs is maintained.

Change-Id: Id80a7e2f815a58750623c133bb30e5ed84a6e2ed
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-18 11:05:11 +00:00
f5b993de4f sio/nuvoton/nct6779d: Correct GPIOBASE virtual LDN
According to datasheet, the enable bit for direct I/O access to GPIO
lines is at CR30[3] of LDN 8, not [0] as currently coded.

Change-Id: Id2f997aebc36a2fcaa8c3763f324d3b288f785d2
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81926
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-18 11:04:25 +00:00
8b5aacca3f nb/intel/gm45: Call mb_post_raminit_setup() later
The only implementations of `mb_post_raminit_setup()` in the tree are
found in Lenovo ThinkPads. These boards use this function to toggle a
SMBus mux, which makes the DIMM SPDs inaccessible. Given that the SPD
data is needed in `setup_sdram_meminfo()` and that there are no other
side-effects, simply move the call to `mb_post_raminit_setup()` after
the call to `setup_sdram_meminfo()`.

TEST=Verify SMBIOS Type 17 information for lenovo/x200 is correct.

Change-Id: I46abffa48e7e0848f9346ce9c6498860e4ece2da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-18 11:03:40 +00:00
7d3e161d70 nb/intel/gm45: Fill in memory info
Fill in memory info so that coreboot can generate SMBIOS Type 17 tables.
The S/N, P/N and module ID fields are only populated for DDR3.

Change-Id: I92060ce05bdf0ca617a3383a2db1fdbd43df6fe4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81861
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jean Lucas
2024-04-18 11:02:46 +00:00
57946ad817 mb/asus/p8z77-m[_pro]: Blink power LED during suspend
Set GPIO27 of PCH to blink before going to sleep. This blinks the
power LED. Revert after waking up.

Tested on p8z77-m. Power LED blinks in suspend.

Change-Id: Ie1b40ae17fa2ef397585b86ac82730099b611dda
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-18 11:00:37 +00:00
4da9b9f0a9 sb/intel/bd82x6x/pch.asl: Break out GPIO blink field
Break out the individual bits of GPIO blink register as was done
for GPIO level register. An upcoming patch will use this.

Change-Id: I6f4749f60a9d569deba4b31f09f07a1321dabf4a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81922
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-18 10:58:19 +00:00
b93d6676d3 mb/asus/p8z77-m[_pro]: Correct PCH GPIO config
According to a boardview, GPIO27 is connected to the front
panel power LED, and should be output.

It will be made to blink before entering S3 suspend in a follow-up.

Change-Id: I7e47f63999e8c0bfbd37e3273d33c00bc035bcbb
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-18 10:57:23 +00:00
f2107579ff mb/google/nissa/var/glassway: Add SPD IDs for two new memory parts
Support Memory for Hynix H58G66AK6BX070 and Samsung
K3KL9L90CM-MGCT in mem_parts_used list, and generate SPD ID for these
parts.

DRAM Part Name                 ID to assign
H58G66AK6BX070                 4 (0100)
K3KL9L90CM-MGCT                5 (0101)

BUG=b:335341310
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
     part_id_gen.go ADL lp5 \
     src/mainboard/google/brya/variants/glassway/memory/ \
     src/mainboard/google/brya/variants/glassway/memory/\
     mem_parts_used.txt"

Change-Id: Ic07ec36a8015ce6433196a93e894b818a515b954
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81955
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
2024-04-18 10:54:37 +00:00
0b70b0b790 cpu/intel/microcode: Defer microcode patching until after DRAM init
Follows Intel SoC recommendation to avoid potential cache contention
issues during early (pre-DRAM) microcode loading.

Source: MTL_ARL_Processor_Family_BiosSpec_Rev1p0
Document Number: 729384

BUG=b:330536271
TEST=Able to boot to ChromeOS.

w/o this patch:

[DEBUG]  microcode: sig=0xa06a4 pf=0x80 revision=0x19
[INFO ]  CBFS: Found 'cpu_microcode_a06a4.bin' @0x1d9c0 size 0x21400
    in mcache @0xfef89680
[INFO ]  VB2:vb2_digest_init() 136192 bytes, hash algo 2, HW
    acceleration enabled
[INFO ]  microcode: load microcode patch
[ERROR]  microcode: Update failed

w/ this patch:

[ERROR]  Microcode Error: Early microcode patching is not supported due
    to NEM limitation

Change-Id: I1e433f5bede036800b27900b4b13a399b4f45d6f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81954
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-18 03:30:44 +00:00
24bc05d797 sb/intel/ibexpeak: Drop USB3 settings from devicetree
ibexpeak has no USB 3 capabilities.

They were kept briefly when its devicetree structure was split from
bd82x6x in commit ab4de83f43 ("sb/intel/ibexpeak: Sever bd82x6x
source dependency") to verify correctness. With that done, they
can go.

Change-Id: I6b847e1532d2e84a7b408a8858c8613b322d0373
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-04-17 17:52:41 +00:00
2ed80b16b3 mb/google/brox: Enable SAGv
Enable SaGv support for brox

BUG=None
BRANCH=None
TEST=Boot brox with SAGv enabled and verify in fsp debug logs

Change-Id: I80c44e7df1d75732c6982b27e44ecd6060b1b3f1
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81556
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-17 17:52:10 +00:00
055c6d5c34 util/crossgcc/buildgcc: Use Intel mirror for ACPICA
The binary hashes from GitHub releases are not stable. Use the Intel
mirror.

Change-Id: If3738b0cdab07c37ac1459a53e399e5de54435d5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80721
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-04-17 17:18:58 +00:00
072e8c34f1 mb/google/brya: Enable UFS driver for edk2 payload
Several brya-based boards use UFS for storage, so enable the edk2 UFS
driver when using the edk2 payload.

TEST=build/boot google/brya (banshee, craaskov), verify internal boot
media functional with edk2 payload.

Change-Id: I3dc018582e974bf73c7668f78da9b81eeb038c01
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81871
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-17 14:34:06 +00:00
4fbb59eb31 mb/google/zork: Enable eMMC driver for edk2 payload
Several zork-based boards use eMMC for storage, so enable the edk2 eMMC
driver when using the edk2 payload.

TEST=build/boot google/zork (morphius, vilboz), verify internal boot
media (both eMMC and NVMe) functional with edk2 payload.

Change-Id: Ib7e98f309594554dbcf1ddd875d47c89bd9e0e44
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-17 14:33:36 +00:00
63359d1bce payloads/edk2: Add Kconfig to enable AMD Picasso eMMC driver
Add a Kconfig to selectively enable the AMD Picasso eMMC driver
recently added to MrChromebox's edk2 fork. When selected, will enable
booting from AMD Picasso devices with eMMC storage.

TEST=tested with rest of patch train

Change-Id: I6536a6f243f6766b913e295afebcf5b965e4e969
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81892
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-17 14:33:11 +00:00
28a147e116 payloads/external: Call $(strip_quotes ) on prebuilt iPXE path
Currently, we keep the double-quotes from Kconfig, resulting in an
invalid path. So just call `strip_quotes` like we do with all other
paths from Kconfig.

Change-Id: Ibcaa59be0fdd84d1fb9e061394fd9b0f7aa1830b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81947
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-17 14:00:24 +00:00
abc3812365 ec/google/chromeec: Update EC headers
Generated using update_ec_headers.sh [EC-DIR].

The original include/ec_commands.h version in the EC repo is:
  9fdd96bfc6 keyboard: Add support for a "Dictation" key
The original include/ec_cmd_api.h version in the EC repo is:
  562316a71e include: Add fingerprint host commands to ec_cmd_api.h

Change-Id: I7ec965d07aa4cb1fe54916845780f342ea3debb9
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81932
Reviewed-by: Forest Mittelberg <bmbm@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-17 13:45:43 +00:00
c1a390f8c9 mb/google/corsola: Add new board variant Veluza
Add a new Krabby follower device 'Veluza'.

BUG=b:333630131
BRANCH=corsola
TEST=none

Change-Id: Idedcbfbddd6d98a51cf28a0963d68f6d8c68382c
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81791
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-17 13:40:23 +00:00
00531f067c mb/up/squared: Make mini PCIe port mode configurable
Add config choice menu and pad configuration to put Mini PCIe port into
mSATA mode.

The vendor firmware's "Chipset->Mini PCIe / mSATA Switch" option has
been used together with the output of inteltool and intel2pm to deduce
the exact pad configuration.

Note: the vendor firmware does not autodetect the mode, and the default
setting for the port is "Mini PCIe".

Tested with Kingston SUV500MS120G mSATA SSD.

Change-Id: Ic2da1dd4252ebb5e373bc65418e321f566d4c10f
Signed-off-by: Reto Buerki <reet@codelabs.ch>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-17 13:39:26 +00:00
93f2f0f7bd arch/x86: Prevent .text/.init overlap with older linkers
Add Kconfig option `X86_BOOTBLOCK_EXTRA_PROGRAM_SZ` to reserve extra
space, avoiding overlap between .text and .init sections when using
older linkers (binutils 2.3x). Default is 1024 bytes (1 KiB) for
ChromeOS, 0 otherwise.

BUG=b:332445618
TEST=Built and booted google/rex (32-bit/64-bit).

Change-Id: I019bf6896d84b2a84dff6f22323f0f446c0740b5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81886
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-17 06:39:48 +00:00
a70493d5b2 mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge)
This is another readily available (used market) system.
Based on autoport.

* All peripherals should work.
* Automatic fan control as well as S3 are working.
* The board was tested to boot Linux and Windows. EHCI debug is
  untested.
* When using MrChromebox edk2 with secure boot build in, the board will
  hang on each boot for about 20 seconds before continuing.

There are some quirks for doing the first flash, see the documentation.

Change-Id: Idf793fe915096cf2553572964faec5c7f8526b9a
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-04-16 15:41:36 +00:00
934a32d752 superio/fintek/f81866d: Fix UART numbers
Change-Id: I996b8e56d943e26ab426f1802ada07cde805286d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81915
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-04-16 15:39:48 +00:00
b921782385 buildgcc: Match the string of downloading percentage more precisely
The command "wget" prints some hyperlink with "%", which will be
filtered in by previous regular expression. So we need to change to
match the string with exactly 3 digits and a percent symbol.

TEST:
echo 45%  | grep -o "\<[0-9]\{1,3\}%"
  45%
echo 1245% | grep -o "\<[0-9]\{1,3\}%"
  <empty>
echo aa%  | grep -o "\<[0-9]\{1,3\}%"
  <empty>

Change-Id: I6ef9e7c87fd4ee6cc707346954d91e6e3af3b939
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-04-16 13:55:22 +00:00
3e5cefcc45 security/tpm: support compiling in multiple TPM drivers
Starting from here CONFIG_TPM1 and CONFIG_TPM2 are no longer mutually
exclusive.

Change-Id: I44c5a1d825afe414c2f5c2c90f4cfe41ba9bef5f
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69162
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-16 13:52:14 +00:00
7c75f8e5b2 payloads/edk2/Makefile: Drop duplicated build string option
The `PRIORITIZE_INTERNAL` option was somehow duplicated, so remove the
extra copy, leaving the one under the MrChromebox repo specific
settings.

TEST=build qemu w/edk2 payload, check build log that the
'PRIORITIZE_INTERNAL' option is only added once to the build string.

Change-Id: I4c4c433184d93337c926e256e77054afc00a2566
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-04-16 13:36:18 +00:00
e538926d30 mb/google/nissa/variant/sundance: Modify i2c device for touch device
1. Remove non-use i2c address 0x10, 0x24 and 0x40 of touch IC for touch screen
2. Add new i2c address 0x5d of Goodix touch IC for touch screen
3. Add new i2c address 0x38 of Focal touch IC for touch pad

BUG=b:333804572
TEST=FW_NAME=sundance emerge-nissa coreboot chromeos-bootimage

Change-Id: I8e2c60820a07b99b69860fd4f6557b448aef2341
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-16 12:05:38 +00:00
71d8f7c2b6 payloads/edk2: Add Kconfig to enable UFS support
Add a Kconfig to selectively enable the UFS DXE driver recently added
to MrChromebox's edk2 fork. When selected, will enable booting from
devices with UFS storage.

TEST=tested with rest of patch train

Change-Id: I0b54d21dc87abf6938c03948830f92ce5097ef7d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81870
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-16 12:03:11 +00:00
9a2266bdc2 mb/google/nissa: Create pujjoga variant
Create the pujjoga variant of nissa reference board by copying the
template files to a new directory named for the variant.

Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.

BUG=b:333839287
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PUJJOGA

Change-Id: Ia8eb11eb65f9013e83abd45eefe7705d05b8697e
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81891
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-16 12:02:34 +00:00
ab4de83f43 sb/intel/ibexpeak: Sever bd82x6x source dependency
It shares southbridge devicetree definition with bd82x6x, causing
changes made there to break builds for boards with this PCH. Give
ibexpeak its own copy.

TEST=abuild tested with lenovo/t410, lenovo/x201, packardbell/ms2290. Timeless binary did not change for all.

Change-Id: I08229ca658bd9c360b6be6137d882d319041b730
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81889
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-16 12:01:09 +00:00
940cbed8d3 mb/packardbell/ms2290: Correct header included
It uses ibexpeak southbridge and should include its pch.h,
not bd82x6x's.

TEST=Timeless binary did not change.

Change-Id: Iafa83b7f3c1cd2d8ab9af51aa331ca673d9a66df
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-16 11:59:46 +00:00
76a015946e nb/intel/haswell: Fix building BDW MRC.bin path with clang
Clang complains that the two enumerations are incompatible. However, the
values themselves are the same (0: mobile, 1: desktop, 5: ULT). So, cast
the function's return value to silence the warning.

Change-Id: If7b5e22e893e9f3f17a15197c65448fb782590f6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81862
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-16 01:47:24 +00:00
41d107019b sb/intel/lynxpoint: Fix AER and L1 sub-state reporting
Program the AER capability header register in a single write because
it's write-once. In addition, only PCH-LP supports L1 sub-states, so
only report the L1 sub-state capability on PCH-LP. This follows what
Lynx Point PCH reference code version 1.9.1 does.

Change-Id: I08bd107eec7a3b2f1701c4657ae104e0818ae035
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57503
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-16 01:46:42 +00:00
6ef23316c2 sb/intel/lynxpoint/pcie.c: Fix 0xf5 register mask
Lynx Point PCH reference code version 1.9.1 masks the upper 4 bits of
the PCIe root port register at offset 0xf5.

Change-Id: I9529ad88d34a5cb4a09843e3165f3a70c5ea22e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57502
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-16 01:46:05 +00:00
fd46b497ea lynxpoint/broadwell: Correct L1 exit latency with ASPM
Lynx Point PCH reference code version 1.9.1 programs the larger L1 exit
latency when ASPM is enabled. Document 535127 (BDW PCH-LP BS) also does
the same. Correct the condition accordingly. On Lynx Point, also remove
a now-redundant write to the LCAP register (offset 0x4c).

Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57501
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-16 01:45:36 +00:00
ebba6da073 mb/google/zork: Increase SMMSTORE size to 256K
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since
a minimum of (2) 64K blocks are needed. Increase the size to 256K to
match other boards in the tree.

TEST=build/boot zork (morphius) with SMMSTORE enabled.

Change-Id: Ifd3be9b0757e270d2f106e2fbebf3991e49dec65
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-15 16:41:33 +00:00
94944053bd mb/google/skyrim: Increase SMMSTORE size to 256K
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since
a minimum of (2) 64K blocks are needed. Increase the size to 256K to
match other boards in the tree.

TEST=build/boot skyrim (frostflow) with SMMSTORE enabled.

Change-Id: I34f9d27c27ab7148dfc530322f741a576c348de7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-15 16:41:24 +00:00
680db8d95f mb/google/myst: Increase SMMSTORE size to 256K
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since
a minimum of (2) 64K blocks are needed. Increase the size to 256K to
match other boards in the tree.

Change-Id: Ic45324b8c5bbd205e889e934c9d5dd17f7775152
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81867
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-15 16:41:05 +00:00
6287ac3702 mb/google/guybrush: Increase SMMSTORE size to 256K
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since
a minimum of (2) 64K blocks are needed. Increase the size to 256K to
match other boards in the tree.

TEST=build/boot guybrush (dewatt) with SMMSTORE enabled.

Change-Id: Ic4fdacd493d83fa3c1683a06d1276b0190f6db8b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-15 16:40:54 +00:00
a2121eab7d mb/amd/*: Increase SMMSTORE size to 256K
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since
a minimum of (2) 64K blocks are needed. Increase the size to 256K to
match other boards in the tree.

Change-Id: I04d57ff7f74d79118652cfe227cf223375df6472
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81865
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-15 16:40:48 +00:00
c5d191b292 mb/google/fizz: Use variant-specific gma-mainboard.ads files
The karma variant, being a Chromebase, has an internal eDP output for
the built-in display whereas the fizz/endeavour variants do not. Use
separate gma-mainboard.ads files so that karma's internal panel works
properly with libgfxinit.

TEST=build google/fizz (fizz/karma) with libgfxinit enabled, ensure
correct gma-mainboard.ads file is included in the build.

Change-Id: Ia6aca538ba8c13b48aa80901222071d704b5f0c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-15 13:36:54 +00:00
db3fe7e8ff sb/intel/bd82x6x: Add four new USB currents
Found by inteltool on HP Pro 3500 Series running vendor firmware version
8.14 Rev.A.

Change-Id: I156787e533c2605e7440548a2d3bf711bb1af5d7
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81427
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-15 13:35:54 +00:00
1a90314ac5 drivers/crb: use crb_tpm_ prefix instead of tpm2_
This prevents name clashes with drivers/spi/tpm and allows both to be
potentially compiled in at the same time.

Change-Id: I0aa2686103546e0696ab8dcf77e2b99bf9734915
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-04-15 13:35:00 +00:00
45145ba805 mb/google/brox: Create greenbayupoc variant
Create the greenbayupoc variant of the brox reference board by copying
the template files to a new directory named for the variant.

BUG=b:329530883
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_GREENBAYUPOC.

Change-Id: I90936d97b41e59c49dd92997146caf580bce1f4f
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
2024-04-15 13:34:11 +00:00
bebdabac0e mb/google/corsola: Add new board variant Skitty
Add a new Krabby follower device 'Skitty'.

BUG=b:331702790
TEST=emerge-corsola coreboot chromeos-bootimage
BRANCH=corsola

Change-Id: I2f12bccfda591a5baf8d23d217b6f1f81b059d15
Signed-off-by: Herbert Wu <herbert1_wu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81772
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Geoffrey Chien <geoffrey_chien@pegatron.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Shawn Ku <shawnku@google.com>
2024-04-15 13:33:34 +00:00
f2782b8328 acpigen_ps2_keybd: Add support for dictation key
Some internal keyboards have a dictation key; this commit simply adds
support for this key by adding the mapping from the scancode to the
Linux keycode for use in the linux,physmap ACPI table.

BUG=b:333101631
TEST=Flash DUT that emits a scancode for a dictation key, verify that it
is mapped to KEY_DICTATE in the Linux kernel.

Change-Id: Iabc56662a9d6b29e84ab81ed93cb46d2e8372de9
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-04-15 13:32:48 +00:00
35130a8e1f soc/amd/picasso: Mark eMMC as non-removable for Windows 10/11 install
Mark eMMC as non-removable to allow Windows 10/11 to install now that
edk2 can boot from it.

Change-Id: If0e14106521f99cb97d1bf421f4d82d1234c2f15
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-04-15 13:31:53 +00:00
1273925999 src/mb: Rename new Makefile.inc files to Makefile.mk
These files were added after the switch.

Change-Id: I1986e4f921e0e56fe5255433d4b9216dc7c4dc59
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81856
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-15 12:39:57 +00:00
dc735c19c7 soc/intel/xeon_sp/spr: Use official microcodes
Use the official microcode updates from intel-microcode submodule
by default. Downstream users can still decide to use their own files.

Change-Id: I58121cc2ca7699d3d26581d7d5875ec74deeeb93
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81637
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-04-15 08:26:56 +00:00
0ad214846c include: Add 'IWYU pragma: export' comment
This pragma says to IWYU (Include What You Use) that the current file
is supposed to provide commented header.

Change-Id: I3acb5e6b18443e454d8174b0b1f9d207c0fb78b5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-15 05:30:24 +00:00
81b7c296d3 soc/intel/broadwell: Add ACPI CIDs for SerialIO devices
Lynxpoint has them, so add them on Broadwell as well.

Change-Id: Iaa3e8044090262a64e58062ec4b116976978ce55
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-04-14 20:58:34 +00:00
f58e536016 lynxpoint/broadwell: Correct PCH-LP PCIe ASPM check
Lynx Point PCH reference code version 1.9.1 checks bit 29 to detect ASPM
on PCH-LP root port #6, not bit 28. Document 535127 (BDW PCH-LP BS) also
uses bit 29 for root port #6. Correct the bit used in the check, as well
as the surrounding comments.

Change-Id: Ie4bd7cbbfc151762f29eab1326567f987b25ab19
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57500
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-14 20:54:16 +00:00
9cd1bf2c17 soc/intel/xeon_sp/spr: Drop microcode constraints
For current generation SPR/EMR you need to add at least
3 different microcodes having about 2MiB of size in total.
This doesn't work with the hardcoded offset and size in Kconfig.

Since it's loaded through FIT there's no need to pass it to FSP-T.
Drop the hardcoded locations and place it somewhere in CBFS.

Test: Booted on ibm/sbp1 with microcode confirmed loaded in
      bootblock on BSP. All the APs also have the correct
      microcode version loaded.
TEST= Build and boot on intel/archercity CRB
      'cat /proc/cpuinfo | grep microcode' result doesn't change
      before and after this patch.


Change-Id: Iaa7007c2b11a860c9c664a7e753440bad7fe858e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81635
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-04-14 20:50:22 +00:00
e2271dc0de soc/intel/xeon_sp: Compress FSP-S
Compress FSP-S to save some space in CBFS.
Reduces the size of debug FSP-S by about 25%.

Test: Still boots on ibm/sbp1.
TEST= Build and boot on intel/archercity CRB.

Change-Id: I6248e7cabbce45f6c2fedfab34f328309f87e868
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81634
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-04-14 20:48:58 +00:00
b61738ce76 drivers/uart/pl011: Enhance struct documentation
Source:
PrimeCell UART (PL011) Technical Reference Manual Revision: r1p5

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I58409b23e3790a052d3bc0ecf6a6bede15b4d76f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80180
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-14 10:10:43 +00:00
b40b6ff53e mb/samsung/stumpy: Set initial fan PWM to 30%
Recent changes to the ITE 8772F SIO code caused the initial fan PWM
to change from 0 to 50%; set it to 30% to reduce fan noise while
still providing some temp control before the OS/ACPI takes over.

TEST=build/boot stumpy to payload, verify fan noise is negligible.

Change-Id: I287e46202ee1c112d1da63c0d8b7889958e3807e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81514
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-13 13:26:25 +00:00
b8c451e375 mb/google/beltino: Set initial fan PWM to 30%
Recent changes to the ITE 8772F SIO code caused the initial fan PWM
to change from 0 to 50%; set it to 30% to reduce fan noise while
still providing some temp control before the OS/ACPI takes over.

TEST=build/boot google/beltino to payload, verify fan noise is
negligible.

Change-Id: I0177235d73e051f02b5333cf1d735556382b919f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81513
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-13 13:26:04 +00:00
e45d6bfd8a superio/ite: Add function to disable PME# output
A function to disable the PME# output was added. This is required to
set up the SuperIO on the "HP Pro 3500 Series" mb.

Change-Id: I94f023ba6eb24b5fb1c5e0b30eb65738f50a87eb
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81589
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-04-13 13:24:12 +00:00
a7c96155b9 superio/ite: Add function to disable 3VSBSW# signal
The 3VSBSW# signal can now also be disabled again which is necessary to
power components down properly in SMM when entering S5. In such cases
the signal will be enabled only in the SMM S3 handler.

Change-Id: I8535176908ec39e9916774135e028cbc7c203474
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81588
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-13 13:24:04 +00:00
9905d1f8a8 superio/ite: Add special fan vectors
A number of ITE SIOs support "special fan control vectors", which
effectively allow non-linear fan speed control. This is for example used
by the vendor firmware of the "HP Pro 3500 Series".

The special vector registers won't be written to until the mb's
devicetree configures `FAN_VECX.tmp_start != 0`.

Change-Id: I93df2b5652fc3fde775b6161fa5bebc4a34d5e94
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-04-13 13:23:12 +00:00
fb51661be1 superio/ite: Unify it8772f with common code
The it8772f is now configured by the much better common code that is
used for other chips in the family as well. This mainly concerns the EC,
the GPIO functionality was not moved to common as it currently lacks a
sane abstraction in any codebase.

The datasheets of the it8772e(f) and it8728f (for reference) were
studied and verified against the common code, adding exceptions where
needed.

Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81310
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-04-13 13:22:58 +00:00
1a7ffa8521 lenovo/haswell: enable ONBOARD_VGA_IS_PRIMARY
Haswell ThinkPads have Nvidia Optimus wired in on some models.
With recent coreboot changes, legacy VGA decode is now disabled
on the iGPU, and the iGPU itself is disabled, when a dGPU is
present. This is a problem on Optimus laptops, because it means
that the Intel GPU would be effectively disabled, when it is the
one that has to handle the framebuffer.

On these boards, you can enable ONBOARD_VGA_IS_PRIMARY so that
coreboot does not disable the iGPU. This is because on Optimus
laptops, the Nvidia GPU is only used for offloaded rendering.

Enable ONBOARD_VGA_IS_PRIMARY by default on these boards.

Change-Id: I8f1e0ca2861d1cc9a9ad41e7c9257aeca1a62a31
Signed-off-by: Leah Rowe <info@minifree.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81645
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-13 11:14:31 +00:00
316d687d3a soc/intel/broadwell/pch/sata.c: Add missing SATA init steps
WildcatPoint-LP BIOS spec lists them, and are the same for Lynxpoint.

Change-Id: Iba28c1591affafeb37097084c2fa58128974bd00
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-13 11:13:58 +00:00
6f75dd0fd0 sandybridge,haswell,broadwell: Use DIV_ROUND_CLOSEST macro
Integer division in C truncates toward zero. When the dividend and the
divisor are positive, one can add half of the divisor to the dividend to
round the division result towards the closest integer. We already have a
macro in commonlib to do just that, so put it to good use.

Tested with BUILD_TIMELESS=1, coreboot images for the Asus P8Z77-V LX2
and the Asrock B85M Pro4 do not change.

Change-Id: I251af82da15049a3a2aa6ea712ae8c9fe859caf6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52651
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-13 10:53:42 +00:00
b7341da191 nb/intel/sandybridge/raminit: Add tCPDED corner case
tCPDED is always 1, except for steppings earlier than Sandy Bridge D0.
Reduces the differences to MRC.bin.

Tested on Lenovo X220: Still boots and runs fine.

Change-Id: I5294173c02f06c601fdb13ed785ee33d7a4e3eca
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79762
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-04-12 18:20:29 +00:00
220bd26b6e nb/intel/sandybridge/raminit: Only write register on Ivy Bridge
Only write register WMM_READ_CONFIG on Ivy Bridge as it's
reserved on Sandy Bridge.

Tested on Lenovo X220: Still boots and runs fine.

Change-Id: Ie14ea06d744b1a8368d32803c6c1ccfb1262532e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79761
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-12 18:19:00 +00:00
d81324eb74 nb/intel/sandybridge/raminit: Drop write to BANDTIMERS_SNB
MRC.bin doesn't write BANDTIMERS_SNB register, so drop the
write. The bits written were targeting a reserved range,
so assume it didn't do anything useful.

Tested on Lenovo X220: Still boots and runs fine.

Change-Id: I920aabd60831c791188af976914553787cc0ff18
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-04-12 18:18:40 +00:00
8204dc395e mb/google/brox: Initialize NOTE_BOOK_MODE GPIO
The GPIO for NOTE_BOOK_MODE has changed from GPP_B17 to GPP_E9. Also
initializing it (if ISH is enabled) to be NF2 (ISH_GP4).  Also took
the liberty of alphabetizing all the ISH GPIOs to they're easier to
search through.

BUG=b:316421831
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
     Make sure that brox device still boots up with this change.

Change-Id: I4a091b58deb855c7a7f1489a9506db2f821503b7
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81789
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12 18:04:04 +00:00
1ce416eda1 mb/dell/optiplex_9020: Fix SATA port maps
Previously incorrect sets of SATA ports were enabled.

There are no publically available schematics, but I am almost certain
the new values are correct.

The original 0x33 value was carlessly copy pasted, and only enables
ports 0, 1, 4, 5, leaving 2, 3 disabled.

On the SFF, with 0x33 only the first 2 ports worked. I have verified
by plugging in devices under the stock firmware that 0, 1, 2 are the
ones that should be enabled, so setting the value to 0x7 per datasheet.
This was also tested in practice to work.

I don't have an MT, but I was told the two white ports didn't work
with 0x33, so those are most certainly ports 3, 4, hence me setting
the value to 0xf. If the MT's working ports are port 0, 1 on the PCH
this is correct.

Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I32cb236b8f8140fba4a04c23161363d21741dcbc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81550
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-12 16:17:08 +00:00
4bbec0c691 tree: Drop duplicated <stdarg.h> and <stdio.h>
<string.h> is supposed to provide <stdarg.h> and <stdio.h>

Change-Id: I021ba535ba5ec683021c4dfc41ac18d9cebbcfd2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81853
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12 04:25:07 +00:00
dc3a6f8593 tree: Drop duplicated <device/pci_{def,type}.h>
<device/pci.h> is supposed to provide <device/pci_{def,type}.h>

Change-Id: Ia645b8dba8c688187a25916f508593f333821f88
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81831
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12 04:24:43 +00:00
9f1030feae tree: Drop duplicated <device/{path,resource}.h>
<device/device.h> is supposed to provide <device/{path,resource}.h>

Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-12 04:24:20 +00:00
97344731ae tree: Drop unused <cbmem.h>
Change-Id: If8be8dc26f2729f55dc6716e6d01e2b801d79e44
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-12 04:24:03 +00:00
ee78dca468 include/device/device.h: Drop duplicated <console/console.h>
Change-Id: Ib81c81843a5252e2ead9ce175cea2fa42f0e8152
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-12 04:23:32 +00:00
a24d002ac2 Makefile.mk: Account for large code model sections in cbfs_struct
Starting with version 18 LLVM puts code and data generated with
-ffunction-section -mcmodel=large inside sections with an 'l' prefix.
This would now also pick up const data in .rodata.

Change-Id: Ie07779ef548337772183ffe2d642f971d8cceae7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-04-12 03:04:06 +00:00
1a4c91aee0 mb/google/brya/var/sundance: Add GPIO table
Fill GPIO table for Sundance.

BUG=b:327520553
TEST=emerge-nissa coreboot

Change-Id: I53ed5874347006985ca5231d1531fa519088f796
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81613
Tested-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-04-12 02:20:36 +00:00
4b5d4acaec tree: Drop unused <timestamp.h>
Change-Id: Ic690a7543f8a1e072650917d7a1e9e3b9dc371a3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-04-11 19:26:12 +00:00
abb89e44be tree: Drop unused <timer.h>
Change-Id: Ib454330c5f584760c47ff0127a720cec5773b922
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-04-11 19:25:49 +00:00
45fa54efdd tree: Drop unused <edid.h>
Change-Id: I66265727b68b6ad10722439314b466298dbfff28
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81821
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-11 19:25:27 +00:00
e9931c8799 tree: Drop unused <halt.h>
Change-Id: Icd00f30a96c53f70babdcb8a77c4b6c2868619d8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-11 19:25:06 +00:00
fd9f697e51 tree: Drop unused <stdlib.h>
Change-Id: Ie7e36cfa5a09d94bb58f12f9bd262255a630424c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81819
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-11 19:24:44 +00:00
31402178c5 tree: Remove blank lines before '}' and after '{'
Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-11 19:19:08 +00:00
1dc8f0272b soc/intel/alderlake: Support missing CLKREQ workaround on RaptorLake FSP
IoT variants of the RaptorLake FSP support the `PchPciePowerGating` and
`PchPcieClockGating` UPDs, so, remove the preprocessor check that only
enabled it for AlderLake FSPs.

Change-Id: I583a4b257b72f992fdb6390d00e187d04a749177
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81803
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-11 19:11:54 +00:00
09a0dc650d drivers/acpi/thermal_zone: Correct Kelvin constant used for conversion
As 0C is 273.15K you could argue that 2731 and 2732 are both correct.
However, 2732 is deemed as correct both throughout the codebase and in
the ACPI specification[1].

[1]: https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/11_Thermal_Management/thermal-control.html#temperature-change-notifications

Change-Id: I845bc750681c7ae6f2d1342b32983b990ce6d296
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81197
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2024-04-11 19:08:10 +00:00
4c333a6b46 soc/intel/**/fast_spi.c: Reorganize some statements
Avoid calling `acpi_device_scope()` and `fast_spi_acpi_hid()` if the
result won't be used. Also, reorder a condition so that compile-time
constants appear first, so as to help the compiler optimize it out.

Change-Id: I42ce55c2978ad9c593c359c5decd5842fb3a97a1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-04-11 18:17:33 +00:00
5eecafe89e mb/google/nissa/var/craaskov: Disable external fivr
In next phase, craaskov will remove external fivr. Use the board
version to config external fivr for backward compatibility and
show message.

BUG=b:330253778
TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS
work normally.

Change-Id: I9280a86bf78caa10b527a6569ac580dfe1d66f60
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81607
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-11 12:16:39 +00:00
2abfbb4b87 mb/google/karis: Add FW_CONFIG and device for VPU
BUG=b:333605309
TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0)
is enabled when bit20 is set, and disabled when cleared.

Change-Id: I6e2230715d783ea7108d71699fd19684ce19e2ff
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-04-11 12:16:03 +00:00
60d5f8f8f0 mb/google/brya: Create trulo variant
This patch adds a new variant trulo for the baseboard trulo.

BUG=b:333314089
TEST=abuild -a -x -p none -t google/brya

Change-Id: I91157d252ef56c8938bfc08ed0f734c5dc7e614d
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81627
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-04-11 11:55:48 +00:00
0368e43e62 mb/google/brya: Add new baseboard trulo
This patch adds a new baseboard trulo. This commit is a stub which
only adds the minimum code needed for a successful build.

BUG=b:333314089
TEST=abuild -a -x -p none -t google/brya

Change-Id: Iad6230064c6b8359698d37c3e0440614cc7b073d
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-11 11:55:41 +00:00
327a0a7baf tree: Drop unused <string.h>
Change-Id: I0e216cbc4acf9571c65c345a1764e74485f89438
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81818
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-11 11:13:18 +00:00
2f9a579048 soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0
MAINBOARD_USES_FSP2_0 selects PLATFORM_USES_FSP2_0 and
POSTCAR_STAGE which are used by all Xeon-SP platforms.

After the removal of MAINBOARD_USES_FSP2_0, PLATFORM_USES_FSP2_0
is implicitly selected by SoC Kconfigs in PLATFORM_USES_FSP2_X,
POSTCAR_STAGE is selected by XEON_SP_COMMON_BASE.

TEST=Build and boot on intel/archercity CRB

Change-Id: I45332d49dd21f9749fce458877777a4b783a1b11
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81783
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-10 10:52:34 +00:00
e2dd36c6bc configs: enable TPM PPI for asrock_b85m_pro4.tpm2_txt_placeholder_acms
This is a good board for compiling TPM PPI sources for the following
reasons (based on `config TPM_PPI` definition):
 - uses TPM
 - the board is not related to ChromeOS
 - ACPI tables are enabled
 - it doesn't use EDK2 payload

At the moment drivers/tpm/ppi.c seems to not be compiled by CI at all,
see CB:69161 and CB:81590.

`CONFIG_TPM_PPI` is off by default but at least several configurations
under `configs/` (Protectli, MSI) should exercise the file because they
use EDK2 payload which changes default value.  This is however negated
by abuild disabling all payloads and thus effectively preventing
`CONFIG_TPM_PPI` from being set.  This board not using EDK2 also ensures
that `CONFIG_TPM_PPI=y` will not disappear after some future
`make savedefconfig`.

Change-Id: I316747a79b3142e9d6188c5986b344c7751d92d7
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81800
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-10 07:24:16 +00:00
e6940c0733 lib/thread.c: Move 'asmlinkage' before type 'void'
Change-Id: Ibd35bef4182ea075ef5fa153e2e47678ffce171b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-10 06:05:55 +00:00
bd5fe989bd tree: Drop unused <elog.h>
Change-Id: I40e2e5a786499abbe2fce63d6e0f1ac1e780ab51
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-10 05:59:00 +00:00
12acf3d1c6 tree: Drop unused <stdio.h>
Change-Id: I26c2abfce3417ed096d945745770fcae91a1e4ad
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81814
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-10 05:58:21 +00:00
68def206f3 mb/google/corsola/var/wugtrio: Correct the display orientation
Set orientation of KD_KD101NE3_40TI to LB_FB_ORIENTATION_RIGHT_UP to
align the volume up/down direction with menu up/down in FW screen.

BUG=b:331870701
TEST=emerge-staryu coreboot chromeos-bootimage, and check FW screen on
     wugtrio, test volume key behaves as expected.
BRANCH=corsola

Change-Id: Ie101cc8b983d3d16587f88fa787ed622e59d27eb
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81752
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-10 04:58:57 +00:00
50b61d39db mb/google/brya: Remove baseboard-specific FMD names
This patch renames the 16MB FMD file to remove the baseboard-specific
name 'Nissa'. This allows other supported baseboards to utilize the
16MB SPI flash. Additionally, the patch attempts to create a generic,
unified 32MB FMD file for both brya and nissa variants.

BUG=b:333314089
TEST=Build and boot Nivviks.

Change-Id: I9151a4bcbe9cc084cc19b1a3e91c0321fe4dcc37
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81676
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-10 03:29:31 +00:00
16131f3625 tree: Drop unused <post.h>
Change-Id: Ic7f6690786661e523292f7382df71ae4ad04d593
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-04-09 22:29:33 +00:00
f3c36d1ac2 soc/intel/alderlake: Fix non-local header treated as local
Change-Id: I93e6989633b9ac1b2738b812e3f8b442ecfdcbf0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09 22:24:19 +00:00
520dae19ea tree: Drop unused <delay.h>
Change-Id: I265e427254ce9f735e65b0631c43f98bc778a34f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81812
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-09 22:23:16 +00:00
54c9bf8e12 tree: Drop unused <console/console.h>
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09 22:22:44 +00:00
f40f3907d5 mb/google/*: Drop unused header file console/console.h
The header file console/console.h is unused, just drop it.

TEST=abuild -t google/corsola -b wugtrio -a
TEST=abuild -t google/geralt -b ciri -a

Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: If3689afe532b63384b7905116c44c598e5fa13ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81685
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2024-04-09 22:22:04 +00:00
e43f387022 soc/intel/xeon_sp: Add iio_ioapic.c
Move the soc_get_ioapic_info for platforms with IIO IO-APICs to
a separate file from src/soc/intel/xeon_sp/acpi.c.

TEST=Build intel/archerticy CRB

Change-Id: I59022b7685539491604724ef3b550da1cfd53f13
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-04-09 12:33:25 +00:00
9d6333c839 soc/samsung: Move 'inline' between storage class and type
Change-Id: Iccdb4770890751b7f9d1b35248fe57993342fd50
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-09 09:20:59 +00:00
ff40cf438e drivers/gfx: Remove unnecessary line continuations
Change-Id: Ic71516ae73d61c9f13876a5acc071645bbe8e866
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81594
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09 09:20:43 +00:00
04b89c5a37 soc/mediatek/common/include/soc: Include header file for check_member
To fix the build error below when include i2c_common.h, we should
include the necessary header for check_member.

"""
src/soc/mediatek/common/include/soc/i2c_common.h:24:42: error: expected ')' before numeric constant
   24 | check_member(mt_i2c_dma_regs, dma_tx_len, 0x24);
      |                                          ^~~~~
      |                                          )
"""

TEST=abuild -t google/geralt -b ciri -a

Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I266571686e452e2b7514afee42ff0a48f8891831
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81684
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09 09:20:20 +00:00
9e6b9992ff drivers/mipi: Fine tune clock for BOE_NV110WUM_L60
Fine tune the panel clock to prevent mipi noise from affecting wifi
band. After tuning, the panel refresh rate keeps at 60Hz and wifi test
passed. Just keep consistent with the Linux kernel panel driver
panel-boe-tv101wum-nl6 [1] configuration.

[1] https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/5029075/59

BUG=b:330807136
TEST=fw screen display normally

Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: Ic44c86f062d4e836f403ee97f2fc6370fff02797
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-09 09:19:56 +00:00
f867c9c547 mb/google/brox: Update verb table to fix headset detection
Correct verbtable value for pin widget 20 of Realtek ALC256 based on the
updated verbtable received from Realtek. Updated Version : 5.0.3.1. This
fixes the headset detection failure, when power_save is enabled in
legacy hda driver.

BUG=b:330433089
BRANCH=None
TEST=Verified headset on Brox
When connected to audiojack in power_save state of legacy hda driver,
headset is detected and audio is resumed.

Change-Id: I71b7d59b3ab5310a0b6cdb31fb5033f94263d151
Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81654
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Terry Cheong <htcheong@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2024-04-08 20:43:27 +00:00
a9497e11e7 mb/google/brya: Sort Kconfig option alphabetically
Change-Id: I878c14058e1edc0f64e37c2fc16b8dcf75b90192
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81631
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-04-08 05:31:12 +00:00
8406fb4e27 lib/program.ld: Account for large code model sections
Starting with version 18 LLVM puts code and data generated with
-ffunction-section -mcmodel=large inside sections with an 'l' prefix.

Change-Id: Ib755673dfa9e71172bbef0a5aec075154c89a97b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81675
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-08 00:02:18 +00:00
e27a26bdef nb/intel/sandybridge/raminit: Update PM_DLL_CONFIG to match MRC.bin
A register dump between native and MRC.bin raminit showed a difference
in the PM_DLL_CONFIG register. Use the same value as MRC.bin uses.

Tested on Lenovo X220: Still boots and works fine.

Change-Id: Iaf6334814c5748e5a3691a572213f433c79f382d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79759
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-07 12:04:03 +00:00
8f14e8e6b2 soc/amd/genoa_poc: Allow using UART with DEBUG_SMI=y
When DEBUG_SMI is selected, common code may use these helpers to handle
addressing and initialising the SoC-specific UART. Therefore, add uart.c
to be compiled into SMM.

Change-Id: If7c6f2346d5f9ffb371d51d1de6f0b695acedf10
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81072
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-07 11:36:25 +00:00
9b9a2c909e MAINTAINERS: take Genoa/Onyx rename into account
When soc/amd/genoa was renamed to soc/amd/genoa_poc and mb/amd/onyx
was renamed to mb/amd/onyx_poc, the MAINTAINERS file wasn't updated, so
no reviewers were added automatically to patches on Gerrit that change
things in soc/amd/genoa_poc or mb/amd/onyx_poc. Fix this by updating the
folder names in the MAINTAINERS file too.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib52781ebc98bd2ce9df495526cfaf9d884aace50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81679
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-07 11:36:13 +00:00
d5744ba90a MAINTAINERS: sort INTEL SoC alphabetically
Place METEORLAKE SoC in alphabetical order.

Change-Id: Ic04163e746ee3e450e58563abbf994e6aa44e69d
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81677
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-04-06 09:03:18 +00:00
afe84274ee drivers/intel/fsp2_0: Enhance portability with uintptr_t/size_t
Replace fixed-width integers for pointers and sizes with uintptr_t and
size_t, promoting portability across 32-bit and 64-bit architectures.

For FSP-API specific UPD assignments, rely on `efi_uintn_t` rather
fixed size datatype uint32_t/uint64_t.

BUG=b:242829490
TEST=Firmware splash screen visible on google/rex0 w/ both 32-bit and
64-bit compilation.

Change-Id: Iab5c612e0640441a2a10e77949416de2afdb8985
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81615
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-04-06 04:32:01 +00:00
9c4d85d83a lib: Refactor bmp_load_logo() implementation
This refactoring ensures bmp_load_logo() takes logo_size as an
argument, returning a valid logo_ptr only if logo_size is non-zero.

This prevents potential errors from mismatched size assumption.

BUG=b:242829490
TEST=google/rex0 builds successfully.

Change-Id: I14bc54670a67980ec93bc366b274832d1f959e50
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81618
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-04-06 04:31:50 +00:00
49437a6945 soc/intel/xeon_sp: Share unlock_pam_regions()
unlock_pam_regions() is needed for SKX and CPX. Put the codes into
chip_gen1.c so that it could be shared among SoC generations.

After shared, unlock_pam_regions() is still called from SKX and
CPX SoC specific codes. SPR will also use chip_gen1.c, but it will
not call unlock_pam_regions().

TEST=Build and boot on intel/archercity CRB

Change-Id: Idbc7dc6dd22a1747a65543666fc714a0872e6b37
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-04-05 10:07:21 +00:00
d57d5e3b37 smmstorev2: Load the communication buffer at SMM setup
This removes the runtime SMI call to set up the communication buffer
for SMMSTORE in favor of setting this buffer up during the installation
of the smihandler.

The reason is that it's less code in the handler and a time costly SMI
is also avoided in ramstage.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I94dce77711f37f87033530f5ae48cb850a39341b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-05 07:10:17 +00:00
c72a65dccd soc/intel/common/block/fast_spi: probe for 2nd flash component
Fast SPI code assumes only one SPI flash is present. The SPI flash
driver for older southbridges is able to detect multichip. See the
spi_is_multichip() in src/southbridge/intel/common/spi.c.

Some boards (e.g. Lenovo ThinkCentre M920 Tiny) still come with two
chips populated instead of one. With this change, both chips are probed,
and the correct total size is calculated. Otherwise, only the first one
was probed, which resulted in an error such as:

SF size 0x1000000 does not correspond to CONFIG_ROM_SIZE 0x1800000!!

Change-Id: I8d7449f9e1470dc234fe5ba5217d3ce4c142b49c
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-04 21:06:26 +00:00
7225656716 tree: Remove duplicated <stdint.h>
<types.h> is supposed to provide <stdint.h>.

Change-Id: Ia68a0dc8fba4a48401e213ebb8356e32f0a019ab
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-04-04 20:22:49 +00:00
c45d5c8c6b util/intelp2m: Add support for TigerLake-H SoC
Add support for TigerLake Halo SoC, based on CNL profile.

Test: Convert GPIO dump from inteltool into coreboot macros for
out-of-tree TGL board.

Change-Id: I26eff225c2045edfe5836283be7b4c63f6b405e8
Signed-off-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
2024-04-04 20:21:08 +00:00
ce88ae5176 arch/x86/bootblock.ld: Account for the .data section
commit b7832de026 (x86: Add .data section support for pre-memory stages)
added a data section to the bootblock. This needs to be accounted for in
the linker script.

Change-Id: I39abe499e5e9edbdacb1697c0a0fc347af3ef9c4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81434
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-04 15:11:34 +00:00
31b505b0f7 mb/google/screebo: Add FW_CONFIG and device for VPU
BUG=b:332488817
TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0)
is enabled when bit20 is set, and disabled when cleared

Change-Id: I6d7b35dbf8ac9b0abb42f64a947b4bb94f3c6b0f
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Daniel Kang <daniel.h.kang@intel.com>
2024-04-04 14:22:31 +00:00
579b8ae59f soc/intel/cache_as_ram_fsp.S: Drop unused preprocessing directives
Change-Id: I42bb15b8534d16401cd06ff803a8425221c5f3c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-04 12:34:18 +00:00
9099a6bb4d drivers/intel/fsp2_0: Support FSP-T in long mode
Call into FSP-T using the protected mode wrapper
and enter long mode in FSP-T support assembly code.

TEST: Booted on ibm/sbp1 in long mode.

Change-Id: Id6b9780b06b4bfbb952e32091ffbf3d0014f2090
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-04 12:32:59 +00:00
e79d97bc3b mb/google/nissa/variant/sundance: Update devicetree settings
Based on schematic and gpio table of sundance, generate overridetree.cb
settings for sundance.

BUG=b:328505938
TEST=FW_NAME=sundance emerge-nissa coreboot chromeos-bootimage

Change-Id: I857be7bc7f98281cac57fef85bf9f3cef2ec14e9
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-04 12:29:41 +00:00
7d4f7fb6a8 mb/google/nissa/var/gothrax: Add touchscreen driver for ILI2901A-A210
I2C slave addresses 0x41.

BUG=b:332458912
BRANCH=None
TEST=emerge-nissa coreboot & working correctly in DUT

Change-Id: I2d26bfd4f415aa128b6256f83bc58987b15a557a
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81610
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-04 12:29:15 +00:00
d3d62d4af9 Makefile.mk: Also add -libs to bootblock when !SEPARATE_ROMSTAGE
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I18bf67cae7af90a92a030e552af6dc6b134a8357
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-04-04 10:41:39 +00:00
37a2fb5353 soc/intel/xeon_sp: Use default soc_get_ioapic_info
intel/common/block/acpi provides default soc_get_ioapic_info for
single IOAPIC model. Use the default soc_get_ioapic_info when
XEON_SP_HAVE_IIO_IOAPIC is not set. This model fits for SPR and
later.

TEST=Build and boot on intel/archercity CRB

Change-Id: I1ecfba49cd9b4dfbb3f11d58d04d07ea1752a131
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-04-04 09:01:42 +00:00
698fa27e82 commonlib: Simplify FSP header inclusion
Include `fsp_header.h` from vendorcode for dynamic FSP_INFO_HEADER
selection.

BUG=b:242829490
TEST=google/rex0 builds successfully with 64-bit FSP.

Change-Id: If165e0517752f320d898cf82f298aa9f5699ae86
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81624
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-04 06:29:40 +00:00
a6dfbeedff vc/intel/fsp: Refactor FSP header inclusion for EDK2 compatibility
This change refactors EDK2 essential header management within the FSP
directory to ensure compatibility.

Header selection is now dynamically based on:

* FSP specification version: Distinguishes between 1.1 and 2.x
* EDK2 revision (for FSP 2.x): Chooses the appropriate FSP info header

FSP Header
|
|-> FSP 1.1 specification FSP_INFO_HEADER
|-> FSP 2.0 specification EDK2 release
    |-> EDK2_2017 FSP_INFO_HEADER
    |-> EDK2_2020 FSP_INFO_HEADER
    |-> EDK2_2021 FSP_INFO_HEADER
    |-> EDK2_2023 FSP_INFO_HEADER

Any .C/.H file requires to include FSP_INFO_HEADER can now just add the
FSP header alone.

BUG=b:242829490
TEST=Able to build google/rex0 with 64-bit FSP.

Change-Id: I29e5002821843c9cffbc8f6317d1062175f014ff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81623
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-04 06:29:20 +00:00
dc781d3a83 vc/intel/edk2: Define FSP_SIG macro for FSP 2.x compatibility
This patch introduces the FSP_SIG macro into EDK2 headers to ensure
compilation compatibility when using FSP 2.x specifications.

Previously, the macro was only defined for FSP 1.1.

BUG=b:242829490
TEST=Successful build of google/rex0 with 64-bit FSP.

Change-Id: I4f97fc303ca2881ccd17b4d149d01c3b671dbbde
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-04-04 06:28:38 +00:00
20dd04872f drivers/intel: Align FSP debug handler with EFI calling convention
Ensures the FSP debug handler adheres to the EFI calling convention,
enabling seamless integration with coreboot infrastructure.

This is critical for 64-bit coreboot and FSP communications.

BUG=b:242829490
TEST=FSP debug logs successfully captured via coreboot event handler.

Change-Id: I9085a6c7d50e58fb56cbbc61da3a0af094d0dc05
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-04-04 06:28:18 +00:00
6daf0b3fda include/efi: Introduce __efiapi for EFI calling convention flexibility
This patch defines __efiapi (based on EFIAPI) for coreboot-compliant
EFI calls. This lays the groundwork for future 64-bit EFI calling
convention support within coreboot/FSP.

BUG=b:242829490
TEST=FSP debug log accessible via coreboot event handler.

Change-Id: I21660f8ebeed3b9ef060118928a940a470492bb8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81620
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-04 06:22:26 +00:00
5462e8e943 mb/google/brya/var/xol: Reduce power limits according to battery status
When battery level is below critical level or battery is not present,
cpus need to run with a power optimized configuration to avoid platform
instabilities such as system power down.

This will check the current battery status and configure cpu power
limits using current PD power value.

BUG=b:328729536
BRANCH=brya
TEST=built and verified MSR PL2/PL4 values.
     Intel doc #614179 introduces how to check current PL values.

[Original MSR PL1/PL2/PL4 register values for xol]
cd /sys/class/powercap/intel-rapl/intel-rapl\:0/
grep . *power_limit*
  constraint_0_power_limit_uw:15000000 <= MSR PL1 (15W)
  constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W)
  constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W)

[When connected 60W adapter without battery]
Before:
  constraint_0_power_limit_uw:15000000
  constraint_1_power_limit_uw:55000000
  constraint_2_power_limit_uw:114000000
After:
  constraint_0_power_limit_uw:15000000
  constraint_1_power_limit_uw:55000000
  constraint_2_power_limit_uw:60000000

[When connected 45W adapter without battery]
Before:
  constraint_0_power_limit_uw:15000000
  constraint_1_power_limit_uw:55000000
  constraint_2_power_limit_uw:114000000
After:
  constraint_0_power_limit_uw:15000000
  constraint_1_power_limit_uw:45000000
  constraint_2_power_limit_uw:45000000

Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81614
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-04-04 06:13:14 +00:00
86b145ad3e mb/google/nissa/var/anraggar: Set EN_SPK_PA to low to avoid noise
In order to avoid the noise caused by the codec output to the audio
jack during the shutdown and poweron process, we will use GPP_A11 for
the codec power supply gate, keep low during the startup process, and
wait for the driver to turn on. This change does not affect the beep
output of depthcharge.

BUG=None
TEST=There is no squeaking sound when turning on and off

Change-Id: I5982be5a8d965086b46861f4c2c758d9bdee6e75
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81629
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-04-04 03:26:19 +00:00
ede452fb99 vendorcode/amd/opensil: Add CPP args to all stages
It does not hurt to do this and makes it possible to link romstage
sources into bootblock.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic7edfdac43c2d71ee3dcbd9d8f59c9799595e7f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79576
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-03 12:47:45 +00:00
fff762ebb2 mb/{bd/bd_egs, iventec/transformers}: Fix building with x86_64
This fixes a warning about casting an integer to a pointer, where the
integer has a different size than the pointer (UINT32).

Change-Id: Iceb7cb1dbdc6f5397823a1737e3baeac96966a78
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81559
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-03 12:47:04 +00:00
d837736a05 drivers/mipi: Fine tune clock for IVO_T109NW41
Fine tune the panel clock to prevent mipi noise from affecting wifi
band. After tuning, the panel refresh rate keeps at 60Hz and wifi test
passed. Just keep consistent with the Linux kernel panel driver
panel-boe-tv101wum-nl6 configuration.

BUG=b:330807136
TEST=fw screen display normally

Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I128b33fbcda9759330a363ebb6cf66415405c488
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81625
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-03 12:46:35 +00:00
7761237dfe util/kconfig: Uprev to Linux 6.8's kconfig
Linux kconfig has its own implementation of KCONFIG_WERROR now, so use
that. This reduces our patch count by 2.

Change-Id: I4f5f1f552e96f8ef7a4c5c0ab2ab7e2b6d798ceb
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81223
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-03 12:28:04 +00:00
96499840aa cpu/x86/topology: Add node ID parser
Currently the SRAT table only exposes one proximity group as
it uses the LAPIC node_id, which is always initialized to 0.

Use CPUID leaf 0x1f or 0xb to gather the node ID and fill it
to make sure that at least one proximity group for every socket
is advertised.

For now the SNC config isn't taken into account.

Change-Id: Ia3ed1e5923aa18ca7619b32cde491fdb4da0fa0d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-04-03 07:35:15 +00:00
9ab5ae7643 mb/google/corsola: Add new board variant Wugtrio
Add a new Staryu follower device 'Wugtrio'. And also enables SD card
support and MIPI panel support.

BUG=b:331870701
TEST=emerge-staryu coreboot chromeos-bootimage
BRANCH=corsola

Change-Id: I586de68da4d0ee2dd5b7baea92ebb06db9fcfe8b
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81585
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-03 06:45:25 +00:00
d0e3ffaacc mb/google/corsola: Move MIPI panel selection to BOARD_SPECIFIC_OPTIONS section
Move starmie mipi panel selection from BOARD_GOOGLE_STARYU_COMMON
section to BOARD_SPECIFIC_OPTIONS section.

BUG=None
TEST=emerge-staryu coreboot chromeos-bootimage
BRANCH=corsola

Change-Id: Ib5792542f55a78c0840b6169b5ecf092e7cefe98
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81602
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-04-03 06:44:51 +00:00
05a7474b74 drivers/intel/fsp2_0: Use coreboot uint8_t type for consistency
This patch replaces UINT8 with uint8_t to align with coreboot's
standard data type conventions.

This promotes consistency within the codebase.

BUG=b:242829490
TEST=Verified firmware splash screen functionality on google/rex0.

Change-Id: I524bf6dc83e4330f155e21691f6b161643f29bd8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81571
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-04-03 04:06:31 +00:00
bb07750b77 util/kconfig: Put our SPDX fix in the patch queue
With this, `quilt pop -a` leads to an original Linux kconfig tree,
making it easier to apply kconfig updates.

Change-Id: I771bbd0f8244cae38317bd5b1f809b74771b176f
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-02 12:40:41 +00:00
4dcf4af010 mb/google/brox: Enable PMC pins to work with PD
Enable SMLINK1 interface for PMC-PD communication to configure Type-C
muxes.

Refer RPL EDS vol 1: 765585.

BUG=b:327622474
BRANCH=None
TEST=Boot image on SKU2 and check PMC-PD working.

Change-Id: Ia678d291e7a14aefe09026e70478fea3f68c8e10
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81207
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Deepti Deshatty <deepti.deshatty@intel.com>
2024-04-02 12:39:39 +00:00
e644fa5b7c mb/google/brya: Make get_soc_power_limit_config() a public function
Make get_soc_power_limit_config() a public function to use on brya
variants. Add prefix 'variant_' for it.

BUG=None
BRANCH=brya
TEST=emerge-brya coreboot

Change-Id: I31f938938e7c9da49c2aa7b52dd4b5f46f793495
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81616
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-02 12:39:14 +00:00
82d080e850 mb/google/nissa/var/sundance: Generate SPD ID for 4 supported memory parts
Add sundance supported memory parts in mem_parts_used.txt, generate
SPD id for this part.

1. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT
2. Hynix   H58G56AK6BX069, H9JCNNNBK3MLYR-N6EE

BUG=b:332201349
TEST=Use part_id_gen to generate related settings

Change-Id: Ieece88b0b2b2ea5f0d6192ee8441e50d3f22a972
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81612
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-04-02 12:38:49 +00:00
42cb9f3de0 mb/google/rex/var/deku: Swap LAN device indices for correct MAC address
Deku has two Ethernet ports. Currently both get assigned the wrong
MAC address due to the LAN devices indices being swapped and
vpd ethernet_mac0() affects device eth1 and vpd ethernet_mac1() affects
device eth0.

Correct the device indices for LAN devices so ethernet_mac[0-1] in vpd
can apply to the correct ethernet ports.

BUG=b:320203629
BRANCH=firmware-rex-15709.B
TEST=vpd -s ethernet_mac0=<mac address0>
     vpd -s ethernet_mac1=<mac address1>
     reboot the system and check ifconfig
     eth0 and eth1 MAC addresses are fetched correctly

Change-Id: Id1508104cbb5cf0a234f34f9db19cc535fdb634b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81564
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
2024-04-02 09:30:10 +00:00
45348cdf39 include/device/pci_ids.h: Add DIDs for MTL Touch controller
When touch controller is configured as THC-SPI mode, DID is 0x7e49 for
THC0, and 0x7e4b for THC1.

0x7e48 and 0x7ea4 are the DIDs when ThcMode is 0 (default) for THC0
and THC1 respectively.

Refer MTL EDS vol 1: 640228.

BUG=b:307775082

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I1b98fdbd8d8588492bcafa0f3998818dc83ff1d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81330
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
2024-04-02 07:46:24 +00:00
5776aef0f3 drivers/mipi: Add support for KD_KD101NE3_40TI panel
Add K&D panel KD_KD101NE3_40TI serializable data to CBFS.
Datasheet: KD101NE3-40TI-A003 _Pre SPEC_20231218.pdf

BUG=b:331870701
TEST=build and check the CBFS include the panel
BRANCH=None

Change-Id: Ibed67d2f3321fef332ab1e80f06225e27d205f71
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81583
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-02 06:12:43 +00:00
778f7c8055 Makefile.mk: make the overlapped error message more informative
Currently, if something is overlapped, you get this:
ERROR: Ramstage region _ramstage overlapped by: fallback/payload fallback/opensbi

This change prints out the start and end of the sections.

Change-Id: Ica8c05b63ed9bbd28e2d3daa4dc7c2f9d8da3f55
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81544
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-04-01 15:00:22 +00:00
c5e467e50c Kconfig: Make GBD_STUB and long mode mutually exclusive
GDB debugging is not implemented with x86 long mode.

Change-Id: Icaf7d0763829d5badf73d38bb8fc3d36cfe18964
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81379
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-01 13:40:37 +00:00
42fa6247f4 soc/intel/xeon_sp: Remove PAM unlock operations
unlock_pam_regions routes Programmable Attribute Map (PAM) access
to DRAM. In SPR, PAM routing to DRAM is covered by FSP. Move the
step to SoC specific codes.

TEST=intel/archercity CRB

Change-Id: I3fd1d806807449e6a4d9d4d2c8a47ce61ed53018
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-01 08:09:26 +00:00
f4a12e1d39 acpi: Add acpigen_write_OSC_pci_domain
Add dynamic PCI domain _OSC ASL generation codes, supporting both
PCIe and CXL domains.

Dynamic SSDT generation is used to generate a list of ASL device
objects based on FSP outputs (e.g. the SoC/SKU configurations)
and _OSC is a method inside these objects (hence it would be
straightforward to be generated altogether, plus some C codes
managed boot configs could be referenced as well).

This usage is optional. It is helpful for cases where the same
code set supports multiple SKUs/SoCs (difficult to be handled by
one set of static SSDT), and the CPU performance is good enough
to run SSDT generation logics with minimal costs.

TEST=intel/archercity CRB

Tested with https://review.coreboot.org/c/coreboot/+/81377.

Change-Id: I711ce5350d718e47feb2912555108801ad7f918d
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-01 08:06:46 +00:00
96d7524ee6 intel/common/pch: Add Kconfig SOC_INTEL_COMMON_IBL_BASE
IBL (Integrated Boot Logic) provides a subset of server
PCH logics for no-PCH solution. IBL is with limited features
and registers exposed, PCIe root ports/USB/SATA/LAN support are
removed.

Change-Id: I8f3d64a2dd3b79ec5a9e4306f40b012b00387259
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81314
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-01 08:04:34 +00:00
f2daf2480b soc/intel/xeon_sp: Redefine data types for GNR
Granite Rapids (6th Gen Xeon-SP) FSP introduces UDS_STACK_RES/
UDS_SOCKET_RES and retires the usages of STACK_RES/
IIO_RESOURCE_INSTANCE. Make redinitions to make Xeon-SP common
codes to work for both 6th Gen before and later.

Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81040
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-01 08:03:45 +00:00
2cb83125bb mb/google/{brya,hades}: use soc index for variant_update_power_limits()
The power_limits_config variable for ADL/RPL is array data, but we got
soc_power_limits_config variable without its index. So correct the
code to get the proper pointer of the data for current CPU SKU.

I tried to override the PL4 value to 80W from 114W with following
table in ramstage.c as a test for bug b/328729536.
```
const struct cpu_power_limits limits[] = {
    {PCI_DID_INTEL_RPL_P_ID3, 15, 6000, 15000, 55000, 55000, 80000},
}
```

And then verified the msr_pl4 value on ChromeOS using Intel PTAT tool.
- Before this patch: msr_pl4 was not changed, it's always 114
- After this patch: msr_pl4 was changed to 80

BUG=None
BRANCH=None
TEST=Built and tested the function could adjust PL4 on xol in local.

Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-01 04:53:11 +00:00
f3b2c6e5dd mb/google/brya/var/xol: Update GPIO settings for speaker and DMIC
Update GPIO configuration according to the schematic changes. The
locations of speaker and DMIC are swapped.
- Speaker: I2S2 -> I2S1
- DMIC: GPP_S2/GPP_S3 -> GPP_R4/GPP_R5

BUG=b:318584606
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage

Change-Id: I3468d79f33d9d9ef8377ccf0f8f628956b02d3c3
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81444
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-04-01 04:48:27 +00:00
4f085915fb mb/google/brox: Configure ISH device based on FW_CONFIG
ISH Firmware name needs to be configured only when full sensing
capabilities are enabled through ISH_ENABLE FW_CONFIG. Similarly DMA
property needs to be added only when UFS is enabled through STORAGE_UFS
FW_CONFIG. Hence configure the ISH device at run-time based on
FW_CONFIG.

BUG=b:319164720
TEST=Build Brox BIOS image and boot to OS.

Change-Id: I678416acd48e03ab77ae299beae6e295a688b8df
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81418
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-01 04:23:49 +00:00
6943b6c8e6 mb/google/nissa/var/glassway: Add 2nd Synaptics touchpad
Add Synaptics touchpad via HID-I2C interface in I2C5 bus for glassway.

BUG=b:331677400
BRANCH=firmware-nissa-15217.B
TEST=emerge-brya coreboot and check touchpad function work.
[INFO ]   input: PNP0C50:00 06CB:CE9B Touchpad as /devices/pci0000:00/0000:00:19.1/i2c_designware.5/i2c-17/i2c-PNP0C50:00/0018:06CB:CE9B.0001/input/input4
[INFO ]   hid-multitouch 0018:06CB:CE9B.0001: input,hidraw0: I2C HID v1.00 Device [PNP0C50:00 06CB:CE9B] on i2c-PNP0C50:00

Change-Id: Ifbb2cb750a80bc6e8f96609257dcd1e695ad1fa4
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-04-01 04:19:16 +00:00
f2492c383c mb/google/nissa: Create sundance variant
Create the sundance variant of nissa reference board by copying the
template files to a new directory named for the variant.

Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.

BUG=b:328505938
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_SUNDANCE

Change-Id: Ia8ba318f18d2cac69898687311631778e61bf2ea
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81347
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2024-04-01 04:18:28 +00:00
8e79a1a298 arch/ppc64: Add arch as supported by the clang compiler
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I1aacff869663e1db74cd485787d7103b9ec5602e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78448
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-04-01 04:16:53 +00:00
a010b7f614 arch/ppc64: Fix inline assembly for clang
Use macros from the Linux kernel 6.5 to make the inline assembly also
compile on clang.

TEST: See that the generated code is identical on GCC and compiles on
clang.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I516033c69e62dfdb38f83285c156d5527917ad55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-04-01 04:16:34 +00:00
347b1170fb mb/google/corsola: Add new board variant 'Kyogre'
Add a new Kingler follower device 'Kyogre'

BUG=b:318614302
TEST=emerge-corsola coreboot

Change-Id: Iae3857a9f8edadcc2eee3500fda2e76c0334221c
Signed-off-by: Kei Hiroyoshi <hiroyoshi.kei@fujitsu.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81218
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-01 04:12:40 +00:00
8ec17cf3e5 soc/intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL
The RPL FSP currently uses HECI commands to retrieve the chipset
initialization version because the MBP HOB creation is disabled
(SkipMbpHob=1). This has resulted in an approximate 150ms increase in
boot time. Investigations are ongoing to determine the cause of the
delay when using HECI commands. As an interim solution, this patch sets
SkipMbpHob=0, enabling the use of MBP HOB or acquiring the chipset
initialization version, which is expected to reduce the boot time.

BUG=b:328430167
TEST= Able to build,boot and collect boot time data of brya.

With this patch:
  963:returning from FspMultiPhaseSiInit     1,337,481 (249,046)

Without this patch:
  963:returning from FspMultiPhaseSiInit     1,496,268 (408,194)

Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Change-Id: I8a99a57b644732074e41051d99e63576f1edd229
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-04-01 04:12:03 +00:00
619535778c vc/intel/fsp/fsp2_0: Add GNR N-1 FSP headers
GNR N-1 FSP headers are a set of stub headers used to fulfill
build sanity check for GNR SoC and CRB codes before the formal
FSP headers are published. The N-1 headers are forward compatible
with the later formal headers.

Change-Id: I1c8125dd64e5a9619073c2f17aeade1d33607870
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-30 13:39:51 +00:00
ec58bebbd6 soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
GraniteRapids (6th Gen Xeon-SP) FSP contains changes in IIO stack
descriptors impacting the way of coreboot's creation of domains.
Separates the codes as preparation for 6th Gen and later platforms.

Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81312
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-30 13:38:18 +00:00
f7e456748f superio/ite: Add full-speed config option
Add Kconfig option for full-speed setting. Some variants do not support
the full-speed at limit configuration (IT8772F). Keep it enabled for all
current variants that use the common EC code as it was previously
enabled unconditionally - datasheets weren't revisited individually.

Change-Id: Icf24ea1c4f41771a18803957456f0aeba0e51b13
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81525
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30 13:00:01 +00:00
82ff48c1b1 superio/ite: Fix incorrect warnings
Fix warning for disabled thermal inputs.

Fix warning for PECI thermal inputs if one was set up previously.
Depending on the mb, the superio will not go through power-on reset and
retain its registers. Do not trigger a warning if the current register
value aligns with the desired value. Don't return early if some input is
already configured for PECI, simply overwrite the configuration.

Both warnings were observed while porting the "HP Pro 3500 Series" mb.

Change-Id: Ibabe1b1ef55f2acb2074eceb535ec684bffc8155
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-30 12:58:00 +00:00
cccada28f7 util/crossgcc: Also build LLVM LD
When doing LTO the clang linker frontend needs to use LLD or gold. Build
LLD as that is the configuration that is best tested.

Change-Id: I3242585f8b5c3426fc6568d3dc47300164d56e3a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-30 10:14:18 +00:00
97ed403650 util/xcompile: Use a more complete clang target
When the compiler is used as a linker frontend clang tries to match the
target string with what it supports internally. If it's not sufficiently
complete it will forward linking to GCC which is not desirable. This is
necessary when doing LTO with clang.

Change-Id: Ie9356a2bc0f5b77e934cc16482d6ccb1961195dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80730
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30 10:13:53 +00:00
e9e31eb4b9 drivers/tpm: Make it compile again
Fix regression introduced in 47e9e8cde1
"security/tpm: replace CONFIG(TPMx) checks with runtime check":

Replace BIOS_WARN with BIOS_WARNING.

Change-Id: Id23cda2f5403effd2a4bda3852f0f300d0e62cdf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81590
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30 08:33:22 +00:00
c0d3cf1052 soc/intel: Remove blank lines before '}' and after '{'
Change-Id: I79b93b0ca446411e2a1feb65d00045e3be85ee8a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-30 08:29:38 +00:00
57351dd872 commonlib: Remove blank lines before '}' and after '{'
Change-Id: I57686e68b4b1bdb28a15b69e55b71c98b0b53a1f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30 07:48:23 +00:00
d586545bf8 superio: Remove blank lines before and after code blocks
Change-Id: I0d2ff9828e83ef927036c561d11f95b54b858cda
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30 07:47:54 +00:00
5d57af9a36 mb/acer: Remove blank lines before '}' and after '{'
Change-Id: I335487ca1b17ab958c0d0238f425b92b430014ca
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30 07:47:30 +00:00
3e4afd1b49 mb/inventec: Remove blank lines before '}' and after '{'
Change-Id: I51dd9eb5a2fef5800670f981275139e932af2be0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81493
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30 07:47:04 +00:00
c55765d681 mb/google: Remove blank lines before '}' and after '{'
Change-Id: If68303cd59b287c8a5c982063b2ab75fd74898d6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-03-30 07:45:40 +00:00
4709d7c028 soc/cavium: Remove blank lines before '}' and after '{'
Change-Id: Id604dc981d6ca0a8163b7477b7916210faa56a77
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30 07:45:25 +00:00
ebbb15f084 mb/emulation: Remove blank lines before '}' and after '{'
Change-Id: I7071cbcc26e2080020e83b894cf4ac4ef46913c3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30 07:45:04 +00:00
45ff2decae mb/amd: Remove blank lines before '}' and after '{'
Change-Id: I2dae34441909f6135b95e7b017659ce4f4666b4e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30 07:44:29 +00:00
44772b29b0 soc/qualcomm: Remove blank lines before '}' and after '{'
Change-Id: If2c2138ed3dc437b924297330805caa8c357853d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81460
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30 07:44:06 +00:00
43225cbdfa soc/rockchip: Remove blank lines before '}' and after '{'
Change-Id: I140daa5b862ffd3a5b5468d7cb9dbdd81426855e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81459
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30 07:43:42 +00:00
54e97b8d6e soc/amd: Remove blank lines before '}' and after '{'
Change-Id: I0203e77dd23fa026cd252abbda50f1e9f6892721
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30 07:43:06 +00:00
58eddfc00c acpi: Remove blank lines before '}' and after '{'
Change-Id: I9ba061fe0b1396ccc1597e26685a6b4e312e3549
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30 07:42:12 +00:00
581c7ee208 arch/x86: Remove blank lines before '}' and after '{'
Change-Id: I1bb4a052a4e74850660944b687c21e817eb437b2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-03-30 07:41:32 +00:00
d293b20b84 cpu/x86/Kconfig: Mark 64bit support as stable
With SMM holding page tables itself, we can consider SMM support stable
and safe enough for general use.

Also update the respective documentation.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ifcf0a1a5097a2d7c064bb709ec0b09ebee13a47d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-28 15:23:21 +00:00
ee83be4d75 cpu/x86: Link page tables in stage if possible
When switching back and forth between 32 to 64 bit mode, for example to
call a 32-bits FSP or to call the payload, new page tables in the
respective stage will be linked.

The advantages of this approach are:
- No need to determine a good place for page tables in CBFS that does
  not overlap.
- Works with non memory mapped flash (however all coreboot targets
  currently do support this)
- If later stages can use their own page tables which fits better with
  the vboot RO/RW flow

A disadvantage is that it increases the stage size. This could be
improved upon by using 1G pages and generating the pages at runtime.

Note: qemu cannot have the page tables in the RO boot medium and needs
to relocate them at runtime. This is why keeping the existing code with
page tables in CBFS is done for now.

TEST: Booted to payload on google/vilbox and qemu/q35

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80337
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-28 15:22:34 +00:00
34684caad5 soc/amd/noncar: Increase bootblock size from 64K to 128K
When linking in page tables more place is needed. Size the bootblock is
top aligned, this has no impact the final size for existing setups.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I23f176d63d3c303b13331a77ad5ac6c7a19073d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-28 15:21:05 +00:00
41eaf2dba3 soc/amd/non_car/memlayout_x86.ld: Top align the code
This does the following:
- Top align the bootblock so that the only the memory needed gets used.
  This might slightly reduce the time the PSP needs to decompress the
  bootblock in memory
- Use a memory directive to assert that the 16bit code is inside the top
  64K segment
- Use the program counter less. While the BDF linker is happy about
  running the program counter backwards, LLD is not. There is no
  downside to this.
- Use a symbol rather that the program counter for sections. LLD gets
  confused when (.) is used along with '<': it places the section at the
  start of the memory region, rather than at the program counter. Using
  a variable name works around this.
- Use a 'last_byte' section to make sure the first instruction is at
  0xfff0. Both the BDF and the LLD linkers seems to work well with this
  code

TEST: Both BFD and LLD are able to link the bootblock

Change-Id: I18bdf262f9c358aa01795b11efcb863686edc79c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-28 15:20:43 +00:00
efc615e239 security/vboot: extract secdata_tpm{1,2}.c
Most of the original secdata_tpm.c was TPM2-specific implementation.

Just moving the code around, with trivial tweaks:
 - drop now unnecessary #ifdef directives from _factory_initialize_tpm()
 - drop leading underscore from _factory_initialize_tpm{1,2}() (external
   identifiers should not start with an underscore in C)
 - drop unused <security/vboot/tpm_common.h> include and sub-includes of
   tss.h which should be considered its part (so this isn't an indirect
   inclusion)
 - fixed formatting of RETURN_ON_FAILURE() which didn't have slashes
   aligned no matter what tab width was used

Change-Id: I0090b748d7d3b2d76a941b87b5885682fd81c4fc
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81415
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-28 15:20:11 +00:00
47e9e8cde1 security/tpm: replace CONFIG(TPMx) checks with runtime check
This prepares the code for enabling both CONFIG_TPM1 and CONFIG_TPM2
during compilation, in which case actual TPM family in use can be
determined at runtime.

In some places both compile-time and runtime checks are necessary.
Yet in places like probe functions runtime state checks don't make sense
as runtime state is defined by results of probing.

Change-Id: Id9cc25aad8d1d7bfad12b7a92059b1b3641bbfa9
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69161
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-28 15:18:04 +00:00
094a051732 security/tpm: resolve conflicts in TSS implementations
No functional changes.  Refactor code such that there won't be any
compiler or linker errors if TSS 1.2 and TSS 2.0 were both compiled
in.

One might want to support both TPM families for example if TPM is
pluggable, while currently one has to reflash firmware along with
switching TPM device.

Change-Id: Ia0ea5a917c46ada9fc3274f17240e12bca98db6a
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-03-28 15:16:19 +00:00
febf9b9f24 security/tpm: make tis_probe() return tpm_family
Via an out parameter. This is needed to be able to dynamically pick TSS
implementation based on the information discovered on probing.

Change-Id: I5006e0cdfef76ff79ce9e1cf280fcd5515ae01b0
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69159
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-28 15:12:32 +00:00
4b76273ac9 soc/mediatek: Remove blank lines before '}' and after '{'
Change-Id: I0ce2b61329efede1ba8a02446610e3eb635ceedc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81462
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-28 09:18:26 +00:00
e6893677c1 lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params
For dram_type 21 the switch case in use_ddr4_params function falls to
default. This adds SPD_DRAM_LPDDR5X dram_type case to switch case block
for dram_type 21 in the function.

With this patch below NOTE will not be observed in the log:
    [NOTE ]  Defaulting to using DDR4 params. Please add dram_type check for 21 to use_ddr4_params

BUG=None
BRANCH=None
TEST=Boot brox SKU1/SKU2 and verify logs for default case

Change-Id: Id78ef90c0dc2e869c1f0424674b982ba64ba3939
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
2024-03-28 07:26:45 +00:00
3ee97e47a6 arch/riscv: remove misaligned load/store/fetch handling
Testing on the unmatched shows the code no longer works completely
correctly; Linux has taken over the handling of misalignment
anyway, because handling it in firmware, with the growing
complexity of the ISA and the awkward way in which it
has to be handled, is more trouble than its worth.

Plus, we don't WANT misalignment handled, magically, in
firmware: the cost of getting it wrong is high (as I've
spent a month learning); the performance is terrible (350x
slowdown; and most toolchains now know to avoid unaligned
load/store on RISC-V anyway.

But, mostly, if alignment problems exist, *we need to know*,
and if they're handled invisibly in firmware, we don't.

The problem with invisible handling was shown a while back
in the Go toolchain: runtime had a small error, such that
many misaligned load/store were happening, and it was
not discovered for some time. Had a trap been directed
to kernel or user on misalignment, the problem would
have been known immediately, not after many months.
(The error, btw, was masking the address with 3,
not 7, to detect misalignment; an easy mistake!).

But, the coreboot code does not work any more any way,
and it's not worth fixing. Remove it.

Tested by booting Linux to runlevel 1; before,
it would hang on an alignment fault, as the
alignment code was failing (somewhere).

This takes the coreboot SBI code much closer to
revival.

Change-Id: I84a8d433ed2f50745686a8c109d101e8718f2a46
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81416
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-27 14:45:06 +00:00
559ca8b5fb mb/google/nissa/var/anraggar: Modify the GPP_F15 of pen to EDGE_BOTH
Currently, simply changing the wake event configuration to ANY does
not completely resolve the issue of inserting a pen not waking the
system. The pen actually needs to wake up the system both when plugged
in and when pulled out. This is because in the pen's GPP_F15
configuration, the original attribute is EDGE_SINGLE, which should be
changed to EDGE_BOTH.

BUG=b:328351027
TEST=insert and remove pen can wakes system up.

Change-Id: I1823afd0bcb86804227117d2d5def38788bc7387
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81441
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-27 14:16:27 +00:00
823b9a6769 mb/google/brya: Create yavista variant
Create the yavista variant of the nissa reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)

BUG=b:321583226
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_YAVISTA.

Change-Id: I6fa464a4dcd9551a42e8746e64c724b3582dbe02
Signed-off-by: Hsueh Rasheed <hsueh.rasheed@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80342
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-27 14:15:44 +00:00
08562ba9b4 cbfstool: Add printing of legacy stage type
This is useful for listing older images.

Change-Id: I588028d4327f59538f7c9920b671458fc631cb4c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-03-27 14:00:56 +00:00
fc95c94d81 soc/intel/xeon_sp/spr: Enable x86_64 support
Fix compilation errors when compiled for x86_64.

Test: Booted on ibm/sbp1 to linux payload.

Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65
Signed-off-by: Arthur Heymans <arthur.heymans@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81280
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-27 09:09:03 +00:00
44955582a7 mb/purism: Remove blank lines before '}' and after '{'
Change-Id: I2285d1bdaa2734658ca1a0cc58ef2294d90d333e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-03-27 06:01:20 +00:00
37d308ea3f mb/google/brox: Fix GPE_EC_WAKE configuration
Wake signal from EC is routed to GPP_D1 and hence GPE_EC_WAKE
corresponds to GPE0_DW1_01. Fix GPE_EC_WAKE configuration.

BUG=b:329026602
TEST=Build Brox BIOS image and boot to OS. Trigger suspend and wake up
using EC generated events like AC connect/disconnect.

Change-Id: Ifb89bd0de7b7fc316792e801ed5a1d3f25ca5b1c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
2024-03-27 01:14:41 +00:00
526b9bba67 mb/msi: Remove blank lines before '}' and after '{'
Change-Id: I4a678b433e3e1a492e2a8e679caf75f4741317cb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81485
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26 23:12:00 +00:00
0f8aabdb26 doc/releases: Fix embedded rST syntax for MyST Parser
After commit 35599f9a66 (Docs: Replace Recommonmark with MyST Parser),
embedded rST should use `{eval-rst}` instead of `eval_rst`. This was
missed during manual rebasing of that patch before it was merged.

Change-Id: I648a95488df25d70e1b581872a19272c51f33b7b
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-26 23:11:33 +00:00
2095aedba8 mb/google/butterfly: Fix compiling for 64bit mode
Change-Id: Ieaaba5b36796d97449896b8475744a21f01e93d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-26 23:10:56 +00:00
d603f7c3fa mb/razer: Remove blank lines before '}' and after '{'
Change-Id: I2c8cc390bed3aef901d6ada19361c35928dfdb0c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81496
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26 23:10:13 +00:00
e45a61585c mb/roda: Remove blank lines before '}' and after '{'
Change-Id: Id039ad885d2f08bc3fe09aca740a72a5820f7fcc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-03-26 23:09:52 +00:00
221a046e73 mb/lenovo: Remove blank lines before '}' and after '{'
Change-Id: I6ece868184dd772fc2c3c472ae2172d1c34fb179
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81484
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26 23:09:28 +00:00
929dfec0bd arch/x86/bootblock.ld: Align the base of bootblock downwards
Instead of using some aritmetics that sometimes works, use the largest
alignment necessary (page tables) and align downwards in the linker
script.

This fixes linking failing when linking in page tables inside the
bootblock.

This can result in a slight increase in bootblock size of at most 4096 -
512 bytes.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I78c6ba6e250ded3f04b12cd0c20b18cb653a1506
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80346
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26 22:53:31 +00:00
e8c3d39edb mb/fb/fbg1701: Move VBOOT key location
Move it downwards allows for a larger bootblock, which comes in handy if
romstage or page tables are linked inside the bootblock.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ib37846c0b039d89396839ffa6047b18bcc228e02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80347
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26 22:52:34 +00:00
d308243bc1 util/xcompile: Add target architecture to CPPFLAGS
In order to preprocess linker scripts the target architecture needs to
be specified. With clang this needs to be set via a cli argument.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4340681e30059d6f18a49a49937668cd3dd39ce1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-03-26 22:51:12 +00:00
44adf4d22f drivers/intel/fsp2_0: Avoid unnecessary extra CBFS access
fsp_mrc_version() function does not need to perform a CBFS access to
to get an address to the FSP-M blob as the caller,
do_fsp_memory_init(), already has it loaded. In addition to make the
code simpler, it avoids an unnecessary decompression of the FSP blob
if `FSP_COMPRESS_FSP_M_LZ4' or `FSP_COMPRESS_FSP_M_LZMA' are set.

TEST=Verified on Meteor Lake rex

Change-Id: If355b5811a09a0b76acc8a297db719d54caedc54
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81256
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2024-03-26 16:12:36 +00:00
969f04fb34 soc/intel/xeon_sp: Update FSP-T UPD for FSP2.4
FSP2.4 and previous FSP versions have different FSP-T UPD
parameter settings.

Change-Id: I48384944ac69636cca2acd8169d3dd15f90362ec
Signed-off-by: Li, Jincheng <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81313
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26 10:14:23 +00:00
3199802045 soc/intel/xeon_sp: Share DDR codes across Xeon-SP platforms
DDR support codes across generations are similar. Share the codes
to improve code reuse.

TEST=intel/archercity CRB

Change-Id: I237d561003671d70dfaaa9823a0cf16d6e1f50cf
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81219
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-26 10:10:48 +00:00
e17113a3f3 libpayload: Include commonlib/helpers.h in libpayload.h for GPL builds
This patch makes the GPL-restricted commonlib helpers available in
libpayload when CONFIG_LP_GPL is selected, as a convenience to GPL
payloads that use them a lot.

Cq-Depend: chromium:5375721
Change-Id: I844c6e700c4c0d557f97da94fa3aa2e868edd756
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-03-25 08:23:35 +00:00
595efe4f20 arch/riscv: add new SBI calls
This is just a start. We are playing catch up.

7 down, 70+ to go.

Signed-off-by: Ronald G Minnich <rminnich@gmail.com>

Change-Id: I5dac8613020e26ec74ac1c74158fc9791553693f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-25 02:47:56 +00:00
c47fa32cb1 mb/google/veyron_{mickey,rialto}: Remove return statement in void function
Return statement is not useful in void function.

Change-Id: I8cf020de335e4da933b7bbdc27b7ac6f31afe885
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81430
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-24 18:53:06 +00:00
abf9c218f0 soc/intel/common/block/cse: Remove return statement in void function
Return statement is not useful in void function.

Change-Id: Idb8e07f48043452b329d255fe457f00317c017ae
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81429
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-24 18:52:59 +00:00
388db91f1d soc/intel/alderlake: Attach timestamp around eSOL call
This patch adds timestamp start/end entries around the eSOL
implementation to track the panel initialization time while rendering
the eSOL screen.

TEST=Able to build and boot google/omnigul.

555: started early sign-off life (eSOL) notification    643,694 (40)
556: finished early sign-off life (eSOL) notification   1,072,143 (428,449)

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I51c04fc4bd2540b3f42e2f896178521d297ef246
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-24 04:24:40 +00:00
c1a094d18e commonlib: Add timestamp entries for eSOL
This patch adds timestamp entries for eSOL (early Sign-Off Life).
This is critical to tracking the panel initialization time while
rendering the eSOL screen.

TEST=Able to build and boot google/omnigul.

555: started early sign-off life (eSOL) notification    643,694 (40)
556: finished early sign-off life (eSOL) notification   1,072,143 (428,449)

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I33f7f3a8622600ef23163faf45e2da7b96d6bbdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81386
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-24 04:24:33 +00:00
38f96b9716 soc/amd/common/noncar/memmap: reduce visibility of memmap_early_dram
The memmap_early_dram struct is now only used inside the non-CAR
memmap.c, so move the struct definition there.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id2bb3d3a9e01e9bae9463c582cb105b95c673a38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-03-23 21:24:32 +00:00
b985cc0440 soc/amd/common/cpu/noncar/memmap: use VGA MMIO defines everywhere
Only the VGA MMIO range used the VGA_MMIO_* defines, but instead of
using constants for the end of the region before that and the beginning
of the region after that, the VGA_MMIO_* defines can be used.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I45c3888efb942cdd15416b730e36a9fb1ddd9697
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-03-23 21:24:15 +00:00
8387400a7b soc/amd/common/cpu/noncar/memmap: make local variables const
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If3424df80655a150f27c7296a5683b528873816b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-03-23 21:24:00 +00:00
556373e354 soc/amd/*/memmap: factor out common read_lower_soc_memmap_resources
Since the code for reporting the memory map below cbmem_top is basically
identical for all non-CAR AMD SoCs, factor this out into a common
read_lower_soc_memmap_resources implementation.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id64462b97d144ccdf78ebb051d82a4aa37f8ee98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81389
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-03-23 21:23:47 +00:00
ca11545ca6 drivers/i2c/tas5825m: Allow using I2C bus
The latest Clevo boards connect the TAS5825M to one of the I2C
connections instead of the SMBus connection. The I2C ops are compatible
with SMBus, so always use them.

Tested on system76/oryp6 (uses SMBus) and in-development system76/oryp12
(uses I2C3). TAS5825M init is successful and speaker output works.

Change-Id: I2233d6977fd460b53e27260cdfabe42e30b98041
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-03-23 18:07:12 +00:00
cb92d28d7a soc/intel/xeon_sp/spr: Move XHCI code into southbridge folder
Move the XHCI code into soc/intel/xeon_sp/ebg where it belongs.

TEST=intel/archercity CRB

Change-Id: I2206ec5426a0f922cfce0e2d968e6806d349a6b2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-23 18:05:34 +00:00
2b24fc7c56 soc/intel/xeon_sp/spr: Drop unused defines
Since there's no code using those defines drop them.

TEST=intel/archercity CRB

Change-Id: I507b08a62ebeae14a1e63f4340b0592605a32477
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81369
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-23 18:03:52 +00:00
757580081d amdfwtool: Use macro to get the table relative address
TEST=Identical binary test on all AMD SOC platform

Change-Id: Iece4ba65e0476543a8d472168d93801714330dde
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78281
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-23 18:02:05 +00:00
df9a040e75 soc/amd/genoa_poc/domain: refactor read_soc_memmap_resources
To bring genoa_poc more in line with the other AMD SoCs, move the
reporting of the memory map up to cbmem_top from the openSIL-specific
add_opensil_memmap function to read_soc_memmap_resources. This is a
preparation for making this code common for all newer AMD SoCs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic06282baa3bb9a65d297b5717697a12d08605d2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81388
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-23 17:29:10 +00:00
4ff23a2246 util/lint: Fix license header regex
A trailing "|" at the end of the regex added a zero length alternative
match, causing all files to match and be filtered out. This was causing
`make lint-stable` to ignore all missing license headers, preventing the
pre-commit git hook and Jenkins from detecting these. Also, a missing
"|" separator between cmos.default and .apcb would cause those files to
be unintentionally scanned.

Change-Id: I70cc3a5adf7edee059883cd3cbe02029776b02ef
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-23 15:58:34 +00:00
d2d7933b48 src: Add missing SPDX license headers
Other files in the commits that added these files were licensed under
GPL-2.0-only, and the project as a whole is GPL-2.0-only, so use that
as the license.

Change-Id: I6c1a7ba582f61f98069ebf3857a8b5bdc8588c3e
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81421
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-23 15:58:17 +00:00
a57e497e2b drivers/intel/ish: Include stdbool.h to identify bool type
When the concerned chip.h file is included in a source file, it causes
compilation error saying unknown type name bool. Fix it by including the
stdbool.h file in the chip.h file.

BUG=None
TEST=Build Brox by including the chip.h file in one of the source files.

Change-Id: I4159e2c281c3e89dc45555ce38ad8637a3bf8587
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2024-03-23 01:10:41 +00:00
200f7b7ee1 arch/riscv: add Kconfig variable RISCV_SOC_HAS_MENVCFG
Older parts do not have the menvcfg csr.
Provide a Kconfig variable, default y, to enable it.
Check the variable in the payload code, when coreboot SBI
is used, and print out if it is enabled.

The SiFive FU540 and FU740 do not support this register;
set the variable to n for those parts.

Add constants for this new CSR.

Change-Id: I6ea302a5acd98f6941bf314da89dd003ab20b596
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81425
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22 23:01:48 +00:00
87fa1d07b5 vc/amd/opensil/genoa_poc/mpio: add debug output for unused chip
Print that the MPIO chip of one of the MPIO-related PCI device functions
is unused and is skipped, if the type is IFTYPE_UNUSED and the
corresponding PCI device function isn't enabled. This allows to
differentiate between this case and the case where the type isn't
IFTYPE_UNUSED.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4fc28d39a229494b487b300b28f92bf3adad66f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-22 21:56:12 +00:00
d7738f7dd2 vc/amd/opensil/genoa_poc/mpio: fix unused MPIO chip warning
When the chip of one of the MPIO-related PCI device functions has the
type IFTYPE_UNUSED, there is no corresponding MPIO engine, so replace
'engine' with 'chip' in the warning.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0f55a3f8e1d220d4eb7b0287d03b7af2e5d2889f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-22 21:56:03 +00:00
b526da297c vc/amd/opensil/genoa_poc/mpio: use device status for port_present
Only report the port as present in the MPIO_PORT_DATA_INITIALIZER_PCIE
macro parameter when the device is enabled; otherwise report the port as
disabled.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieaa2af6c5ff3fc7e25992e7fdf14d37ee4a57d62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81342
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-22 21:55:52 +00:00
e261aa0aa7 vc/amd/opensil/genoa_poc/mpio: simplify per_device_config arguments
Since we're already passing a pointer to the corresponding device to
per_device_config, we don't need to pass the chip_info as separate
parameter. Before moving the PCIe port function device below the MPIO
chip, the chip_info struct was from a different device, so that change
allows this simplification.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0466f7ad2f5c9874d45712fa9f89b978bd2a09bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-22 21:50:03 +00:00
4b187551d2 vc/amd/opensil/genoa_poc/mpio: move PCIe port function below mpio chip
Move the gpp_bridge_* device functions that are bridges to the external
PCIe ports below the corresponding mpio chip. This avoids the need for
dummy devices and does things in a slightly more coreboot-native way.

TEST=PCIe lane config reported by openSIL is identical

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Varshit Pandya <pandyavarshit@gmail.com>
Change-Id: I7e39bf68d30d7d00b16f943953e8207d6fe9ef41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81340
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22 21:49:41 +00:00
15784f1b03 mb/starlabs/starbook: Correct alphabetisation of Kconfig options
Change-Id: I7626fe9d4740e9f141a674fa457b0714fc38ed91
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22 16:22:21 +00:00
7c15e0c466 mb/starlabs/starbook/adl: Set RP9 detection timeout to 50ms
Certain SSDs are not detected in the default time window, so
change this to 50ms to allow these SSDs to be detected.

Change-Id: I60e66096ef9ea0146a1bc72c5c74234353509439
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81398
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22 16:21:53 +00:00
c8ae83eeb7 mb/starlabs/starbook/adl: Disable the Clock Request 4 GPIO
The CPU port is not used so disable it.

Change-Id: Ia150f99c4679323f08e44b0885af04113dfabd87
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22 16:21:36 +00:00
8d287af572 mb/starlabs/starbook/{adl,rpl}: Correct the ClkReq GPIO comments
Change-Id: I8dc80c5bdde61f3c2dc5c9dc67fbc752de7a103f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22 16:21:11 +00:00
185652e273 Revert "mb/starlabs/starbook/{adl,rpl}: Disable GpioOverride"
This reverts commit 8902dfa2bd.

This was originally assumed to be an FSP/Descriptor/PMC mismatch
but it turns out that the problem was coreboot incorrectly
detecting ASPM support on devices.

Revert so that a proper fix can be applied.

Change-Id: I3f83e79c1b21a6c3799abed4a279b8bd59ac3570
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81395
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22 16:20:47 +00:00
5827ffcdaf mb/starlabs/starbook/adl: Correct the layout
Adjust the size of the ME partition to match the descriptor

Change-Id: Ibdec5121518452ec16cebcc4f2fb563355373be3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81394
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22 16:20:12 +00:00
f1826583b0 mb/starlabs/starbook/{adl,rpl}: Disable CNVi
No variants were ever built with CNVi cards, so disable
this device.

Change-Id: I3725465eae0c7ade3dafa03add151353818ee761
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22 16:19:56 +00:00
6bfe01e507 soc/intel/xeon_sp: Include soc_util.h in Xeon-SP common codes
Different SoC generations might have different FSP header files. It is
recommended to put these uncommon header files in soc_util.h so that
Xeon-SP codes refer to soc_util.h to include them in a clean way.

TEST=intel/archercity CRB

Change-Id: Icfc20921efe00bc69b0c16c665f65f5baae4c309
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81229
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22 14:35:29 +00:00
14ea5c858a vc/intel/fsp/twinlake: Add FspProducerDataHeader.h header
This patch is to add FspProducerDataHeader.h header file to support MRC
version Info in TWL.

BUG=b:296433836

Change-Id: Ie33c681676d2a699b7aec8185dbdb90555ef8fe2
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81037
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-22 13:54:27 +00:00
01515c5dcd soc/intel/alderlake: select UDK_202111_BINDING for ADL-N
ADL-N FSP uses 202111 Edk2. select UDK_202111_BINDING Kconfig for ADL-N
SoC.

BUG=b:296433836
TEST=Able to build and boot google/crassk.

Change-Id: If277ede4307515035389cd0e9d34c15cc80f278c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80274
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22 13:53:48 +00:00
ceebacca02 mb/lenovo/s230u: Fix compiling for 64bit mode
This fixes the warning when an integer is cast to a pointer of a
different size.

Change-Id: Ide2827ec1b86dcbd804be9f3269c6c968cb4257b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-22 13:41:08 +00:00
760b572e0d vc/intel/edk2-stable202111: Resolve compilation error in EDK2 202111
Remove those MSVC compiler defaults checks so that the GCC defaults for
wchar_t can be used with UDK_202111_BINDING Kconfig.

Compilation error:
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Base.h:807:25:
error: static assertion failed: "sizeof (L\'A\') does not meet UEFI
Specification Data Type requirements"
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Base.h:807:25:
error: static assertion failed: "sizeof (L\"A\") does not meet UEFI
Specification Data Type requirements"

BUG=b:296433836
TEST=Able to build google/crassk with UDK_202111_BINDING.

Change-Id: Ib2716436a910b43a5e546afdedb9eec88c5da8c6
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81328
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22 13:38:46 +00:00
b417cb88df mb/google/nissa/var/anraggar: Update touchscreen enable pin to GPP_C0
Assign GPP_C0 and enable only the touchscreen. Before modification,
GPP_C0 supplies power to the touchscreen and sensor at the same time.
Now the hardware circuit has been modified, GPP_C0 supplies power to the
touchscreen alone. After the software is synchronously modified, when
the device enters suspend(S0ix), GPP_C0 will not enable VDD, which can
reduce the standby power consumption of the touchscreen when it is
suspended(S0ix), which is about 2.1mW.

BUG=b:304920262
TEST= touchscreen function workable

Change-Id: Ia06209aa8303be4fc0669c5d6e5d7a06e8e9ab99
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81265
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-03-22 13:38:11 +00:00
e8f9d18e88 amdfwtool: Only update count in header in only one function
Other function calls don't have to worry about the fletcher error.

TEST=Binary identical test on all AMD SOC platform

Change-Id: I7c9d653100b476b52d6d1d80c41d0c3d765f7be3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-22 13:35:16 +00:00
dc68ada3a0 arch/x86: Fix typo for macro CPUID_FEATURE_HTT
Change-Id: I9b29233e75483cda6bf7723cf79632f6b04233b0
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-21 20:37:51 +00:00
e80d06284f amdfwtool: Move linking BHD2 to PSP2 from main to link funcion
Move the complexity from main to function, so the main flow is easy to
understand.

TEST=Identical test on all AMD SOC platform

Change-Id: Ia549a0d08c2a60b8858440543ac8d8b5259017dd
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-21 20:37:10 +00:00
a779b989a2 mb/google/brox: Configure I2C timing for I2C devices
Configure I2C0/1 timing in devicetree to meet timing requirement.
(THIGH(us) minimum is 0.6us).

Before:
I2C0 : THIGH(us) 0.595us
I2C1 : THIGH(us) 0.582us

After:
I2C0 : THIGH(us) 0.673us
I2C1 : THIGH(us) 0.666us

Change-Id: I79af4fde4eb08d4eb896794756a633701bebb755
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81348
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-03-21 17:52:12 +00:00
1ba3d1630a Makefile.mk: Enable string-compare command option
Change-Id: I7b05b6dd8f1de8689bfcc6825beb728111f6e54a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81184
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-21 16:16:33 +00:00
b2d86f1f05 util/smmstoretool/fv.c: fix 3 formatting issues
Change-Id: If27218df40e58f249769b3d84c0cd4c299e2282b
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-21 16:14:57 +00:00
c8575728b5 util/docker/: Drop recommonmark pip module
The documentation is now built using MyST Parser, so Recommonmark can be
dropped.

Change-Id: I7f6810c9429573c0c51d3d72b36e9fc2ae2185f5
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80313
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-21 16:12:32 +00:00
35599f9a66 Docs: Replace Recommonmark with MyST Parser
Recommonmark has been deprecated since 2021 [1] and the last release was
over 3 years ago [2]. As per their announcement, Markedly Structured
Text (MyST) Parser [3] is the recommended replacement.

For the most part, the existing documentation is compatible with MyST,
as both parsers are built around the CommonMark flavor of Markdown. The
main difference that affects coreboot is how the Sphinx toctree is
generated. Recommonmark has a feature called auto_toc_tree, which
converts single level lists of references into a toctree:

* [Part 1: Starting from scratch](part1.md)
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)

MyST Parser does not provide a replacement for this feature, meaning the
toctree must be defined manually. This is done using MyST's syntax for
Sphinx directives:

```{toctree}
:maxdepth: 1

Part 1: Starting from scratch <part1.md>
Part 2: Submitting a patch to coreboot.org <part2.md>
Part 3: Writing unit tests <part3.md>
Managing local additions <managing_local_additions.md>
Flashing firmware <flashing_firmware/index.md>
```

Internally, auto_toc_tree essentially converts lists of references into
the Sphinx toctree structure that the MyST syntax above more directly
represents.

The toctrees were converted to the MyST syntax using the following
command and Python script:

`find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py`

```
import re
import sys

in_list = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()

with open(sys.argv[1], "w") as f:
    for line in lines:
        match = re.match(r"^[-*+] \[(.*)\]\((.*)\)$", line)
        if match is not None:
            if not in_list:
                in_list = True
                f.write("```{toctree}\n")
                f.write(":maxdepth: 1\n\n")
            f.write(match.group(1) + " <" + match.group(2) + ">\n")
        else:
            if in_list:
                f.write("```\n")
            f.write(line)
            in_list = False

    if in_list:
        f.write("```\n")
```

While this does add a little more work for creating the toctree, this
does give more control over exactly what goes into the toctree. For
instance, lists of links to external resources currently end up in the
toctree, but we may want to limit it to pages within coreboot.

This change does break rendering and navigation of the documentation in
applications that can render Markdown, such as Okular, Gitiles, or the
GitHub mirror. Assuming the docs are mainly intended to be viewed after
being rendered to doc.coreboot.org, this is probably not an issue in
practice.

Another difference is that MyST natively supports Markdown tables,
whereas with Recommonmark, tables had to be written in embedded rST [4].
However, MyST also supports embedded rST, so the existing tables can be
easily converted as the syntax is nearly identical.

These were converted using
`find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"`

Makefile.sphinx and conf.py were regenerated from scratch by running
`sphinx-quickstart` using the updated version of Sphinx, which removes a
lot of old commented out boilerplate. Any relevant changes coreboot had
made on top of the previous autogenerated versions of these files were
ported over to the newly generated file.

From some initial testing the generated webpages appear and function
identically to the existing documentation built with Recommonmark.

TEST: `make -C util/docker docker-build-docs` builds the documentation
successfully and the generated output renders properly when viewed in
a web browser.

[1] https://github.com/readthedocs/recommonmark/issues/221
[2] https://pypi.org/project/recommonmark/
[3] https://myst-parser.readthedocs.io/en/latest/
[4] https://doc.coreboot.org/getting_started/writing_documentation.html

Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-21 16:11:56 +00:00
9203e25a35 util/docker: Update Dockerfiles for building documentation
Update all pip packages related to coreboot's documentation to their
latest available version, and update the doc.coreboot.org base image
to Alpine 3.19.1. Add myst-parser in preparation to switch from
Recommonmark to MyST Parser.

TEST: The documentation builds and renders properly when built using
the updated container.

Change-Id: I8df4aadabc49c0201a836333745fe138184595ac
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80312
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-21 16:11:37 +00:00
af68bf25aa docker/doc.coreboot.org: Install pip modules into virtual env
Currently, pip modules are installed system-wide, which may cause
conflicts with modules installed using the package manager. Newer
versions of the Alpine base image also mark its system wide Python
installation as an externally managed environment, which will cause
pip to return an error as per recent Python recommendations [1].

TEST:
- `make -C util/docker doc.coreboot.org` builds the container
  successfully
- `make -C util/docker docker-build-docs` builds the documentation
  successfully

[1] https://peps.python.org/pep-0668/

Change-Id: Idd9cc5e6fb28b42ef8e4fa5db01eb9ef192ba0ec
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-03-21 16:10:44 +00:00
b348154e5e mb/google/zork: Update APCB to increase UMA size to 128MB
The previous value of 32MB was set to meet Google's ChromeOS reqs,
but hampers real-world performance in Linux/Windows, so increase it
to 128MB to match the "auto" default for the Picasso UEFI firmware.

TEST=build/boot Windows on google/zork (morphius), verify UMA set
to 128MB.

Change-Id: I8c6487a4cb8155f826d20fd3ceca87859829199c
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81364
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2024-03-21 15:18:44 +00:00
d4d6d6c8d0 drivers/intel/dptf: Add DCFG support
After final production, it's possible by setting particular
bit using DCFG the OEM/ODM locks down thermal tuning beyond
what is usually done on the given platform.

In that case user space calibration tools should not try
to adjust the thermal configuration of the system.

By adding new DCFG (Device Configuration) it allows the
OEM/ODM to control this thermal tuning mechanism. They can
configure it by adding dcfg config under overridetree.cb file.
The default value for all bits is 0 to ensure default behavior
and backwards compatibility.

For an example if Bit 0 being set represents Generic DTT UI
access control is disabled and Bit 2 being set represents DTT
shell access control is disabled.
Each bit represents different configuration access control
for DTT as per BIOS specification document #640237.

It also gives the provision for user space to check the current
mode. This mode value is based on BIOS specification document
number #640237.

BUG=b:272382080
TEST=Build, boot on rex board and dump SSDT to check DCFG value.
 Also, verified the newly added sysfs attribute "production_mode"
 present under /sys/bus/platform/devices/INTC1042:00 path.

Change-Id: I507c4d6eee565d39b2f42950d888d110ab94de64
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78386
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-21 13:16:55 +00:00
e4e29c9e78 vendorcode/cavium: Use unsigned integers in struct bitfields
Bitfields with signed integers are not valid C code. This fixes
compilation with clang v16.0.6.

Change-Id: I0b2add2f1078a88347fea7dc65d422d0e5a210a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80638
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-21 11:23:24 +00:00
f426df3f68 mb/google/brya: Create a tivviks variant
This patch creates a new tivviks variant, which is a Twinlake
platform. This variant uses Nivviks board mounted with the
Twinlake SOC and hence the plan is to reuse the existing
nivviks code.

BUG=b:327550938
TEST= Genearte the Tivviks firmware builds and verify with boot check.

Change-Id: Ia833a1dad45e13cd271506ade364b116c5880982
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81262
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-21 07:21:03 +00:00
59ee65d271 soc/intel/adl: Guard TWL SoC missing UPDs for build integrity
Adds config-based guards for Usb4CmMode and CnviWifiCore UPDs, specific
to Twin Lake SoCs (SOC_INTEL_TWINLAKE).

Prevents compilation errors due to missing UPD definitions.

BUG=b:330654700
TEST=Able to build google/tivviks.

Change-Id: I6e0a9a7536df6295e23bf06003539e56bb98a311
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81376
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-21 07:20:56 +00:00
55a7d90a50 mb/google/brox: support ISH
Set FW_CONFIG bit 21 to enable ISH PCI device and define ISH main
firmware name so ISH shim loader can load firmware from file system.

ISH also need to be enabled if STORAGE_UFS is set.

BUG=b:280329972
TEST= Set bit CBI FW_CONFIG bit 21
      Boot Brox board, check that ISH is enabled and loaded
      lspci shows: 00:12.0 Serial controller: Intel Corporation Alder
Lake-P Integrated Sensor Hub (rev 01).

Change-Id: Iadc5108c62737d27642a6948c00b5c122541aaba
Signed-off-by: Li Feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80773
Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Yuval Peress <peress@google.com>
2024-03-20 21:57:27 +00:00
929ef5f7f1 vc/amd/opensil/*/mpio: add IFTYPE_UNUSED mpio_type enum element
Add IFTYPE_UNUSED as first element to the mpio_type enum. This allows
checking if the type was set in the devicetree, since the default will
now be IFTYPE_UNUSED. If the type is set to IFTYPE_UNUSED although the
corresponding PCI device function, a warning is printed and the PCI
device function is disabled.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85e2589c021b4f05662369fd551146b6f2fa0ad4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-20 19:06:14 +00:00
c12ef5d7b7 vc/amd/opensil/genoa_poc/mpio: add IFTYPE_ prefix to mpio_type values
Add an IFTYPE_ prefix to all elements of the mpio_type enum to have more
specific names.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I229a3402c36941ee5347e3704fcf8d8a1bbc78a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81338
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-20 19:05:49 +00:00
f7aafacb33 vc/amd/opensil/stub/mpio: change mpio_engine_type prefix to IFTYPE
Change the prefix of the elements of the mpio_engine_type enum from
ENGINE_ to IFTYPE_.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: If81c5ea01ba147b71b423004a2199b348ffac99a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-20 19:05:38 +00:00
b91f421118 amdfwtool: Check sanity before filling the data array
Change-Id: I8284c35a0124ba4588d199024e28d3445c681896
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>wq
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78763
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-20 13:44:57 +00:00
58b250c301 soc/intel/elkhartlake/Kconfig: Rename FSPRel.bin to FSP.fd
With the last FSP submodule update for Elkhart Lake commit f8df905e7b
("3rdparty/fsp: Update submodule to upstream master"), the binary name
was changed to FSP.fd.

Change-Id: Ibc87ea2744e971d58e9a402f7cf04ef3f316f3b8
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-20 13:42:13 +00:00
b81b7da92f amdfwtool: Set the cookie when the table header is created
When the table is created, the cookie is known.
When the packing going on, the cookie in header can be checked to see
where we are.

TEST=Identical test on all AMD SOC platform

Change-Id: I300e30292c68a14b44c637b26a13b308dc9c0388
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81254
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-20 13:36:14 +00:00
eea834bcfd amdfwtool: Move the header creation into integration function
Before every integration there is a header creation. We can put them
together. And the parameters for PSP/BIOS tables are useless.

TEST=Identical test on all AMD SOC platform

Change-Id: Ia9d78bb8145855203048208fcd67f8b9cd9d3199
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-20 13:35:19 +00:00
f360095d93 amdfwtool: Add functions to link all the tables
The purpose of integration function is to pack the FWs into table. We
need to remove other process. Create a dedicate function to link all
the tables together. And this linking function is only called when
both the level 1 and level 2 directory are created. This simplifies
the main function and logic.

TEST=Identical test on all AMD SOC platform

Change-Id: Ieaf97208e943c79d7b76ea62eea9355138c220b9
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-20 13:34:57 +00:00
e4214b7939 amdfwtool: Move the address of tables to the context
Instead of being local variables. This can be easier to find all
the tables anywhere.

TEST=Identical test on all AMD SOC platform

Change-Id: I98b7d01e32c75b4f13e23d496cd3de3da900678d
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-20 13:34:32 +00:00
bb1f81271b cpu/x86/smm: Pass full SMRAM region info to SMM runtime
This data is used by smm_region_overlaps_handler(). Callers use this
helper to determine if it's safe to read/write to memory buffers taken
from untrusted input.

coreboot SMI handlers must not be confused into writing over any SMRAM
subregion, which includes the TSEG_STAGE_CACHE and chipset-specific area
(sometimes, IED), not just the handlers.

If stage cache writes were permitted, this could compromise the
integrity of the S3 resume path.

The consequences to overwriting the chipset-specific area are undefined.

Change-Id: Ibd9ed34fcfd77a4236b5cf122747a6718ce9c91f
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80703
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-20 06:11:20 +00:00
6b4522e2aa libpayload: gdb: Make die_if() format string a literal
CB:77969 made minor changes to the die_if() macro. One of the
consequences is that the format string passed to it can no longer be a
real `char *` variable, it needs to actually be a string literal. In the
vast majority of call sites that is already the case, but there was one
instance in the GDB code where we're reusing the same format string many
times and for that reason put it into a const variable. Fix that by
turning it into a #define macro instead. (Even though this technically
duplicates the format string, the linker is able to merge identical
string literals together again, so it doesn't really end up taking more
space.)

Change-Id: I532a04b868f12aa0e3c01422c075ddaade251827
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81361
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-19 22:50:03 +00:00
ebc6f9d2e1 mb/google/brox: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS in brox Kconfig.
This enables a single binary for both SKU1 and SKU2. For SKU2, upon
boot from cold reset, it will disable the UFS Controller and then
trigger a warm boot.

BUG=b:329209576
BRANCH=None
TEST=Boot image on SKU1/SKU2 and check S0ix working.

Change-Id: Iabd0b3a83aa386e09310b671632368807a4018d4
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
2024-03-19 22:04:04 +00:00
27a0506308 Makefile.mk: Include build/dsdt.d at the same time as DEPENDENCIES
Instead of including the generated dependency file during the evaluation
of asl_template, add it to the DEPENDENCIES variable so that it is
included at the same time as the rest of the .d files in the top level
Makefile. This makes the handling of .d files cleaner as all of them are
processed in the same way. Tracking all of them in a single variable
also prevents any from being missed if any post-processing is performed
on them, such as running them through the fixdep utility from the Linux
kernel project to replace the config.h dependency with only the configs
that are used.

This should be safe since asl_template is evaluated while calling
includemakefiles, which is occurs before the files in DEPENDENCIES are
included.

TEST:
1. Build dell/e6400
2. Run `touch src/mainboard/dell/e6400/dsdt.asl` (defined as a
   prerequisite of build/dsdt.aml in build/dsdt.d)
3. Run `make --debug=b`
4. Verify that dsdt.aml was rebuilt due dsdt.asl being newer than target

Change-Id: Ie8271d1e172395917f2859c8bbfd2041ddc572ca
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80383
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-19 19:28:30 +00:00
83a31b0755 Makefile: Drop unused variable originalobjs
This was added in commit 963bed546f (Make: Use unaltered object list for
dependency inclusion) to fix an issue caused by ramstage-postprocess.
The logic for handling dependency inclusion changed in commit db273065f6
(build system: extend src-to-obj for non-.c/.S files), causing the
variable to become unused.

Change-Id: I011ff2070bc31ab9ddf2536873555d0157f91fce
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-19 19:27:44 +00:00
4dac520707 arch/x86: Directly return result of IS_POWER_OF_2()
Change-Id: I314d726deaed30e69121126ba6834e4c7cafd090
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-03-19 17:04:40 +00:00
de37be8a1a cpu/x86: Use correct config flag for 1GiB page table
The commit below uses USE_1G_PAGETABLES config flag instead of
the correct USE_1G_PAGES_TLB.
"commit ecbc243a45
("cpu/x86: Add 1GiB pages for memory access up to 512GiB")"

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-03-19 15:03:18 +00:00
a7fbef4c19 MAINTAINERS: Update email address of Jonathan for Xeon SP
Change-Id: Icbf04f347a02670d0bf38e0328fa6b523d6851b5
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-19 14:54:22 +00:00
d714ab63a4 mb/google/nissa/var/craaskov: Update eMMC DLL settings
Update eMMC DLL settings based on Craaskov board.

BUG=b:318323026
TEST=executed 2500 cycles of cold boot successfully on all eMMC sku

Change-Id: I56f8329c28261c2bcae9d058da929be6763b293c
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-19 13:36:13 +00:00
19453ec7a6 mb/google/nissa/var/glassway: Tune I2C timings for 400 kHz
Update touchpad and touchscreen I2C timing.
- Data hold time: 300ns - 900ns

BUG=b:328724191
BRANCH=firmware-nissa-15217.B
TEST=Check wave form and met the spec.
     I2C1 (touchscreen) Hold time from 83.58ns to 413.87ns
     I2C5 (touchpad)    Hold time from 95.93ns to 425.27ns

Change-Id: I65fb1298f9e96ab0b63aba436f6a319f21b38925
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Shawn Ku <shawnku@google.com>
2024-03-19 13:35:46 +00:00
b5a7bad724 mb/google/nissa/var/glassway: Adjust touchscreen power sequencing
Adjust touchscreen power sequencing for eKTH5015M.

The INX touch panel (eKTH5015M) contains a pull-up register which causes TCHSCR_REPORT_EN pull-up abnormally from Z1 power on.Because the t25 must be at least greater than 20ms, TCHSCR_REPORT_EN is initialized to GPO_L in the early stage (romstage) to meet the spec.

BUG=b:328170008
BRANCH=firmware-nissa-15217.B
TEST=Build and check I2C devices timing meet spec.
[INFO ]  input: Elan Touchscreen as /devices/pci0000:00/0000:00:15.1/i2c_designware.1/i2c-10/i2c-ELAN0001:00/input/in4

Change-Id: I50f9c21ddee2bc9c1d313f63049cb587b4ae047a
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81135
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-19 13:35:11 +00:00
194128a3af cpu/x86/mtrr: Error out caching limitation during NEM
Improves user experience by highlighting a possibility of runtime
hangs caused by unsupported WB caching during NEM.

Recently we have encountered an issue on Intel platform and came to
know about the NEM logical limitation where due to cache sets are not
in power_on_two running into a runtime hang upon enabling WB caching.

BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot on google/ovis and google/rex (including Ovis with
non-power-of-two cache configuration).

Change-Id: Ic4fbef1fcc018856420428139683897634c9f85d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81336
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-03-19 13:02:04 +00:00
85e3fe12ed drivers/intel/fsp2_0: Use DECLARE_REGION for FSP-M heap
There are 2 ways of referring to linker symbols, as extern
u8[] or extern u8*. Only the former will be correctly
initiated into an immediate operand (a constant) to asm.

DECLARE_REGION defines reference in form of extern u8[].
Use DECLARE_REGION as a standard way for these references.

TEST=intel/archercity CRB

Change-Id: I5f7d7855592d99b074f7ef49c285a13f8105f089
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81097
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-19 13:00:50 +00:00
bb50190bec soc/intel/xeon_sp: Drop RMRR entry for USB
Drop RMRR entry for XHCI controller since it's not under BIOS control.
There's no USB-PS/2 emulation done in SMM, hence it's not needed.

TEST=intel/archercity CRB

Change-Id: I5afd68371d71a00988fe0f8a6045ec5ce2adc6a1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81297
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-19 10:59:08 +00:00
43d260745a soc/intel/xeon_sp: Drop uncore_fill_ssdt
Let ACPI DSDT figure out by itself if a stack is enabled.
Allows to drop uncore_fill_ssdt() on all platforms.

TEST=intel/archercity CRB

Change-Id: Ib9051d608147f2de228509ff6b13871ca3183979
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81273
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-19 10:19:22 +00:00
49fe84e2c2 soc/intel/xeon_sp/spr: Enable 512 MMCONF buses by default
As of now coreboot only supported one PCI segment group and thus the
MMCONF size had to be limited to 256 buses on ibm/sbp1. Since the
default FSP doesn't allow to disable unused IIO stacks a patched
version had to be used. Those unused IIO stacks consume lots of PCI
bus ranges, leaving no free buses for the secondary side behind PCI
bridges. The IIO disable mechanism doesn't work after ACPI G3 exit
and thus requires multiple reboots when the previous state was G3.

Since coreboot now supports multi PCI segment groups enable 512
MMCONF buses on 4S platforms by default and drop the IIO stack
disable UPDs on ibm/sbp1. This allows to boot faster without the
need for a patched FSP.

The use of multiple PCI segment groups might prevent legacy software
from working properly, however the only board where multiple PCI
segment groups are used uses u-root as default payload.

TEST=Booted on ibm/sbp1 to ubuntu22.04 using two PCI segment groups.
TEST=intel/archercity CRB

Change-Id: I4e6e5eca1196d4ab50e43b4b58d24eca444ab519
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-19 10:18:21 +00:00
8061957cc1 soc/intel/xeon_sp: Initial support for PCI multi segment groups
Add PCI enumeration support by reading the PCIeSegment reported in the
FSP HOB and add it when creating the PCI domain for each stack.

The PCI enumeration will be able to scan the additional PCI segment
groups and properly handle those devices.

TEST=Booted on ibm/sbp1 with multiple PCI segment groups enabled
      to ubuntu 22.04.
TEST=intel/archercity CRB

Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79878
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-19 09:56:49 +00:00
d425e881e3 soc/intel/xeon_sp: Add SATC PCI segment group support
For every PCI segment group generate a new SATC header.
Allows to generate proper ACPI code when multiple PCI segment
groups are enabled.

TEST=Booted on ibm/sbp1 with multiple PCI segment groups.
      Properly generates multiple SATC headers.
TEST=intel/archercity CRB

Change-Id: I93b8ee05a7e6798e034f7a5da2c6883f0ee7a0e5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-19 09:18:20 +00:00
f95565311a arch/riscv: add constants for Base Extension
Get used to this rate of change, SBI adds one new function a month,
on average, for the last 7 years.

Signed-off-by: Ronald G Minnich <rminnich@gmail.com>

Change-Id: Iaad763464678d1921dfefdbee1e39fba2fe5585a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-03-19 03:07:26 +00:00
965db62429 symbols: Add __maybe_unused flag to region variable symbols
In DECLARE_REGION and DECLARE_OPTIONAL_REGION, a set of 3 variables
will be defined, that is the region 'base', 'end' and 'size'.
However, in many codes, the users will only selectively use 'end'
or 'size' instead of both of them, which will trigger compiler errors
for unused variables. This patch sets __maybe_unused attributes on
'end' and 'size' so that users do not need to use all of them.

TEST=intel/archercity CRB

Change-Id: Ia5ed183b2dd7a474ce51de47dbc1f9e3f61e5a41
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81209
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-18 16:53:36 +00:00
950da598d6 3rdparty/amd_blobs: update submodule pointer
Update the amd_blobs submodule pointer to now include the following
commit:

  picasso: Update PSP fw to version 00.08.14.7B

TEST=Mandolin boots to the Windows 10 desktop and the GPU driver works

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If1bd0b37bebcdd600465dbd48162792e2c32bfb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81263
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-18 15:03:35 +00:00
18cf3f7966 amdfwtool: Compact the parameter transfering
Remove redundant parameter "debug" from open_process_config().

Change-Id: Ib91a505838d7be4980d6b4f1e95fb8601fbbfd16
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81201
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-18 14:56:29 +00:00
d22c2c8772 amdfwtool: Remove the dissociated combo BIOS table for recovery A/B
For recovery A/B mode, the BIOS tables level 2 are traced by PSP table
instead of ROMSIG. There should not be a dedicated BIOS table, nor a
combo BIOS table.

Change-Id: I8735bd91b32bc9a0e4fc70d293e8d836d5e9c36b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81137
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-18 14:55:08 +00:00
686d810092 soc/intel/xeon_sp/uncore_acpi: Fix debug print
The DMAR entries of type "PCI" have no "Enumeration ID" and thus
there's no need to print it. Drop all unused Enumeration IDs to
simplify the code and debug prints.

Document ID: Intel Virtualization Technology for Directed I/O
Architecture Specification, Rev. 4.0, Order Number: D51397-015

TEST=intel/archercity CRB

Change-Id: I009fbfb9f9d62855d351c5db2d3d88722b5dbfa2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81186
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-18 13:54:46 +00:00
3e4b517265 genbuild_h: Fix and harden major/minor version parsing
Our major version is suddenly two digits long to represent the year.
This can't be parsed with the current sed scripts. To make sure that
no unparsed data ends up in our major/minor versions,  we'll run sed
with `-n' and only print the extracted numbers if anything. Also, to
allow us to use the version numbers in C code, we strip leading zeros
(a leading 0 identifies octal numbers, so for instance 08 for August
is not a valid number).

This can result in empty major/minor version strings, so we move the
default `0' to the final variable expansion.

As a bonus, this makes an explicit check if the numbers can be parsed
unnecessary.

Change-Id: Ie39381a8ef4b971556168b6996efeefe6adf2b14
Reported-by: Christoph Zechner <christophz@vrvis.at>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81290
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17 20:08:56 +00:00
5c769ab711 util/intelmetool: Print the address in map_physical errors in hex
Previously the incorrect 'd' format specifier was used despite the '0x'
prefix implying hex to the user.

Change-Id: Ib97bd86ee0e0c8fe8c3785e22a4d9f6def3cae61
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-17 19:08:48 +00:00
e079379576 amdfwtool: Set the level based on cookie
It was complicated and weird to check both the cookie and whether one
table is a null pointer. Just checking the cookie is enough.

TEST=Identical test on all AMD SOC platform

Change-Id: Icab74714990f74e11fd5e899661e4e2d41230541
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81208
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17 16:58:04 +00:00
07e050804f amdfwtool: Set the table size only for FWs
The entry in the table has two categaries, file and pointer. For the
pointer, it does not take table space. The ISH, PSP level 2, BIOS
table are all the pointer type. So integration function only packs FWs
located in folder amd_blobs. And only FWs increase the table size.

So the table size is only set once. Later calls only update the count
and fletcher. The table has a header at least, so the size can not be
0.

The fill_dir_header can take the parameter count as 0, such PSP level
1 only with ISH-A and ISH-B. It doesn't have any file type entries.

This actually reverts
  https://review.coreboot.org/c/coreboot/+/78274
and adds other changes.

TEST=Identical test on all AMD SOC platform

Change-Id: I5dfbbb55912c8e37243c351427a8df89c12e5da8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81255
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17 16:56:43 +00:00
caa50f30b7 commonlib: list: Include <stdint.h>
The list macros use uintptr_t, so they need to include the header that
declares it.

Change-Id: I56b2a988bb11d40c8761717bcd02a8199c077046
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81288
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17 16:53:30 +00:00
c00c14077d libpayload: Make GPL commonlib includes available to payloads and tests
CB:77968 made some non-BSD commonlib files part of libpayload when
CONFIG_LP_GPL is set. This patch exports those headers to the payload
(again only when CONFIG_LP_GPL is set) so that payloads can also call
the functions in them directly.

Also make those includes available to tests so that their functions can
be tested. There's no menuconfig for unit tests, so they are included
unconditionally, but this should be fine since the tests are standalone
and won't have to link with any proprietary third-party code.

Change-Id: Ifc3e52ee5c3e51520f7b7d44b483bfcb0e8380f8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-03-17 16:53:06 +00:00
614fb7a51c drivers/spi: Add support for GD25LR512ME flash rom
This device is used on the AMD BirmanPlus board.

Change-Id: Iadb819e89a349d074e5ae9f4b62a06176f1f8f64
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-17 16:50:25 +00:00
b668f41cce payloads/edk2: Set the EDK2 repository to custom for UPL
UPL requires the Shim Layer, and those patches exist in the
`starlabsltd` fork.

Set the repository to custom, to allow this fork and branch to
be selected correctly.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ieca72498bde51a184d689670449b66ccc78d658a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81277
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-03-17 16:50:06 +00:00
25e308b79a mb/google/nissa/var/anraggar: Add pen insert/remove for wakeup
Currently, inserting the pen does not wake the system, only removing
the pen does. This is caused by the wake event configuration being
DEASSERTED, so change it to ANY.

BUG=b:328351027
TEST=insert and remove pen can wakes system up.

Change-Id: Icdea995c2be04ea459e985f79269e49faf88248d
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-03-17 16:43:51 +00:00
deb54cc0b2 mb/google/brya: Create bujia variant
Create the bujia variant of the brask reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:327549688
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_BUJIA

Change-Id: I453a50f1aa64f8d4119bf0f860d928aa3e00a144
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81198
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2024-03-17 16:43:01 +00:00
58d3090a97 src/Kconfig: Make it possible to override CCACHE in site-local
The value for CCACHE in site-local/Kconfig gets overridden by the
default in src/Kconfig. Remove the default to make overrides possible.

Change-Id: I6b9dbbb31caa3ef09afd7ecb355c01bd53807b39
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-17 16:37:54 +00:00
7765f4d43b vc/amd/opensil: don't use source path when using stub
Add a 'depends on' statement so that path/to/opensil/source is only
active when the stub is not built.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ic050ff0fa3f428e6adff3357f476fcd8a88cdf7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81189
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17 16:36:10 +00:00
ee01de8034 soc/amd/phoenix: make openSIL stub optional
Convert the 'select SOC_AMD_OPENSIL_STUB' statement to a config option
and give it a prompt.  This allows for internal development of openSIL
and corresponding coreboot source, and controllable using a defconfig.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I2b48e2bbf71cd94ac7ecec13834ba36aa6c241ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-17 16:35:56 +00:00
4866712b04 soc/intel/mtl: Enable RAMTOP caching at SoC level for MTL devices
This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` configuration
at the SoC level for all MTL devices. This change streamlines the
configuration process, avoiding redundant selections on individual
mainboards.

BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot functionality on google/ovis and google/rex.

Change-Id: I3aa3a83c190d0a0e93c267222a9dca0ac7651f9c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-03-17 11:55:29 +00:00
aaacd5083a mb/google/rex: Reland RAMTOP caching for Ovis
This patch ensures Ovis baseboard can select RAMTOP caching to improve
the boot time w/o any runtime hang.

BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot on google/ovis with ~30ms savings in boot time.

Change-Id: Ic0b73eb8fb9cd6ca70d3d7168b79dfd0fbc550e3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-03-17 11:55:18 +00:00
9355f318fa soc/intel/cmn/ramtop: Refactor MTRR handling for RAMTOP range
This patch refactors RAMTOP MTRR type selection to address a critical
NEM logic bug on SoCs with non-power-of-two cache sets. This bug can
cause runtime hangs when Write Back (WB) caching is enabled.

Workaround: Force MTRR type to WC (Write Combining) on affected SoCs
when the cache set count is not a power of two.

BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot on google/ovis and google/rex (including Ovis with
non-power-of-two cache configuration).

Change-Id: Ia9a8f0d37d581b05c19ea7f9b1a07933caa956d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81269
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17 11:55:08 +00:00
a4c91e15f8 arch/x86: Add API to check if cache sets are power-of-two
Introduce a function to determine whether the number of cache sets is
a power of two. This aligns with common cache design practices that
favor power-of-two counts for efficient indexing and addressing.

BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified functionality on google/ovis and google/rex (including
a non-power-of-two Ovis configuration).

Change-Id: I819e0d1aeb4c1dbe1cdf3115b2e172588a6e8da5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81268
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17 11:54:58 +00:00
bbf884ddbd util/lint/lint: Fix shellcheck errors in getopt support for darwin
Posix shell doesn't support '=='

Change-Id: Icbdc4204f4c07d806e721fa39f96694c4df00e8d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81285
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17 08:26:00 +00:00
a46dd5cd4b ec/hp/kbc1126/acpi: Drop unnecessary _STA methods
_STA unconditionally returning 0xF is pretty much the default[1] and
should be removed to reduce some noise.

[1] https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/06_Device_Configuration/Device_Configuration.html#sta-device-status

Change-Id: I0390767aa866e322c762038c12116a15b280af1a
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-16 15:20:04 +00:00
f77a28ac1f ec/hp/kbc1126/acpi: Drop unnecessary method arguments
Method(..., 0, NotSerialized) is the default[1] and can be reduced to
Method(...) which reduces some noise.

TEST=Timeless build produces the same binary

[1] https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/19_ASL_Reference/ACPI_Source_Language_Reference.html#method-declare-control-method

Change-Id: Ic24e004500a7fa2a5a5b38a3f6f0e13e4ce7dfac
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81205
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2024-03-16 15:19:29 +00:00
99b069baa6 3rdparty/intel-microcode: Update submodule to upstream main
Updating from commit id ece0d29:
2023-11-14 10:19:09 -0600 - (microcode-20231114 Release)

to commit id 41af345:
2024-03-11 19:11:14 -0600 - (microcode-20240312 Release)

This brings in 1 new commits:
41af345 microcode-20240312 Release

Change-Id: Iaea865100661776c5331cba6c92ef51dfd410159
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-15 12:11:23 +00:00
3588243177 mb/google/brya/var/xol: Modify clkreq to clksrc mapping for NVMe
NVMe using clk_src[0] and clk_req[1] mapping to hardware design,
Due to inconsistency between PMC firmware and FSP, we need to set
clk_src to clk_req number, not same as hardware mapping in coreboot.
Then swap correct setting to clk_src=0,clk_req=1 in mFIT.

BUG=b:328318578
TEST=build firmware and veirfy suspend function on NVMe SKU DUT.

Cq-Depend: chrome-internal:7063434
Change-Id: I1777310782a0f4417bd1bb21287bec5852be966e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81230
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-15 12:11:11 +00:00
3ac72f8cf2 brox: ish: Add Kconfigs for ISH
Modeled after the Rex Kconfigs for ISH.

Change-Id: Ic670d550a9aaad64e52489d895b8aac2aee4b5ed
Signed-off-by: Yuval Peress <peress@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81050
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-15 12:10:39 +00:00
b3e336c51d treewide: Move stdlib.h to commonlib
This patch moves commonlib/stdlib.h -> commonlib/bsd/stdlib.h, since
all code is BSD licensed anyway.
It also moves some code from libpayloads stdlib.h to
commonlib/bsd/stdlib.h so that it can be shared with coreboot. This is
useful for a subsequent commit that adds devicetree.c into commonlib.

Also we don't support DMA on arm platforms in coreboot (only libpayload)
therefore `dma_malloc()` has been removed and `dma_coherent()` has been
moved to architecture specific functions. Any architecture that tries to
use `dma_coherent()` now will get a compile time error. In order to not
break current platforms like mb/google/herobrine which make use of the
commonlib/storage/sdhci.c controller which in turn uses `dma_coherent` a
stub has been added to arch/arm64/dma.c.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I3a7ab0d1ddcc7ce9af121a61b4d4eafc9e563a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-03-15 10:09:43 +00:00
8627112424 soc/intel/xeon_sp: Rewrite acpi_fill_dmar
Rewrite the function by iterating IOMMU (Input/Output Memory
Management Unit) devices instead of iterating socket and stacks,
which is more aligned to coreboot infrastructure.

TEST=intel/archercity CRB

coreboot DRHD generation is compared, the order of sections are
changed as expected but the content is kept equvalient.

Change-Id: I700513e05181303cf3f4effc793a872eb23340cb
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81228
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14 20:15:27 +00:00
6747acb917 soc/intel/xeon_sp: Rewrite acpi_create_drhd
Obtain IOMMU (Input/Output Memory Management Unit) info and
enumerate devices using device utils instead of FSP HOB interface,
which might change across SoC generations and no ambiguity across
multiple PCIe segments.

TEST=intel/archercity CRB

coreboot DRHD generation log no changes before and after

Change-Id: Ic5c404899172a0e4fba2721b8e8ca6c1f0856698
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81227
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14 20:12:59 +00:00
07781e8268 intelblocks/pmc: Assign initial values to pmc_gpe_init variables
pmc_gpe_init uses soc_get_gpi_gpe_configs to initialize dw0, dw1
and dw2. dw0, dw1 and dw2 are uninitialized before calling
soc_get_gpi_gpe_configs. This is error prone for some soc
implementations where soc_get_gpi_gpe_configs does nothing.

This patch is simple, just to assign zero values to dw0, dw1 and
dw0, to enhance the code robustness.

TEST=intel/archercity CRB

Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Change-Id: I8a710a2ac1482eed8c11977d51b187d834122d26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81210
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14 20:02:49 +00:00
72298ae964 arch/riscv: support physical memory protection (PMP) registers
PMP (Physical Memory Protection) is a feature of the RISC-V
Privileged Architecture spec, that allows defining region(s) of
the address space to be protected in a variety of ways: ranges
for M mode can be protected against access from lower privilege
levels, and M mode can be locked out of accessig to memory
reserved for lower privilege levels. Limits on Read, Write, and
Execute are allowed. In coreboot, we protect against Write and
Execute of PMP code from lower levels, but allow Reading, so as
to ease data structure access. PMP is not a security boundary,
it is an accident prevention device.

PMP is used here to protect persistent ramstage code that is
used to support SBI, e.g. printk and some data structures. It
also protects the SBI stacks. Note that there is one stack per
hart. There are 512- and 1024-hart SoC's being built today, so
the stack should be kept small.

PMP is not a general purpose protection mechanism and it is easy
to get around it. For example, S mode can stage a DMA that
overwrites all the M mode code. PMP is, rather, a way to avoid
simple accidents. It is understood that PMP depends on proper OS
behavior to implement true SBI security (personal conversation
with a RISC-V architect). Think of PMP as "Protection Minus
Protection".

PMP is also a very limited resource, as defined in the
architecture. This language is instructive: "PMP entries are
described by an 8-bit configuration register and one XLEN-bit
address register. Some PMP settings additionally use the address
register associated with the preceding PMP entry. Up to 16 PMP
entries are supported. If any PMP entries are implemented, then
all PMP CSRs must be implemented, but all PMP CSR fields are
WARL and may be hardwired to zero. PMP CSRs are only accessible
to M-mode."

In other words if you implement PMP even a little, you have to
impelement it all; but you can implement it in part by simply
returning 0 for a pmpcfg. Also, PMP address registers (pmpaddr)
don't have to implement all the bits. On a SiFive FU740, for
example, PMP only implements bits 33:0, i.e. a 34 bit address.

PMPs are just packed with all kinds of special cases. There are
no requirements that you read back what you wrote to the pmpaddr
registers. The earlier PMP code would die if the read did not
match the write, but, since pmpaddr are WARL, that was not
correct. An SoC can just decide it only does 4096-byte
granularity, on TOR PMP types, and that is your problem if you
wanted finer granulatiry. SoC's don't have to implement all the
high order bits either.

And, to reiterate, there is no requirement about which of the pmpcfg
are implemented. Implementing just pmpcfg15 is allowed.

The coreboot SBI code was written before PMP existed. In order
for coreboot SBI code to work, this patch is necessary.

With this change, a simple S-mode payload that calls SBI putchar
works:

1:
li a7, 1
li a0, 48
ecall
j 1b

Without this change, it will not work.

Getting this to build on RV32 required changes to the API,
as it was incorrect. In RV32, PMP entries are 34 bits.
Hence, the setup_pmp needed to accept u64. So,
uinptr_t can not be used, as on 32 bits they are
only 32 bit numbers. The internal API uses uintptr_t,
but the exported API uses u64, so external code
does not have to think about right shifts on base
and size.

Errors are detected: an error in base and size will result
in a BIOS_EMERG print, but not a panic.
Boots not bricks if possible.

There are small changes to the internal API to reduce
stack pressure: there's no need to have two pmpcfg_t
on the stack when one will do.

TEST: Linux now boots partly on the SiFive unmatched. There are
changes in flight on the coreboot SBI that will allow Linux to
boot further, but they are out of scope for this patch.
Currently, clk_ignore_unused is required, this requires a
separate patch.

Change-Id: I6edce139d340783148cbb446cde004ba96e67944
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2024-03-14 19:33:01 +00:00
091fb05312 soc/intel/xeon_sp: Add utils to detect domain0 and stack0
In Xeon-SP, the domain0, which is located at stack0, usually needs
special handling due to the compatible devices on it (HEPT, IO-APIC
and legacy IOs). This patch adds util function detect whether a
give domain or stack is with such a role.

TEST=intel/archercity CRB

Change-Id: I2f26b4ac54091c24c554f17964502c364288aa40
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-14 18:59:51 +00:00
e0c935b0dc soc/intel/xeon_sp: Add domain role checking utils
For Xeon-SP, there are 4 main domain roles (PCIe/CXL/IOAT/UBOX).
This patch adds util function to check whether a given domain
belongs to one of these roles, or a give device belongs to
a domain of the specific role.

TEST=intel/archercity CRB

Change-Id: I6b31c29564c774c27e86f55749ca9eca057a0cfe
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-14 18:58:32 +00:00
e357ac3321 soc/intel/xeon_sp: Use common _CRS code generation
Drop SoC specific code and use generic implementation provided
by pci_domain_fill_ssdt.

TEST=Booted on IBM/SBP1 to Ubuntu 22.04.
TEST=intel/archercity CRB

Change-Id: I8b0bc2eb02569b5d74f8521d79e0af8fee880c80
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80796
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-14 18:56:43 +00:00
abc274474a soc/intel/xeon_sp: Drop IIO_UDS argument
Use CONFIG_MAX_SOCKET instead of the IIO_UDS hob.
Allows to drop the argument in Xeon-SP common layer.

TEST=intel/archercity CRB

Change-Id: I05ec127f2bf84d3c242c3b0bca9709a0a7a4b52b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81181
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-14 18:55:29 +00:00
b94022525d util/nixshell: Add a dev shell for i386 arch
Add a Nix shell file to provide a simple environment for coreboot
development of i386 architecture. Currently, this environment is
capable of completing Tutorial Part 1 in https://doc.coreboot.org.

The Nix shell can be used by running the following command:

  $ nix-shell --pure util/nixshell/devshell-i386.nix

The `--pure` parameter is optional.

In Nixpkgs, there is a package called 'coreboot-toolchain'. It
fetches the source code of coreboot, build crossgcc, and export
it as output. With the binary cache mechanism of Nix, crossgcc
can be directly downloaded and used without compiling on user's
machine.

This Nix shell has been tested on a NixOS laptop and a Debian 12
server, and they both work fine.

Change-Id: Idcfe10be214e9bca590a62b8a207267493a4861f
Signed-off-by: Crabtux <crabtux@mail.ustc.edu.cn>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-14 18:15:51 +00:00
78b634a766 ec/hp/kbc1126: Use ec/acpi/ec.h instead of its own implementation
This also does some light cleaning up:
 - Place spaces in function names to make it easier to read.
 - Adds a newline to a console message.

TEST=Tested to work on HP ProBook 450 G3

Change-Id: I73e60c5baa9db6874e480ecef41cf1006150e081
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81204
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14 15:53:48 +00:00
d045074b91 vendorcode/edk2-stable202302: Remove wchar_t asserts
Remove those MSVC compiler defaults checks so that the GCC defaults for
wchar_t can be used. The FSP interface does not depend on wchar_t.

TEST: the resulting binaries are the same for intel/mtlrvp

Change-Id: I0ee1abc7e9ba46665838b63a6cfe0f4aa300114c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-03-14 15:53:09 +00:00
2fd6a6758b mb/google/nissa/var/glassway: Add 2nd touchscreen via SSFC config
Define SSFC bit 0-1 in coreboot for add 2nd BOE G7500 touchscreen.

BUG=b:329339069
BRANCH=firmware-nissa-15217.B
TEST=Check touchscreen can detect and function work.
[INFO ]  input: GTCH7503:00 2A94:A804 as /devices/pci0000:00/0000:00:15.1/i2c_designware.1/i2c-10/i2c-GTCH7503:00/0014

Change-Id: I85688919864e3cac1beb2442ef3e23fe9d5f916c
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-14 15:38:57 +00:00
f8df905e7b 3rdparty/fsp: Update submodule to upstream master
Updating from commit id dd98487:
2024-02-16 17:16:05 -0800 - (Fix EagleStreamFspBinPkg Path)

to commit id cc6399e:
2024-03-04 15:40:41 +0800 - (IoT MTL-UH & MTL-PS PV (3471_49) FSP)

This brings in 8 new commits:
cc6399e IoT MTL-UH & MTL-PS PV (3471_49) FSP
193dfbe Merge branch 'master' of https://github.com/intel/FSP
c89f32a IoT ADL-S MR7 (4445_05) FSP
bd31c89 IoT ADL-P MR6 (4445_04) FSP
738e498 Copy TGL FirmwareVersionInfoHob.h
9e7be91 IoT ADL-S MR7 (4445_05) FSP
56fb36c IoT ADL-P MR6 (4445_04) FSP
4707bc7 Elkhart Lake IPU2024.2 FSP

Change-Id: Ifa21950d6088b561f923587ca0f797de2983b67d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-14 10:17:09 +00:00
860202a317 mb/google/brox: Enable EC SW Sync
Now that EC software sync has been verified to work on Brox, we can
enable it by default.

BUG=b:326152804
BRANCH=None
TEST=Verify that SW sync occurs

Change-Id: I3d356c006fc448125605761f7328d1f1e203a7c4
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81211
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-13 22:34:02 +00:00
06e3dcac45 cbfs: Remove broken remnants of PAYLOAD_INFO feature
PAYLOAD_INFO is a very old feature that can add a key/value information
section to a payload file. It seems to have only ever been generated by
coreinfo and never really read by anything.

Since CB:1721 in 2012, the feature has been inadvertently broken in
practice since the `.note.pinfo` sections that contain the information
get discarded from the payload before cbfstool gets to see them. Since
CB:28647 in 2018, support for the section in the SELF loader was
(inadvertently?) dropped, so if someone actually fed cbfstool a payload
ELF that did have a `.note.pinfo` section, modern coreboot would refuse
to boot the payload entirely (which is probably not a good state to
leave things in).

This patch removes the code to generate PAYLOAD_INFO entries entirely,
but leaves the support to parse and extract those sections from old
payloads in place in cbfstool.

Change-Id: I40d8e9b76a171ebcdaa2eae02d54a1ca5e592c85
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-13 18:51:11 +00:00
092a1398f6 Revert "soc/intel/xeon_sp: Rewrite acpi_create_drhd"
This reverts commit 6995efbd1b.

Reason for revert: Submitted out of order and broke the coreboot build:

src/soc/intel/xeon_sp/uncore_acpi.c:275:6: error: call to undeclared function 'is_dev_on_domain0'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
  275 |         if (is_dev_on_domain0(iommu)) {
      |             ^
src/soc/intel/xeon_sp/uncore_acpi.c:343:35: error: call to undeclared function 'is_dev_on_ioat_domain'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
  343 |         if (CONFIG(HAVE_IOAT_DOMAINS) && is_dev_on_ioat_domain(iommu)) {
      |                                          ^
src/soc/intel/xeon_sp/uncore_acpi.c:423:4: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference]
  423 |                         assert(vtd_mmio_cap != 0xffffffffffffffff);
      |                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
src/include/assert.h:85:27: note: expanded from macro 'assert'
   85 | #define assert(statement)       ASSERT(statement)
      |                                 ^~~~~~~~~~~~~~~~~
src/include/assert.h:56:7: note: expanded from macro 'ASSERT'
   56 |         if (!__build_time_assert(x) && !(x)) {                          \
      |              ^~~~~~~~~~~~~~~~~~~~~~
src/include/assert.h:27:40: note: expanded from macro '__build_time_assert'
   27 |         (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0)
      |                                               ^~~~~~~~~~~~~~~~
src/include/assert.h:105:2: note: expanded from macro 'dead_code_t'
  105 |         *(type *)(uintptr_t)0; \
      |         ^~~~~~~~~~~~~~~~~~~~~
src/soc/intel/xeon_sp/uncore_acpi.c:423:4: note: consider using __builtin_trap() or qualifying pointer with 'volatile'
src/include/assert.h:85:27: note: expanded from macro 'assert'
   85 | #define assert(statement)       ASSERT(statement)
      |                                 ^
src/include/assert.h:56:7: note: expanded from macro 'ASSERT'
   56 |         if (!__build_time_assert(x) && !(x)) {                          \
      |              ^
src/include/assert.h:27:40: note: expanded from macro '__build_time_assert'
   27 |         (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0)
      |                                               ^
src/include/assert.h:105:2: note: expanded from macro 'dead_code_t'
  105 |         *(type *)(uintptr_t)0; \
      |         ^
src/soc/intel/xeon_sp/uncore_acpi.c:455:3: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference]
  455 |                 assert(ptr);
      |                 ^~~~~~~~~~~
src/include/assert.h:85:27: note: expanded from macro 'assert'
   85 | #define assert(statement)       ASSERT(statement)
      |                                 ^~~~~~~~~~~~~~~~~
src/include/assert.h:56:7: note: expanded from macro 'ASSERT'
   56 |         if (!__build_time_assert(x) && !(x)) {                          \
      |              ^~~~~~~~~~~~~~~~~~~~~~
src/include/assert.h:27:40: note: expanded from macro '__build_time_assert'
   27 |         (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0)
      |                                               ^~~~~~~~~~~~~~~~
src/include/assert.h:105:2: note: expanded from macro 'dead_code_t'
  105 |         *(type *)(uintptr_t)0; \
      |         ^~~~~~~~~~~~~~~~~~~~~
src/soc/intel/xeon_sp/uncore_acpi.c:455:3: note: consider using __builtin_trap() or qualifying pointer with 'volatile'
src/include/assert.h:85:27: note: expanded from macro 'assert'
   85 | #define assert(statement)       ASSERT(statement)
      |                                 ^
src/include/assert.h:56:7: note: expanded from macro 'ASSERT'
   56 |         if (!__build_time_assert(x) && !(x)) {                          \
      |              ^
src/include/assert.h:27:40: note: expanded from macro '__build_time_assert'
   27 |         (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0)
      |                                               ^
src/include/assert.h:105:2: note: expanded from macro 'dead_code_t'
  105 |         *(type *)(uintptr_t)0; \
      |         ^
src/soc/intel/xeon_sp/uncore_acpi.c:540:7: error: call to undeclared function 'is_domain0'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
  540 |                 if (is_domain0(dev_get_pci_domain(dev))) {
      |                     ^
src/soc/intel/xeon_sp/uncore_acpi.c:546:2: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference]
  546 |         assert(iommu0);
      |         ^~~~~~~~~~~~~~
src/include/assert.h:85:27: note: expanded from macro 'assert'
   85 | #define assert(statement)       ASSERT(statement)
      |                                 ^~~~~~~~~~~~~~~~~
src/include/assert.h:56:7: note: expanded from macro 'ASSERT'
   56 |         if (!__build_time_assert(x) && !(x)) {                          \
      |              ^~~~~~~~~~~~~~~~~~~~~~
src/include/assert.h:27:40: note: expanded from macro '__build_time_assert'
   27 |         (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0)
      |                                               ^~~~~~~~~~~~~~~~
src/include/assert.h:105:2: note: expanded from macro 'dead_code_t'
  105 |         *(type *)(uintptr_t)0; \
      |         ^~~~~~~~~~~~~~~~~~~~~
src/soc/intel/xeon_sp/uncore_acpi.c:546:2: note: consider using __builtin_trap() or qualifying pointer with 'volatile'
src/include/assert.h:85:27: note: expanded from macro 'assert'
   85 | #define assert(statement)       ASSERT(statement)
      |                                 ^
src/include/assert.h:56:7: note: expanded from macro 'ASSERT'
   56 |         if (!__build_time_assert(x) && !(x)) {                          \
      |              ^
src/include/assert.h:27:40: note: expanded from macro '__build_time_assert'
   27 |         (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0)
      |                                               ^
src/include/assert.h:105:2: note: expanded from macro 'dead_code_t'
  105 |         *(type *)(uintptr_t)0; \
      |         ^

Change-Id: I8b66177119ea5f55913a16aae06a3dcb807c2c64
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-13 18:02:03 +00:00
014ec7c704 Revert "soc/intel/xeon_sp: Rewrite acpi_fill_dmar"
This reverts commit 6833e8c01a.

Reason for revert: Submitted out of order and broke the coreboot build.

src/soc/intel/xeon_sp/uncore_acpi.c:275:6: error: call to undeclared function 'is_dev_on_domain0'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
  275 |         if (is_dev_on_domain0(iommu)) {
      |             ^
src/soc/intel/xeon_sp/uncore_acpi.c:343:35: error: call to undeclared function 'is_dev_on_ioat_domain'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
  343 |         if (CONFIG(HAVE_IOAT_DOMAINS) && is_dev_on_ioat_domain(iommu)) {
      |                                          ^
src/soc/intel/xeon_sp/uncore_acpi.c:423:4: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference]
  423 |                         assert(vtd_mmio_cap != 0xffffffffffffffff);
      |                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
src/include/assert.h:85:27: note: expanded from macro 'assert'
   85 | #define assert(statement)       ASSERT(statement)
      |                                 ^~~~~~~~~~~~~~~~~
src/include/assert.h:56:7: note: expanded from macro 'ASSERT'
   56 |         if (!__build_time_assert(x) && !(x)) {                          \
      |              ^~~~~~~~~~~~~~~~~~~~~~
src/include/assert.h:27:40: note: expanded from macro '__build_time_assert'
   27 |         (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0)
      |                                               ^~~~~~~~~~~~~~~~
src/include/assert.h:105:2: note: expanded from macro 'dead_code_t'
  105 |         *(type *)(uintptr_t)0; \
      |         ^~~~~~~~~~~~~~~~~~~~~
src/soc/intel/xeon_sp/uncore_acpi.c:423:4: note: consider using __builtin_trap() or qualifying pointer with 'volatile'
src/include/assert.h:85:27: note: expanded from macro 'assert'
   85 | #define assert(statement)       ASSERT(statement)
      |                                 ^
src/include/assert.h:56:7: note: expanded from macro 'ASSERT'
   56 |         if (!__build_time_assert(x) && !(x)) {                          \
      |              ^
src/include/assert.h:27:40: note: expanded from macro '__build_time_assert'
   27 |         (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0)
      |                                               ^
src/include/assert.h:105:2: note: expanded from macro 'dead_code_t'
  105 |         *(type *)(uintptr_t)0; \
      |         ^
src/soc/intel/xeon_sp/uncore_acpi.c:455:3: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference]
  455 |                 assert(ptr);
      |                 ^~~~~~~~~~~
src/include/assert.h:85:27: note: expanded from macro 'assert'
   85 | #define assert(statement)       ASSERT(statement)
      |                                 ^~~~~~~~~~~~~~~~~
src/include/assert.h:56:7: note: expanded from macro 'ASSERT'
   56 |         if (!__build_time_assert(x) && !(x)) {                          \
      |              ^~~~~~~~~~~~~~~~~~~~~~
src/include/assert.h:27:40: note: expanded from macro '__build_time_assert'
   27 |         (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0)
      |                                               ^~~~~~~~~~~~~~~~
src/include/assert.h:105:2: note: expanded from macro 'dead_code_t'
  105 |         *(type *)(uintptr_t)0; \
      |         ^~~~~~~~~~~~~~~~~~~~~
src/soc/intel/xeon_sp/uncore_acpi.c:455:3: note: consider using __builtin_trap() or qualifying pointer with 'volatile'
src/include/assert.h:85:27: note: expanded from macro 'assert'
   85 | #define assert(statement)       ASSERT(statement)
      |                                 ^
src/include/assert.h:56:7: note: expanded from macro 'ASSERT'
   56 |         if (!__build_time_assert(x) && !(x)) {                          \
      |              ^
src/include/assert.h:27:40: note: expanded from macro '__build_time_assert'
   27 |         (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0)
      |                                               ^
src/include/assert.h:105:2: note: expanded from macro 'dead_code_t'
  105 |         *(type *)(uintptr_t)0; \
      |         ^
src/soc/intel/xeon_sp/uncore_acpi.c:540:7: error: call to undeclared function 'is_domain0'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
  540 |                 if (is_domain0(dev_get_pci_domain(dev))) {
      |                     ^
src/soc/intel/xeon_sp/uncore_acpi.c:546:2: error: indirection of non-volatile null pointer will be deleted, not trap [-Werror,-Wnull-dereference]
  546 |         assert(iommu0);
      |         ^~~~~~~~~~~~~~
src/include/assert.h:85:27: note: expanded from macro 'assert'
   85 | #define assert(statement)       ASSERT(statement)
      |                                 ^~~~~~~~~~~~~~~~~
src/include/assert.h:56:7: note: expanded from macro 'ASSERT'
   56 |         if (!__build_time_assert(x) && !(x)) {                          \
      |              ^~~~~~~~~~~~~~~~~~~~~~
src/include/assert.h:27:40: note: expanded from macro '__build_time_assert'
   27 |         (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0)
      |                                               ^~~~~~~~~~~~~~~~
src/include/assert.h:105:2: note: expanded from macro 'dead_code_t'
  105 |         *(type *)(uintptr_t)0; \
      |         ^~~~~~~~~~~~~~~~~~~~~
src/soc/intel/xeon_sp/uncore_acpi.c:546:2: note: consider using __builtin_trap() or qualifying pointer with 'volatile'
src/include/assert.h:85:27: note: expanded from macro 'assert'
   85 | #define assert(statement)       ASSERT(statement)
      |                                 ^
src/include/assert.h:56:7: note: expanded from macro 'ASSERT'
   56 |         if (!__build_time_assert(x) && !(x)) {                          \
      |              ^
src/include/assert.h:27:40: note: expanded from macro '__build_time_assert'
   27 |         (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0)
      |                                               ^
src/include/assert.h:105:2: note: expanded from macro 'dead_code_t'
  105 |         *(type *)(uintptr_t)0; \
      |         ^

Change-Id: If919d6fa578a82fbb6bc5e1fd2adf4e9f59cab95
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81232
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-13 18:01:53 +00:00
e1ea9656cd payloads: allow selecting a file for FLAT_BINARY
085c97363e introduced a bug in that we
could not select a file to use, and, in fact, the payload was never
installed into the image in this case.

Add FLAT_BINARY to the predicate enabling a file selection dialog.

Change-Id: I8174b656b1e6ebb3663172f473e4070b30f19126
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81183
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-13 17:09:20 +00:00
186907c4f7 mb/google/brya/var/omniknight: Pull down USI_REPORT_EN in romstage
Pull down USI_REPORT_EN(GPP_C6) in romstage to solve
an abnormal peek pull high before BL_EN.

Because power sequence no meet spec, pre #comment36,
it may have ghost touch.

BUG=b:326337003
TEST=FW_NAME=omnigul emerge-brya coreboot, measurement of HW and test
touch detection by evtest

Change-Id: I66f4a7915f135927fbc0a16254dece202dfc23a2
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80769
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-03-13 14:50:59 +00:00
6833e8c01a soc/intel/xeon_sp: Rewrite acpi_fill_dmar
Rewrite the function by iterating IOMMU (Input/Output Memory
Management Unit) devices instead of iterating socket and stacks,
which is more aligned to coreboot infrastructure.

TEST=intel/archercity CRB

coreboot DRHD generation is compared, the order of sections are
changed as expected but the content is kept equvalient.

Change-Id: I4c1cbf8d8fc93f746640efc3a82c539dcb3fdee2
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-13 14:39:23 +00:00
6995efbd1b soc/intel/xeon_sp: Rewrite acpi_create_drhd
Obtain IOMMU (Input/Output Memory Management Unit) info and
enumerate devices using device utils instead of FSP HOB interface,
which might change across SoC generations and no ambiguity across
multiple PCIe segments.

TEST=intel/archercity CRB

coreboot DRHD generation log no changes before and after

Change-Id: Idcfa899c764ffe51db5ed202ead07ad7b6868864
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81048
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-13 14:39:13 +00:00
785a7aab14 soc/intel/mtl: Improve functions in soc_info.c
Remove debug message since it's static information.
Remove additional uint_8 varience and return below settings
directly:
1. CONFIG_SOC_INTEL_USB2_DEV_MAX
2. CONFIG_SOC_INTEL_USB3_DEV_MAX
3. MAX_TYPE_C_PORTS
4. CONFIG_MAX_TBT_ROOT_PORTS
5. CONFIG_MAX_ROOT_PORTS
6. CONFIG_MAX_PCIE_CLOCK_SRC
7. CONFIG_SOC_INTEL_UART_DEV_MAX
8. CONFIG_SOC_INTEL_I2C_DEV_MAX
9. CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX

BUG=none
TEST=Build and test on rex/karis, system can boot to OS

Change-Id: I26e882d2d9dcbef84718924aaab3864d89c58f39
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-03-13 14:00:22 +00:00
7ee7b137a7 util/inteltool: Add support for Alder Lake-N
Reference: Intel Processor and Intel Core i3 N-Series Datasheet,
Volume 1 of 2 (#759603)

Change-Id: Ib3225088fa08fb7e5a60c87d0f1f6b3001f5b562
Signed-off-by: Brandon Weeks <me@brandonweeks.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-03-13 13:59:31 +00:00
30bd24fd26 Docs: Update gerrit guidelines for -1 reviews
The -1 review authority has been moved from all registered users to
users in the "reviewers" category. The reviewers group is for people
who have submitted patches to coreboot.

This change is taking the project back to how it was before 2016, and
is not due to any issues that we're seeing. The reason it was initially
changed was that in 2016, before we required all comments to be resolved
so the patch could be merged, it was easy to overlook comments that
should have been addressed. Now that the process has changed, the -1
right is no longer needed for all users simply to bring attention to
the comment.

The feeling in the leadership meeting was that since it's relatively
easy to get to reviewer status, this should not be an undue burden on
anyone.

Change-Id: I0b7f3dcc80b9122b0f923e6703da73391654d26c
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-03-13 13:58:36 +00:00
7f92210485 soc/intel/xeon_sp: Add device find utils
For Xeon-SP, it's common pattern to find devices under specific
socket, stack and domain. This patch adds util function for
these operations.

TEST=intel/archercity CRB

Change-Id: I163eacae363334919fd66d571b7e0415e77bd52d
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-13 08:42:30 +00:00
873112ac34 mb/amd/birman_plus: Update glinda DXIO descriptors per schematics
glinda FP8 SOC PCIe lanes are updated per the Birman+ schematics 
document 105-D99700-00C revision 1.0. 

Change-Id: If22e57fc57b4824550f2dfa8b843a7809c85dbb6
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81036
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-12 14:47:11 +00:00
085c97363e payloads/Kconfig: Add flat binary as payload option
This add another choice option for adding a flat binary instead of an
ELF or some other payload. It keeps the IS_PAYLOAD_FLAT_BINARY hidden in
the menuconfig because it is generally not configurable but dependent on
the payload you selected.
CONFIG_PAYLOAD_OPTIONS has been exposed to be configurable in commit
f0055e4a81 (payloads/Kconfig: Add flat binary as payload option) as part
trying to enable flat binary payloads. CONFIG_PAYLOAD_OPTIONS do not
need to be configurable though unless you have a flat binary. The patch
therefore takes a different appraoch by adding a new payload type
besides PAYLOAD_ELF and PAYLOAD_FIT.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: If775e0846f9a5631da3fc103bdd9e6aea0be879a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-12 14:40:27 +00:00
564ef09ad6 mb/google/brya/var/xol: Use unified AP FW for UFS/Non-UFS SKUs
Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS to use unified AP
FW for UFS/Non-UFS SKUs.

BUG=b:326481458
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage

Change-Id: I85c3c1c7ccaae9d46b66d3e7a2efea6dc9056188
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81107
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-12 14:39:24 +00:00
531c45e075 soc/intel/common/block: Add support for watchdog
Implement watchdog for intel based platform by filling ACPI Watchdog
Action Table (WDAT) table.
The WDAT ACPI table encompasses essential watchdog functions, including:
- Setting and retrieving countdown/timeout values
- Starting and stopping the watchdog
- Pinging the watchdog
- Retrieving the cause of the last reboot, whether it was triggered by
the watchdog or another reason

The general purpose register TCO_MESSAGE1 stores the reason for the most
recent reboot rather than the original register TCO2_STS. This is
because the firmware must clear TCO2_STS, and it can't be reused for
storing this information for the operating system.

The watchdog is designed for use by the OS through certain defined
actions in the WDAT table. It relies on the ACPI Power Management Timer,
which may result in an increase in power consumption.

BUG=b:314260167
TEST=Enable CONFIG_ACPI_WDAT_WDT and CONFIG_USE_PM_ACPI_TIMER in the
config. Enable CONFIG_WDAT_WDT in the kernel config. Build and deploy
both firmware and kernel to the device. Trigger the watchdog by
performing the command: “cat > /dev/watchdog”. Wait approximately 30
seconds for the watchdog to reset the device.

Change-Id: Iaf7971f8407920a553fd91d2ed04193c882e08f1
Signed-off-by: Marek Maslanka <mmaslanka@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-12 13:01:13 +00:00
a0b7c06d07 soc/intel/xeon_sp: Rewrite acpi_create_satc
SATC is for RCiEPs (Root Complex Integrated EndPoints) but not
limited to IOAT domains. Rewrite the func by iterating all domains
and its RCiEPs. Currently the codes only support 1 PCIe segment.

TEST=intel/archercity CRB

coreboot SATC generation logs are unchanged before and after.

Change-Id: I1dfc56ccf279b77cfab4ae3457aa8799d2d57a34
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81049
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-12 11:32:42 +00:00
a454b62937 soc/intel/xeon_sp: Create CXL domains
SPR CXL IIO stack is divided into 2 PCI domains. The 1st domain
is a PCI domain with single bus number and PCIe RCiEPs (Root
Complex Integrated End Points) on it. The 2nd domain is a CXL
domain with remaining buses for CXL 1.0/1.1 end points and
possible SR-IOV (Single Root IO Virtualizaton) VFs (Virtual
Function) if any.

TEST=intel/archercity CRB

P.S. The SUT is not with CXL cards however we hope this refactor
could be integrated first as an improvement of the design.

Change-Id: I643bcfbae7b6e8cfe11c147cc89374bc6b4d5a80
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81099
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-12 11:32:00 +00:00
c4e68f6080 mb/google/brya: Create nova variant
Create the nova variant of the brask reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)

BUG=b:328711879
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_NOVA

Change-Id: Ie1cee43f0e2545288130bcc5152075603695c395
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
2024-03-11 16:00:04 +00:00
7c58dd6ce8 vc/amd/opensil/stub: add stub MPIO driver
Add a stub MPIO chip driver to the openSIL stub code, so that the
devicetree entries needed for the MPIO chip can already be added to the
mainboard's devicetree files. This driver won't do anything, but still
allows the register settings in the devicetree to be set to make
switching over to the actual openSIL code and the corresponding glue
code easier.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib4f5c232859b9abcd10bfa5c21e2f2c3a70b4b0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-11 14:05:16 +00:00
0c74b7c167 drivers/intel/fsp2_0: Perform MP init post FSP-MultiPhase SI Init
FSP can also make use of Multi-Processor services during its
multi-phase stages. If `USE_INTEL_FSP_MP_INIT' is set and
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI' unset coreboot cannot
take MP ownership as FSP-S may still use EDK2 MP services
concurrently.

TEST=verified on Lunar Lake RVP board (lnlrvp)

Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec92
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80691
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09 23:47:56 +00:00
5d0fa0de70 arch/riscv: Remove typedefs
typedefs violate our coding-style

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Id51eda53b6b53ed2cc66c0339c03c855c12c1bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81124
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2024-03-09 23:47:19 +00:00
56c3444d85 util/docker/Makefile: Create Documentation/_build for docker-build-docs
If the host directory of a bind mount does not exist, Docker will create
it. However, the newly created directory will be owned by root due to
the Docker service running within a root context. The docker command in
the recipe for docker-build-docs binds Documentation/_build to /data-out
within the container, so if it doesn't already exist, the documentation
builder will be unable to copy the HTML output into /data-out since it
runs with the same UID and GID as the host user.

By creating, if necessary, the _build directory before the `docker run`
command, there should always be an existing directory owned by the host
user for docker to bind /data-out to (ignoring the case of an existing
_build directory the current user does not have permission to write to),
avoiding the issue where it cannot write the output.

TEST: make -C util/docker docker-build-docs completes without issues
with and without an existing Documentation/_build directory

Change-Id: I6be9bc1fdca48f4d924f5c07cc261189ab6862fd
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81127
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-09 23:46:00 +00:00
a49dafc7d2 soc/intel/common/mp_init: Fix USE_INTEL_FSP_MP_INIT use-case
Commit 829e8e65b9 ("soc/intel: Use common codeflow for MP init")
brokes `USE_INTEL_FSP_MP_INIT' by making `init_cpus' function
static. This function needs to be accessible from
src/drivers/intel/fsp2_0/fsp_mpinit.c.

TEST=Verified on Meteor Lake rex board

Change-Id: Idb8cdfef7b4279da2c7dff344c95fe446a605934
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-09 23:45:00 +00:00
c8d47169f4 soc/intel/alderlake: Add Raptor Lake System Agent Device IDs
Add System Agent IDs for Raptor Lake SKUs based on RPL Datasheet
(Doc ID: 743844) & EDS Vol 1 (Doc ID: 640555).

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I805040c65852742f1bbc43b443e115bcb0a930aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81115
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09 23:44:09 +00:00
255f927515 soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP
With this patch, all domain creation logics are moved into the scope
of attach_iio_stack/chip_common.c for the ease of maintenance
and future SoC integration where the domain creation process for
specific stack types might be overridden.

TEST=intel/archercity CRB

1. Boot to CentOS 9 Stream Cloud.
2. Compare PCIe enumeration and ACPI table generation logs before and
and after this patch, no changes.

Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81098
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09 23:42:34 +00:00
0665d0e236 drivers/spi: Add GD25LR256E support
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id405ed990101a1ceda5e09c6db835f8302047f5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-09 23:39:06 +00:00
8e1e1acce7 mb/google/brya/var/xol: Disable unused controllers
Disable unused controllers in overridetree.cb by referring to xol proto2
schematics. Enabling unused controllers blocks entering s0ix.

- I2C3
- SATA
- PCIE RP8
- PCIE RP9
- GSPI1

BUG=b:328318578
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage

Change-Id: I1be7caf8234c32406aa2cff8fc7fe9fa39b16d89
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81105
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09 23:38:03 +00:00
db339b5492 mb/google/brya/var/xol: Update psys_pmax value to 122W
Update psys_pmax value to 122 from 145. This value is from internal
power team.

BUG=None
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage

Change-Id: I8bc58343d5736e2457db006972dc229e16d3fe59
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81104
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-09 23:36:56 +00:00
aba7a34df2 mb/google/brya/var/xol: Configure Acoustic noise mitigation
Enable Acoustic noise mitigation for xol. The setting values are from
internal power team.

- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to SLEW_FAST_4
- Set FastPkgCRampDisable VCCIA and VCCGT to 1

BUG=None
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage

Change-Id: I6165ae6ca73d1467a1d2cc7bd545298bd4c2f54f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81103
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-09 23:36:28 +00:00
f02e00a97a tests: Add DEBUG make commandline option to generate debug symbols
Sometimes when a test doesn't work it's convenient to run it through
GDB. This patch adds a variable you can set on the make commandline to
conveniently enable all the compiler flags needed to make that work.

Change-Id: I3ac80ad095e0b72cc3176cbf915d1f390cd01558
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81112
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-03-09 23:35:36 +00:00
52b81845de arch/riscv: Add SMP support for exception handler
Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68841
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
2024-03-09 23:34:25 +00:00
5787a4c53b mb/amd/onyx_poc/devicetree: explicitly assign PCIe engine type
Explicitly assign the 'PCIE' value to the 'type' field of the
corresponding MPIO chips in the devicetree. Since the mpio_type enum
element 'PCIE' has the value 0, this won't change the behavior, but
explicitly assigning this makes this easier to understand.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I84a364cf16c99ba11f67cf033962bbf2c982f6ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81095
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-09 23:32:12 +00:00
a8bde89bbd soc/intel/alderlake: Remove the guard for CnviWifiCore
The CnviWifiCore UPD exists for ADL (version 4263) and RPL
(version 4415). Remove the guard so it is set correctly.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9943ee43a442a43d75e78d1551e46dcea39db357
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81079
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09 23:29:31 +00:00
7e5db6da89 mb/google/brox: Enable Wake on WLAN for SKU1
For SKU1, wake pin is WLAN_PCIE_WAKE_ODL.
Update gpio config and corresponding ACPI for WoWLAN.

BUG=b:327379404
BRANCH=None
TEST=Boot image on SKU1 and check Wake on WLAN from S0ix.

Change-Id: I04c35da2c9ac57cafdf7f7a35d83ab2e7a05fe4a
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2024-03-09 23:28:01 +00:00
89e056bdf1 util/smmstoretool: support processing ROMs
Input file is parsed for FMAP and SMMSTORE region which is used if
found.  Otherwise, the whole file is assumed to be the region.  Passing
an image with FMAP that lacks SMMSTORER is an error.

Change-Id: Ieab555d7bbcfa4dadf6a5070d1297acd737440fb
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-09 23:26:41 +00:00
04bd965143 util: add smmstoretool for editing SMMSTORE
Offline SMMSTORE variable modification tool.  Can be used to
pre-configure ROM image or debug EFI state stored in a dump.

Change-Id: I6c1c06f1d0c39c13b5be76a3070f09b715aca6e0
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-09 23:22:55 +00:00
7a51acfbe9 cpu/x86/smm: Set up page tables in safe SMRAM
Relying on page tables being in RO flash is not safe in every setup,
therefore set up some page tables in SMRAM that the permanent smihandler
can use.

Tested on QEMU.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Icb3086abd577b9abb9966dd910a264a873ace4ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80336
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09 23:15:34 +00:00
1879b6a34a drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
Intel Firmware Support Package 2.4 specification (document 736809)
brings some significant changes compared to version 2.3 (document
644852):

1. It supports FSP-M multi-phase init. Some fields have been added to
   the FSP header data structure for this purpose.

2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be
   used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively.

3. It support 64-bits FSP but 64-bits support will be provided by
   subsequent patch.

Note that similarly to what is done for silicon initialization,
timestamps and post-codes are used during the memory initialization
multi-phase.

[736809]
https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf

[644852]
https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-External-Architecture-Specification.pdf

TEST=verified on Lunar Lake RVP board (lnlrvp)

Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-03-08 16:59:25 +00:00
7eb014eba2 drivers/intel/fsp2_0: Add "silicon" to the multiphase callback name
The `platform_fsp_multi_phase_init_cb' callback is specific to FSP-S,
let's rename it 'platform_fsp_silicon_multi_phase_init_cb' to avoid
any confusion.

Change-Id: I86b69e2069f08023e6f48464f6df4593710aa9ee
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-08 16:59:10 +00:00
cee8eb25c8 vc/intel/fsp/mtl: Update header files from 3471_85 to 3471_91
Update header files for FSP for Meteor Lake platform to version 3471_91,
previous version being 3471_85.

FSPM:
1. Address offset changes

BUG=b:327688959
TEST=Able to build and boot google/rex to ChromeOS.

Change-Id: I5a71232018dfefec63b0a83d1e87717e238a4a0a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80782
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-08 07:15:22 +00:00
7d83441ae0 soc/intel/xeon_sp/spr: Fix IOAT resources
Do not generate empty mem32 resources for CPMx or HQMx stacks.
Switch existing arguments to make sure that base is bigger than
limit to indicate that the resource is invalid.

Change-Id: I679563e97c33c7ee35d402674972e55f521eafa8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80793
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-07 13:30:11 +00:00
64d2fd0777 soc/intel/xeon_sp: Share numa.c among Xeon-SP platforms
NUMA will be supported by SPR and future generations.

TEST=intel/archercity CRB

Change-Id: I0d494f8e560059d9c8d5338cef9a6ffe34e59e26
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-07 13:28:01 +00:00
04fde7ed37 soc/intel/xeon_sp: Unshare UDK binding among Xeon-SP platforms
TEST=intel/archercity CRB

Change-Id: I285549daad87fe1ad6e8a94853e0a92cd5930e04
Signed-off-by: Li, Jincheng <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81041
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-07 13:27:17 +00:00
a5bdf8e8df soc/intel/xeon_sp: Add memory type check utils
FSP memory type representations change across Xeon-SP SoCs.
This patch adds type check utils to abstract the differences.

TEST=intel/archercity CRB

Change-Id: I2f5f3c0f16dc50bc739146e46afce2e5fbf4f62c
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-07 13:26:49 +00:00
cb6a35edd5 arch/riscv: Makefile.mk: Fix incorrect config variable
ARCH_RISCV_PMP should be CONFIG_ARCH_RISCV_PMP. Rename it.

Change-Id: I2a22acae5cd9f30e01c491653bf7fc7b7765d815
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81086
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-06 23:48:52 +00:00
e067003327 vc/amd/opensil/genoa_poc/memmap: use GiB define
Use the GiB define to make the 4 GiB boundary used in some places in the
code a bit easier to read.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I81877a5d293c883d2e31bdb18ae3b22b8a44e62f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-06 19:40:02 +00:00
d4a1ba47b9 vc/amd/opensil/genoa_poc/memmap: use get_top_of_mem_below_4gb
Use get_top_of_mem_below_4gb instead of open-coding the functionality.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5885e9ad89ed9f0aa657c56804e98c352267267f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-06 19:39:42 +00:00
a640b123f5 amdfwtool: Change&Record the current table in integration function
Align with the function integrating PSP FWs. And it is the integration
function's responsibility.

TEST=Identical test on all AMD platforms

Change-Id: I1a98614f3a5756a462b01085e9565b52cf9a9343
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-06 11:05:43 +00:00
e35c502a57 amdfwtool: Move code related to getting options to a new file
Cleanup the messy code. The code left in main is all about filling
tables.

To help to do this,
1. Some local variables are put into global struct.
2. Add some functions. Set some functions to global.

TEST=Identical test on all AMD platforms

Change-Id: Ia25c3fd5de7ae48054359f0f6551d91d7a4f6828
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-06 11:05:07 +00:00
fc3fcf2103 amdfwtool: Set the table size for L1 separately
The space defined by size of the L1 table can not overlap with ISH
header. For other cases, the size defines the directory and its
content.

The PSP spec does not say it quite clearly. This change is partly
based on guess and can make extraction tool work so far.

Change-Id: Id4fbc6d57d7ea070a9478649a96af92be9441289
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-06 11:04:20 +00:00
40e0748ef8 soc/intel/xeon_sp: Add ACPI names
Set the unused 'name' property of the domain device and store
the ACPI name. Every IIO stack can have multiple domain devices,
each owning a subset of the available bus range within the stack.

The name will be used in future changes to generate ACPI names
in SSDT code generation. It can also be used to identify the domain
type by looking at the first two characters of the name.

Change-Id: Ic4cc81d198fb88300394055682a3954bf22db570
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80792
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-06 09:40:13 +00:00
384a9c973c mb/google/nissa/var/glassway: Tune eMMC DLL values
Update eMMC DLL values to improve initialization reliability.

BUG=b:327123701
TEST=Improve reboot on MB with eMMC smoothly.

Change-Id: Ice9ee217acf7dc6e3e704bc82529e0b9a8faf184
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80779
Reviewed-by: Shawn Ku <shawnku@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
2024-03-06 08:30:37 +00:00
d31b1091e7 mb/sifive/sifive-unmatched: add support for spi1 x4 mode
Tested on an unmatched, both SPI1 x1 and x4
work now.

Change-Id: Ida7f195eb6e4fc85018ceb83cf317595127c4af5
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-06 04:33:52 +00:00
4d9549b95f soc/intel: Add definition of D0 stepping for TigerLake Halo
Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8
Signed-off-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-05 23:29:17 +00:00
5015a35f48 soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E ports
ACPI _PRT method was missing from PEG (SoC PCI-E) links, resulting in OS
complaining about interrupt routing.

'pcieport 0000:00:06.0: can't derive routing for PCI INT A'
'nvme 0000:04:00.0: PCI INT A: not connected'
'Interrupt: pin A routed to IRQ -2147483648'

TEST=Boot Linux and Windows 10 on TGL-H platform with PEG0/PEG1
populated with PCI-E devices - Radeon RX 7800XT and Kingston KC3000 NVME
SSD. Check logs and stability while running 3D application and disk
benchmark at the same time.

Change-Id: If102522efa1a67b362b14d859d9e27a37bad85a4
Signed-off-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80848
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-05 23:28:21 +00:00
07cfe5392a soc/intel/xeon_sp: Move MEM_ADDR_64MB_SHIFT_BITS to Xeon-SP
Move MEM_ADDR_64MB_SHIFT_BITS from FSP headers to Xeon-SP common layer
to reduce the dependency.

TEST=intel/archercity CRB

Change-Id: I4e1a652ad58233f7514cb9b23813d75144b8d435
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-05 21:40:56 +00:00
dca7eb5125 mb/google/oak: Don't build the ChromeEC codebase by default
Currently, the oak boards are the only boards that build the ChromeEC
by default as a part of the coreboot build.

As a part of replacing the chromeec submodule with a different build
mechanism, disable this default.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Idd4fe45e52dbdd1c8dccf0d2c09d5cf6d61aa839
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81023
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
2024-03-05 21:37:37 +00:00
0201d989f2 drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug
Starting with Intel CPX there is a bug in the reference code during
the Pipe init. This code synchronises the CAR between sockets in FSP-M.
This code implicitly assumes that the FSP heap is right above the
RC heap, where both of them are located at the bottom part of CAR.

Work around this issue by making that implicit assumption done in FSP
explicit in the coreboot linker script and allocation.

TEST=intel/archercity CRB

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>

Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80579
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-05 21:26:39 +00:00
67166a7eb2 lib/program.ld: Make (NOLOAD) and to_load more explicit
(NOLOAD) indicates that the section occupies no space in the file, but
does take up space in memory during process execution. It's typically
used for bss sections which contain uninitialized global/static
variables.

to_load makes sure the section is part of the program headers. This is
needed for instance with relocatable stages to know how much memory the
program will use.

Although the BFD linker makes some good guesses making this a NOOP,
other linkers like LLD need to mark these sections more explicitly.

Change-Id: Ic14543ba580abe7a34c69bba714eae8cce504977
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80803
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-03-05 21:22:59 +00:00
ee1cb8f463 mb/emulation/qemu-riscv: Change to -bios option
This changes the virt target so that it can be run with the -bios option
and a pflash backend for the flash. QEMU can now be run as follows:

qemu -M virt -m 1G -nographic -bios build/coreboot.rom \
        -drive if=pflash,file=./build/coreboot.rom,format=raw

coreboot will start in DRAM, but still have a flash to put CBFS onto and
to load subsequent stages and payload from.

Tested bootflow:
coreboot -> OpenSBI -> Linux -> u-root

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2024-03-05 18:57:29 +00:00
3304c1cbad mb/asus/p8x7x-series: Revert to native max_mem_clock_mhz of 800
The setting was reduced to 666 for native raminit in commit
7039edd2da (SNB+MRC boards: Migrate MRC settings to
devicetree) based on boot test results at the time.

With more changes merged, additional native raminit tests were
done on p8z77-m. It is now possible for previously failing
memory configurations to operate at full speed. This, combined
with multiple reports on gerrit that this family does work at
800, warrants returning the setting to what it was.

Change-Id: I1fbe9c8d076fcd633f71424d60585681c40677c4
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79726
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-05 16:57:01 +00:00
12756e6794 Revert "vc/intel/edk2: Remove edk2-stable202111 support"
This reverts commit b5f6320c69.

ADL-N FSP uses 202111 Edk2. There are structure definition changes
between 202005 and 202111. One of change is in FSP_INFO_HEADER structure.
This patch is to bring back support of edk2-stable202111.

BUG=b:296433836
TEST=Able to build google/crassk.

Change-Id: Id1d3e2c5b368a479e637f3ab3d18e242607849ed
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-05 14:06:34 +00:00
1b53eb1077 ec/google/chromeec: Enclose Kconfig in 'if/endif' block
Instead of having things depend on EC_GOOGLE_CHROMEEC, just put an if/
endif block around the configs.

The 'source' line stays outside of the if block because the source
always happens, even if it's inside an if/endif block. Each of the
sub-Kconfigs here already has an if/endif block surrounding the
contents.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If88ba7d36ae04d879332037292c5cf9a3c8c3cab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2024-03-05 14:04:51 +00:00
cc5cef633d mb/google/brya/var/xol: Add VGPIO configurations for PEG60
Add VGPIO configurations for NVMe on PEG60.

BUG=b:326481458, b:372086400
BRANCH=firmware-brya-14505.B
TEST=Verified DUT could detect NVMe.
     Install ChromeOS into NVMe and boot from it.

Change-Id: I5520dc2a4bf6e788701a774674d223b7e8ad5b44
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-05 14:04:29 +00:00
735524529a mb/google/nissa/var/gothrax: Add probe and GPIO config for touchpanel
Add FW_CONFIG probe to separate touch panel settings.
  TOUCH_PANEL_ENABLE/TOUCH_PANEL_DISABLE
Use different gpio tables based on the value of TOUCH_PANEL.

BUG=b:325987249
TEST=emerge-nissa coreboot and run in DUT

Change-Id: I23c62406a932815ff1cfafe05b70468b1f9cca54
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kyle Lin <kylelinck@google.com>
2024-03-05 11:58:26 +00:00
809d8c5d28 soc/intel/xeon_sp: Drop unused helper functions
Change-Id: Ib319643f6b0b91d8c5854da531e035d333f04d75
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80143
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-05 11:27:36 +00:00
47e6882891 soc/intel/xeon_sp: Drop code to locate the UBOX bus
Drop the code to retrieve the UBOX bus numbers. Only keep
a minial function that works when called from socket0 to retrieve
the bus for UBOX(1).

Change-Id: I2b18f02f62b69ec7c73cd5665102cb6bfc6e64b5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80102
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-05 11:26:58 +00:00
6cb6bfff38 soc/intel/xeon_sp/util: Enhance lock_pam0123
- Only compile code in ramstage
- Lock PAM on all sockets
- Instead of manually crafting S:B:D:F numbers for each PCI device
  search for the devices by PCI vendor and device ID.

This adds PCI multi-segment support without any further code
modifications, since the correct PCI segment will be stored in the
devicetree.

Change-Id: Ic8b3bfee8f0d02790620280b30a9dc9a05da1be8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-05 11:24:38 +00:00
3b0d573dc2 soc/intel/cmn/cse: Deprecate CONFIG_SOC_INTEL_CSE_RW_VERSION
This patch marks CONFIG_SOC_INTEL_CSE_RW_VERSION as deprecated, as
future platforms will automatically determine the CSE RW version using
CSE RW partition.

BUG=b:327842062
TEST=CSE RW update successful on Screebo.

Change-Id: I8c3e5c759e4d9a43c3bce3a0c032086f17592a67
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80924
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2024-03-05 10:17:22 +00:00
cac81cd120 vc/google/chromeos: Implement dynamic ChromeOS boot logo selection
* Introduces logic to display context-specific boot splash logos.
* Logo selection considers:
    * Chromebook-Plus hardware compliance (using factory_config).
    * VPD-based product segmentation (soft-branded vs. regular
      chromebook).
    * Default Chromebook logo as fallback for regular Chromebook.

This patch fixes the problem where existing logic was unable to pick
correct ChromeOS boot splash logo based on the product segmentation.

Relation between product segment and boot splash screen:

1. Chromebook-Plus Hard-branded device: Renders "cb_plus_logo.bmp" logo
2. Chromebook-Plus Soft-branded device: Renders "cb_plus_logo.bmp" logo
3. Regular Chromebook device: Renders "cb_logo.bmp"

BUG=b:324107408
TEST=Verified logo selection based on compliance and product
requirements.

Change-Id: I9bb1e868764738333977bd8c990bea4253c9d37b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-05 10:17:08 +00:00
dc073ca75c drivers/vpd: Add vpd_get_feature_level() API
This patch introduces the vpd_get_feature_level() API to specifically
extract the "feature_level" field from the "feature_device_info" VPD
key.

This is used to distinguish between Chromebook-Plus and regular
Chromebook devices.

The previous vpd_get_feature_device_info() API is removed as
vpd_get_feature_level() is enough to find VPD and extract the data.

Note: The new API decodes the base64-encoded "feature_device_info" VPD
data.

BUG=b:324107408
TEST=Able to build and boot google/rex0.

Change-Id: I76fc220ed792abdfefb0b1a37873b5b828bfdda8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80805
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-05 10:17:00 +00:00
3266dcbff0 mb/google/brya/var/dochi: Add wifi sar table
Add wifi sar table for dochi

BUG=b:326137130
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Change-Id: Iaf90756eb318bef1ffcda9368a976c0ca209a100
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-05 02:49:22 +00:00
8e365396d4 riscv/mb/qemu: fix DRAM probing
Current version of qemu raise an exception when accessing invalid
memory.  Modify the probing code to temporary redirect the exception
handler like on ARM platform.
Also move saving of the stack frame out to trap_util.S to have all at
the same place for a future rewrite.

TEST=boots to ramstage
Change-Id: I25860f688c7546714f6fdbce8c8f96da6400813c
Signed-off-by: Philipp Hug <philipp@hug.cx>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36486
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04 23:43:46 +00:00
f3ae0f0cfb mb/google/guybrush: turn off SD ASPM L1.1/L1.2
Turn off SD ASPM L1.1/L1.2 as w/a for wlan DMA resume failure

We completed 4 runs for each of the 2 tests - power_idle and power_VideoCall. Here are the averages for both the tests:

L1ss disabled SD plugged power idle test: 735.3875
L1ss enabled SD plugged power idle test: 737.2335

L1ss disabled SD plugged power video test: 333.29325
L1ss enabled SD plugged power video test: 333.442


BUG=b:254382832
TEST=test pass over 10k cycles

Signed-off-by: Jason Nien <finaljason@gmail.com>
Change-Id: I4d903f0f6333ffa18069e42be3c932aeae8013d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80237
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04 23:12:22 +00:00
59495c929b LinuxBoot/targets/u-root.mk: Correct config for UROOT_ARCH
The using config string for amd64 as UROOT_ARCH contains typo

Correct using CONFIG_LINUXBOOT_X86_64

BUG = N/A
TEST = Build boot facebook monolith

Change-Id: I6cfefb3f8e4e61bd56ca0fe3239000db8c07b088
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77605
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04 23:08:14 +00:00
fa97970e85 payloads/depthcharge: Add DEPTHCHARGE_REPO and DEPTHCHARGE_BRANCH
Move hard-coded repo and repo name to Kconfig as default value

DEPTHCHARGE_REPO default to:
https://chromium.googlesource.com/chromiumos/platform/depthcharge

DEPTHCHARGE_BRANCH default to:
origin/main

When DEPTHCHARGE_MASTER=y, DEPTHCHARGE_BRANCH can be used to point
out a particular branch.

This change enable to use mirrored internal depthcharge repo and
branch for early SOC development (before upstreaming SOC and
dephthcharge code).

TEST=Build coreboot and check the repo remote link from:
payloads/external/depthcharge/depthcharge

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Icca10aa770b7b7a6e010f58bcf1e4f0a3401681a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80726
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
2024-03-04 22:47:08 +00:00
d6850f3109 payloads/LinuxBoot: Build the linux kernel with -j $(CPUS)
Build the Linux kernel with the same amount of jobs as coreboot.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ie7af5aef4560b8d4dd840d9c578f8a2a4c387400
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78644
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-04 22:36:27 +00:00
2fa8caba50 lib/ramdetect: Limit probe size to function argument
This avoids probing above the function argument where other things than
DRAM could be mapped.

Change-Id: Ie7f915c6e150629eff235ee94719172467a54db2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-03-04 22:15:53 +00:00
b6efe17137 arch/x86/Kconfig: Deduplicate ARCH_SUPPORTS_CLANG selection
Change-Id: Iced69e0bce345748a43eb1c14bf17a683e26ba60
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81020
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-04 18:25:31 +00:00
13e2042ff5 mb/dell: Add OptiPlex 7020/9020 port
The OptiPlex 7020 and 9020 use physically identical motherboards.

WARNING: PWM fan control doesn't work via the EC and the fan runs at a
fixed speed. There is likely more EC init to reverse engineer.

Each model comes in the following form factors:
- 7020: SFF, MT
- 9020: USFF (not currently supported), SFF, MT

(7020 SFF) Boots Linux and Windows 10:
- Tested with an i3-4160 and i5-4460
- DRAM init works using the MRC (4G, 4G+4G)
- iGPU init works using libgfxinit (VGA, 2x DP)
- PCIe 16x: tested, ok
- PCIe 4x: tested, ok
- All USB2 and USB3 ports work
- SMSC SCH5555 Super I/O: serial works, PS/2 untested
- Audio: back and front output works, internal speaker works,
         mic inputs untested
- Ethernet: tested, works

(9020 MT)
- Tested by Michael Büchler (thanks for the overridetree)

Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55232
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-03-04 18:24:40 +00:00
1e2821882f nb/haswell: Disable iGPU when dGPU is used
This is usually is handled by Haswell mrc.bin, disabling VGA
decode on the iGPU when a dGPU is installed. However, Broadwell
mrc.bin does not, so the iGPU and dGPU are both enabled.

This patch disables legacy VGA cycles for iGPU, under such
conditions. It has been tested on Broadwell mrc.bin when
using a graphics card on Dell OptiPlex 9020 SFF (currently
under review at this time of writing, submitted by Mate
Kukri).

This patch has also been tested when Haswell mrc.bin is used,
and there are seemingly no breaking changes caused by it.

Change-Id: I1df0a3aa42f8475b7741007bf3e28c2e089d916b
Signed-off-by: Leah Rowe <info@minifree.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-04 15:22:21 +00:00
787b2b44af mb/google/brya: Enable CSE telemetry for ADL-N
BUG=none
TEST=Verify CSE telemetry data in boot time data on Yahiko.

Before:
```
yahiko-rev9 ~ # cbmem -t
71 entries total:

   0:1st timestamp                                     197,583 (0)
```

After:
```
yahiko-rev9 ~ # cbmem -t
76 entries total:

 990:CSME ROM started execution                        0
 944:CSE sent 'Boot Stall Done' to PMC                 49,000
 945:CSE started to handle ICC configuration           49,000 (0)
 946:CSE sent 'Host BIOS Prep Done' to PMC             51,000 (2,000)
 947:CSE received 'CPU Reset Done Ack sent' from PMC   168,000 (117,000)
   0:1st timestamp                                     195,861 (27,861)
```

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I3f90d0462cb766655bf8e59a90bc550ceefb2256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79768
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04 15:13:39 +00:00
b1ed9f4f87 mb/system76/adl,rpl: Add 50ms timeout for PCIe 3.0 RPs
The FSP may fail to detect PCIe 4.0 devices in PCIe 3.0 slots on S3
resume. This issue has only been experienced on lemp12, and only with
Samsung drives, but implies it could happen on other systems or with
other drives as well. A timeout of 50ms is arbitrarily chosen.

Tested on lemp12 with Samsung 980 PRO (FW: 3B2QGXA7, 5B2QGXA7) and 990
PRO (FW: 4B2QJXD7) drives.

Change-Id: I4f44fc429c52e407b7566d6bb6dd31b2cf85c48d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80756
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04 14:54:09 +00:00
a78388508c mb/system76/adl: Remove duplicate PchHdaAudioLinkHdaEnable
This UPD is hooked up in devicetree since commit 854bd492fc
("mb/{system76,msi}: Enable PchHdaAudioLinkHdaEnable via devicetree").

As these boards were in development when the change happened, they still
had the UPD set via romstage. Remove them now so they are only set in
devicetree.

Change-Id: I393e2c7b0134a31feae20f8992d7fd447ff7ee59
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80755
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-03-04 14:53:42 +00:00
daa4fb2ca2 mb/system76/adl,rpl: Enable PchHdaSdiEnable
Commit 4a58d14506 ("soc/intel/alderlake: Hook up UPD PchHdaSdiEnable")
and commit 2d48238618 ("soc/intel/alderlake: Set PchHdaSdiEnable for
Alder Lake") hooked up this UPD in devicetree, causing the FSP default
to be overridden (now disabled by default).

Enable SDI to fix the following error:

    [DEBUG]  PCI: 00:00:1f.3 init
    [DEBUG]  azalia_audio: base = 0xbfbcc000
    [DEBUG]  azalia_audio: No codec!
    [DEBUG]  PCI: 00:00:1f.3 init finished in 5 msecs

Tested on gaze17-3050: Speaker output works again.

Change-Id: Iceac1faec939ce9eea68c335929f96ec5f2bd132
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-03-04 14:53:18 +00:00
8b495c2706 mb/system76/rpl: Add TCSS ACPI for all boards
Fixes ACPI errors about missing methods:

    ACPI BIOS Error (bug): Could not resolve symbol [_SB.PCI0.TDM0], AE_NOT_FOUND (20230628/dswload2-162)
    ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230628/psobject-220)
    ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x0010)
    ACPI BIOS Error (bug): Could not resolve symbol [_SB.PCI0.TRP0], AE_NOT_FOUND (20230628/dswload2-162)
    ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230628/psobject-220)

Tested on lemp12: ACPI errors in dmesg are gone.

Change-Id: I9b79cb04f57a27af2a6c8f3118e573f7ac0041e5
Signed-off-by: Dan Campbell <dan@compiledworks.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80791
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04 14:52:35 +00:00
d45f6ea35f mb/google/brox: Update Verbtable for beep functionality
For boot beep functionality, relevant register values are
required to be updated.

BUG=b:324528901
BRANCH=None
TEST=Build & verified Boot Beep functionality on Brox

Change-Id: If236c8ac173a279db676af412377fa4e4122c1cd
Signed-off-by: poornima tom <poornima.tom@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80416
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04 14:51:44 +00:00
92a9d93144 amdfwtool: Move the functions to handle_file.c
Change-Id: I4cfec13cbc2a86dc352758541cce915a838e0d0f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78305
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04 14:50:53 +00:00
80b853e626 amdfwtool: Remove the function's dependency to ctx
This is for next CL to move the write_body to another source,
handle_file.c.
https://review.coreboot.org/c/coreboot/+/78305

Removing amdfwtool_cleanup in write_body will not change the
result. Write_body returns to main and amdfwtool_cleanup still ends up
getting called.

Change-Id: I639828498fa45911f430500735e90ddc198b6af5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78304
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04 14:50:44 +00:00
bcdbb44805 soc/intel/cmn/cse: Use CSE RW partition version directly for CBFS entry
This patch automates the process of determining the CSE RW version used
for the CBFS entry, eliminating the need for manual configuration in
CONFIG_SOC_INTEL_CSE_RW_VERSION.

How to get CSE RW Version:
1. Open CSE RW file as per CONFIG_SOC_INTEL_CSE_RW_FILE
2. Read offset 16 (0x10) to know the CSE version
3. Format:
   - CSE_VERSION_MAJOR : offset 16-17
   - CSE_VERSION_MINOR : offset 18-19
   - CSE_VERSION_HOTFIX: offset 20-21
   - CSE_VERSION_HOTFIX: offset 22-23

Benefits:
 - Removes error-prone manual version updates.
 - Prevents boot loops due to mismatched CSE RW versions (actual vs config)
 - Eliminates the need for SKU-specific CSE version limitations.

BUG=b:327842062
TEST=CSE RW update successful on Screebo with this patch.

Example Debug Output:

[DEBUG]  cse_lite: RO version = 18.0.5.2066
[DEBUG]  cse_lite: RW version = 18.0.5.2107

Change-Id: I0165d81b0e4b38e0e097956f250bb7484d774145
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80923
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04 13:34:03 +00:00
4efd2e3aae mb/google/brya/var/xol: Update NVMe clock source index to 0
Change ClkSrc index for NVME to 0 from 1 by referring to proto2
schematics.

BUG=b:326481458
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage

Change-Id: I7ea1cd7d8e16d4cee953e931d2f1829eae7d1978
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80768
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-04 02:57:30 +00:00
b44a388821 Revert "Revert "mb/sifive: Add Hifive Unmatched mainboard""
This reverts commit ec7b480760.

Reason for revert: <Reland>

I made the commit out of order with the fu740 commit; that's now
merged so there should be no problem.

Signed-off-by: ron minnich <rminnich@gmail.com>

Change-Id: I2fb8c2e0a7fcd5f26f4a004e0949332b108b6fcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
2024-03-03 22:57:54 +00:00
2ccb8e7891 soc/sifive/fu740: Add FU740 SOC
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4a8fe02ef0adcb939aa65377a35874715c5ee58a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
2024-03-03 21:20:03 +00:00
ec7b480760 Revert "mb/sifive: Add Hifive Unmatched mainboard"
This reverts commit e26bcaefbe.

Reason for revert: Patch submitted out of order.

Change-Id: I71c024b13411c4e0c9b4d6358f9cd31c57bbbfe2
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2024-03-02 18:09:05 +00:00
e26bcaefbe mb/sifive: Add Hifive Unmatched mainboard
working:
Linux v6.3.5
poweroff via Linux PMIC driver
UART console output
SPI -> SDCARD
I2C -> PMIC
16 GB LPDDR4 memory
VSC8541XMV-02 (gigabit ethernet PHY)
PCIe x16 Slot
M.2 NVMe Slot
MSEL: only '1100' has been tested

untested:
M.2 WiFi/Bluetooth Slot

tested bootflow:
ZSBL -> coreboot --FDT-> Linuxboot -> uroot --kexec-> ubuntu

defconfig used:
CONFIG_VENDOR_SIFIVE=y
CONFIG_BOARD_SIFIVE_HIFIVE_UNMATCHED=y
CONFIG_PAYLOAD_NONE=n
CONFIG_PAYLOAD_ELF=y
CONFIG_PAYLOAD_FILE="[path-to-linux]/arch/riscv/boot/Image"
CONFIG_PAYLOAD_IS_FLAT_BINARY=y
CONFIG_PAYLOAD_OPTIONS="-l 0x82000000 -e 0x82000000"
CONFIG_COMPRESSED_PAYLOAD_LZMA=y

uroot kexec command:
kexec -d --cmdline "console=ttySIF0 root=/dev/mmcblk0p1 debug" \
         --initrd /mnt/boot/initrd.img-6.5.0-9-generic \
                  /mnt/boot/vmlinuz-6.5.0-9-generic

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ife0afdce89d5a1a1b936c30c8027f1bc191b8c53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
2024-03-02 16:36:33 +00:00
62407ac197 mb/google/nissa/var/glassway: Select drivers for gpio-keys and GL9750
Add 2 configuration on Kconfig for glassway.
- DRIVERS_GENERIC_GPIO_KEYS
- DRIVERS_GENESYSLOGIC_GL9750

BUG=b:319071869
BRANCH=firmware-nissa-15217.B
TEST=Local build successfully and boot to OOBE normally.

Change-Id: Id7e358d2f472cd435d2828f6256f5ee91dfb8ef6
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80766
Reviewed-by: Shawn Ku <shawnku@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-02 06:33:31 +00:00
98ecb1612c lint: Make lint work on Darwin
Darwin's getopt does not support the same parameters as the
util-linux version and so it is not possible to commit any
changes because lint fails.

Change-Id: Ife26083d2de080af9ed3d509945720051ca14bd7
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80436
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-02 03:55:01 +00:00
343ef6fc3f Update MAINTAINERS file
Change-Id: Ic924b8faf44473fa4bac5c033a8e784e41581292
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-02 03:11:08 +00:00
ff2d863515 drivers/intel/gma: Allow SPARK function with side effects
Explicitly specifying the aspect `Side_Effects' is necessary for GCC
toolchains from 14.0 on. As older toolchains don't know the aspect,
we have to silence a warning about it, though.

Change-Id: I1eb879f57437587dc11d879fcc4042a70d384786
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80616
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-01 18:46:30 +00:00
0ada3dafd0 acpi/acpigen_pci_root_resource_producer: zero-pad ranges
Print bus number, IO and MMIO ranges as fixed length zero-padded
hexadecimal numbers. The bus numbers are 1 byte long, the IO range
values are 2 bytes long and the MMIO range values can be up to 8 bytes
long, so use '%02x', '%04llx' and '%016llx' in the corresponding parts
of the format string.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Iea45094a3988d57f8640a98fd7214d33ed1d7ccb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-03-01 16:24:22 +00:00
5ad8a5fa47 superio/acpi: Add SUPERIO_PNP_NO_DIS to support always active LDNs
Some LDNs do not implement the activate bit at all, e.g. ITE GPIO LDNs
are an example where the LDN is always active. The pnp_generic.asl can
be used to describe the GPIO LDN resources configured by the platform,
however the register 0x30 is always 0 for these LDNs, so OS will not
claim the reported resource for the GPIO device, because _STA will
return inactive LDN.

Add SUPERIO_PNP_NO_DIS macro to generate _STA method returning an
always active LDN and skip _DIS generation. Define the SUPERIO_PNP_NO_DIS
for SIOs which use the pnp_generic.asl preserving the previous states,
except the ITE GPIO LDNs.

Change-Id: Ieb827fdffe7660b875cba6ca99b0560b4cab66b4
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80496
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-01 15:37:48 +00:00
53f26e400d MAINTAINERS: Add Dinesh Gehlot as ADL SOC and BRYA MB maintainer
Change-Id: I6ad9dbe3bd073f3c43878beec201491b87694fc3
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-01 15:11:40 +00:00
32d3a005d2 drivers/mrc_cache: Deselect MRC_CACHE_USING_MRC_VERSION by default
EDK2 version binding is irrelevant for MRC_CACHE_USING_MRC_VERSION
as this is SoC FSP choice to enable/disable this feature. So deselect
the option and leave it to SoC codes to enable it depending on needs.

Change-Id: I84fdcfbf3c833a7ccb259a1a1d4be0bcfe291dc3
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80693
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-01 14:22:21 +00:00
119fdfb0f1 soc/intel/meteorlake: Select MRC_CACHE_USING_MRC_VERSION
MRC_CACHE_USING_MRC_VERSION is irrelevant to the EDK2 binding version
and should not be enabled under specific version conditions, so select
this at SoC level.

Change-Id: I10594df7c8fdc5cfe9b68975e01ae65859735544
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80728
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-01 14:21:58 +00:00
03a207de06 mb/google/nissa/var/glassway: Add GPIO table
Refer to the reference board of nivviks, and update GPIO settings
via glassway schematic of ca24a_r10_240108_v3_mb_gsen_gmr.pdf.

BUG=b:319071869
BRANCH=firmware-nissa-15217.B
TEST=Local build successfully and boot to OOBE normally.

Change-Id: I0de743746160c6eb081cb9a061ac1703b01ba5b4
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-01 14:05:45 +00:00
67862de79f mb/google/link: Use automatic fan control
Several users complained of link's fan not running at all, particularly
when using ChromeOS Flex. Enabling auto fan control at boot/s3 resume
resolved the issue for them.

Change-Id: I8f0db6b6c94fac2e0dcb580be0f6df839780c38c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80713
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-01 00:34:27 +00:00
9bb70d55c0 ec/chromeec: Enable auto fan control on startup
Several older ChromeOS boards have issues with fan control on cold boot
and/or on S3 resume, so add functionality to allow those boards to
programmatically enable auto fan control.

TEST=build/boot google/link, verify fan ramps up/down accordingly with
CPU load.

Change-Id: I08a8562531f8af0c71230477d0221d536443f096
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2024-03-01 00:33:37 +00:00
ba210367b6 doc/releases: Add 24.02.1 release section
Change-Id: I4d217c3dba4aa3ec30732b914009a6e9d53371c7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80798
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29 23:48:04 +00:00
9362b1935c device/pnp_device: fix log levels for unassigned resource messages
Commit a662777b6f ("pnp_device: don't treat missing PNP_MSC devicetree
entry as error") lowered the log level for every resource without the
assigned bit set except for the IRQ0 and IRQ1 PNP device resources.
Commit df84fff80f ("device/pnp_device: Demote unassigned resource
printk to NOTICE") lowered the log level for the IRQ0 and IRQ1 PNP
device resources to a lower log level than for the other warnings that
are less likely a problem. Fix this regression by using the BIOS_NOTICE
log level for all PNP resources that don't have the IORESOURCE_ASSIGNED
bit set.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I232e60ef7ae672e18cc1837b8e6a0427d01c142b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80774
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29 21:40:49 +00:00
9d08ad5bac mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OS
No Windows driver exists or is needed, so hide to prevent an unknown
device from being listed in Windows Device Manager. Same change was
made for frostflow variant previously.

TEST=build/boot Win11 on skyrim, verify unknown device for the
fingerprint reader no longer present.

Change-Id: Ia700aa4ccd478bc734db012e1419e566a5dcf493
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80711
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29 16:17:49 +00:00
e549ee093b soc/amd: move common pci_domain_fill_ssdt implementation to acpi/
Even though it has an 'amd_' prefix, the amd_pci_domain_fill_ssdt
implementation doesn't contain any AMD-specific code and can also be
used by other SoCs. So factor it out, move the implementation to
src/acpi/acpigen_pci_root_resource_producer.c, and rename it to
pci_domain_fill_ssdt. When a SoC now assigns pci_domain_fill_ssdt to its
domain operation's acpi_fill_ssdt function pointer, the PCI domain
resource producer information will be added to the SSDT.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7bd8568cf0b7051c74adbedfe0e416a0938ccb99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80464
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29 15:39:06 +00:00
d361163f6b mb/amd/birman_plus: Add glinda SOC option for Birman+
Change-Id: I1efeb7cf1dca31e2a7e17f483f8882925b55e7ea
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2024-02-29 13:10:59 +00:00
adf042f6c6 lib/rtc: Fix off-by-one error in February day count in leap year
The month argument passed to rtc_month_days is 0-based, not 1-based.
This results in the RTC being reverted to the build date constantly
on 29th February 2024.

Change-Id: If451e3e3471fef0d429e255cf297050a525ca1a2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80790
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2024-02-29 13:07:02 +00:00
cce6dfbf49 mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)
The M700 / M900 Tiny boards are USFF PCs that come with Skylake LGA1151
processors. M700 comes with B150 chipset, M900 comes with Q170 and is
vPro capable.

There is an onboard discrete TPM 1.2. Intel PTT fTPM can also be enabled
in vendor FW, but for now it's not used here.

LPSS UART for debugging is available on pins 17,18 on the underside of
the mainboard, but it is not enabled by default.

Tested unit is M900 with i5-6500T. Boots to Fedora 38 w/ kernel 6.5.5
and Windows 11.

Tested and working:

- Serial port (via optional module)
- Rear DisplayPort connectors
- Graphics w/ libgfxinit
- Ethernet
- SATA
- NVMe
- Internal speaker, front combo jack, rear line-out
- Discrete TPM 1.2
- USB ports (Port 1 untested, apparently broken on my unit)
- M.2 2230 Wi-Fi slot (needs ASPM L1s disabled)
- S3 suspend
- ME disable via NVRAM setting

Untested:

- Front mic input
- Optional expansion headers: DisplayPort, USB, PS/2, SATA / PCIe

Change-Id: I6786e068ec03c8bf243e1767cd7b9d50512ea77f
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-29 09:20:43 +00:00
e2d6f7e4d7 mb/clevo/tgl-u: hda_verbs: correct vendor value comments
The vendor vendor values for the  hda verbs´ location field  were
decoded wrong because of relying on the wrong bit shift value in
`device/azalia_device.h`. Since this was fixed now, correct the
comments.

Change-Id: I45b1d09d5a11b357ac2a20ef448ea642540cdc99
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80720
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-29 03:13:44 +00:00
98cec2a2c9 mainboard/lenovo: Add ThinkCentre M710s (Skylake)
The processor may be a Pentium or 6/7th generation Core i3/i5/i7.
This port was tested on an i5-7400.

Working:
 - Can boot Ubuntu 22.04.1 (Linux 6.5.0) using payloads:
   - SeaBIOS
   - TianoCore EDK 2
 - Internal flashing (from coreboot)
 - PEG
 - PCIe
 - SATA
 - M.2 SSD
 - M.2 WLAN (+ Bluetooth)
 - LAN
 - USB
 - Memory card reader
 - CPU fan
 - VGA (DP bridge)
 - Display ports
 - Audio (output)
 - COM1
 - TPM

Not Working:
 - SuperIO related things
 - Power button LED
 - PCIe clock related things and AER issues (LiveCD)
 - Some drm issue when using EDK 2 and libgfxinit (LiveCD)
 - ME cleaner

Untested:
 - Audio (input)

Won't Test:
 - COM2 header
 - LPT header
 - PS/2 keyboard and mouse

Thanks to Nico Huber and everyone else on the IRC for helping me write
my first port!

Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80343
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29 03:13:21 +00:00
4e8bbc11d0 include/device/azalia_device.h: Merge location1 and location2
This changes the location to be expressed as a combination of ORs. This
allows aliases for special locations.

For example, `AZALIA_REAR_PANEL` is easier to read than
`AZALIA_EXTERNAL_PRIMARY_CHASSIS, AZALIA_SPECIAL7`.

References:
 - Intel High Definition Audio Specification, rev. 1.0a, page 180,
   Table 110. Location.

Change-Id: I5a61a37ed70027700f07f1532c500f04d7a16ce1
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-29 03:13:08 +00:00
4a62b8a599 include/device: Merge enums from azalia_device.h and azalia.h
We were keeping 2 copies of the same thing (albeit there were some
slight differences). As azalia_device.h is used much more in the
codebase this was kept as the base and then some of the nice features
of azalia.h were incorporated.

The significant changes are:
 - All enum names now use the `AZALIA_` prefix.

This also drops the AzaliaPinConfiguration enum as it was never used
since added in 2013.

Change-Id: Ie874b083a18963679981a9cd2b25d123890d628e
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80695
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2024-02-29 03:12:43 +00:00
9620b3d152 include/device/azalia_device.h: Correct location2 shift to 28 bits
The location is specified to be in range of 29:24, which is further
divided into upper bits (location2) [5:4] and lower bits (location1)
[3:0].

This also corrects the resulting values of clevo/l140mu.

References:
 - Intel High Definition Audio Specification, rev. 1.0a, page 178,
   Figure 74. Configuration Data Structure.

TEST=Timeless build using AZALIA_PIN_DESC() and without now produce the
same binary.

Change-Id: Ia5a3431b70783cb88e866d0fd8ea5530100f3d52
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80727
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29 03:11:56 +00:00
10291e800c amdfwtool: Use Makefile.mk for Makefile settings
When updating the Makefiles, to keep from having to update two files at
the same time, import Makefile.mk into the external Makefile. This
allows the bulk of the settings to be in a single location.

While I'm here, I adjusted the print statements to match the rest of
coreboot.

Change-Id: Id5b869f49b34b22e6a02fc086e7b42975141a87e
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-29 02:24:09 +00:00
f6ea67cba1 mb/qemu/fw_cfg: Support using DMA to select fw_cfg file
Commit 8dc95ddbd4 ("emulation/qemu-i440fx: use fw_cfg_dma for
fw_cfg_read") adds DMA support to interface with the QEMU firmware
configuration device, and uses it to read from the "files" exposed by
the device. However, the file selection step still uses port-based IO.

Use DMA for fw_cfg file selection when possible, as a step towards
porting this driver to other architectures.

Change-Id: I46f9915e6df04d371c7084815f16034c7e9879d4
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-29 02:11:01 +00:00
7b7bddc015 Revert "lib: Explicitly declare heap as NOLOAD"
This reverts commit 99bf23c9e7.

This patch causes the boot regression at depthcharge with below
error signature. Able to boot to OS after reverting this patch.

```
Starting depthcharge on Rex...
WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
fw_config match found: AUDIO=MAX98360_ALC5682I_I2S
Looking for NVMe Controller 0x30069a60 @ 00:06:00
libc/lp_vboot.c:25 vboot_get_context(): vboot workbuf could not be initialized,
error: 0x10080030
Ready for GDB connection.
```

Change-Id: I8d49e2dc49cd2935a9d8023c989869ec9558039e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80775
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29 00:11:09 +00:00
8d9ce363f8 soc/intel/xeon_sp/util: Locate PCU by PCI device ID
Instead of manually crafting S:B:D:F numbers for each PCI device
search for the devices by PCI vendor and device ID.

This adds PCI multi-segment support without any further code
modifications, since the correct PCI segment will be stored in the
devicetree.

Change-Id: I1dcad4ba3fbc0295d74e1bf832cce95f014fd7bf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80095
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-28 17:30:57 +00:00
106d7b30b9 soc/intel/xeon_sp: Locate PCU by PCI device ID
Instead of manually crafting S:B:D:F numbers for each PCI device
search for the devices by PCI vendor and device ID.

This adds PCI multi-segment support without any further code
modifications, since the correct PCI segment will be stored in the
devicetree.

Intel Document-ID: 735086
Intel Document-ID: 612246

Tested: On SPR 4S all PCU on all 4 sockets could be found and locked.

Change-Id: I06694715cba76b101165f1cef66d161b0f896b26
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80093
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-28 17:25:51 +00:00
3cfcffe49c cpu/x86/(sipi|smm): Pass on CR3 from ramstage
To allow for more flexibility like generating page tables at runtime or
page tables that are part of the ramstage, add a parameter to
sipi_vector.S and smm_stub.S so that APs use the same page tables as the
BSP during their initialization.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I1250ea6f63c65228178ee66e06d988dadfcc2a37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80335
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-02-28 12:12:59 +00:00
f45fcd1cf3 drivers/vpd: Add API to read "feature_device_info" VPD
This patch introduces an API for reading "feature_device_info" VPD
data. This information is essential for correctly differentiating
ChromeOS product segments (e.g., Chromebook-Plus vs. standard
Chromebook models).

BUG=b:324107408
TEST=Build and boot successful on google/yahiko with this change.

Change-Id: I8d49e2dc49cd2935a9d8023c989869eb9558039d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-28 11:05:42 +00:00
be426e0722 mb/google/brya/var/xol: Add storage option in FW_CONFIG
Add STORAGE config in FW_CONFIG to support NVME sku.

- STORAGE_UFS : 0
- STORAGE_NVME: 1

BUG=b:326481458
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage

Change-Id: Id8316f643ba9a55319b67431a24a507e92419aa7
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80767
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-28 11:03:52 +00:00
354a54ac84 soc/intel/tigerlake: Remove IOM Mctp command from TCSS ASL
Port fix from Alder Lake to not set/reset IOM MCTP during
D3 cold entry or exit.

Ports 5008d34003 ("soc/intel/adl: Remove IOM Mctp command from TCSS
ASL"):

> Recently as part of s0ix hang issue, it was found that sending IOM
> MCTP command as part of TCSS D3 Cold enter-exit sequence created an
> issue.

> We discovered that due to change in hardware sequence, ADL should not
> set/reset IOM MCTP during D3 cold entry or exit. This patch removes
> the bit setting from ASL file to prevent hang in the system.

> This patch also removes obsolete Pcode mailbox communication which
> is no longer required for ADL.

> BUG=b:220796339
> BRANCH=firmware-brya-14505.B
> TEST=Check if hang issue is resolved with the CL and no other
> regression
> observed

> https://review.coreboot.org/c/coreboot/+/62861

Test: build/boot drobit to Win11. Verify TCSS XHCI power management
working and USB Root Hub doesn't Code 43 in device manager

Change-Id: I40a537fd2b0c821caf282f52aaff1874f54325f1
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80719
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-27 20:41:51 +00:00
377845a9d4 soc/intel/tigerlake: Fix processor hang while plug unplug of TBT device
Port 9c348a7b7e ("soc/intel/alderlake: Fix processor hang while plug
unplug of TBT device") from Alder Lake to fix a similar issue present
on Tiger Lake:

> Processor hang is observed while hot plug unplug of TBT device. BIOS
> should execute TBT PCIe RP RTD3 flow based on the value of
> TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if
> BIT30 in TBT FW version is not set.

> BUG=b:194880254

> https://review.coreboot.org/c/coreboot/+/56503

Change-Id: Ie5409111d4239be86c0b153f01b4fe5fc6af352c
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80718
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-27 20:41:22 +00:00
9bbfafbef8 Kconfig: Make the SEPARATE_ROMSTAGE default configurable in other files
This also sets a good default in arch and vboot to have a separate
romstage when it makes sense.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I09ab5f8c79917bf93c9d5c9dfd157c652478b186
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80580
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-27 20:35:11 +00:00
9f0443c264 device/pciexp_device.c: Fix setting Max Payload Size
Current implementation assumes that the endpoint device is connected
directly to the PCIe Root Port, which does not always have to be true.
In a case where there is a PCIe switch between the endpoint and the
root port, the Max Payload Size capability may differ across the
devices in the chain and coreboot will not set a correct Max Payload
Size. This results in a PCIe device malfunction in pre-OS environment,
e.g. if the Ethernet NICs are connected behind a PCIe switch, the iPXE
fails to obtain the DHCP configuration.

Fix this by traversing the topology and programming the highest common
Max Payload Size in the given PCIe device chain during enumeration.
Once finished, the root port has the highest common Max Payload Size
supported by all the devices in the chain. So at the end of root port
bus scan, propagate the root port's Max Payload Size to all downstream
devices to keep Max Payload Size in sync within the whole chain.

TEST=Perform successful dhcp command in iPXE on the NIC connected to
the PCIe root port via ASMedia ASM1806 PCIe switch and again on the
NIC connected directly to the PCIe root port.

Change-Id: I24386dc208363b7d94fea46dec25c231a3968225
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2024-02-27 20:23:12 +00:00
2009f7c0b7 mb/qemu/fw_cfg: Use fw_cfg_read() to read SMBIOS data
The QEMU firmware configuration driver can help initialize SMBIOS tables
using the table data that QEMU provides over the device. While doing so,
it reads from the device "file" manually using port-based IO.

Use the fw_cfg_read() helper function to read the SMBIOS-related file,
so that the driver is easier to port the driver to other architectures.

Change-Id: I18e60b8e9de34f2b0ff67af4113beec1d7467329
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80367
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-27 20:22:18 +00:00
dd63418f81 mb/qemu/fw_cfg: Fix build when not generating SMBIOS tables
Parts of the QEMU firmware configuration device driver refers to SMBIOS
related kconfig values. These depend on GENERATE_SMBIOS_TABLES and are
undefined if it isn't enabled, causing a build error.

Cover the SMBIOS-related region in this driver with an #if directive
checking the necessary config option. This is mostly to help port the
driver to non-x86 architectures where support for generating SMBIOS
tables isn't there yet.

Change-Id: I3ff388d4574eb52686a5dda3dcbc3d64a7ce6f7b
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80366
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-27 20:21:54 +00:00
afc2051554 Docs/releases: Finalize 24.02 release notes
Change-Id: I5ba6619ee7ed408a33548ab5b6f7d2a2143e88e7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80751
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-27 20:18:42 +00:00
df84fff80f device/pnp_device: Demote unassigned resource printk to NOTICE
Often times not all available resources are used on a PNP function, so
those resources not being specified is intentional, not an error. Keep
the printk but demote it so it doesn't pollute a normal cbmem log.

TEST=build/boot purism/librem_cnl (Mini v2), verify errors in cbmem
related to RTC IO/IRQ not being assigned are no longer present.

Change-Id: I3d9f22a06088596e14680190aede2d69880001fa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80645
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-27 20:18:00 +00:00
c3a34a4828 soc/intel/common/lpc: Don't open a window for unassigned resources
Don't attempt to open a PMIO window for a resource which doesn't have
the IORESOURCE_ASSIGNED flag set, since there is no point in doing so
and there's a high likelihood that the base address is 0, which will
throw an error.

TEST=build/boot purism/librem_cnl (Mini v2), ensure no errors in cbmem
log for attempting to open a PMIO window for unaassigned resources with
base address 0.

Change-Id: Ifba14a8f134ba12d5f5e9fdbac775d4f82b4c4de
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-27 20:17:50 +00:00
1aecff447d mb/google/nissa/var/glassway: Add initial override devicetree
Refer to the reference board of nivviks, and update devicetree settings
via glassway schematic of ca24a_r10_240108_v3_mb_gsen_gmr.pdf.

BUG=b:319071869
BRANCH=firmware-nissa-15217.B
TEST=Local build successfully and boot to OOBE normally.

Change-Id: Ibbb10a373bd5fa52a0833b81133517d2a088536b
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80742
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-27 07:06:00 +00:00
25b70d9326 Documentation/tutorial/part1.md: Reformat Redhat package description
Convert multiline Redhat package list to one-line code markup.

Change-Id: I1ba38bf2fc767a3f1694c55cf50e137ce10bfd75
Signed-off-by: Juan José García-Castro Crespo <jjgcc@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-26 20:01:31 +00:00
b397e98124 mb/google/rex/var/deku: replace IOEX with GPIOs
IOEX was replaced with GPIOs, this CL makes the required changes

BUG=b:325533052
TEST=Built FW image correctly.

Change-Id: I09ebba336b179cb36c6801b47ee0be5ade08c257
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80570
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-26 19:51:24 +00:00
e3df5714cd mb/google/rex/var/deku: Correct GPIO F19/F20 to not connected
GPP_F19 and GPP_F20 sre set incorrectly previously. Change them to not
connected according to schematics.

BUG=b:305793886
TEST=Built FW image correctly.

Change-Id: Ifb6da1f8696f44cb47be3d1de83c55e62b12a9e9
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80569
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-26 19:51:14 +00:00
6fe59ccf89 Documentation: Add 24.05 release notes template
In preparation for the upcoming release, add the template for the
24.05 release and update index.md.

Change-Id: Ic8fdf82519ffa4001bcc06bdd808eaebdde18a1e
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-02-26 19:01:28 +00:00
55b3c0466c docker/coreboot-sdk: Add meson
This is needed to build opensil. With meson and ninja added to the
coreboot-sdk image there is no need have them in the jenkins node image.

Change-Id: I36188ae895f2a770f1dc4528f332c09bf386db73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-26 17:25:00 +00:00
6d1560f05d Documentation/tutorial/part1.md: Install libssl-dev and pkg-config on Debian
Missing pkg-config and libcrypto when building coreboot (Step 6) on
Debian 12 (bookworm). Add required packages to Step 1, libssl-dev and
pkg-config.

Change-Id: I5df06611a934d1ef85c8335764f4f6e0f241c9a9
Signed-off-by: Juan José García-Castro Crespo <jjgcc@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80722
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-26 14:58:37 +00:00
5ff6bf30d8 util/amdfwtool: build amdfwtool only for all tools or AMD CPUs
When we're building non-AMD processors, don't bother building amdfwtool
unless we're specifically building all of the tools like for abuild.

Change-Id: I9021674a06d65a79e24020790d317ab947c505fe
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80714
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-26 14:50:18 +00:00
309534183f mb/hp/snb_ivb_desktops: Make baseboard more generic
In preparation to merging all the other HP sandy/ivy desktops in here
as variants.

Move hda_verb.c, early_init.c, gma-mainboard.ads and data.vbt into
variant directories.

Kconfig:
Move options not common to the others under the variants instead.

devicetree:
Move XHCI to variant overridetrees (8200 gen has no USB 3)

board_info.txt:
Make it more generic. It seems to be copied from 8200 SFF and
inaccurate to Z220 anyway.

TEST: BUILD_TIMELESS=1 & Don't include .config in ROM image. CMT and
SFF ROMs are (SHA1) same as before.

Change-Id: Icce22efb8d353359781db3f03c67058d8fbe11b8
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-02-26 13:12:30 +00:00
99bf23c9e7 lib: Explicitly declare heap as NOLOAD
The GNU BFD linker makes a good guess that this section should not be
loaded, however other linkers like LLVM LD need this to be made explicit
in order for the section to have the NOBITS, rather than PROGBITS
attribute set.

Change-Id: I3ca7221d10f144f608823e0b9624533780fbf335
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80735
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-02-26 13:00:54 +00:00
a06175523c soc/mediatek: Add MEDIATEK_DRAM_ADAPTIVE config to support dram adaptive
Starting from MT8195, MediaTek platform supports "dram adaptive" to
automatically detect dram information, including channel, rank, die
size..., and can automatically configure EMI settings. So we can just
pass a placeholder param blob to `mt_mem_init_run` by enabling this
option.

Platforms (MT8173, MT8183, MT8192) which do not support "dram adaptive"
need to implement `get_sdram_config` to get onboard DRAM configuration
info.

TEST=emerge-geralt coreboot && emerge-asurada coreboot
TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is set to y on geralt
TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is no set on asurada

Change-Id: I05a01b1ab13fbf19b2a908c48a540a5c2e1ccbdc
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-02-26 13:00:08 +00:00
caabde1806 superio/ite: Add IT8629E
Unfortunately, the datasheet for IT8629E is not public. Therefore, we
will use the functionally closest chip (i.e. IT8728F) as a reference
and try to reverse-engineer where necessary.

IT8629E seems to be very similar to IT8628E (again, no public
datasheets), as the chip id is 0x8628.

Known differences:
 - LDN 0x08 (functionality is unknown)
 - Supports 6 fans

Change-Id: I44d0377da11f0e118017caa4357012df9373b322
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80344
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-26 12:59:19 +00:00
0a1d68ff80 soc/intel/alderlake: Add kconfig for Twin Lake
Mainboards using Intel Twin Lake (TWL) SoC shall select
SOC_INTEL_TWINLAKE.

BUG=none
BRANCH=firmware-nissa-15217.B
TEST=Build and boot Google/Yaviks with Twin Lake kconfig enabled

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ie4c5d137ee54512313344f853e7ca66d1fd25003
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80688
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-26 11:18:24 +00:00
7fbef1b112 lib: Remove heap from rmodules
No rmodule was using heap.

Change-Id: I0bc049a5231dabbec1c962a99ef875eddcc4ac6e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-02-26 10:10:07 +00:00
259fc2b119 mb/google/rex/var/deku: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing.

Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST

The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:

bootblock (A20/0, A19/1)
|
v
romstage (A20/1)

Ideally, we don't need SSD power sequencing at ramstage, hence, remove
the logic from ramstage.

TEST=Able to build and boot google/deku using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.

Change-Id: Iedaff8a793f1ba5d2b97352b95c4dfdd2b818ebd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80664
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-25 03:57:10 +00:00
9305ccada1 mb/google/rex/var/karis: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing.

Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST

The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:

bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
|
v
ramstage (A19/1, A20/1)

Ideally, we don't need SSD power sequencing at ramstage, but due to the
fact that Karis has RO locked, any change in the bootblock won't be
applicable for FSI'ed karis devices. Therefore, we're keeping the
existing ramstage power sequencing flow as is

TEST=Able to build and boot google/karis using NVMe without any
problems. S0ix and read/write from/to SSD are also normal.

Change-Id: I79171a7830b75f5c20bbe30023f2814a62743a13
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80663
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-25 03:56:59 +00:00
313fdb28ca mb/google/rex/var/ovis: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing.

Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST

The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:

bootblock (A20/0, A19/1)
|
v
romstage (A20/1)

Ideally, we don't need SSD power sequencing at ramstage, hence, remove
the logic from ramstage.

TEST=Able to build and boot google/ovis using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.

Change-Id: I891b5a6d2c29f5d940793a4e90215265f2a4fcd8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-25 03:56:52 +00:00
4bbace87aa mb/google/rex/var/rex0: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing.

Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST

The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:

bootblock (A20/0, A19/1)
|
v
romstage (A20/1)

Ideally, we don't need SSD power sequencing at ramstage, hence, remove
the logic from ramstage.

TEST=Able to build and boot google/rex0 using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.

Change-Id: Idde2f7693771f1d7e3171e51232d1bb899bfe33e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-25 03:56:44 +00:00
f0277dbbe6 mb/google/rex/var/screebo: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing.

Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST

The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:

bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
|
v
ramstage (A19/1, A20/1)

Ideally, we don't need SSD power sequencing at ramstage, but due to the
fact that Screebo has RO locked, any change in the bootblock won't be
applicable for FSI'ed screebo devices. Therefore, we're keeping the
existing ramstage power sequencing flow as is.

TEST=Able to build and boot google/screebo using NVMe without any
problems. S0ix and read/write from/to SSD are also normal.

Change-Id: I0ee1fa4613178da8771c9e6b5ee871e50ea6324c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80640
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-25 03:56:37 +00:00
04d6eb1eae crossgcc: Upgrade CMake from 3.27.7 to version 3.28.3
Change-Id: I17758e23da25d610a0b462dfd388c53b89315242
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-24 22:26:11 +00:00
15d55439da soc/amd/glinda: Update GPP_CLK_OUTPUT_AVAILABLE to 7
Glinda started as a copy of mendocino and GPP_CLK_OUTPUT_AVAILABLE was
not updated. GPP_CLK_OUTPUT_AVAILABLE should be 7 as per Processor
Programming Reference (PPR) (#57254), table "GPP ClkREQB Mapping".

Change-Id: I26e9dea58b2ddf5cbedbcccb8bcbc5f9efab3165
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80701
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-24 19:27:37 +00:00
a99b580c75 treewide: Move list.h to commonlib
It is needed in order to move device_tree.c into commonlib in a
subsequent commit.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I16eb7b743fb1d36301f0eda563a62364e7a9cfec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77968
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-24 11:49:46 +00:00
366ceeef0f vboot: Enable new arm64 SIMD crypto acceleration
This patch passes the correct flag to vboot to enable SIMD crypto
acceleration on arm64 devices. This uses a core part of the ISA and
should thus be supported on all arm64 SoCs -- so we normally always
want it enabled, but there should still be a Kconfig in case a SoC wants
to use the hwcrypto interface for its own (off-CPU) crypto acceleration
engine instead. (You could also disable it to save a small amount of
code size at the cost of speed, if necessary.)

Change-Id: I3820bd6b7505202b7edb6768385ce5deb18777a4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-02-24 02:02:34 +00:00
c57b902f9b Update vboot submodule to upstream main
Updating from commit id 3d37d2aa:
2024-01-15 Makefile: Support FIRMWARE_ARCH=mock for firmware unit tests

to commit id 09fcd218:
2024-02-22 Makefile: Test compiler for -Wincompatible-function-pointer-types

This brings in 26 new commits:
09fcd218 Makefile: Test compiler for -Wincompatible-function-pointer-types
00e8c2d8 tests: Run hwcrypto RSA tests for arm64
d3387824 firmware: Add vectorized modexp() implementation for arm64 (NEON)
8856e04b tests: Stop exporting ENABLE_HWCRYPTO_RSA_TESTS to test scripts
6abd9cc0 Makefile: Separate ${ARCH_DIR}, split arm/arm64, remove symlinks
e7f567d1 test_update: Skip ifdtool-dependent tests when not available
1a0f8df8 libvboot_host: Check for undefined symbols
c0806280 vboot_host: Expose dynamic library
2ff5784d vboot: Remove 2kernel.c from vboot_host library
6e472468 Add crdyshim keygen script and devkeys
8a711468 scripts/keygeneration: Move generate_ed25519_key to common.sh
57e2092d scripts/image_signing: Call futility instead of its symlinks
0fa2ea47 scripts/image_signing/make_dev_ssh.sh: Improve parameter removal
1d32db3b Makefile: Remove genfuzztestcases from runtestscripts prerequisites
f6ff822b README: Add 'futility sign' and 'futility verify' to useful utilities
a717c83d tests: Replace vbutil_{firmware,kernel} with 'futility sign'
94c82417 *.sh: Unify indentation with 2 spaces
23d25957 utility/dev_debug_vboot: Replace vbutil_firmware with 'futility verify'
fd20901f cgpt/futility: bundle as a subtool
dccc5a31 image_signing: Add support for signing Flexor kernel image
660b6675 futility/cmd_show: Add "::verified" summary to vblock parseable output
2fcff1e4 tests/*.sh: Replace vbutil_firmware with 'futility verify'
c6b13823 make_dev_firmware.sh: Replace vbutil_firmware with 'futility show'
d260d094 firmware: 2modpow_sse2: Clean up calculation of `mu`
2596679a Add -Wint-conversion and -Wincompatible-function-pointer-types
39fb6201 futility: update: Use ifdtool to unlock ME
f8016c2b make_keyblock: change to parsing key prefix

Change-Id: Ibc6daef30092b1b31f3dd08f3aed02ba31fd12d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-02-24 02:02:29 +00:00
e1fc17f3c3 soc/amd/common/acp: use clrsetbits32p to avoid need for casts
Use clrsetbits32p instead of clrsetbits32 to not need to cast the
uintptr_t address to void * in the function call.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic29bf04866a7e1d5c831422f31803a724a41069b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-02-23 16:44:46 +00:00
4e3d2a16ff vc/amd/opensil/genoa_poc/mpio/chip: fix typo in pcie_aspm enum name
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I60ac259d2aa0bd500063a5c841ba33e576e022f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80702
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-23 16:44:01 +00:00
b9e80df84e soc/amd/glinda: Use gpp_clk_setup_common function
In follow up to commit 0452d0939e ("soc/amd: Factor out gpp_clk_setup function") use gpp_clk_setup_common for glinda as well.

Change-Id: If0c1cda0d36de48c7f7315a1b8203b0e53f63f75
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80699
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-02-23 16:33:01 +00:00
0d19289e84 arch/x86/ioapic: use uintptr_t for IOAPIC base address
Use uintptr_t for the IOAPIC base parameter of the various IOAPIC-
related functions to avoid needing type casts in the callers. This also
allows dropping the VIO_APIC_VADDR define and consistently use the
IO_APIC_ADDR define instead.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I912943e923ff092708e90138caa5e1daf269a69f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-02-23 15:13:37 +00:00
a138cfb422 soc/amd/glinda: Use pcie_gpp_dxio_update_clk_req_config
This function turns off gpp_clk for the devices which are disabled, and
adds the code to fix up the clock configuration depending on dxio
descriptors. Also this brings glinda in line with cezanne, mendocino,
phoenix and picasso. This also prepares glinda to use the common
function gpp_clk_setup_common.

Change-Id: Id66d1b7f0d8ec9a7cbd378ad6ad7d68eeab531f0
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80415
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-23 14:52:21 +00:00
961ed9fe27 soc/intel/adl: Set slp-s0 counter frequency
System sleep time (SLP_S0 signal asserted) is measured in ticks, for
Alder Lake soc in 122us (i.e. ~8197Hz) granularity/ticks.

BUG=b:301854636
TEST=/sys/devices/system/cpu/cpuidle/
low_power_idle_system_residency_us" will show system idle residency time

Change-Id: I449f7ed0d9ef891ae5266e8fd784a063a75e38eb
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-23 14:28:52 +00:00
6cc725466b vc/intel/fsp2/twinlake: Add FSP headers
Add FSP header files for Twin Lake. Currently these are just a copy of
ADL-N headers.

BUG=none
BRANCH=firmware-nissa-15217.B
TEST=Build and boot Google/Yaviks with Twin Lake kconfig enabled

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I37579335c784866ebbf978e28936abf046a85b48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-23 07:58:02 +00:00
425e421e8c soc/intel/xeon_sp: Locate PCI devices by Ven/Dev ID
Since the ACPI code is looking for VtdBars, that only appear on
Vtd devices, search for the Vtd device in devicetree.
With the previous commit the VtdBar is now exposed as a resource
on the Vtd device and thus can easily be accessed and used.

Drop the FSP HOB parsing and just use coreboot native functions.
Allows the code to work with multiple PCI segment groups.

Change-Id: I2c752dc595ac4c901f2b3a96718e256e413c76a7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-02-23 07:45:33 +00:00
9fa4048e2d soc/intel/xeon_sp: Add helper functions
Provide a helper function to locate PCI devices on a given socket
by their PCI vendor and device IDs and functions to return
information about the current device, like the corresponding stack
and socket.
In addition add functions to return "location" information, like stack
and socket affiliation.
This becomes handy when locating devices and generating ACPI code.

Change-Id: I266360588548ba579f46b228c4d5b3ae6e39a029
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80094
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-02-23 07:45:15 +00:00
89cacb9050 soc/intel/xeon_sp/uncore: Read VtdBar
Read the VtdBar and add it to the resources of the host bridge PCI
device. The BAR is already marked as PciResourceMem32 in the parent
PCI domain.
This allows easy probing for VTD devices with enabled VtdBars in the
next commit, without the need to look up the stack HOB.

Change-Id: Id579a94e653473f3dd0dccea6e33dc64f792d028
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-23 07:45:08 +00:00
1d3838b623 riscv/mb/qemu: fix qemu invocation comment
Change-Id: I773fb39801f180fead584942dfb385fcde9d2680
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80262
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: ron minnich <rminnich@gmail.com>
2024-02-22 22:34:57 +00:00
4f1ba69b3c soc/intel/common/lpc: Skip setting resources for disabled devices
If a downstream LPC device (eg, SIO function) is disabled, we shouldn't
attempt to open PMIO windows for it, as those functions often have
unset IO bases (which default to 0), resulting in false errors like:
[ERROR] LPC IO decode base 0!

TEST=build/boot purism/librem_cnl (Mini v2), verify no LPC IO errors
in cbmem log for disabled SIO functions.

Change-Id: I92c79fc01be21466976f3056242f6d1824878eab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-22 22:19:35 +00:00
b6d16fb3fa soc/intel/braswell/gpio_support: drop unused get_gpio
The get_gpio function in this file is both unused and it shouldn't use
a signed int to pass in the MMIO base address and offset.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3b08bad040ad175b37175ef21d0a0a29525c4478
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-02-22 22:19:11 +00:00
1e113bc878 libpayload: Remove legacy CBFS API
It's been several years already since we announced the deprecation of
the legacy CBFS API for payloads. It's time to remove it completely.

Change-Id: I0ed157ac2d1376b8dff4537af9a63731064b45f6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80650
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-02-22 21:18:39 +00:00
4ed5b1723d mb/google/brox: Disable Early EC Sync
Early EC Sync does not need to be enabled in coreboot as EFS2 is being
enabled in the EC.

BUG=b:326152804
BRANCH=None
TEST=emerge-brox coreboot
     To be tested with EC sync enabled

Change-Id: I08bdbe9f3dcea837b0b148adc137c03d3461877a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80689
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-22 19:04:13 +00:00
2b64dbeb93 soc/intel/xeon_sp: Print device path when reporting resources
As there are multiple Vtd devices, print the path of each when reporting
resource registers.

Change-Id: I5d3a6484ed7c7b9760fce0f3a02a15ca26c2cbd2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80549
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-02-22 14:58:00 +00:00
836a6d8081 soc/intel/xeon_sp: Align resources to 4K
The lower bit of the BAR might be used for something else,
like enable bits, so mask the lower 12 bits and align all
base address to 4K.

Confirmed that all BARs have a minimum alignment of 4K, so that
masking the lower bits doesn't change the reported address.

The alignment of the VTD BARs is:
- VTD_MMCFG_BASE_CSR 64 MiB
- VTD_MMIOL_CSR       1 MiB
- VTD_NCMEM_BASE_CSR 64 MiB
- VTD_TSEG_BASE_CSR   1 MiB
- VTD_BAR_CSR         4 KiB

Change-Id: I9a7b963c0074246616968dd15c147f4916297d59
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-22 14:57:49 +00:00
313b18abe5 soc/intel/xeon_sp: Refactor IOAT compiler optimization outs
IOAT logics are optimized out for non-IOAT platforms where
CONFIG(HAVE_IOAT_DOMAINS) as false.

This patch puts CONFIG(HAVE_IOAT_DOMAINS) check together ahead
of is_ioat_iio_stack_res() check in the corresponding if
statement to fulfill the optimization outs.

TEST=intel/archercity CRB

Change-Id: I2d16c6ff5320bc9195a1033b6d55e3d997b19b88
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80683
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-22 14:13:26 +00:00
2eee78aeb4 soc/intel/alderlake: Remove Alder Lake M SKU
ADL-M is not commercially available, so it can be removed.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If769989f7a0434e32ebbcc8eac9b965b70ca71ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-22 13:40:17 +00:00
9c40215ef2 mb/intel/adlrvp: Remove ADLRVP_M mainboard
These boards are not commerically available so can be removed.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Icc853a9df44a4a770db76e119644f0b4c7fcc2c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-22 13:39:53 +00:00
fb401e74da soc/intel/alderlake: Sync UPD Usb4CmMode with Kconfig
The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set
the UPD to match this to avoid the connection type being mismatched.

If it's mismatched, the TBT port will time out.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8a99db165301ce08caf55aac0e33ca1994559d62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80486
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-22 13:39:06 +00:00
b8f49c6d38 mb/google/rex/variants/deku: Enable PCIe wifi device
BUG=b:320203629
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot built FW image correctly.

Change-Id: I8db065e25e21406f1966d8020a3b926b3a62ae12
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-22 13:37:31 +00:00
8bdcda7708 mb/google/nissa/var/glassway: Generate SPD ID for supported memory parts
Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.

DRAM Part Name                 ID to assign
K3KL8L80CM-MGCT                0 (0000)
K3KL6L60GM-MGCT                1 (0001)
H58G56AK6BX069                 2 (0010)
H9JCNNNBK3MLYR-N6E             3 (0011)

BUG=b:319071869
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
     part_id_gen.go ADL lp5 \
     src/mainboard/google/brya/variants/glassway/memory/ \
     src/mainboard/google/brya/variants/glassway/memory/\
     mem_parts_used.txt"

Change-Id: I00ae3efe8e554f44cee5a27ac88c5d65eb95f7fb
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
2024-02-22 13:37:05 +00:00
599b340b5e tests/lib/ux_locales-test: Simplify macros
The cmocka problem of sanitizing XML strings has been fixed in CB:80382.
Therefore the helper macros UX_LOCALES_GET_TEXT_FOUND_TEST() and
UX_LOCALES_GET_TEXT_NOT_FOUND_TEST() can be merged into one.

TEST=make unit-tests JUNIT_OUTPUT=y -j

Change-Id: Ic3199e2a061550282fb08122943994c835845543
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
2024-02-22 08:05:23 +00:00
bba6a21625 i2c/drivers/generic: Add support for including a rotation matrix
The Rotation Matrix allows the specification of a 3x3 matrix
representing the orientation of devices, such as accelerometers.
Each value in the matrix can be one of -1, 0, or 1, indicating the
transformation applied to the device's axes.

It is expected by Linux and required for the OS to interpret
the data from the device correctly. It is used by various drivers,
mainly in `iio/accel`.

It was tested on Ubuntu, by rotating the device and verifying the
orientation was correct.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id4a940d999a0e300a6fe21269f18bab6e3c0523c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80179
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-02-21 19:56:56 +00:00
7ae2e2840d mb/amd/birman_plus: Add Birman+ board support for Phoenix SOC
1) Initial commit for upstreaming Birmanplus mainboard changes.
2) Add the DXIO descriptors for Birmanplus mainboard.

Change-Id: I075dcf0214f8dc8b33b0e429d83d270b2f0952e1
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-02-21 19:03:52 +00:00
0978973d3f 3rdparty/fsp: Update submodule to upstream master
Updating from commit id 507ef01:
2024-01-11 10:49:14 +0800 - (IoT ADL-S MR6 (4115_09) FSP)

to commit id dd98487:
2024-02-16 17:16:05 -0800 - (Fix EagleStreamFspBinPkg Path)

This brings in 6 new commits:
dd98487 Fix EagleStreamFspBinPkg Path
fcf623b Fix MAX_VMD_STACKS_PER_SOCKET
e07f875 Fix EagleStream BSF File
85f37ab Idaville FSP - New UPDs for SSC
98e497f IoT RPL-P MR1 (4445_03) FSP
fc5e3c9 IoT RPL-P MR1 (4445_03) FSP

Change-Id: If7d852e1a92d8409a5161797c0aa3a55a71c8b49
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-02-21 16:21:47 +00:00
7552eb210c lib/lzmadecode: Allow for 8 byte reads on 64bit
This adds an optimization to lzma decode to also read from the boot
medium in chunks of 8 bytes if that is the general purpose register
length instead of always 4 bytes. It depends on the cache / memory / spi
controller whether this is faster, but it's likely to be either the same
or faster.

TESTED
- google/vilboz: cached boot medium
64bit before - 32bit - 64bit after
load FSP-M: 35,674 - 35,595 - 34,690
load ramstage: 42,134 - 43,378 - 40,882
load FSP-S: 24,954 - 25,496 - 24,368

- foxconn/g41m: uncached boot medium for testing
64bit before - 32bit - 64bit after
load ramstage: 51,164 - 51,872 - 51,894

Change-Id: I890c075307c0aec877618d9902ea352ae42a3bfa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-02-21 16:19:05 +00:00
f317068fc3 mb/ocp/*: Remove unused ACPI opregion
The base for this region is a magic number and none for the fields are
used, which likely means this was simply copied from a different
firmware.

Change-Id: I217bbd0b098cd15ef296854cc6262d651f11d10e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73183
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-21 16:17:22 +00:00
1e7f1c0658 mb/google/brya/var/xol: Add support memory parts
Add support memory parts for Xol.

- Samsung K3KL6L60GM-MGCT
- Samsung K3KL8L80CM-MGCT

BUG=b:319506033
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage
     Proto board can boot to ChromeOS.

Change-Id: Ic6a36e40f0f93109f296c5cc67a368ace81bd217
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80637
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-21 14:29:48 +00:00
a79ef93e82 mb/google/brya/var/xol: Update memory configuration
Update memory configuration following proto schematics.

BUG=b:319506033
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage
     Proto board can boot to ChromeOS.

Change-Id: I59aabe0870317092f59701bdf88b53bf9731377a
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-21 14:29:09 +00:00
12781b64cb soc/intel/alderlake: Include ADL-N ID 5
This patch adds support for using ADL N 4-core MCH ID 0x4618.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7b9fc64ccf8e2401dcd55607e8f09b348efb3182
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80166
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-21 14:28:52 +00:00
a2f47bbd93 mb/google/brya/var/xol: Update thermal policy
Update initial DTT policy and TCC setting for Xol. The setting values
are from internal power team.

- Critical CPU temparature: 105 -> 99
- TCC offset: 90 -> 94

BUG=b:323989520
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage

Change-Id: I546b313a1e6af16029309174a5bed2d1e4aa4d11
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80410
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-21 13:48:05 +00:00
c6df1ac62c mb/google/nissa/var/anraggar: Change tdp_pl1_override from 6 W to 15 W
Set tdp_pl1_override to 15 for performance required by the thermal team.

Fix policies.critical index from 2 to 0.

BUG=b:313833488
TEST=emerge-nissa coreboot

Change-Id: I5341bd3d4842f9298a2f5d9e589918bb1b06ba69
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-21 13:47:47 +00:00
3f06e6c740 mb/google/volteer: Disable PM ACPI timer to fix S0i3 regression
Keeping the PM timer enabled will disqualify an ADL system from entering
S0i3, and will also cause an increase in power during suspend states.
The PM timer is not required for brya boards, therefore disabling it.
Fixes: 0e90580 (soc/intel: transition full control over PM Timer from
FSP to coreboot)

This mirrors an identical commit for google/brya: 1ce0f3aab7
("mb/google/brya: Fix S0i3 regression")

TEST=Boot Linux on google/drobit, verify S0i3 counter incrementing after
exiting S0ix suspend states.

Change-Id: I644e42388c0f6127512bf52e774b79721601ecc9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80612
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-21 13:47:31 +00:00
d6e287f410 mb/google/brya: Create glassway variant
Create the glassway variant of the nivviks reference board by copying
the template files to a new directory named for the variant.

BUG=b:319071869
BRANCH=firmware-nissa-15217.B
TEST=None

Change-Id: I597666a5be6f71b82c7baddbe343da3d5117dd1c
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-21 06:09:33 +00:00
91c8827e62 3rdparty/cmocka: Update cmocka to latest stable-1.1
New patches:
8be3737 cmocka: Fix assert_memory_equal() display
fb38de9 cmake: disable `-Wdeclaration-after-statement`
a74d9cd Sanitize XML strings.
4e92198 Improve c_strreplace implementation
ea6ab8b cmake: Set CMOCKA_LIBRARIES in package config for backwards compatibility
53de473 cmocka: Add overflow check for test_calloc()
e738d6e tests: Add test for test_calloc()
a01cc69 Bump version to 1.1.7
123f00e cpack: Update ignore files for source package generation
f1e1615 Bump version 1.1.6
35dd06e tests: The exception handler doesn't work on Windows
9d72cf9 tests: Raise segmantation fault
2b20a4d tests: Rename exceptions tests array
4cd1fda tests: Better match for test_exception_handler
8ad2c4e cmake: Fix path relocation in pkgconfig file for mingw
3137fa5 cmake: Do not use CMAKE_(BINARY|SOURCE)_DIR for compile_commands.json
6e9d32f Improve INSTALL.md
c4da7e1 doc: Link to the examples for mocking
b13f29b include: Update copyright year info
98c451d include: Define strtok_r with Visual Studio
4aae816 gitlab-ci: Move memory and ub sanitizer to analysis stage
559381b gitlab-ci: Move freebsd to test stage
ce43813 examples: Add missing compile and link options
5ead982 gitlab-ci: Introduce stages
5f366b6 gitlab-ci: Fix typo in fedora/mingw32 build
77476f7 gitlab-ci: Use gitlab windows runners
200393b gitlab-ci: Reformat yaml
406591a tests: Initialize 'struct stat' in test_assert_macros.c
b201da5 cmake: Fix path where to find cmocka.dll
a47b3da include: Improved call ordering documentation
61b1fb9 doc: Remove redundant words
2cc8cba Fix issue with fail_msg

TEST=make unit-tests
TEST=make unit-tests JUNIT_OUTPUT=y
TEST=(cd payloads/libpayload; make unit-tests)
TEST=(cd payloads/libpayload; make unit-tests JUNIT_OUTPUT=y)

Change-Id: I60b37021e2587cc32c755719ef40a650a1c14b59
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80382
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-21 04:59:52 +00:00
4222b2cf30 lib/hardwaremain: align '\' in multi-line macro
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5967cebad3ad52b5cbc7babc0c808039d7da5227
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80635
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-20 14:25:45 +00:00
97eafb5126 mb/google/brox: enable DPTF functionality for brox
Enable DPTF functionality for brox board

BRANCH=None
BUG=b:324360936
TEST=Built and tested on brox board

Change-Id: I0315f7f45688ccc36d321d6be4fa4fac7559a16b
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-20 13:45:23 +00:00
3d5fd72c0f soc/intel/xeon_sp: Put SRAT util macros into Xeon-SP ACPI header
Macros MAX_ACPI_MEMORY_AFFINITY_COUNT and MAX_SRAT_MEM_ENTRIES_PER_IMC
are ACPI table specific, and could be used across Xeon-SP SoCs.
This patch moves their definition from FSP header to Xeon-SP layer
ACPI header.

TEST=intel/archercity CRB

Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Change-Id: I6c3a84b04a452bc8d4217947a7d12f050c94b56b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80629
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-20 12:42:11 +00:00
3108ba5a07 soc/intel/xeon_sp: Use ACPI common flags in SRAT generation
Move the definition of SRAT memory flags (SRAT_ACPI_MEMORY_ENABLED
and SRAT_ACPI_MEMORY_NONVOLATILE) from FSP header to ACPI common
codes.

TEST=intel/archercity CRB

Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Change-Id: I6aa5c20c9556fd5d680406518d19a83801b0852c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-02-20 12:40:48 +00:00
08f1f05bf6 soc/intel/xeon_sp: Add support for is_ioat_iio_stack_res
IOAT is the term for the on-chip accelerator technology of
Xeon-SP. In CPX and SPR, IOAT stack is also named as DINO stack.
Different SoC has different check criteria for IOAT stacks,
this patch introduces an util function to abstract these differences
as well as cleaning up the usage of names.

TEST=intel/archercity CRB

Change-Id: I376928ad89b68b294734000678dad6f070d3c97d
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80578
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-20 12:40:15 +00:00
94ff128c91 treewide: Remove unused CHIPs
No devicetree uses these anymore.

Change-Id: Ia65a0a56a6668a13761bad35f6a44ed8f6a35a78
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72600
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-20 11:01:36 +00:00
52b51db1d9 util/crossgcc: Update LLVM from 16.0.6 to 17.0.6
Change-Id: Ifed410f4b7fdc358535f01850328c642d19ff1f6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-20 10:38:23 +00:00
824ba49a0b crossgcc: Upgrade binutils from 2.41 to 2.42
Change-Id: I6e9b2dac6fed702e8e353290971699cb9ee05dfc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-20 10:37:46 +00:00
2892 changed files with 303757 additions and 14496 deletions

2
3rdparty/fsp vendored

2
3rdparty/vboot vendored

34
AUTHORS
View File

@ -39,7 +39,9 @@ Alexandru Gagniuc
Alexey Buyanov
Alexey Vazhnov
Alice Sell
Alicja Michalska
Allen-KH Cheng
Alper Nebi Yasak
Amanda Hwang
American Megatrends International, LLC
Amersel
@ -62,6 +64,7 @@ Anna Karaś
Annie Chen
Anton Kochkov
Ao Zhong
Appukuttan V K
Arashk Mahshidfar
Arec Kao
Ariel Fang
@ -93,6 +96,7 @@ Bora Guvendik
Boris Barbulovski
Boris Mittelberg
Brandon Breitenstein
Brandon Weeks
Brian Norris
Bryant Ou
Carl-Daniel Hailfinger
@ -101,6 +105,7 @@ Caveh Jalali
Cavium Inc.
Chao Gui
Chen-Tsung Hsieh
Chen. Gang C
Chia-Ling Hou
Chien-Chih Tseng
Chris Wang
@ -128,6 +133,7 @@ Da Lao
Daisuke Nojiri
Damien Zammit
Dan Callaghan
Dan Campbell
Daniel Campello
Daniel Gröber
Daniel Kang
@ -181,6 +187,7 @@ Eltan B.V
Eltan B.V.
Elyes Haouas
Eran Mitrani
Eren Peng
Eric Biederman
Eric Lai
Eric Peers
@ -194,13 +201,16 @@ Evan Green
Evgeny Zinoviev
Fabian Groffen
Fabian Kunkel
Fabian Meyer
Fabio Aiuto
Fabrice Bellard
Facebook, Inc.
Fei Yan
Felix Friedlander
Felix Held
Felix Singer
Fengquan Chen
Filip Lewiński
Flora Fu
Florian Laufenböck
Francois Toguo Fotso
@ -214,7 +224,7 @@ Free Software Foundation, Inc.
Freescale Semiconductor, Inc.
Furquan Shaikh
Gaggery Tsai
Gang C Chen
Gang C Chen
Garmin Chang
Gary Jennejohn
George Trudeau
@ -234,6 +244,7 @@ HardenedLinux
Harsha B R
Harshit Sharma
Henry C Chen
Herbert Wu
Hewlett Packard Enterprise Development LP
Hewlett-Packard Development Company, L.P.
Himanshu Sahdev
@ -286,6 +297,7 @@ Jason Zhao
jason-ch chen
Jason-jh Lin
Jay Patel
Jean Lucas
Jeff Chase
Jeff Daly
Jeff Li
@ -307,6 +319,7 @@ Jitao Shi
Joe Pillow
Joe Tessler
Joel Kitching
Joel Linn
Joey Peng
Johanna Schander
John Su
@ -325,6 +338,7 @@ Jordan Crouse
Jörg Mische
Joseph Smith
Josie Nordrum
Juan José García-Castro Crespo
Julia Tsai
Julian Schroeder
Julian Stecklina
@ -337,6 +351,7 @@ Kangheui Won
Kapil Porwal
Karol Zmyslowski
Karthik Ramasubramanian
Kei Hiroyoshi
Keith Hui
Keith Packard
Kenneth Chan
@ -367,9 +382,11 @@ Lawrence Chang
Leah Rowe
Lean Sheng Tan
Lei Wen
Lennart Eichhorn
Lenovo Group Ltd
Leo Chou
Li-Ta Lo
Li1 Feng
Liam Flaherty
Libra Li
Libretrend LDA
@ -397,6 +414,7 @@ Marc Bertens
Marc Jones
Marco Chen
Marek Kasiewicz
Marek Maślanka
Marek Vasut
Mario Scheithauer
Marius Gröger
@ -465,10 +483,12 @@ Myles Watson
Nancy.Lin
Naresh Solanki
Nathan Lu
Naveen R. Iyer
Neill Corlett
Network Appliance Inc.
Nicholas Chin
Nicholas Sielicki
Nicholas Sudsgaard
Nick Barker
Nick Chen
Nick Vaccaro
@ -502,6 +522,7 @@ Paul Fagerburg
Paul Menzel
Paul2 Huang
Paulo Alcantara
Pavan Holla
Pavel Sayekat
Paz Zcharya
PC Engines GmbH
@ -520,6 +541,7 @@ Philipp Deppenwiese
Philipp Hug
Piotr Kleinschmidt
Po Xu
Poornima Tom
Prasad Malisetty
Prashant Malani
Pratik Vishwakarma
@ -529,6 +551,7 @@ Protectli
Purism SPC
Purism, SPC
Qii Wang
Qinghong Zeng
Qualcomm Technologies, Inc.
Quanta Computer INC
Raihow Shi
@ -572,6 +595,7 @@ Robinson P. Tryon
Rockchip, Inc.
Rocky Phagura
Roger Lu
Roger Wang
Roja Rani Yarubandi
Romain Lievin
Roman Zippel
@ -745,12 +769,14 @@ Wojciech Macek
Wolfgang Denk
Won Chung
Wonkyu Kim
Wuxy
Wuxy
Xiang W
Xin Ji
Xixi Chen
Xuxin Xiong
YADRO
Yan Liu
Yang Wu
Yann Collet
Yaroslav Kurlaev
YH Lin
@ -767,6 +793,7 @@ Yuanliding
Yuchen He
Yuchen Huang
Yunlong Jia
Yuval Peress
Zachary Yedidia
Zanxi Chen
Zhanyong Wang
@ -776,10 +803,11 @@ Zhi7 Li
Zhiqiang Ma
Zhixing Ma
Zhiyong Tao
zhongtian wu
Zhongtian Wu
Zhuohao Lee
Ziang Wang
Zoey Wu
Zoltan Baldaszti
小田喜陽彦
忧郁沙茶
陳建宏

View File

@ -1,60 +1,20 @@
## SPDX-License-Identifier: GPL-2.0-only
# Makefile for Sphinx documentation
# Minimal makefile for Sphinx documentation
#
# You can set these variables from the command line.
SPHINXOPTS ?=
SPHINXBUILD = sphinx-build
SPHINXAUTOBUILD = sphinx-autobuild
PAPER =
BUILDDIR = _build
# You can set these variables from the command line, and also
# from the environment for the first two.
SPHINXOPTS ?=
SPHINXBUILD ?= sphinx-build
SPHINXAUTOBUILD = sphinx-autobuild
SOURCEDIR = .
BUILDDIR = _build
# Internal variables.
PAPEROPT_a4 = -D latex_paper_size=a4
PAPEROPT_letter = -D latex_paper_size=letter
ALLSPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) .
# the i18n builder cannot share the environment and doctrees with the others
I18NSPHINXOPTS = $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) .
.PHONY: help
# Put it first so that "make" without argument is like "make help".
help:
@echo "Please use \`make <target>' where <target> is one of"
@echo " html to make standalone HTML files"
@echo " dirhtml to make HTML files named index.html in directories"
@echo " singlehtml to make a single large HTML file"
@echo " pickle to make pickle files"
@echo " json to make JSON files"
@echo " htmlhelp to make HTML files and a HTML help project"
@echo " qthelp to make HTML files and a qthelp project"
@echo " applehelp to make an Apple Help Book"
@echo " devhelp to make HTML files and a Devhelp project"
@echo " epub to make an epub"
@echo " epub3 to make an epub3"
@echo " latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter"
@echo " latexpdf to make LaTeX files and run them through pdflatex"
@echo " latexpdfja to make LaTeX files and run them through platex/dvipdfmx"
@echo " text to make text files"
@echo " man to make manual pages"
@echo " texinfo to make Texinfo files"
@echo " info to make Texinfo files and run them through makeinfo"
@echo " gettext to make PO message catalogs"
@echo " changes to make an overview of all changed/added/deprecated items"
@echo " xml to make Docutils-native XML files"
@echo " pseudoxml to make pseudoxml-XML files for display purposes"
@echo " linkcheck to check all external links for integrity"
@echo " doctest to run all doctests embedded in the documentation (if enabled)"
@echo " coverage to run coverage check of the documentation (if enabled)"
@echo " dummy to check syntax errors of document sources"
@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
.PHONY: clean
clean:
rm -rf $(BUILDDIR)
.PHONY: html
html:
$(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html
@echo
@echo "Build finished. The HTML pages are in $(BUILDDIR)/html."
.PHONY: help Makefile.sphinx
.PHONY: livehtml
livehtml:
@ -63,172 +23,7 @@ livehtml:
@echo
$(SPHINXAUTOBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)
.PHONY: dirhtml
dirhtml:
$(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml
@echo
@echo "Build finished. The HTML pages are in $(BUILDDIR)/dirhtml."
.PHONY: singlehtml
singlehtml:
$(SPHINXBUILD) -b singlehtml $(ALLSPHINXOPTS) $(BUILDDIR)/singlehtml
@echo
@echo "Build finished. The HTML page is in $(BUILDDIR)/singlehtml."
.PHONY: pickle
pickle:
$(SPHINXBUILD) -b pickle $(ALLSPHINXOPTS) $(BUILDDIR)/pickle
@echo
@echo "Build finished; now you can process the pickle files."
.PHONY: json
json:
$(SPHINXBUILD) -b json $(ALLSPHINXOPTS) $(BUILDDIR)/json
@echo
@echo "Build finished; now you can process the JSON files."
.PHONY: htmlhelp
htmlhelp:
$(SPHINXBUILD) -b htmlhelp $(ALLSPHINXOPTS) $(BUILDDIR)/htmlhelp
@echo
@echo "Build finished; now you can run HTML Help Workshop with the" \
".hhp project file in $(BUILDDIR)/htmlhelp."
.PHONY: qthelp
qthelp:
$(SPHINXBUILD) -b qthelp $(ALLSPHINXOPTS) $(BUILDDIR)/qthelp
@echo
@echo "Build finished; now you can run "qcollectiongenerator" with the" \
".qhcp project file in $(BUILDDIR)/qthelp, like this:"
@echo "# qcollectiongenerator $(BUILDDIR)/qthelp/coreboot.qhcp"
@echo "To view the help file:"
@echo "# assistant -collectionFile $(BUILDDIR)/qthelp/coreboot.qhc"
.PHONY: applehelp
applehelp:
$(SPHINXBUILD) -b applehelp $(ALLSPHINXOPTS) $(BUILDDIR)/applehelp
@echo
@echo "Build finished. The help book is in $(BUILDDIR)/applehelp."
@echo "N.B. You won't be able to view it unless you put it in" \
"~/Library/Documentation/Help or install it in your application" \
"bundle."
.PHONY: devhelp
devhelp:
$(SPHINXBUILD) -b devhelp $(ALLSPHINXOPTS) $(BUILDDIR)/devhelp
@echo
@echo "Build finished."
@echo "To view the help file:"
@echo "# mkdir -p $$HOME/.local/share/devhelp/coreboot"
@echo "# ln -s $(BUILDDIR)/devhelp $$HOME/.local/share/devhelp/coreboot"
@echo "# devhelp"
.PHONY: epub
epub:
$(SPHINXBUILD) -b epub $(ALLSPHINXOPTS) $(BUILDDIR)/epub
@echo
@echo "Build finished. The epub file is in $(BUILDDIR)/epub."
.PHONY: epub3
epub3:
$(SPHINXBUILD) -b epub3 $(ALLSPHINXOPTS) $(BUILDDIR)/epub3
@echo
@echo "Build finished. The epub3 file is in $(BUILDDIR)/epub3."
.PHONY: latex
latex:
$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
@echo
@echo "Build finished; the LaTeX files are in $(BUILDDIR)/latex."
@echo "Run \`make' in that directory to run these through (pdf)latex" \
"(use \`make latexpdf' here to do that automatically)."
.PHONY: latexpdf
latexpdf:
$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
@echo "Running LaTeX files through pdflatex..."
$(MAKE) -C $(BUILDDIR)/latex all-pdf
@echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex."
.PHONY: latexpdfja
latexpdfja:
$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex
@echo "Running LaTeX files through platex and dvipdfmx..."
$(MAKE) -C $(BUILDDIR)/latex all-pdf-ja
@echo "pdflatex finished; the PDF files are in $(BUILDDIR)/latex."
.PHONY: text
text:
$(SPHINXBUILD) -b text $(ALLSPHINXOPTS) $(BUILDDIR)/text
@echo
@echo "Build finished. The text files are in $(BUILDDIR)/text."
.PHONY: man
man:
$(SPHINXBUILD) -b man $(ALLSPHINXOPTS) $(BUILDDIR)/man
@echo
@echo "Build finished. The manual pages are in $(BUILDDIR)/man."
.PHONY: texinfo
texinfo:
$(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo
@echo
@echo "Build finished. The Texinfo files are in $(BUILDDIR)/texinfo."
@echo "Run \`make' in that directory to run these through makeinfo" \
"(use \`make info' here to do that automatically)."
.PHONY: info
info:
$(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo
@echo "Running Texinfo files through makeinfo..."
make -C $(BUILDDIR)/texinfo info
@echo "makeinfo finished; the Info files are in $(BUILDDIR)/texinfo."
.PHONY: gettext
gettext:
$(SPHINXBUILD) -b gettext $(I18NSPHINXOPTS) $(BUILDDIR)/locale
@echo
@echo "Build finished. The message catalogs are in $(BUILDDIR)/locale."
.PHONY: changes
changes:
$(SPHINXBUILD) -b changes $(ALLSPHINXOPTS) $(BUILDDIR)/changes
@echo
@echo "The overview file is in $(BUILDDIR)/changes."
.PHONY: linkcheck
linkcheck:
$(SPHINXBUILD) -b linkcheck $(ALLSPHINXOPTS) $(BUILDDIR)/linkcheck
@echo
@echo "Link check complete; look for any errors in the above output " \
"or in $(BUILDDIR)/linkcheck/output.txt."
.PHONY: doctest
doctest:
$(SPHINXBUILD) -b doctest $(ALLSPHINXOPTS) $(BUILDDIR)/doctest
@echo "Testing of doctests in the sources finished, look at the " \
"results in $(BUILDDIR)/doctest/output.txt."
.PHONY: coverage
coverage:
$(SPHINXBUILD) -b coverage $(ALLSPHINXOPTS) $(BUILDDIR)/coverage
@echo "Testing of coverage in the sources finished, look at the " \
"results in $(BUILDDIR)/coverage/python.txt."
.PHONY: xml
xml:
$(SPHINXBUILD) -b xml $(ALLSPHINXOPTS) $(BUILDDIR)/xml
@echo
@echo "Build finished. The XML files are in $(BUILDDIR)/xml."
.PHONY: pseudoxml
pseudoxml:
$(SPHINXBUILD) -b pseudoxml $(ALLSPHINXOPTS) $(BUILDDIR)/pseudoxml
@echo
@echo "Build finished. The pseudo-XML files are in $(BUILDDIR)/pseudoxml."
.PHONY: dummy
dummy:
$(SPHINXBUILD) -b dummy $(ALLSPHINXOPTS) $(BUILDDIR)/dummy
@echo
@echo "Build finished. Dummy builder generates no files."
# Catch-all target: route all unknown targets to Sphinx using the new
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
%: Makefile.sphinx
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)

View File

@ -5,18 +5,34 @@ backwards support for ACPI 1.0 and is only compatible to ACPI version 2.0 and
upwards.
- [SSDT UID generation](uid.md)
```{toctree}
:maxdepth: 1
SSDT UID generation <uid.md>
```
## GPIO
- [GPIO toggling in ACPI AML](gpio.md)
```{toctree}
:maxdepth: 1
GPIO toggling in ACPI AML <gpio.md>
```
## Windows-specific ACPI documentation
- [Windows-specific documentation](windows.md)
```{toctree}
:maxdepth: 1
Windows-specific documentation <windows.md>
```
## ACPI specification - Useful links
- [ACPI Specification 6.5](https://uefi.org/specs/ACPI/6.5/index.html)
- [ASL 2.0 Syntax](https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-operators-and-expressions)
- [Predefined ACPI Names](https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#predefined-acpi-names)
```{toctree}
:maxdepth: 1
ACPI Specification 6.5 <https://uefi.org/specs/ACPI/6.5/index.html>
ASL 2.0 Syntax <https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-operators-and-expressions>
Predefined ACPI Names <https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#predefined-acpi-names>
```

View File

@ -1141,4 +1141,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
## References:
* [AMD Glossary of terms](https://www.amd.com/system/files/documents/glossary-of-terms-20220505-for-web.pdf)
```{toctree}
:maxdepth: 1
AMD Glossary of terms <https://www.amd.com/system/files/documents/glossary-of-terms-20220505-for-web.pdf>
```

View File

@ -5,7 +5,15 @@ architectures.
## RISC-V
- [RISC-V documentation](riscv/index.md)
```{toctree}
:maxdepth: 1
RISC-V documentation <riscv/index.md>
```
## x86
- [x86 documentation](x86/index.md)
```{toctree}
:maxdepth: 1
x86 documentation <x86/index.md>
```

View File

@ -2,12 +2,14 @@
This section contains documentation about coreboot on x86 architecture.
* [x86 PAE support](pae.md)
```{toctree}
:maxdepth: 1
x86 PAE support <pae.md>
```
## State of x86_64 support
At the moment there's only experimental x86_64 support.
The `emulation/qemu-i440fx` and `emulation/qemu-q35` boards do support
*ARCH_RAMSTAGE_X86_64* , *ARCH_POSTCAR_X86_64* and *ARCH_ROMSTAGE_X86_64*.
Some SOCs now support 64bit mode. Search for HAVE_X86_64_SUPPORT in Kconfig.
In order to add support for x86_64 the following assumptions were made:
* The CPU supports long mode
@ -15,7 +17,6 @@ In order to add support for x86_64 the following assumptions were made:
* All code that is to be run must be below 4GiB in physical memory
* The high dword of pointers is always zero
* The reference implementation is qemu
* The CPU supports 1GiB hugepages
* x86 payloads are loaded below 4GiB in physical memory and are jumped
to in *protected mode*
@ -43,8 +44,12 @@ Basic support for x86_64 has been implemented for QEMU mainboard target.
## Reference implementation
The reference implementation is
* [QEMU i440fx](../../mainboard/emulation/qemu-i440fx.md)
* [QEMU Q35](../../mainboard/emulation/qemu-q35.md)
```{toctree}
:maxdepth: 1
QEMU i440fx <../../mainboard/emulation/qemu-i440fx.md>
QEMU Q35 <../../mainboard/emulation/qemu-q35.md>
```
## TODO
* Identity map memory above 4GiB in ramstage
@ -54,7 +59,6 @@ The reference implementation is
1. Fine grained page tables for SMM:
* Must not have execute and write permissions for the same page.
* Must allow only that TSEG pages can be marked executable
* Must reside in SMRAM
2. Support 64bit PCI BARs above 4GiB
3. Place and run code above 4GiB
@ -62,13 +66,10 @@ The reference implementation is
* Fix compilation errors
* Test how well CAR works with x86_64 and paging
* Improve mode switches
* Test libgfxinit / VGA Option ROMs / FSP
## Known bugs on real hardware
## Known problems on real hardware
According to Intel x86_64 mode hasn't been validated in CAR environments.
Until now it could be verified on various Intel platforms and no issues have
been found.
Running VGA rom directly fails. Yabel works fine though.
## Known bugs on KVM enabled qemu

View File

@ -1,6 +1,10 @@
# Community
* [Code of Conduct](code_of_conduct.md)
* [Language style](language_style.md)
* [Community forums](forums.md)
* [coreboot at conferences](conferences.md)
```{toctree}
:maxdepth: 1
Code of Conduct <code_of_conduct.md>
Language style <language_style.md>
Community forums <forums.md>
coreboot at conferences <conferences.md>
```

View File

@ -1,46 +1,34 @@
# -*- coding: utf-8 -*-
import subprocess
from recommonmark.parser import CommonMarkParser
import sphinx
# Get Sphinx version
major = 0
minor = 0
patchlevel = 0
version = sphinx.__version__.split(".")
if len(version) > 1:
major = int(version[0])
minor = int(version[1])
if len(version) > 2:
patchlevel = int(version[2])
# Add any paths that contain templates here, relative to this directory.
templates_path = ['_templates']
# The suffix(es) of source filenames.
source_suffix = ['.md']
# The master toctree document.
master_doc = 'index'
# General information about the project.
project = u'coreboot'
copyright = u'CC-by 4.0 the coreboot project'
author = u'the coreboot project'
# The version info for the project you're documenting, acts as replacement for
# |version| and |release|, also used in various other places throughout the
# built documents.
# Configuration file for the Sphinx documentation builder.
#
# The full version, including alpha/beta/rc tags.
# For the full list of built-in configuration values, see the documentation:
# https://www.sphinx-doc.org/en/master/usage/configuration.html
# -- Project information -----------------------------------------------------
# https://www.sphinx-doc.org/en/master/usage/configuration.html#project-information
import subprocess
project = 'coreboot'
copyright = 'CC-by 4.0 the coreboot project'
author = 'the coreboot project'
release = subprocess.check_output(('git', 'describe')).decode("utf-8")
# The short X.Y version.
version = release.split("-")[0]
extensions = []
# Load recommonmark, supported since 1.8+
if major >= 2 or (major == 1 and minor >= 8):
extensions += ['recommonmark']
# -- General configuration ---------------------------------------------------
# https://www.sphinx-doc.org/en/master/usage/configuration.html#general-configuration
extensions = ["myst_parser"]
myst_heading_anchors = 5
templates_path = ['_templates']
exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
# The name of the Pygments (syntax highlighting) style to use.
pygments_style = 'sphinx'
# Try to load DITAA
try:
@ -57,62 +45,11 @@ else:
# Usually you set "language" from the command line for these cases.
language = 'en'
# List of patterns, relative to source directory, that match files and
# directories to ignore when looking for source files.
# This patterns also effect to html_static_path and html_extra_path
exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
# -- Options for HTML output -------------------------------------------------
# https://www.sphinx-doc.org/en/master/usage/configuration.html#options-for-html-output
# The name of the Pygments (syntax highlighting) style to use.
pygments_style = 'sphinx'
# A list of ignored prefixes for module index sorting.
# modindex_common_prefix = []
# If true, keep warnings as "system message" paragraphs in the built documents.
# keep_warnings = False
# If true, `todo` and `todoList` produce output, else they produce nothing.
todo_include_todos = False
# -- Options for HTML output ----------------------------------------------
# The theme to use for HTML and HTML Help pages. See the documentation for
# a list of builtin themes.
#
html_theme = 'sphinx_rtd_theme'
# Add any paths that contain custom static files (such as style sheets) here,
# relative to this directory. They are copied after the builtin static files,
# so a file named "default.css" will overwrite the builtin "default.css".
html_static_path = ['_static']
html_css_files = [
'theme_overrides.css', # override wide tables in RTD theme
]
# Output file base name for HTML help builder.
htmlhelp_basename = 'corebootdoc'
enable_auto_toc_tree = True
class MyCommonMarkParser(CommonMarkParser):
# remove this hack once upstream RecommonMark supports inline code
def visit_code(self, mdnode):
from docutils import nodes
n = nodes.literal(mdnode.literal, mdnode.literal)
self.current_node.append(n)
def setup(app):
from recommonmark.transform import AutoStructify
# Load recommonmark on old Sphinx
if major == 1 and minor < 8:
app.add_source_parser('.md', MyCommonMarkParser)
app.add_config_value('recommonmark_config', {
'enable_auto_toc_tree': True,
'enable_auto_doc_ref': False, # broken in Sphinx 1.6+
'enable_eval_rst': True,
'url_resolver': lambda url: '/' + url
}, True)
app.add_transform(AutoStructify)

View File

@ -395,8 +395,8 @@ Gerrit user roles
There are a few relevant roles a user can have on Gerrit:
- The anonymous user can check out source code.
- A registered user can also comment and give "+1" and "-1" code reviews.
- A reviewer can also give "+2" code reviews.
- A registered user can also comment and give "+1" code reviews.
- A reviewer can give "-1" and "+2" code reviews.
- A core developer can also give "-2" (that is, blocking) code reviews
and submit changes.

View File

@ -1,7 +1,11 @@
# Contributing
* [Coding Style](coding_style.md)
* [Gerrit Guidelines](gerrit_guidelines.md)
* [Project Ideas](project_ideas.md)
* [Documentation Ideas](documentation_ideas.md)
* [Google Summer of Code](gsoc.md)
```{toctree}
:maxdepth: 1
Coding Style <coding_style.md>
Gerrit Guidelines <gerrit_guidelines.md>
Project Ideas <project_ideas.md>
Documentation Ideas <documentation_ideas.md>
Google Summer of Code <gsoc.md>
```

View File

@ -8,10 +8,14 @@ For details on how to connect device drivers to a mainboard, see [Driver Devicet
Some of the drivers currently available include:
* [Intel DPTF](dptf.md)
* [IPMI KCS](ipmi_kcs.md)
* [SMMSTORE](smmstore.md)
* [SMMSTOREv2](smmstorev2.md)
* [SoundWire](soundwire.md)
* [USB4 Retimer](retimer.md)
* [CBFS SMBIOS hooks](cbfs_smbios.md)
```{toctree}
:maxdepth: 1
Intel DPTF <dptf.md>
IPMI KCS <ipmi_kcs.md>
SMMSTORE <smmstore.md>
SMMSTOREv2 <smmstorev2.md>
SoundWire <soundwire.md>
USB4 Retimer <retimer.md>
CBFS SMBIOS hooks <cbfs_smbios.md>
```

View File

@ -128,7 +128,11 @@ data or modify the currently running kernel.*
## External links
* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf)
```{toctree}
:maxdepth: 1
A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI <https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf>
```
Note, this differs significantly from coreboot's implementation.
[SMM]: ../security/smm.md

View File

@ -124,25 +124,9 @@ additional calling arguments are passed via `%ebx`.
**NOTE**: The size of the struct entries are in the native word size of
smihandler. This means 32 bits in almost all cases.
#### - SMMSTORE_CMD_INIT = 4
#### - SMMSTORE_CMD_INIT_DEPRECATED = 4
This installs the communication buffer to use and thus enables the
SMMSTORE handler. This command can only be executed once and is done
by the firmware. Calling this function at runtime has no effect.
The additional parameter buffer `%ebx` contains a pointer to the
following struct:
```C
struct smmstore_params_init {
uint32_t com_buffer;
uint32_t com_buffer_size;
} __packed;
```
INPUT:
- `com_buffer`: Physical address of the communication buffer (CBMEM)
- `com_buffer_size`: Size in bytes of the communication buffer
Unused, returns SMMSTORE_REG_UNSUPPORTED.
#### - SMMSTORE_CMD_RAW_READ = 5
@ -215,7 +199,11 @@ running kernel.
## External links
* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf)
```{toctree}
:maxdepth: 1
A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI <https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf>
```
Note that this differs significantly from coreboot's implementation.
[SMM]: ../security/smm.md

View File

@ -17,13 +17,21 @@ Please add any helpful or informational links and sections as you see fit.
* [Part 1: PCI-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-in-x86x64-architecture-part-1-pci-based-systems/)
* [Part 2: PCI express-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-x86x64-architecture-part-2-pci-express-based-systems/)
* [PCIe elastic buffer](https://www.mindshare.com/files/resources/mindshare_pcie_elastic_buffer.pdf)
* [Boot Guard and PSB have user-hostile defaults](https://mjg59.dreamwidth.org/58424.html)
```{toctree}
:maxdepth: 1
Boot Guard and PSB have user-hostile defaults <https://mjg59.dreamwidth.org/58424.html>
```
## General Information
* [OS Dev](https://wiki.osdev.org/Categorized_Main_Page)
* [Interface BUS](http://www.interfacebus.com/)
```{toctree}
:maxdepth: 1
OS Dev <https://wiki.osdev.org/Categorized_Main_Page>
Interface BUS <http://www.interfacebus.com/>
```
## OpenSecurityTraining2
@ -43,10 +51,14 @@ modified works back to the community.
Below is a list of currently available courses that can help understand the
inner workings of coreboot and other firmware-related topics:
* [coreboot design principles and boot process](https://ost2.fyi/Arch4031)
* [x86-64 Assembly](https://ost2.fyi/Arch1001)
* [x86-64 OS Internals](https://ost2.fyi/Arch2001)
* [x86-64 Intel Firmware Attack & Defense](https://ost2.fyi/Arch4001)
```{toctree}
:maxdepth: 1
coreboot design principles and boot process <https://ost2.fyi/Arch4031>
x86-64 Assembly <https://ost2.fyi/Arch1001>
x86-64 OS Internals <https://ost2.fyi/Arch2001>
x86-64 Intel Firmware Attack & Defense <https://ost2.fyi/Arch4001>
```
There are [additional security courses](https://p.ost2.fyi/courses) at the site
as well (such as
@ -54,47 +66,79 @@ as well (such as
## Firmware Specifications & Information
* [System Management BIOS - SMBIOS](https://www.dmtf.org/standards/smbios)
* [Desktop and Mobile Architecture for System Hardware - DASH](https://www.dmtf.org/standards/dash)
* [PNP BIOS](https://www.intel.com/content/dam/support/us/en/documents/motherboards/desktop/sb/pnpbiosspecificationv10a.pdf)
```{toctree}
:maxdepth: 1
System Management BIOS - SMBIOS <https://www.dmtf.org/standards/smbios>
Desktop and Mobile Architecture for System Hardware - DASH <https://www.dmtf.org/standards/dash>
PNP BIOS <https://www.intel.com/content/dam/support/us/en/documents/motherboards/desktop/sb/pnpbiosspecificationv10a.pdf>
```
### ACPI
* [ACPI Specs](https://uefi.org/acpi/specs)
* [ACPI in Linux](https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf)
* [ACPI 5 Linux](https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-ACPI5.pdf)
* [ACPI 6 Linux](https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_Linux_0.pdf)
```{toctree}
:maxdepth: 1
ACPI Specs <https://uefi.org/acpi/specs>
ACPI in Linux <https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf>
ACPI 5 Linux <https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-ACPI5.pdf>
ACPI 6 Linux <https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_Linux_0.pdf>
```
### Security
* [Intel Boot Guard](https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard)
```{toctree}
:maxdepth: 1
Intel Boot Guard <https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard>
```
## Hardware information
* [WikiChip](https://en.wikichip.org/wiki/WikiChip)
* [Sandpile](https://www.sandpile.org/)
* [CPU-World](https://www.cpu-world.com/index.html)
* [CPU-Upgrade](https://www.cpu-upgrade.com/index.html)
```{toctree}
:maxdepth: 1
WikiChip <https://en.wikichip.org/wiki/WikiChip>
Sandpile <https://www.sandpile.org/>
CPU-World <https://www.cpu-world.com/index.html>
CPU-Upgrade <https://www.cpu-upgrade.com/index.html>
```
### Hardware Specifications & Standards
* [Bluetooth](https://www.bluetooth.com/specifications/specs/) - Bluetooth SIG
* [eMMC](https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED)
```{toctree}
:maxdepth: 1
eMMC <https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED>
```
* [eSPI](https://cdrdv2.intel.com/v1/dl/getContent/645987) - Intel
* [I2c Spec](https://web.archive.org/web/20170704151406/https://www.nxp.com/docs/en/user-guide/UM10204.pdf),
[Appnote](https://www.nxp.com/docs/en/application-note/AN10216.pdf) - NXP
* [I2S](https://www.nxp.com/docs/en/user-manual/UM11732.pdf) - NXP
* [I3C](https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED)
* [Memory](https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED)
```{toctree}
:maxdepth: 1
I3C <https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED>
Memory <https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED>
```
* [NVMe](https://nvmexpress.org/developers/) - NVMe Specifications
* [LPC](https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf) - Intel
* [PCI / PCIe / M.2](https://pcisig.com/specifications) - PCI-SIG - (LOGIN REQUIRED)
```{toctree}
:maxdepth: 1
PCI / PCIe / M.2 <https://pcisig.com/specifications) - PCI-SIG - (LOGIN REQUIRED>
```
* [Power Delivery](https://www.usb.org/documents) - USB Implementers Forum
* [SATA](https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED)
```{toctree}
:maxdepth: 1
SATA <https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED>
```
* [SMBus](http://www.smbus.org/specs/) - System Management Interface Forum
* [Smart Battery](http://smartbattery.org/specs/) - Smart Battery System Implementers Forum
* [USB](https://www.usb.org/documents) - USB Implementers Forum
@ -133,5 +177,9 @@ as well (such as
## Infrastructure software
* [Kconfig](https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html)
* [GNU Make](https://www.gnu.org/software/make/manual/)
```{toctree}
:maxdepth: 1
Kconfig <https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html>
GNU Make <https://www.gnu.org/software/make/manual/>
```

View File

@ -75,7 +75,7 @@ $(call add_intermediate, add_mrc_data)
Note that the second line must start with a tab, not spaces.
```eval_rst
```{eval-rst}
See also :doc:`../tutorial/managing_local_additions`.
```

View File

@ -167,7 +167,7 @@ could cause catastrophic failures, up to and including your mainboard!
As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register
supports four different types of GPIO reset as:
```eval_rst
```{eval-rst}
+------------------------+----------------+-------------+-------------+
| | | PAD Reset ? |
+ PAD Reset Config + Platform Reset +-------------+-------------+

View File

@ -1,10 +1,14 @@
# Getting Started
* [coreboot architecture](architecture.md)
* [Build System](build_system.md)
* [Submodules](submodules.md)
* [Kconfig](kconfig.md)
* [Writing Documentation](writing_documentation.md)
* [Setting up GPIOs](gpio.md)
* [Adding devices to a device tree](devicetree.md)
* [Frequently Asked Questions](faq.md)
```{toctree}
:maxdepth: 1
coreboot architecture <architecture.md>
Build System <build_system.md>
Submodules <submodules.md>
Kconfig <kconfig.md>
Writing Documentation <writing_documentation.md>
Setting up GPIOs <gpio.md>
Adding devices to a device tree <devicetree.md>
Frequently Asked Questions <faq.md>
```

View File

@ -11,8 +11,12 @@ configuration front end in coreboot today.
The official Kconfig source and documentation is kept at kernel.org:
- [Kconfig source](https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/scripts/kconfig)
- [Kconfig Language Documentation](https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt)
```{toctree}
:maxdepth: 1
Kconfig source <https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/scripts/kconfig>
Kconfig Language Documentation <https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt>
```
The advantage to using Kconfig is that it allows users to easily select the
high level features of the project to be enabled or disabled at build time.

View File

@ -22,7 +22,7 @@ the power sequence timing parameters, which are usually named T[N] and also
referenced in Intel's respective registers listing. You need the values for
`PP_ON_DELAYS`, `PP_OFF_DELAYS` and `PP_DIVISOR` for your `devicetree.cb`:
```eval_rst
```{eval-rst}
+-----------------------------+---------------------------------------+-----+
| Intel docs | devicetree.cb | eDP |
+-----------------------------+---------------------------------------+-----+

View File

@ -170,34 +170,38 @@ for example OpenBSD, is probably the closest cousin of our approach.
Contents:
* [Getting Started](getting_started/index.md)
* [Tutorial](tutorial/index.md)
* [Contributing](contributing/index.md)
* [Community](community/index.md)
* [Payloads](payloads.md)
* [Distributions](distributions.md)
* [Technotes](technotes/index.md)
* [ACPI](acpi/index.md)
* [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md)
* [Display panel](gfx/display-panel.md)
* [CPU Architecture](arch/index.md)
* [Platform independent drivers](drivers/index.md)
* [Northbridge](northbridge/index.md)
* [System on Chip](soc/index.md)
* [Mainboard](mainboard/index.md)
* [Payloads](lib/payloads/index.md)
* [Libraries](lib/index.md)
* [Options](lib/option.md)
* [Security](security/index.md)
* [SuperIO](superio/index.md)
* [Vendorcode](vendorcode/index.md)
* [Utilities](util.md)
* [Software Bill of Materials](sbom/sbom.md)
* [Project infrastructure & services](infrastructure/index.md)
* [Boards supported in each release directory](releases/boards_supported_on_branches.md)
* [Release notes](releases/index.md)
* [Acronyms & Definitions](acronyms.md)
* [External Resources](external_docs.md)
* [Documentation License](documentation_license.md)
```{toctree}
:maxdepth: 1
Getting Started <getting_started/index.md>
Tutorial <tutorial/index.md>
Contributing <contributing/index.md>
Community <community/index.md>
Payloads <payloads.md>
Distributions <distributions.md>
Technotes <technotes/index.md>
ACPI <acpi/index.md>
Native Graphics Initialization with libgfxinit <gfx/libgfxinit.md>
Display panel <gfx/display-panel.md>
CPU Architecture <arch/index.md>
Platform independent drivers <drivers/index.md>
Northbridge <northbridge/index.md>
System on Chip <soc/index.md>
Mainboard <mainboard/index.md>
Payloads <lib/payloads/index.md>
Libraries <lib/index.md>
Options <lib/option.md>
Security <security/index.md>
SuperIO <superio/index.md>
Vendorcode <vendorcode/index.md>
Utilities <util.md>
Software Bill of Materials <sbom/sbom.md>
Project infrastructure & services <infrastructure/index.md>
Boards supported in each release directory <releases/boards_supported_on_branches.md>
Release notes <releases/index.md>
Acronyms & Definitions <acronyms.md>
External Resources <external_docs.md>
Documentation License <documentation_license.md>
```
[Documentation]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/Documentation/

View File

@ -93,11 +93,19 @@ You can see all the builds in the main jenkins interface:
Most of the time on the builders is taken up by the coreboot main and
coreboot gerrit builds.
* [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/)
```{toctree}
:maxdepth: 1
coreboot gerrit build <https://qa.coreboot.org/job/coreboot-gerrit/>
```
([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend))
* [coreboot main build](https://qa.coreboot.org/job/coreboot/)
```{toctree}
:maxdepth: 1
coreboot main build <https://qa.coreboot.org/job/coreboot/>
```
([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend))

View File

@ -4,9 +4,17 @@ This section contains documentation about our infrastructure
## Services
* [Project services](services.md)
* [Administrator's handbook](admin.md)
```{toctree}
:maxdepth: 1
Project services <services.md>
Administrator's handbook <admin.md>
```
## Jenkins builders and builds
* [Setting up Jenkins build machines](builders.md)
* [Coverity Scan integration](coverity.md)
```{toctree}
:maxdepth: 1
Setting up Jenkins build machines <builders.md>
Coverity Scan integration <coverity.md>
```

View File

@ -3,7 +3,11 @@
This section contains documentation about coreboot internal technical
information and libraries.
- [Flashmap and Flashmap Descriptor](flashmap.md)
- [ABI data consumption](abi-data-consumption.md)
- [Timestamps](timestamp.md)
- [Firmware Configuration Interface](fw_config.md)
```{toctree}
:maxdepth: 1
Flashmap and Flashmap Descriptor <flashmap.md>
ABI data consumption <abi-data-consumption.md>
Timestamps <timestamp.md>
Firmware Configuration Interface <fw_config.md>
```

View File

@ -8,4 +8,8 @@ selected mainboard.
## FIT
- [uImage.FIT support](fit.md)
```{toctree}
:maxdepth: 1
uImage.FIT support <fit.md>
```

View File

@ -5,7 +5,7 @@ Acer models Aspire M3800, Aspire M5800 and possibly more.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | Intel G43 (called x4x in coreboot code) |
+------------------+--------------------------------------------------+
@ -69,7 +69,7 @@ Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
## Flashing coreboot
```eval_rst
```{eval-rst}
+-------------------+---------------------+
| Type | Value |
+===================+=====================+
@ -122,7 +122,7 @@ $ sudo flashrom \
-w coreboot.rom
```
```eval_rst
```{eval-rst}
In addition to the information here, please see the
:doc:`../../tutorial/flashing_firmware/index`.
```

View File

@ -33,7 +33,7 @@ Three items are marked in this picture
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+--------------------+
| Type | Value |
+=====================+====================+
@ -53,7 +53,7 @@ Three items are marked in this picture
## Technology
```eval_rst
```{eval-rst}
+---------------+------------------------------+
| Fan control | Using fintek F81803A |
+---------------+------------------------------+
@ -63,7 +63,7 @@ Three items are marked in this picture
## Description of pictures within this document
```eval_rst
```{eval-rst}
+----------------------------+----------------------------------------+
|pademelon.jpg | Motherboard with components identified |
+----------------------------+----------------------------------------+

View File

@ -11,7 +11,7 @@ Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/inde
FSP Information:
```eval_rst
```{eval-rst}
+-----------------------------+-------------------+-------------------+
| FSP Project Name | Directory | Specification |
+-----------------------------+-------------------+-------------------+
@ -114,7 +114,7 @@ facing towards the bottom of the board.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Skylake/Kaby Lake (LGA1151) |
+------------------+--------------------------------------------------+

View File

@ -5,7 +5,7 @@ Bridge and Ivy Bridge CPUs.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+
@ -71,7 +71,7 @@ extlinux
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -115,7 +115,7 @@ $ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom
The use of `--noverify-all` is required since the Management Engine
region is not readable even by the host.
```eval_rst
```{eval-rst}
In addition to the information here, please see the
:doc:`../../tutorial/flashing_firmware/index`.
```

View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASRock H81M-HDS].
## Required proprietary blobs
```eval_rst
```{eval-rst}
Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
```
@ -75,7 +75,7 @@ facing towards the bottom of the board.
in coreboot. The `coretemp` driver can still be used for accurate CPU
temperature readings from an OS.
```eval_rst
```{eval-rst}
Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
```
@ -111,7 +111,7 @@ Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/haswell/index` |
+------------------+--------------------------------------------------+

View File

@ -14,7 +14,7 @@ and their GPU is [Sea Islands] (GCN2-based).
A10 Richland is recommended for the best performance and working IOMMU.
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| A88XM-E | |
+------------------+--------------------------------------------------+
@ -36,7 +36,7 @@ A10 Richland is recommended for the best performance and working IOMMU.
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+

View File

@ -15,7 +15,7 @@ Both "Trinity" and "Richland" desktop processing units are working,
the CPU architecture in these CPUs/APUs is [Piledriver],
and their GPU is [TeraScale 3] (VLIW4-based).
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| F2A85-M | |
+------------------+--------------------------------------------------+
@ -35,7 +35,7 @@ and their GPU is [TeraScale 3] (VLIW4-based).
+------------------+--------------------------------------------------+
```
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| F2A85-M LE | |
+------------------+--------------------------------------------------+
@ -55,7 +55,7 @@ and their GPU is [TeraScale 3] (VLIW4-based).
+------------------+--------------------------------------------------+
```
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| F2A85-M PRO | |
+------------------+--------------------------------------------------+
@ -77,7 +77,7 @@ and their GPU is [TeraScale 3] (VLIW4-based).
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+

View File

@ -10,7 +10,7 @@ This page describes how to run coreboot on the ASUS P2B-LS mainboard.
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+---------------------------+
| Type | Value |
+=====================+===========================+
@ -90,7 +90,7 @@ for only CPU models that the board will actually be run with.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | Intel I440BX |
+------------------+--------------------------------------------------+

View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the ASUS P3B-F mainboard.
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+---------------------------+
| Type | Value |
+=====================+===========================+
@ -88,7 +88,7 @@ for only CPU models that the board will actually be run with.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | Intel I440BX |
+------------------+--------------------------------------------------+

View File

@ -32,7 +32,7 @@ This page describes how to run coreboot on the [ASUS P5Q] desktop board.
## Flashing coreboot
```eval_rst
```{eval-rst}
+-------------------+----------------+
| Type | Value |
+===================+================+
@ -56,7 +56,7 @@ You can flash coreboot into your motherboard using [this guide].
## Technology
```eval_rst
```{eval-rst}
+------------------+---------------------------------------------------+
| Northbridge | Intel P45 (called x4x in coreboot code) |
+------------------+---------------------------------------------------+

View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8H77-V].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+----------------+
| Type | Value |
+=====================+================+
@ -69,7 +69,7 @@ flash externally.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8H61-M LX].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -84,7 +84,7 @@ region is not readable even by the host.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8H61-M Pro].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -78,7 +78,7 @@ region is not readable even by the host.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8H77-V].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+----------------+
| Type | Value |
+=====================+================+
@ -56,7 +56,7 @@ work. The flash chip is socketed, so it's easy to remove and reflash.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8Z77-M].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+----------------+
| Type | Value |
+=====================+================+
@ -112,7 +112,7 @@ therefore they currently do nothing under coreboot.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8Z77-M PRO]
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+----------------+
| Type | Value |
+=====================+================+
@ -143,7 +143,7 @@ easy to remove and reflash.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [ASUS P8Z77-V].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+----------------+
| Type | Value |
+=====================+================+
@ -86,7 +86,7 @@ See [Asus Wi-Fi Go! v1].
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

View File

@ -8,7 +8,7 @@ through a proprietary 16-1 pin connector.
I managed to grope the most pinout of the proprietary connector.
See [Mini PCIe pinout] for more info.
```eval_rst
```{eval-rst}
+------------+----------+-----------+------------+----------+-----------+
| WIFIGO Pin | Usage | mPCIe pin | WIFIGO Pin | Usage | mPCIe pin |
+============+==========+===========+============+==========+===========+

View File

@ -17,7 +17,7 @@
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+----------------+
| Type | Value |
+=====================+================+
@ -58,7 +58,7 @@
## Technology
```eval_rst
```{eval-rst}
+---------------+----------------------------------------+
| SoC | :doc:`../../soc/cavium/cn81xx/index` |
+---------------+----------------------------------------+

View File

@ -2,7 +2,7 @@
## Hardware
### Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------+
| CPU | Intel i7-8550U |
+------------------+--------------------------------+
@ -15,7 +15,7 @@
```
### Flash chip
```eval_rst
```{eval-rst}
+---------------------+-----------------+
| Type | Value |
+=====================+=================+

View File

@ -6,7 +6,7 @@ This page describes how to run coreboot on Dell OptiPlex 9010 SFF.
## Technology
```eval_rst
```{eval-rst}
+------------+---------------------------------------------------------------+
| CPU | Intel Core 2nd Gen (Sandybridge) or 3rd Gen (Ivybridge) |
+------------+---------------------------------------------------------------+
@ -28,7 +28,7 @@ More specifications on [Dell OptiPlex 9010 specifications].
## Required proprietary blobs
```eval_rst
```{eval-rst}
+------------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+==================+=================================+=====================+
@ -50,7 +50,7 @@ signature `SMSCUBIM`. The easiest way to do this is to use [UEFITool] and
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+--------------------------+
| Type | Value |
+=====================+==========================+

View File

@ -3,6 +3,9 @@
## Building coreboot and running it in QEMU
- Configure coreboot and run `make` as usual
- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to
convert coreboot to an ELF that QEMU can load
- Run `qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf`
Run QEMU
```
qemu-system-riscv64 -M virt -m 1G -nographic -bios build/coreboot.rom \
-drive if=pflash,file=./build/coreboot.rom,format=raw
```

View File

@ -63,7 +63,7 @@ Specifically, it's a Winbond W25Q64FV (3.3V), whose datasheet can be found
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| SoC | Intel Atom Processor N3710 |
+------------------+--------------------------------------------------+

View File

@ -14,7 +14,7 @@ Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/inde
FSP Information:
```eval_rst
```{eval-rst}
+-----------------------------+-------------------+-------------------+
| FSP Project Name | Directory | Specification |
+-----------------------------+-------------------+-------------------+
@ -116,7 +116,7 @@ output.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| SoC | Intel Kaby Lake U |
+------------------+--------------------------------------------------+

View File

@ -14,7 +14,7 @@ The default options for this board should result in a fully working image:
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+--------+
| Type | Value |
+=====================+========+
@ -56,7 +56,7 @@ To do this gently take the SPI flash out of its socket and flash with your progr
## Technology
```eval_rst
```{eval-rst}
+------------------+------------------+
| Northbridge | Intel Pinevew |
+------------------+------------------+

View File

@ -6,7 +6,7 @@ This motherboard [also works with Libreboot](https://libreboot.org/docs/install/
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Type | Value |
+==================+==================================================+
@ -30,7 +30,7 @@ This motherboard [also works with Libreboot](https://libreboot.org/docs/install/
## Preparation
```eval_rst
```{eval-rst}
For more datails how to get sources and build the toolchain, see :doc:`../../tutorial/part1`.
```
@ -140,7 +140,7 @@ Built gigabyte/ga-g41m-es2l (GA-G41M-ES2L)
## Flashing coreboot
```eval_rst
```{eval-rst}
In addition to the information here, please see the
:doc:`../../tutorial/flashing_firmware/index`.
```

View File

@ -5,7 +5,7 @@ from [Gigabyte].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -59,7 +59,7 @@ However, this makes DualBIOS unable to recover from a bad flash for some reason.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

View File

@ -74,7 +74,7 @@ The EHCI debug port is the left USB3 port.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Sandy/Ivy Bridge (FCPGA988) |
+------------------+--------------------------------------------------+

View File

@ -80,7 +80,7 @@ Schematic of this laptop can be found on [Lab One].
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Sandy/Ivy Bridge (FCPGA988) |
+------------------+--------------------------------------------------+

View File

@ -7,7 +7,7 @@ checkout the [code on gerrit] to build coreboot for the laptop.
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -66,7 +66,7 @@ clip to read and flash the chip.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

View File

@ -13,7 +13,7 @@ The following things are still missing from this coreboot port:
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+-------------------------+
| Type | Value |
+=====================+=========================+
@ -128,7 +128,7 @@ as otherwise there's not enough space near the flash.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

View File

@ -5,7 +5,7 @@ from [HP].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+-------------+
| Type | Value |
+=====================+=============+
@ -42,7 +42,7 @@ Wake on LAN is active works great.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

View File

@ -124,7 +124,7 @@ The board can be debugged with EHCI debug. The EHCI debug port is the USB port o
## Technology
```eval_rst
```{eval-rst}
+------------------+-----------------------------+
| SoC | Intel Broadwell |
+------------------+-----------------------------+

View File

@ -138,7 +138,7 @@ The board can be debugged with EHCI debug. The EHCI debug port is the USB port o
## Technology
```eval_rst
```{eval-rst}
+------------------+-----------------------------+
| CPU | Intel Haswell-ULT |
+------------------+-----------------------------+

View File

@ -0,0 +1,103 @@
# HP Pro 3500 Series
This page describes how to run coreboot on the [Pro 3500 Series]
desktop from [HP].
## State
All peripherals should work. Automatic fan control as well as S3 are
working. The board was tested to boot Linux and Windows. EHCI debug
is untested. When using MrChromebox edk2 with secure boot build in, the
board will hang on each boot for about 20 seconds before continuing.
With disabled ME, the SuperIO will not get CPU temperatures via PECI and
therefore the automatic fan control will not increase the fan speed.
## Flashing coreboot
```{eval_rst}
+---------------------+-------------------------+
| Type | Value |
+=====================+=========================+
| Socketed flash | No |
+---------------------+-------------------------+
| Model | W25Q64FVSIG |
+---------------------+-------------------------+
| Size | 8 MiB |
+---------------------+-------------------------+
| In circuit flashing | Yes |
+---------------------+-------------------------+
| Package | SOIC-8 |
+---------------------+-------------------------+
| Write protection | See below |
+---------------------+-------------------------+
| Dual BIOS feature | No |
+---------------------+-------------------------+
| Internal flashing | Yes |
+---------------------+-------------------------+
```
### Flash layout
The original layout of the flash should look like this:
```
00000000:00000fff fd
00400000:007fffff bios
00001000:003fffff me
00fff000:00000fff gbe
00fff000:00000fff pd
```
### Internal programming
The SPI flash can be accessed using [flashrom] (although it reports as
"N25Q064..3E", it works fine).
With a missing FDO jumper, `fd` region is read-only, `bios` region is
read-write and `me` region is locked. Vendor firmware will additionally
protect the flash chip. After shorting the FDO jumper (E2) full
read-write access is granted.
Do **NOT shutdown** the operating system **after flashing** coreboot
from the vendor firmware! This will brick your device because the bios
region will be modified on shutdown. Cut the AC power or do a restart
from the OS.
**Position of FDO jumper (E2) close to the F_USB3**
![][pro_3500_jumper]
[pro_3500_jumper]: pro_3500_series_jumper.avif
### External programming
External programming with an SPI adapter and [flashrom] does work, but
it powers the whole southbridge complex. The average current will be
400mA but spikes may be higher. Connect the power to the flash or the
programming header next to the flash otherwise programming is unstable.
The supply needs to quickly reach 3V3 or else the chip is also unstable
until cleanly power cycled.
**Position of SOIC-8 flash and pin-header near ATX power connector**
![][pro_3500_flash]
[pro_3500_flash]: pro_3500_series_flash.avif
## Technology
```{eval_rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+
| Southbridge | bd82x6x (bd82h61) |
+------------------+--------------------------------------------------+
| CPU | model_206ax |
+------------------+--------------------------------------------------+
| SuperIO | IT8779E (identifies as IT8772F via register) |
+------------------+--------------------------------------------------+
| EC | Fixed function as part of SuperIO |
+------------------+--------------------------------------------------+
| Coprocessor | Intel ME |
+------------------+--------------------------------------------------+
```
[Pro 3500 Series]: https://support.hp.com/us-en/document/c03364089
[HP]: https://www.hp.com/
[flashrom]: https://flashrom.org/Flashrom

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@ -13,7 +13,7 @@ The following things are still missing from this coreboot port:
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+-------------+
| Type | Value |
+=====================+=============+
@ -58,7 +58,7 @@ even interchangeable, so should do coreboot images built for them.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+

View File

@ -4,240 +4,393 @@ This section contains documentation about coreboot on specific mainboards.
## 51NB
- [X210](51nb/x210.md)
```{toctree}
:maxdepth: 1
X210 <51nb/x210.md>
```
## Acer
- [G43T-AM3](acer/g43t-am3.md)
```{toctree}
:maxdepth: 1
G43T-AM3 <acer/g43t-am3.md>
```
## AMD
- [pademelon](amd/pademelon/pademelon.md)
```{toctree}
:maxdepth: 1
pademelon <amd/pademelon/pademelon.md>
```
## ASRock
- [H77 Pro4-M](asrock/h77pro4-m.md)
- [H81M-HDS](asrock/h81m-hds.md)
- [H110M-DVS](asrock/h110m-dvs.md)
```{toctree}
:maxdepth: 1
H77 Pro4-M <asrock/h77pro4-m.md>
H81M-HDS <asrock/h81m-hds.md>
H110M-DVS <asrock/h110m-dvs.md>
```
## ASUS
- [A88XM-E](asus/a88xm-e.md)
- [F2A85-M](asus/f2a85-m.md)
- [P2B-LS](asus/p2b-ls.md)
- [P3B-F](asus/p3b-f.md)
- [P5Q](asus/p5q.md)
- [P8C WS](asus/p8c_ws.md)
- [P8H61-M LX](asus/p8h61-m_lx.md)
- [P8H61-M Pro](asus/p8h61-m_pro.md)
- [P8H77-V](asus/p8h77-v.md)
- [P8Z77-M](asus/p8z77-m.md)
- [P8Z77-M Pro](asus/p8z77-m_pro.md)
- [P8Z77-V](asus/p8z77-v.md)
- [wifigo_v1](asus/wifigo_v1.md)
```{toctree}
:maxdepth: 1
A88XM-E <asus/a88xm-e.md>
F2A85-M <asus/f2a85-m.md>
P2B-LS <asus/p2b-ls.md>
P3B-F <asus/p3b-f.md>
P5Q <asus/p5q.md>
P8C WS <asus/p8c_ws.md>
P8H61-M LX <asus/p8h61-m_lx.md>
P8H61-M Pro <asus/p8h61-m_pro.md>
P8H77-V <asus/p8h77-v.md>
P8Z77-M <asus/p8z77-m.md>
P8Z77-M Pro <asus/p8z77-m_pro.md>
P8Z77-V <asus/p8z77-v.md>
wifigo_v1 <asus/wifigo_v1.md>
```
## Cavium
- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
```{toctree}
:maxdepth: 1
CN81XX EVB SFF <cavium/cn8100_sff_evb.md>
```
## Clevo
- [N130WU / N131WU](clevo/n130wu/index.md)
```{toctree}
:maxdepth: 1
N130WU / N131WU <clevo/n130wu/index.md>
```
## Dell
- [OptiPlex 9010 SFF](dell/optiplex_9010.md)
```{toctree}
:maxdepth: 1
OptiPlex 9010 SFF <dell/optiplex_9010.md>
```
## Emulation
The boards in this section are not real mainboards, but emulators.
- [Spike RISC-V emulator](emulation/spike-riscv.md)
- [QEMU RISC-V emulator](emulation/qemu-riscv.md)
- [QEMU AArch64 emulator](emulation/qemu-aarch64.md)
- [QEMU x86 Q35](emulation/qemu-q35.md)
- [QEMU x86 PC](emulation/qemu-i440fx.md)
- [QEMU POWER9](emulation/qemu-power9.md)
```{toctree}
:maxdepth: 1
Spike RISC-V emulator <emulation/spike-riscv.md>
QEMU RISC-V emulator <emulation/qemu-riscv.md>
QEMU AArch64 emulator <emulation/qemu-aarch64.md>
QEMU x86 Q35 <emulation/qemu-q35.md>
QEMU x86 PC <emulation/qemu-i440fx.md>
QEMU POWER9 <emulation/qemu-power9.md>
```
## Facebook
- [FBG-1701](facebook/fbg1701.md)
- [Monolith](facebook/monolith.md)
```{toctree}
:maxdepth: 1
FBG-1701 <facebook/fbg1701.md>
Monolith <facebook/monolith.md>
```
## Foxconn
- [D41S](foxconn/d41s.md)
```{toctree}
:maxdepth: 1
D41S <foxconn/d41s.md>
```
## Gigabyte
- [GA-G41M-ES2L](gigabyte/ga-g41m-es2l.md)
- [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md)
```{toctree}
:maxdepth: 1
GA-G41M-ES2L <gigabyte/ga-g41m-es2l.md>
GA-H61M-S2PV <gigabyte/ga-h61m-s2pv.md>
```
## HP
- [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
- [Compaq Elite 8300 USDT](hp/compaq_8300_usdt.md)
- [Z220 Workstation SFF](hp/z220_sff.md)
```{toctree}
:maxdepth: 1
Compaq 8200 Elite SFF <hp/compaq_8200_sff.md>
Compaq Elite 8300 USDT <hp/compaq_8300_usdt.md>
Pro 3500 Series <hp/pro_3500_series.md>
Z220 Workstation SFF <hp/z220_sff.md>
```
### EliteBook series
- [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md)
- [HP Sure Start](hp/hp_sure_start.md)
- [EliteBook 2170p](hp/2170p.md)
- [EliteBook 2560p](hp/2560p.md)
- [EliteBook 8760w](hp/8760w.md)
- [EliteBook Folio 9480m](hp/folio_9480m.md)
- [EliteBook 820 G2](hp/elitebook_820_g2.md)
```{toctree}
:maxdepth: 1
HP Laptops with KBC1126 EC <hp/hp_kbc1126_laptops.md>
HP Sure Start <hp/hp_sure_start.md>
EliteBook 2170p <hp/2170p.md>
EliteBook 2560p <hp/2560p.md>
EliteBook 8760w <hp/8760w.md>
EliteBook Folio 9480m <hp/folio_9480m.md>
EliteBook 820 G2 <hp/elitebook_820_g2.md>
```
## Intel
- [DG43GT](intel/dg43gt.md)
- [DQ67SW](intel/dq67sw.md)
- [KBLRVP11](intel/kblrvp11.md)
```{toctree}
:maxdepth: 1
DG43GT <intel/dg43gt.md>
DQ67SW <intel/dq67sw.md>
KBLRVP11 <intel/kblrvp11.md>
```
## Kontron
- [mAL-10](kontron/mal10.md)
```{toctree}
:maxdepth: 1
mAL-10 <kontron/mal10.md>
```
## Lenovo
- [Mainboard codenames](lenovo/codenames.md)
- [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md)
- [R60](lenovo/r60.md)
- [T4xx common](lenovo/t4xx_series.md)
- [X2xx common](lenovo/x2xx_series.md)
- [vboot](lenovo/vboot.md)
```{toctree}
:maxdepth: 1
Mainboard codenames <lenovo/codenames.md>
Hardware Maintenance Manual of ThinkPads <lenovo/thinkpad_hmm.md>
R60 <lenovo/r60.md>
T4xx common <lenovo/t4xx_series.md>
X2xx common <lenovo/x2xx_series.md>
vboot <lenovo/vboot.md>
```
### GM45 series
- [X200 / T400 / T500 / X301 common](lenovo/montevina_series.md)
- [X301](lenovo/x301.md)
```{toctree}
:maxdepth: 1
X200 / T400 / T500 / X301 common <lenovo/montevina_series.md>
X301 <lenovo/x301.md>
```
### Arrandale series
- [T410](lenovo/t410.md)
```{toctree}
:maxdepth: 1
T410 <lenovo/t410.md>
```
### Sandy Bridge series
- [T420](lenovo/t420.md)
- [T420 / T520 / X220 / T420s / W520 common](lenovo/Sandy_Bridge_series.md)
- [X1](lenovo/x1.md)
```{toctree}
:maxdepth: 1
T420 <lenovo/t420.md>
T420 / T520 / X220 / T420s / W520 common <lenovo/Sandy_Bridge_series.md>
X1 <lenovo/x1.md>
```
### Ivy Bridge series
- [T430](lenovo/t430.md)
- [T530 / W530](lenovo/w530.md)
- [T430 / T530 / X230 / W530 common](lenovo/Ivy_Bridge_series.md)
- [T431s](lenovo/t431s.md)
- [X230s](lenovo/x230s.md)
- [Internal flashing](lenovo/ivb_internal_flashing.md)
```{toctree}
:maxdepth: 1
T430 <lenovo/t430.md>
T530 / W530 <lenovo/w530.md>
T430 / T530 / X230 / W530 common <lenovo/Ivy_Bridge_series.md>
T431s <lenovo/t431s.md>
X230s <lenovo/x230s.md>
Internal flashing <lenovo/ivb_internal_flashing.md>
```
### Haswell series
- [T440p](lenovo/t440p.md)
```{toctree}
:maxdepth: 1
T440p <lenovo/t440p.md>
```
## Libretrend
- [LT1000](libretrend/lt1000.md)
```{toctree}
:maxdepth: 1
LT1000 <libretrend/lt1000.md>
```
## MSI
- [MS-7707](msi/ms7707/ms7707.md)
```{toctree}
:maxdepth: 1
MS-7707 <msi/ms7707/ms7707.md>
```
## OCP
- [Delta Lake](ocp/deltalake.md)
- [Tioga Pass](ocp/tiogapass.md)
```{toctree}
:maxdepth: 1
Delta Lake <ocp/deltalake.md>
Tioga Pass <ocp/tiogapass.md>
```
## Open Cellular
- [Elgon](opencellular/elgon.md)
```{toctree}
:maxdepth: 1
Elgon <opencellular/elgon.md>
```
## PC Engines
- [APU1](pcengines/apu1.md)
- [APU2](pcengines/apu2.md)
```{toctree}
:maxdepth: 1
APU1 <pcengines/apu1.md>
APU2 <pcengines/apu2.md>
```
## Portwell
- [PQ7-M107](portwell/pq7-m107.md)
```{toctree}
:maxdepth: 1
PQ7-M107 <portwell/pq7-m107.md>
```
## Prodrive
- [Hermes](prodrive/hermes.md)
```{toctree}
:maxdepth: 1
Hermes <prodrive/hermes.md>
```
## Purism
- [Librem 14](purism/librem_14.md)
- [Librem Mini](purism/librem_mini.md)
```{toctree}
:maxdepth: 1
Librem 14 <purism/librem_14.md>
Librem Mini <purism/librem_mini.md>
```
## Protectli
- [FW2B / FW4B](protectli/fw2b_fw4b.md)
- [FW6A / FW6B / FW6C](protectli/fw6.md)
- [VP2420](protectli/vp2420.md)
- [VP4630 / VP4650 / VP4670](protectli/vp46xx.md)
```{toctree}
:maxdepth: 1
FW2B / FW4B <protectli/fw2b_fw4b.md>
FW6A / FW6B / FW6C <protectli/fw6.md>
VP2420 <protectli/vp2420.md>
VP4630 / VP4650 / VP4670 <protectli/vp46xx.md>
```
## Roda
- [RK9 Flash Header](roda/rk9/flash_header.md)
```{toctree}
:maxdepth: 1
RK9 Flash Header <roda/rk9/flash_header.md>
```
## SiFive
- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
```{toctree}
:maxdepth: 1
SiFive HiFive Unleashed <sifive/hifive-unleashed.md>
```
## Star Labs Systems
- [LabTop Mk III](starlabs/labtop_kbl.md)
- [LabTop Mk IV](starlabs/labtop_cml.md)
- [StarLite Mk III](starlabs/lite_glk.md)
- [StarLite Mk IV](starlabs/lite_glkr.md)
- [StarBook Mk V](starlabs/starbook_tgl.md)
- [StarBook Mk VI](starlabs/starbook_adl.md)
- [Flashing devices](starlabs/common/flashing.md)
```{toctree}
:maxdepth: 1
LabTop Mk III <starlabs/labtop_kbl.md>
LabTop Mk IV <starlabs/labtop_cml.md>
StarLite Mk III <starlabs/lite_glk.md>
StarLite Mk IV <starlabs/lite_glkr.md>
StarBook Mk V <starlabs/starbook_tgl.md>
StarBook Mk VI <starlabs/starbook_adl.md>
Flashing devices <starlabs/common/flashing.md>
```
## Supermicro
- [X9SAE](supermicro/x9sae.md)
- [X10SLM+-F](supermicro/x10slm-f.md)
- [X11 LGA1151 series](supermicro/x11-lga1151-series/x11-lga1151-series.md)
- [Flashing using the BMC](supermicro/flashing_on_vendorbmc.md)
```{toctree}
:maxdepth: 1
X9SAE <supermicro/x9sae.md>
X10SLM+-F <supermicro/x10slm-f.md>
X11 LGA1151 series <supermicro/x11-lga1151-series/x11-lga1151-series.md>
Flashing using the BMC <supermicro/flashing_on_vendorbmc.md>
```
## System76
- [Adder Workstation 1](system76/addw1.md)
- [Adder Workstation 2](system76/addw2.md)
- [Adder Workstation 3](system76/addw3.md)
- [Bonobo Workstation 14](system76/bonw14.md)
- [Bonobo Workstation 15](system76/bonw15.md)
- [Darter Pro 6](system76/darp6.md)
- [Darter Pro 7](system76/darp7.md)
- [Darter Pro 8](system76/darp8.md)
- [Darter Pro 9](system76/darp9.md)
- [Galago Pro 4](system76/galp4.md)
- [Galago Pro 5](system76/galp5.md)
- [Galago Pro 6](system76/galp6.md)
- [Galago Pro 7](system76/galp7.md)
- [Gazelle 15](system76/gaze15.md)
- [Gazelle 16](system76/gaze16.md)
- [Gazelle 17](system76/gaze17.md)
- [Gazelle 18](system76/gaze18.md)
- [Lemur Pro 9](system76/lemp9.md)
- [Lemur Pro 10](system76/lemp10.md)
- [Lemur Pro 11](system76/lemp11.md)
- [Lemur Pro 12](system76/lemp12.md)
- [Oryx Pro 5](system76/oryp5.md)
- [Oryx Pro 6](system76/oryp6.md)
- [Oryx Pro 7](system76/oryp7.md)
- [Oryx Pro 8](system76/oryp8.md)
- [Oryx Pro 9](system76/oryp9.md)
- [Oryx Pro 10](system76/oryp10.md)
- [Oryx Pro 11](system76/oryp11.md)
- [Serval Workstation 13](system76/serw13.md)
```{toctree}
:maxdepth: 1
Adder Workstation 1 <system76/addw1.md>
Adder Workstation 2 <system76/addw2.md>
Adder Workstation 3 <system76/addw3.md>
Bonobo Workstation 14 <system76/bonw14.md>
Bonobo Workstation 15 <system76/bonw15.md>
Darter Pro 6 <system76/darp6.md>
Darter Pro 7 <system76/darp7.md>
Darter Pro 8 <system76/darp8.md>
Darter Pro 9 <system76/darp9.md>
Galago Pro 4 <system76/galp4.md>
Galago Pro 5 <system76/galp5.md>
Galago Pro 6 <system76/galp6.md>
Galago Pro 7 <system76/galp7.md>
Gazelle 15 <system76/gaze15.md>
Gazelle 16 <system76/gaze16.md>
Gazelle 17 <system76/gaze17.md>
Gazelle 18 <system76/gaze18.md>
Lemur Pro 9 <system76/lemp9.md>
Lemur Pro 10 <system76/lemp10.md>
Lemur Pro 11 <system76/lemp11.md>
Lemur Pro 12 <system76/lemp12.md>
Oryx Pro 5 <system76/oryp5.md>
Oryx Pro 6 <system76/oryp6.md>
Oryx Pro 7 <system76/oryp7.md>
Oryx Pro 8 <system76/oryp8.md>
Oryx Pro 9 <system76/oryp9.md>
Oryx Pro 10 <system76/oryp10.md>
Oryx Pro 11 <system76/oryp11.md>
Serval Workstation 13 <system76/serw13.md>
```
## Texas Instruments
- [Beaglebone Black](ti/beaglebone-black.md)
```{toctree}
:maxdepth: 1
Beaglebone Black <ti/beaglebone-black.md>
```
## UP
- [Squared](up/squared/index.md)
```{toctree}
:maxdepth: 1
Squared <up/squared/index.md>
```

View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on the [Intel DG43GT] desktop.
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -79,7 +79,7 @@ The layout of the header is:
## Technology
```eval_rst
```{eval-rst}
+------------------+---------------------------------------------------+
| Northbridge | Intel G43 (called x4x in coreboot code) |
+------------------+---------------------------------------------------+

View File

@ -4,7 +4,7 @@ The Intel DQ67SW is a microATX-sized desktop board for Intel Sandy Bridge CPUs.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+
@ -67,7 +67,7 @@ The Intel DQ67SW is a microATX-sized desktop board for Intel Sandy Bridge CPUs.
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -104,7 +104,7 @@ the PCI configuration space of the LPC Interface Bridge, is set.
It is possible to program the chip is to attach an external programmer
with an SOIC-8 clip.
```eval_rst
```{eval-rst}
Another way is to boot the vendor firmware in UEFI mode and exploit the
unpatched S3 Boot Script vulnerability. See this page for a similar procedure:
:doc:`../lenovo/ivb_internal_flashing`.
@ -126,7 +126,7 @@ The boot script contains an entry that writes 0x02 to memory at address
Interface Bridge [0][1]. The value 0x02 sets the BLE bit, and the modification
prevents this by making it write a 0 instead.
```eval_rst
```{eval-rst}
After suspending and resuming the board, the BIOS region can be flashed with
a coreboot image, e.g. using flashrom. Note that the ME region is not readable,
so the `--noverify-all` flag is necessary. Please refer to the

View File

@ -23,7 +23,7 @@
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -65,7 +65,7 @@ $ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all
## Technology
```eval_rst
```{eval-rst}
+------------------+---------------------------------------------------+
| CPU | Kaby lake H (i7-7820EQ) |
+------------------+---------------------------------------------------+

View File

@ -6,7 +6,7 @@ processors.
## Technology
```eval_rst
```{eval-rst}
+------------------+----------------------------------+
| COMe Type | mini pin-out type 10 |
+------------------+----------------------------------+

View File

@ -3,7 +3,7 @@
This information is valid for all supported models, except T430s, [T431s](t431s.md) and [X230s](x230s.md).
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+--------------------------------+
| Type | Value |
+=====================+================================+
@ -37,7 +37,7 @@ This information is valid for all supported models, except T430s, [T431s](t431s.
exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB.
* ROM chip size should be set to 12MiB.
```eval_rst
```{eval-rst}
Please also have a look at :doc:`../../tutorial/flashing_firmware/index`.
```

View File

@ -1,7 +1,7 @@
# Lenovo Sandy Bridge series
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+--------------------+
| Type | Value |
+=====================+====================+

View File

@ -1,6 +1,6 @@
# Lenovo mainboard codenames
```eval_rst
```{eval-rst}
.. csv-table::
:header: "Marketing name", "Development codename"
:file: codenames.csv

View File

@ -19,7 +19,11 @@ that was discovered and fixed later.
- USB drive (in case you need to downgrade BIOS)
- Linux install that (can be) loaded in UEFI mode
- [CHIPSEC](https://github.com/chipsec/chipsec)
```{toctree}
:maxdepth: 1
CHIPSEC <https://github.com/chipsec/chipsec>
```
## BIOS versions
@ -27,7 +31,7 @@ Below is a table of BIOS versions that are vulnerable enough for our
goals, per model. The version number means that you need to downgrade to
that or earlier version.
```eval_rst
```{eval-rst}
+------------+--------------+
| Model | BIOS version |
+============+==============+

View File

@ -20,7 +20,7 @@ touch any other regions:
## Installing without ME firmware
```eval_rst
```{eval-rst}
.. Note::
**ThinkPad R500** has slightly different flash layout (it doesn't have
``gbe`` region), so the process would be a little different for that model.
@ -51,7 +51,7 @@ your backup with **ifdtool**](#modifying-flash-descriptor-using-ifdtool), or
Pick the layout according to your chip size from the table below and save it to
the `new_layout.txt` file:
```eval_rst
```{eval-rst}
+---------------------------+---------------------------+---------------------------+
| 4 MiB chip | 8 MiB chip | 16 MiB chip |
+===========================+===========================+===========================+
@ -102,7 +102,7 @@ $ make
If your flash is not 8 MiB, you need to change values of `flcomp_density1` and
`flreg1_limit` in the `ifd-x200.set` file according to following table:
```eval_rst
```{eval-rst}
+-----------------+-------+-------+--------+
| | 4 MiB | 8 MiB | 16 MiB |
+=================+=======+=======+========+
@ -144,7 +144,7 @@ Then build coreboot and flash whole `build/coreboot.rom` to the chip.
The flash layouts of the OEM firmware are as follows:
```eval_rst
```{eval-rst}
+---------------------------------+---------------------------------+
| 4 MiB chip | 8 MiB chip |
+=================================+=================================+

View File

@ -5,7 +5,7 @@
* TPM not working with VBOOT and C_ENV bootblock (works without C_ENV BB)
## Flashing instructions
```eval_rst
```{eval-rst}
+---------------------+--------------------------------+
| Type | Value |
+=====================+================================+

View File

@ -10,7 +10,7 @@ Librebox).
To build a minimal working coreboot image some blobs are required (assuming
only the BIOS region is being modified).
```eval_rst
```{eval-rst}
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+
@ -98,7 +98,7 @@ The platform contains an LR-i7S65T1 baseboard (LR-i7S65T2 with two NICs not
sold yet). More details on [baseboard site]. Unfortunately the board manual is
not publicly available.
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Core i7-6500U |
+------------------+--------------------------------------------------+

View File

@ -9,7 +9,7 @@
* IME 7.0.4.1197
## Flash chip (Winbond 25Q32BV)
```eval_rst
```{eval-rst}
+---------------------+--------------------+
| Type | Value |
+=====================+====================+

View File

@ -200,7 +200,7 @@ and [u-root] as initramfs.
## Technology
```eval_rst
```{eval-rst}
+------------------------+---------------------------------------------+
| Processor (1 socket) | Intel Cooper Lake Scalable Processor |
+------------------------+---------------------------------------------+

View File

@ -80,7 +80,7 @@ u-root.
## Technology
```eval_rst
```{eval-rst}
+------------------------+---------------------------------------------+
| Processor (2 sockets) | Intel Skylake Scalable Processor LGA3647 |
+------------------------+---------------------------------------------+

View File

@ -9,7 +9,7 @@ from [OpenCellular].
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+
@ -69,7 +69,7 @@ Dediprog compatible pinout.
## Technology
```eval_rst
```{eval-rst}
+---------------+----------------------------------------+
| SoC | :doc:`../../soc/cavium/cn81xx/index` |
+---------------+----------------------------------------+

View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on PC Engines APU1 platform.
## Technology
```eval_rst
```{eval-rst}
+------------+--------------------------------------------------------+
| CPU | AMD G series T40E APU |
+------------+--------------------------------------------------------+
@ -23,7 +23,7 @@ This page describes how to run coreboot on PC Engines APU1 platform.
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+--------------------------+
| Type | Value |
+=====================+==========================+

View File

@ -4,7 +4,7 @@ This page describes how to run coreboot on PC Engines APU2 platform.
## Technology
```eval_rst
```{eval-rst}
+------------+---------------------------------------------------------------+
| CPU | AMD G series GX-412TC |
+------------+---------------------------------------------------------------+
@ -25,7 +25,7 @@ This page describes how to run coreboot on PC Engines APU2 platform.
To build working coreboot image some blobs are needed.
```eval_rst
```{eval-rst}
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+
@ -41,7 +41,7 @@ blobs are listed and available is: *3rdparty/southbridge/amd/avalon/PSP*
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+--------------------------+
| Type | Value |
+=====================+==========================+

View File

@ -61,7 +61,7 @@ serial/video/pcie ports might be available.
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| SoC | Intel Atom Processor N3710 |
+------------------+--------------------------------------------------+

View File

@ -32,7 +32,7 @@ The board features:
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | CoffeeLake + CoffeeLake R (Core + Xeon) |
+------------------+--------------------------------------------------+

View File

@ -9,7 +9,7 @@ This page describes how to run coreboot on the [Protectli FW2B] and
To build a minimal working coreboot image some blobs are required (assuming
only the BIOS region is being modified).
```eval_rst
```{eval-rst}
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+
@ -91,7 +91,7 @@ connected via [FE1.1 USB 2.0 hub].
- FW2B:
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Celeron J3060 |
+------------------+--------------------------------------------------+
@ -107,7 +107,7 @@ connected via [FE1.1 USB 2.0 hub].
- FW4B:
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Celeron J3160 |
+------------------+--------------------------------------------------+

View File

@ -9,7 +9,7 @@ This page describes how to run coreboot on the [Protectli FW6].
To build a minimal working coreboot image some blobs are required (assuming
only the BIOS region is being modified).
```eval_rst
```{eval-rst}
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+
@ -92,7 +92,7 @@ used SoC.
- FW6A:
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Celeron 3865U |
+------------------+--------------------------------------------------+
@ -106,7 +106,7 @@ used SoC.
- FW6B:
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Core i3-7100U |
+------------------+--------------------------------------------------+
@ -120,7 +120,7 @@ used SoC.
- FW6C:
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Core i5-7200U |
+------------------+--------------------------------------------------+

View File

@ -10,7 +10,7 @@ This page describes how to run coreboot on the [Protectli VP2420].
To build a minimal working coreboot image some blobs are required (assuming
only the BIOS region is being modified).
```eval_rst
```{eval-rst}
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+
@ -66,7 +66,7 @@ MX25L12835F - [datasheet][MX25L12835F].
## Technology
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Celeron J6412 |
+------------------+--------------------------------------------------+
@ -80,8 +80,12 @@ MX25L12835F - [datasheet][MX25L12835F].
## Useful links
- [VP2420 Hardware Overview](https://protectli.com/kb/vp2400-series-hardware-overview/)
- [VP2420 Product Page](https://protectli.com/product/vp2420/)
- [Protectli TPM module](https://protectli.com/product/tpm-module/)
- [MX25L12835F](https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf)
- [flashrom](https://flashrom.org/Flashrom)
```{toctree}
:maxdepth: 1
VP2420 Hardware Overview <https://protectli.com/kb/vp2400-series-hardware-overview/>
VP2420 Product Page <https://protectli.com/product/vp2420/>
Protectli TPM module <https://protectli.com/product/tpm-module/>
MX25L12835F <https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf>
flashrom <https://flashrom.org/Flashrom>
```

View File

@ -10,7 +10,7 @@ This page describes how to run coreboot on the [Protectli VP46xx].
To build a minimal working coreboot image some blobs are required (assuming
only the BIOS region is being modified).
```eval_rst
```{eval-rst}
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+
@ -84,7 +84,7 @@ ITE IT8786E or IT8784E, but the configuration is the same on this platform.
- VP4630:
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Core i3-10110U |
+------------------+--------------------------------------------------+
@ -98,7 +98,7 @@ ITE IT8786E or IT8784E, but the configuration is the same on this platform.
- VP4650:
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Core i5-10210U |
+------------------+--------------------------------------------------+
@ -112,7 +112,7 @@ ITE IT8786E or IT8784E, but the configuration is the same on this platform.
- VP4670:
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Core i7-10810U |
+------------------+--------------------------------------------------+
@ -126,9 +126,13 @@ ITE IT8786E or IT8784E, but the configuration is the same on this platform.
## Useful links
- [VP4600 Hardware Overview](https://protectli.com/kb/vp4600-hardware-overview/)
- [VP4630 Product Page](https://protectli.com/product/vp4630/)
- [Protectli TPM module](https://protectli.com/product/tpm-module/)
```{toctree}
:maxdepth: 1
VP4600 Hardware Overview <https://protectli.com/kb/vp4600-hardware-overview/>
VP4630 Product Page <https://protectli.com/product/vp4630/>
Protectli TPM module <https://protectli.com/product/tpm-module/>
```
[Protectli VP46xx]: https://protectli.com/vault-6-port/
[MX25L12835F]: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf

View File

@ -2,7 +2,7 @@
This page describes how to run coreboot on the [Purism Librem 14].
```eval_rst
```{eval-rst}
+------------------+------------------------------------------------------+
| CPU | Intel Core i7-10710U |
+------------------+------------------------------------------------------+
@ -23,7 +23,7 @@ This page describes how to run coreboot on the [Purism Librem 14].
To build a minimal working coreboot image some blobs are required (assuming
only the BIOS region is being modified).
```eval_rst
```{eval-rst}
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+

View File

@ -2,7 +2,7 @@
This page describes how to run coreboot on the [Purism Librem Mini].
```eval_rst
```{eval-rst}
+------------------+--------------------------------------------------+
| CPU | Intel Core i7-8565U/8665U (v1) |
| | Intel Core i7-10510U (v2) |
@ -25,7 +25,7 @@ This page describes how to run coreboot on the [Purism Librem Mini].
To build a minimal working coreboot image some blobs are required (assuming
only the BIOS region is being modified).
```eval_rst
```{eval-rst}
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+

View File

@ -45,7 +45,7 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+

View File

@ -42,7 +42,7 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+

View File

@ -41,7 +41,7 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+

View File

@ -41,7 +41,7 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+

View File

@ -78,7 +78,7 @@ make
## Flashing coreboot
```eval_rst
```{eval-rst}
+---------------------+------------+
| Type | Value |
+=====================+============+

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